1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg/tcg-op.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "qemu/qemu-print.h" 27 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 31 #include "tricore-opcodes.h" 32 #include "exec/translator.h" 33 #include "exec/translation-block.h" 34 #include "exec/target_page.h" 35 #include "exec/log.h" 36 37 #define HELPER_H "helper.h" 38 #include "exec/helper-info.c.inc" 39 #undef HELPER_H 40 41 #define DISAS_EXIT DISAS_TARGET_0 42 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 43 #define DISAS_JUMP DISAS_TARGET_2 44 45 /* 46 * TCG registers 47 */ 48 static TCGv cpu_PC; 49 static TCGv cpu_PCXI; 50 static TCGv cpu_PSW; 51 static TCGv cpu_ICR; 52 /* GPR registers */ 53 static TCGv cpu_gpr_a[16]; 54 static TCGv cpu_gpr_d[16]; 55 /* PSW Flag cache */ 56 static TCGv cpu_PSW_C; 57 static TCGv cpu_PSW_V; 58 static TCGv cpu_PSW_SV; 59 static TCGv cpu_PSW_AV; 60 static TCGv cpu_PSW_SAV; 61 62 static const char *regnames_a[] = { 63 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 64 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 65 "a12" , "a13" , "a14" , "a15", 66 }; 67 68 static const char *regnames_d[] = { 69 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 70 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 71 "d12" , "d13" , "d14" , "d15", 72 }; 73 74 typedef struct DisasContext { 75 DisasContextBase base; 76 target_ulong pc_succ_insn; 77 uint32_t opcode; 78 /* Routine used to access memory */ 79 int mem_idx; 80 int priv; 81 uint64_t features; 82 uint32_t icr_ie_mask, icr_ie_offset; 83 } DisasContext; 84 85 static int has_feature(DisasContext *ctx, int feature) 86 { 87 return (ctx->features & (1ULL << feature)) != 0; 88 } 89 90 enum { 91 MODE_LL = 0, 92 MODE_LU = 1, 93 MODE_UL = 2, 94 MODE_UU = 3, 95 }; 96 97 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 98 { 99 CPUTriCoreState *env = cpu_env(cs); 100 uint32_t psw; 101 int i; 102 103 psw = psw_read(env); 104 105 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 106 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 107 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 108 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 109 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 110 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 111 112 for (i = 0; i < 16; ++i) { 113 if ((i & 3) == 0) { 114 qemu_fprintf(f, "\nGPR A%02d:", i); 115 } 116 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 117 } 118 for (i = 0; i < 16; ++i) { 119 if ((i & 3) == 0) { 120 qemu_fprintf(f, "\nGPR D%02d:", i); 121 } 122 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 123 } 124 qemu_fprintf(f, "\n"); 125 } 126 127 /* 128 * Functions to generate micro-ops 129 */ 130 131 /* Macros for generating helpers */ 132 133 #define gen_helper_1arg(name, arg) do { \ 134 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 135 gen_helper_##name(tcg_env, helper_tmp); \ 136 } while (0) 137 138 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 139 TCGv arg00 = tcg_temp_new(); \ 140 TCGv arg01 = tcg_temp_new(); \ 141 TCGv arg11 = tcg_temp_new(); \ 142 tcg_gen_sari_tl(arg00, arg0, 16); \ 143 tcg_gen_ext16s_tl(arg01, arg0); \ 144 tcg_gen_ext16s_tl(arg11, arg1); \ 145 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 146 } while (0) 147 148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 149 TCGv arg00 = tcg_temp_new(); \ 150 TCGv arg01 = tcg_temp_new(); \ 151 TCGv arg10 = tcg_temp_new(); \ 152 TCGv arg11 = tcg_temp_new(); \ 153 tcg_gen_sari_tl(arg00, arg0, 16); \ 154 tcg_gen_ext16s_tl(arg01, arg0); \ 155 tcg_gen_sari_tl(arg11, arg1, 16); \ 156 tcg_gen_ext16s_tl(arg10, arg1); \ 157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 158 } while (0) 159 160 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 161 TCGv arg00 = tcg_temp_new(); \ 162 TCGv arg01 = tcg_temp_new(); \ 163 TCGv arg10 = tcg_temp_new(); \ 164 TCGv arg11 = tcg_temp_new(); \ 165 tcg_gen_sari_tl(arg00, arg0, 16); \ 166 tcg_gen_ext16s_tl(arg01, arg0); \ 167 tcg_gen_sari_tl(arg10, arg1, 16); \ 168 tcg_gen_ext16s_tl(arg11, arg1); \ 169 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 170 } while (0) 171 172 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 173 TCGv arg00 = tcg_temp_new(); \ 174 TCGv arg01 = tcg_temp_new(); \ 175 TCGv arg11 = tcg_temp_new(); \ 176 tcg_gen_sari_tl(arg01, arg0, 16); \ 177 tcg_gen_ext16s_tl(arg00, arg0); \ 178 tcg_gen_sari_tl(arg11, arg1, 16); \ 179 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 180 } while (0) 181 182 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 183 TCGv_i64 ret = tcg_temp_new_i64(); \ 184 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 185 \ 186 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 187 gen_helper_##name(ret, arg1, arg2); \ 188 tcg_gen_extr_i64_i32(rl, rh, ret); \ 189 } while (0) 190 191 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 192 TCGv_i64 ret = tcg_temp_new_i64(); \ 193 \ 194 gen_helper_##name(ret, tcg_env, arg1, arg2); \ 195 tcg_gen_extr_i64_i32(rl, rh, ret); \ 196 } while (0) 197 198 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 199 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 200 ((offset & 0x0fffff) << 1)) 201 202 /* For two 32-bit registers used a 64-bit register, the first 203 registernumber needs to be even. Otherwise we trap. */ 204 static inline void generate_trap(DisasContext *ctx, int class, int tin); 205 #define CHECK_REG_PAIR(reg) do { \ 206 if (reg & 0x1) { \ 207 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 208 } \ 209 } while (0) 210 211 /* Functions for load/save to/from memory */ 212 213 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 214 int16_t con, MemOp mop) 215 { 216 TCGv temp = tcg_temp_new(); 217 tcg_gen_addi_tl(temp, r2, con); 218 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 219 } 220 221 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 222 int16_t con, MemOp mop) 223 { 224 TCGv temp = tcg_temp_new(); 225 tcg_gen_addi_tl(temp, r2, con); 226 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 227 } 228 229 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 230 { 231 TCGv_i64 temp = tcg_temp_new_i64(); 232 233 tcg_gen_concat_i32_i64(temp, rl, rh); 234 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 235 } 236 237 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 238 DisasContext *ctx) 239 { 240 TCGv temp = tcg_temp_new(); 241 tcg_gen_addi_tl(temp, base, con); 242 gen_st_2regs_64(rh, rl, temp, ctx); 243 } 244 245 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 246 { 247 TCGv_i64 temp = tcg_temp_new_i64(); 248 249 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 250 /* write back to two 32 bit regs */ 251 tcg_gen_extr_i64_i32(rl, rh, temp); 252 } 253 254 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 255 DisasContext *ctx) 256 { 257 TCGv temp = tcg_temp_new(); 258 tcg_gen_addi_tl(temp, base, con); 259 gen_ld_2regs_64(rh, rl, temp, ctx); 260 } 261 262 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 263 MemOp mop) 264 { 265 TCGv temp = tcg_temp_new(); 266 tcg_gen_addi_tl(temp, r2, off); 267 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 268 tcg_gen_mov_tl(r2, temp); 269 } 270 271 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 272 MemOp mop) 273 { 274 TCGv temp = tcg_temp_new(); 275 tcg_gen_addi_tl(temp, r2, off); 276 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 277 tcg_gen_mov_tl(r2, temp); 278 } 279 280 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 281 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 282 { 283 TCGv temp = tcg_temp_new(); 284 TCGv temp2 = tcg_temp_new(); 285 286 CHECK_REG_PAIR(ereg); 287 /* temp = (M(EA, word) */ 288 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 289 /* temp = temp & ~E[a][63:32]) */ 290 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 291 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 292 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 293 /* temp = temp | temp2; */ 294 tcg_gen_or_tl(temp, temp, temp2); 295 /* M(EA, word) = temp; */ 296 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 297 } 298 299 /* tmp = M(EA, word); 300 M(EA, word) = D[a]; 301 D[a] = tmp[31:0];*/ 302 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 303 { 304 TCGv temp = tcg_temp_new(); 305 306 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 307 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 308 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 309 } 310 311 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 312 { 313 TCGv temp = tcg_temp_new(); 314 TCGv temp2 = tcg_temp_new(); 315 CHECK_REG_PAIR(reg); 316 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 317 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 318 cpu_gpr_d[reg], temp); 319 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 320 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 321 } 322 323 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 324 { 325 TCGv temp = tcg_temp_new(); 326 TCGv temp2 = tcg_temp_new(); 327 TCGv temp3 = tcg_temp_new(); 328 CHECK_REG_PAIR(reg); 329 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 330 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 331 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 332 tcg_gen_or_tl(temp2, temp2, temp3); 333 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 334 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 335 } 336 337 /* We generate loads and store to core special function register (csfr) through 338 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 339 macros R, A and E, which allow read-only, all and endinit protected access. 340 These macros also specify in which ISA version the csfr was introduced. */ 341 #define R(ADDRESS, REG, FEATURE) \ 342 case ADDRESS: \ 343 if (has_feature(ctx, FEATURE)) { \ 344 tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \ 345 } \ 346 break; 347 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 348 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 349 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 350 { 351 /* since we're caching PSW make this a special case */ 352 if (offset == 0xfe04) { 353 gen_helper_psw_read(ret, tcg_env); 354 } else { 355 switch (offset) { 356 #include "csfr.h.inc" 357 } 358 } 359 } 360 #undef R 361 #undef A 362 #undef E 363 364 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 365 since no exception occurs */ 366 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 367 case ADDRESS: \ 368 if (has_feature(ctx, FEATURE)) { \ 369 tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \ 370 } \ 371 break; 372 /* Endinit protected registers 373 TODO: Since the endinit bit is in a register of a not yet implemented 374 watchdog device, we handle endinit protected registers like 375 all-access registers for now. */ 376 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 377 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 378 int32_t offset) 379 { 380 if (ctx->priv == TRICORE_PRIV_SM) { 381 /* since we're caching PSW make this a special case */ 382 if (offset == 0xfe04) { 383 gen_helper_psw_write(tcg_env, r1); 384 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 385 } else { 386 switch (offset) { 387 #include "csfr.h.inc" 388 } 389 } 390 } else { 391 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 392 } 393 } 394 395 /* Functions for arithmetic instructions */ 396 397 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 398 { 399 TCGv t0 = tcg_temp_new_i32(); 400 TCGv result = tcg_temp_new_i32(); 401 /* Addition and set V/SV bits */ 402 tcg_gen_add_tl(result, r1, r2); 403 /* calc V bit */ 404 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 405 tcg_gen_xor_tl(t0, r1, r2); 406 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 407 /* Calc SV bit */ 408 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 409 /* Calc AV/SAV bits */ 410 tcg_gen_add_tl(cpu_PSW_AV, result, result); 411 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 412 /* calc SAV */ 413 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 414 /* write back result */ 415 tcg_gen_mov_tl(ret, result); 416 } 417 418 static inline void 419 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 420 { 421 TCGv temp = tcg_temp_new(); 422 TCGv_i64 t0 = tcg_temp_new_i64(); 423 TCGv_i64 t1 = tcg_temp_new_i64(); 424 TCGv_i64 result = tcg_temp_new_i64(); 425 426 tcg_gen_add_i64(result, r1, r2); 427 /* calc v bit */ 428 tcg_gen_xor_i64(t1, result, r1); 429 tcg_gen_xor_i64(t0, r1, r2); 430 tcg_gen_andc_i64(t1, t1, t0); 431 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 432 /* calc SV bit */ 433 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 434 /* calc AV/SAV bits */ 435 tcg_gen_extrh_i64_i32(temp, result); 436 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 437 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 438 /* calc SAV */ 439 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 440 /* write back result */ 441 tcg_gen_mov_i64(ret, result); 442 } 443 444 static inline void 445 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 446 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 447 void(*op2)(TCGv, TCGv, TCGv)) 448 { 449 TCGv temp = tcg_temp_new(); 450 TCGv temp2 = tcg_temp_new(); 451 TCGv temp3 = tcg_temp_new(); 452 TCGv temp4 = tcg_temp_new(); 453 454 (*op1)(temp, r1_low, r2); 455 /* calc V0 bit */ 456 tcg_gen_xor_tl(temp2, temp, r1_low); 457 tcg_gen_xor_tl(temp3, r1_low, r2); 458 if (op1 == tcg_gen_add_tl) { 459 tcg_gen_andc_tl(temp2, temp2, temp3); 460 } else { 461 tcg_gen_and_tl(temp2, temp2, temp3); 462 } 463 464 (*op2)(temp3, r1_high, r3); 465 /* calc V1 bit */ 466 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 467 tcg_gen_xor_tl(temp4, r1_high, r3); 468 if (op2 == tcg_gen_add_tl) { 469 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 470 } else { 471 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 472 } 473 /* combine V0/V1 bits */ 474 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 475 /* calc sv bit */ 476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 477 /* write result */ 478 tcg_gen_mov_tl(ret_low, temp); 479 tcg_gen_mov_tl(ret_high, temp3); 480 /* calc AV bit */ 481 tcg_gen_add_tl(temp, ret_low, ret_low); 482 tcg_gen_xor_tl(temp, temp, ret_low); 483 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 484 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 485 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 486 /* calc SAV bit */ 487 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 488 } 489 490 /* ret = r2 + (r1 * r3); */ 491 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 492 { 493 TCGv_i64 t1 = tcg_temp_new_i64(); 494 TCGv_i64 t2 = tcg_temp_new_i64(); 495 TCGv_i64 t3 = tcg_temp_new_i64(); 496 497 tcg_gen_ext_i32_i64(t1, r1); 498 tcg_gen_ext_i32_i64(t2, r2); 499 tcg_gen_ext_i32_i64(t3, r3); 500 501 tcg_gen_mul_i64(t1, t1, t3); 502 tcg_gen_add_i64(t1, t2, t1); 503 504 tcg_gen_extrl_i64_i32(ret, t1); 505 /* calc V 506 t1 > 0x7fffffff */ 507 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 508 /* t1 < -0x80000000 */ 509 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 510 tcg_gen_or_i64(t2, t2, t3); 511 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 512 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 513 /* Calc SV bit */ 514 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 515 /* Calc AV/SAV bits */ 516 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 517 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 518 /* calc SAV */ 519 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 520 } 521 522 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 523 { 524 TCGv temp = tcg_constant_i32(con); 525 gen_madd32_d(ret, r1, r2, temp); 526 } 527 528 static inline void 529 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 530 TCGv r3) 531 { 532 TCGv t1 = tcg_temp_new(); 533 TCGv t2 = tcg_temp_new(); 534 TCGv t3 = tcg_temp_new(); 535 TCGv t4 = tcg_temp_new(); 536 537 tcg_gen_muls2_tl(t1, t2, r1, r3); 538 /* only the add can overflow */ 539 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 540 /* calc V bit */ 541 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 542 tcg_gen_xor_tl(t1, r2_high, t2); 543 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 544 /* Calc SV bit */ 545 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 546 /* Calc AV/SAV bits */ 547 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 548 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 549 /* calc SAV */ 550 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 551 /* write back the result */ 552 tcg_gen_mov_tl(ret_low, t3); 553 tcg_gen_mov_tl(ret_high, t4); 554 } 555 556 static inline void 557 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 558 TCGv r3) 559 { 560 TCGv_i64 t1 = tcg_temp_new_i64(); 561 TCGv_i64 t2 = tcg_temp_new_i64(); 562 TCGv_i64 t3 = tcg_temp_new_i64(); 563 564 tcg_gen_extu_i32_i64(t1, r1); 565 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 566 tcg_gen_extu_i32_i64(t3, r3); 567 568 tcg_gen_mul_i64(t1, t1, t3); 569 tcg_gen_add_i64(t2, t2, t1); 570 /* write back result */ 571 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 572 /* only the add overflows, if t2 < t1 573 calc V bit */ 574 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 575 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 576 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 577 /* Calc SV bit */ 578 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 579 /* Calc AV/SAV bits */ 580 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 581 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 582 /* calc SAV */ 583 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 584 } 585 586 static inline void 587 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 588 int32_t con) 589 { 590 TCGv temp = tcg_constant_i32(con); 591 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 592 } 593 594 static inline void 595 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 596 int32_t con) 597 { 598 TCGv temp = tcg_constant_i32(con); 599 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 600 } 601 602 static inline void 603 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 604 TCGv r3, uint32_t n, uint32_t mode) 605 { 606 TCGv t_n = tcg_constant_i32(n); 607 TCGv temp = tcg_temp_new(); 608 TCGv temp2 = tcg_temp_new(); 609 TCGv_i64 temp64 = tcg_temp_new_i64(); 610 switch (mode) { 611 case MODE_LL: 612 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 613 break; 614 case MODE_LU: 615 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 616 break; 617 case MODE_UL: 618 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 619 break; 620 case MODE_UU: 621 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 622 break; 623 } 624 tcg_gen_extr_i64_i32(temp, temp2, temp64); 625 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 626 tcg_gen_add_tl, tcg_gen_add_tl); 627 } 628 629 static inline void 630 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 631 TCGv r3, uint32_t n, uint32_t mode) 632 { 633 TCGv t_n = tcg_constant_i32(n); 634 TCGv temp = tcg_temp_new(); 635 TCGv temp2 = tcg_temp_new(); 636 TCGv_i64 temp64 = tcg_temp_new_i64(); 637 switch (mode) { 638 case MODE_LL: 639 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 640 break; 641 case MODE_LU: 642 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 643 break; 644 case MODE_UL: 645 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 646 break; 647 case MODE_UU: 648 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 649 break; 650 } 651 tcg_gen_extr_i64_i32(temp, temp2, temp64); 652 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 653 tcg_gen_sub_tl, tcg_gen_add_tl); 654 } 655 656 static inline void 657 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 658 TCGv r3, uint32_t n, uint32_t mode) 659 { 660 TCGv t_n = tcg_constant_i32(n); 661 TCGv_i64 temp64 = tcg_temp_new_i64(); 662 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 663 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 664 switch (mode) { 665 case MODE_LL: 666 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 667 break; 668 case MODE_LU: 669 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 670 break; 671 case MODE_UL: 672 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 673 break; 674 case MODE_UU: 675 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 676 break; 677 } 678 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 679 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 680 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 681 tcg_gen_sub_i64(temp64, temp64_2, temp64); 682 tcg_gen_shli_i64(temp64, temp64, 16); 683 684 gen_add64_d(temp64_2, temp64_3, temp64); 685 /* write back result */ 686 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 687 } 688 689 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 690 691 static inline void 692 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 693 TCGv r3, uint32_t n, uint32_t mode) 694 { 695 TCGv t_n = tcg_constant_i32(n); 696 TCGv temp = tcg_temp_new(); 697 TCGv temp2 = tcg_temp_new(); 698 TCGv temp3 = tcg_temp_new(); 699 TCGv_i64 temp64 = tcg_temp_new_i64(); 700 701 switch (mode) { 702 case MODE_LL: 703 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 704 break; 705 case MODE_LU: 706 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 707 break; 708 case MODE_UL: 709 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 710 break; 711 case MODE_UU: 712 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 713 break; 714 } 715 tcg_gen_extr_i64_i32(temp, temp2, temp64); 716 gen_adds(ret_low, r1_low, temp); 717 tcg_gen_mov_tl(temp, cpu_PSW_V); 718 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 719 gen_adds(ret_high, r1_high, temp2); 720 /* combine v bits */ 721 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 722 /* combine av bits */ 723 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 724 } 725 726 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 727 728 static inline void 729 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 730 TCGv r3, uint32_t n, uint32_t mode) 731 { 732 TCGv t_n = tcg_constant_i32(n); 733 TCGv temp = tcg_temp_new(); 734 TCGv temp2 = tcg_temp_new(); 735 TCGv temp3 = tcg_temp_new(); 736 TCGv_i64 temp64 = tcg_temp_new_i64(); 737 738 switch (mode) { 739 case MODE_LL: 740 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 741 break; 742 case MODE_LU: 743 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 744 break; 745 case MODE_UL: 746 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 747 break; 748 case MODE_UU: 749 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 750 break; 751 } 752 tcg_gen_extr_i64_i32(temp, temp2, temp64); 753 gen_subs(ret_low, r1_low, temp); 754 tcg_gen_mov_tl(temp, cpu_PSW_V); 755 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 756 gen_adds(ret_high, r1_high, temp2); 757 /* combine v bits */ 758 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 759 /* combine av bits */ 760 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 761 } 762 763 static inline void 764 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 765 TCGv r3, uint32_t n, uint32_t mode) 766 { 767 TCGv t_n = tcg_constant_i32(n); 768 TCGv_i64 temp64 = tcg_temp_new_i64(); 769 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 770 771 switch (mode) { 772 case MODE_LL: 773 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 774 break; 775 case MODE_LU: 776 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 777 break; 778 case MODE_UL: 779 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 780 break; 781 case MODE_UU: 782 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 783 break; 784 } 785 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 786 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 787 tcg_gen_sub_i64(temp64, temp64_2, temp64); 788 tcg_gen_shli_i64(temp64, temp64, 16); 789 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 790 791 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 792 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 793 } 794 795 796 static inline void 797 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 798 TCGv r3, uint32_t n, uint32_t mode) 799 { 800 TCGv t_n = tcg_constant_i32(n); 801 TCGv_i64 temp64 = tcg_temp_new_i64(); 802 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 803 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 804 switch (mode) { 805 case MODE_LL: 806 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 807 break; 808 case MODE_LU: 809 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 810 break; 811 case MODE_UL: 812 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 813 break; 814 case MODE_UU: 815 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 816 break; 817 } 818 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 819 gen_add64_d(temp64_3, temp64_2, temp64); 820 /* write back result */ 821 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 822 } 823 824 static inline void 825 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 826 TCGv r3, uint32_t n, uint32_t mode) 827 { 828 TCGv t_n = tcg_constant_i32(n); 829 TCGv_i64 temp64 = tcg_temp_new_i64(); 830 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 831 switch (mode) { 832 case MODE_LL: 833 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 834 break; 835 case MODE_LU: 836 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 837 break; 838 case MODE_UL: 839 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 840 break; 841 case MODE_UU: 842 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 843 break; 844 } 845 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 846 gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); 847 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 848 } 849 850 static inline void 851 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 852 uint32_t mode) 853 { 854 TCGv t_n = tcg_constant_i32(n); 855 TCGv_i64 temp64 = tcg_temp_new_i64(); 856 switch (mode) { 857 case MODE_LL: 858 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 859 break; 860 case MODE_LU: 861 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 862 break; 863 case MODE_UL: 864 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 865 break; 866 case MODE_UU: 867 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 868 break; 869 } 870 gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high); 871 } 872 873 static inline void 874 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 875 { 876 TCGv temp = tcg_temp_new(); 877 TCGv temp2 = tcg_temp_new(); 878 879 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 880 tcg_gen_shli_tl(temp, r1, 16); 881 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 882 } 883 884 static inline void 885 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 886 { 887 TCGv t_n = tcg_constant_i32(n); 888 TCGv temp = tcg_temp_new(); 889 TCGv temp2 = tcg_temp_new(); 890 TCGv_i64 temp64 = tcg_temp_new_i64(); 891 switch (mode) { 892 case MODE_LL: 893 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 894 break; 895 case MODE_LU: 896 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 897 break; 898 case MODE_UL: 899 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 900 break; 901 case MODE_UU: 902 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 903 break; 904 } 905 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 906 tcg_gen_shli_tl(temp, r1, 16); 907 gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2); 908 } 909 910 911 static inline void 912 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 913 uint32_t n, uint32_t mode) 914 { 915 TCGv t_n = tcg_constant_i32(n); 916 TCGv_i64 temp64 = tcg_temp_new_i64(); 917 switch (mode) { 918 case MODE_LL: 919 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 920 break; 921 case MODE_LU: 922 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 923 break; 924 case MODE_UL: 925 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 926 break; 927 case MODE_UU: 928 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 929 break; 930 } 931 gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 932 } 933 934 static inline void 935 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 936 { 937 TCGv temp = tcg_temp_new(); 938 TCGv temp2 = tcg_temp_new(); 939 940 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 941 tcg_gen_shli_tl(temp, r1, 16); 942 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 943 } 944 945 static inline void 946 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 947 { 948 TCGv t_n = tcg_constant_i32(n); 949 TCGv temp = tcg_temp_new(); 950 TCGv temp2 = tcg_temp_new(); 951 TCGv_i64 temp64 = tcg_temp_new_i64(); 952 switch (mode) { 953 case MODE_LL: 954 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 955 break; 956 case MODE_LU: 957 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 958 break; 959 case MODE_UL: 960 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 961 break; 962 case MODE_UU: 963 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 964 break; 965 } 966 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 967 tcg_gen_shli_tl(temp, r1, 16); 968 gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2); 969 } 970 971 static inline void 972 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 973 { 974 TCGv t_n = tcg_constant_i32(n); 975 gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); 976 } 977 978 static inline void 979 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 980 { 981 TCGv t_n = tcg_constant_i32(n); 982 gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); 983 } 984 985 static inline void 986 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 987 uint32_t up_shift) 988 { 989 TCGv temp = tcg_temp_new(); 990 TCGv temp2 = tcg_temp_new(); 991 TCGv temp3 = tcg_temp_new(); 992 TCGv_i64 t1 = tcg_temp_new_i64(); 993 TCGv_i64 t2 = tcg_temp_new_i64(); 994 TCGv_i64 t3 = tcg_temp_new_i64(); 995 996 tcg_gen_ext_i32_i64(t2, arg2); 997 tcg_gen_ext_i32_i64(t3, arg3); 998 999 tcg_gen_mul_i64(t2, t2, t3); 1000 tcg_gen_shli_i64(t2, t2, n); 1001 1002 tcg_gen_ext_i32_i64(t1, arg1); 1003 tcg_gen_sari_i64(t2, t2, up_shift); 1004 1005 tcg_gen_add_i64(t3, t1, t2); 1006 tcg_gen_extrl_i64_i32(temp3, t3); 1007 /* calc v bit */ 1008 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1009 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1010 tcg_gen_or_i64(t1, t1, t2); 1011 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1012 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1013 /* We produce an overflow on the host if the mul before was 1014 (0x80000000 * 0x80000000) << 1). If this is the 1015 case, we negate the ovf. */ 1016 if (n == 1) { 1017 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1018 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1019 tcg_gen_and_tl(temp, temp, temp2); 1020 tcg_gen_shli_tl(temp, temp, 31); 1021 /* negate v bit, if special condition */ 1022 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1023 } 1024 /* Calc SV bit */ 1025 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1026 /* Calc AV/SAV bits */ 1027 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1028 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1029 /* calc SAV */ 1030 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1031 /* write back result */ 1032 tcg_gen_mov_tl(ret, temp3); 1033 } 1034 1035 static inline void 1036 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1037 { 1038 TCGv temp = tcg_temp_new(); 1039 TCGv temp2 = tcg_temp_new(); 1040 if (n == 0) { 1041 tcg_gen_mul_tl(temp, arg2, arg3); 1042 } else { /* n is expected to be 1 */ 1043 tcg_gen_mul_tl(temp, arg2, arg3); 1044 tcg_gen_shli_tl(temp, temp, 1); 1045 /* catch special case r1 = r2 = 0x8000 */ 1046 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1047 tcg_gen_sub_tl(temp, temp, temp2); 1048 } 1049 gen_add_d(ret, arg1, temp); 1050 } 1051 1052 static inline void 1053 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1054 { 1055 TCGv temp = tcg_temp_new(); 1056 TCGv temp2 = tcg_temp_new(); 1057 if (n == 0) { 1058 tcg_gen_mul_tl(temp, arg2, arg3); 1059 } else { /* n is expected to be 1 */ 1060 tcg_gen_mul_tl(temp, arg2, arg3); 1061 tcg_gen_shli_tl(temp, temp, 1); 1062 /* catch special case r1 = r2 = 0x8000 */ 1063 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1064 tcg_gen_sub_tl(temp, temp, temp2); 1065 } 1066 gen_adds(ret, arg1, temp); 1067 } 1068 1069 static inline void 1070 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1071 TCGv arg3, uint32_t n) 1072 { 1073 TCGv temp = tcg_temp_new(); 1074 TCGv temp2 = tcg_temp_new(); 1075 TCGv_i64 t1 = tcg_temp_new_i64(); 1076 TCGv_i64 t2 = tcg_temp_new_i64(); 1077 TCGv_i64 t3 = tcg_temp_new_i64(); 1078 1079 if (n == 0) { 1080 tcg_gen_mul_tl(temp, arg2, arg3); 1081 } else { /* n is expected to be 1 */ 1082 tcg_gen_mul_tl(temp, arg2, arg3); 1083 tcg_gen_shli_tl(temp, temp, 1); 1084 /* catch special case r1 = r2 = 0x8000 */ 1085 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1086 tcg_gen_sub_tl(temp, temp, temp2); 1087 } 1088 tcg_gen_ext_i32_i64(t2, temp); 1089 tcg_gen_shli_i64(t2, t2, 16); 1090 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1091 gen_add64_d(t3, t1, t2); 1092 /* write back result */ 1093 tcg_gen_extr_i64_i32(rl, rh, t3); 1094 } 1095 1096 static inline void 1097 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1098 TCGv arg3, uint32_t n) 1099 { 1100 TCGv temp = tcg_temp_new(); 1101 TCGv temp2 = tcg_temp_new(); 1102 TCGv_i64 t1 = tcg_temp_new_i64(); 1103 TCGv_i64 t2 = tcg_temp_new_i64(); 1104 1105 if (n == 0) { 1106 tcg_gen_mul_tl(temp, arg2, arg3); 1107 } else { /* n is expected to be 1 */ 1108 tcg_gen_mul_tl(temp, arg2, arg3); 1109 tcg_gen_shli_tl(temp, temp, 1); 1110 /* catch special case r1 = r2 = 0x8000 */ 1111 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1112 tcg_gen_sub_tl(temp, temp, temp2); 1113 } 1114 tcg_gen_ext_i32_i64(t2, temp); 1115 tcg_gen_shli_i64(t2, t2, 16); 1116 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1117 1118 gen_helper_add64_ssov(t1, tcg_env, t1, t2); 1119 tcg_gen_extr_i64_i32(rl, rh, t1); 1120 } 1121 1122 static inline void 1123 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1124 TCGv arg3, uint32_t n) 1125 { 1126 TCGv_i64 t1 = tcg_temp_new_i64(); 1127 TCGv_i64 t2 = tcg_temp_new_i64(); 1128 TCGv_i64 t3 = tcg_temp_new_i64(); 1129 TCGv_i64 t4 = tcg_temp_new_i64(); 1130 TCGv temp, temp2; 1131 1132 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1133 tcg_gen_ext_i32_i64(t2, arg2); 1134 tcg_gen_ext_i32_i64(t3, arg3); 1135 1136 tcg_gen_mul_i64(t2, t2, t3); 1137 if (n != 0) { 1138 tcg_gen_shli_i64(t2, t2, 1); 1139 } 1140 tcg_gen_add_i64(t4, t1, t2); 1141 /* calc v bit */ 1142 tcg_gen_xor_i64(t3, t4, t1); 1143 tcg_gen_xor_i64(t2, t1, t2); 1144 tcg_gen_andc_i64(t3, t3, t2); 1145 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1146 /* We produce an overflow on the host if the mul before was 1147 (0x80000000 * 0x80000000) << 1). If this is the 1148 case, we negate the ovf. */ 1149 if (n == 1) { 1150 temp = tcg_temp_new(); 1151 temp2 = tcg_temp_new(); 1152 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1153 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1154 tcg_gen_and_tl(temp, temp, temp2); 1155 tcg_gen_shli_tl(temp, temp, 31); 1156 /* negate v bit, if special condition */ 1157 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1158 } 1159 /* write back result */ 1160 tcg_gen_extr_i64_i32(rl, rh, t4); 1161 /* Calc SV bit */ 1162 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1163 /* Calc AV/SAV bits */ 1164 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1165 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1166 /* calc SAV */ 1167 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1168 } 1169 1170 static inline void 1171 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1172 uint32_t up_shift) 1173 { 1174 TCGv_i64 t1 = tcg_temp_new_i64(); 1175 TCGv_i64 t2 = tcg_temp_new_i64(); 1176 TCGv_i64 t3 = tcg_temp_new_i64(); 1177 1178 tcg_gen_ext_i32_i64(t1, arg1); 1179 tcg_gen_ext_i32_i64(t2, arg2); 1180 tcg_gen_ext_i32_i64(t3, arg3); 1181 1182 tcg_gen_mul_i64(t2, t2, t3); 1183 tcg_gen_sari_i64(t2, t2, up_shift - n); 1184 1185 gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2); 1186 } 1187 1188 static inline void 1189 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1190 TCGv arg3, uint32_t n) 1191 { 1192 TCGv_i64 r1 = tcg_temp_new_i64(); 1193 TCGv t_n = tcg_constant_i32(n); 1194 1195 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1196 gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1197 tcg_gen_extr_i64_i32(rl, rh, r1); 1198 } 1199 1200 /* ret = r2 - (r1 * r3); */ 1201 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1202 { 1203 TCGv_i64 t1 = tcg_temp_new_i64(); 1204 TCGv_i64 t2 = tcg_temp_new_i64(); 1205 TCGv_i64 t3 = tcg_temp_new_i64(); 1206 1207 tcg_gen_ext_i32_i64(t1, r1); 1208 tcg_gen_ext_i32_i64(t2, r2); 1209 tcg_gen_ext_i32_i64(t3, r3); 1210 1211 tcg_gen_mul_i64(t1, t1, t3); 1212 tcg_gen_sub_i64(t1, t2, t1); 1213 1214 tcg_gen_extrl_i64_i32(ret, t1); 1215 /* calc V 1216 t2 > 0x7fffffff */ 1217 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1218 /* result < -0x80000000 */ 1219 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1220 tcg_gen_or_i64(t2, t2, t3); 1221 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1222 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1223 1224 /* Calc SV bit */ 1225 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1226 /* Calc AV/SAV bits */ 1227 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1228 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1229 /* calc SAV */ 1230 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1231 } 1232 1233 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1234 { 1235 TCGv temp = tcg_constant_i32(con); 1236 gen_msub32_d(ret, r1, r2, temp); 1237 } 1238 1239 static inline void 1240 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1241 TCGv r3) 1242 { 1243 TCGv t1 = tcg_temp_new(); 1244 TCGv t2 = tcg_temp_new(); 1245 TCGv t3 = tcg_temp_new(); 1246 TCGv t4 = tcg_temp_new(); 1247 1248 tcg_gen_muls2_tl(t1, t2, r1, r3); 1249 /* only the sub can overflow */ 1250 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1251 /* calc V bit */ 1252 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1253 tcg_gen_xor_tl(t1, r2_high, t2); 1254 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1255 /* Calc SV bit */ 1256 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1257 /* Calc AV/SAV bits */ 1258 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1259 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1260 /* calc SAV */ 1261 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1262 /* write back the result */ 1263 tcg_gen_mov_tl(ret_low, t3); 1264 tcg_gen_mov_tl(ret_high, t4); 1265 } 1266 1267 static inline void 1268 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1269 int32_t con) 1270 { 1271 TCGv temp = tcg_constant_i32(con); 1272 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1273 } 1274 1275 static inline void 1276 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1277 TCGv r3) 1278 { 1279 TCGv_i64 t1 = tcg_temp_new_i64(); 1280 TCGv_i64 t2 = tcg_temp_new_i64(); 1281 TCGv_i64 t3 = tcg_temp_new_i64(); 1282 1283 tcg_gen_extu_i32_i64(t1, r1); 1284 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1285 tcg_gen_extu_i32_i64(t3, r3); 1286 1287 tcg_gen_mul_i64(t1, t1, t3); 1288 tcg_gen_sub_i64(t3, t2, t1); 1289 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1290 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1291 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1292 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1293 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1294 /* Calc SV bit */ 1295 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1296 /* Calc AV/SAV bits */ 1297 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1298 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1299 /* calc SAV */ 1300 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1301 } 1302 1303 static inline void 1304 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1305 int32_t con) 1306 { 1307 TCGv temp = tcg_constant_i32(con); 1308 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1309 } 1310 1311 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1312 { 1313 TCGv temp = tcg_constant_i32(r2); 1314 gen_add_d(ret, r1, temp); 1315 } 1316 1317 /* calculate the carry bit too */ 1318 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1319 { 1320 TCGv t0 = tcg_temp_new_i32(); 1321 TCGv result = tcg_temp_new_i32(); 1322 1323 tcg_gen_movi_tl(t0, 0); 1324 /* Addition and set C/V/SV bits */ 1325 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1326 /* calc V bit */ 1327 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1328 tcg_gen_xor_tl(t0, r1, r2); 1329 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1330 /* Calc SV bit */ 1331 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1332 /* Calc AV/SAV bits */ 1333 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1334 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1335 /* calc SAV */ 1336 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1337 /* write back result */ 1338 tcg_gen_mov_tl(ret, result); 1339 } 1340 1341 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1342 { 1343 TCGv temp = tcg_constant_i32(con); 1344 gen_add_CC(ret, r1, temp); 1345 } 1346 1347 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1348 { 1349 TCGv t0 = tcg_temp_new_i32(); 1350 TCGv result = tcg_temp_new_i32(); 1351 1352 /* Addition, carry and set C/V/SV bits */ 1353 tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C); 1354 /* calc V bit */ 1355 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1356 tcg_gen_xor_tl(t0, r1, r2); 1357 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1358 /* Calc SV bit */ 1359 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1360 /* Calc AV/SAV bits */ 1361 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1362 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1363 /* calc SAV */ 1364 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1365 /* write back result */ 1366 tcg_gen_mov_tl(ret, result); 1367 } 1368 1369 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1370 { 1371 TCGv temp = tcg_constant_i32(con); 1372 gen_addc_CC(ret, r1, temp); 1373 } 1374 1375 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1376 TCGv r4) 1377 { 1378 TCGv temp = tcg_temp_new(); 1379 TCGv temp2 = tcg_temp_new(); 1380 TCGv result = tcg_temp_new(); 1381 TCGv mask = tcg_temp_new(); 1382 TCGv t0 = tcg_constant_i32(0); 1383 1384 /* create mask for sticky bits */ 1385 tcg_gen_setcond_tl(cond, mask, r4, t0); 1386 tcg_gen_shli_tl(mask, mask, 31); 1387 1388 tcg_gen_add_tl(result, r1, r2); 1389 /* Calc PSW_V */ 1390 tcg_gen_xor_tl(temp, result, r1); 1391 tcg_gen_xor_tl(temp2, r1, r2); 1392 tcg_gen_andc_tl(temp, temp, temp2); 1393 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1394 /* Set PSW_SV */ 1395 tcg_gen_and_tl(temp, temp, mask); 1396 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1397 /* calc AV bit */ 1398 tcg_gen_add_tl(temp, result, result); 1399 tcg_gen_xor_tl(temp, temp, result); 1400 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1401 /* calc SAV bit */ 1402 tcg_gen_and_tl(temp, temp, mask); 1403 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1404 /* write back result */ 1405 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1406 } 1407 1408 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1409 TCGv r3, TCGv r4) 1410 { 1411 TCGv temp = tcg_constant_i32(r2); 1412 gen_cond_add(cond, r1, temp, r3, r4); 1413 } 1414 1415 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1416 { 1417 TCGv temp = tcg_temp_new_i32(); 1418 TCGv result = tcg_temp_new_i32(); 1419 1420 tcg_gen_sub_tl(result, r1, r2); 1421 /* calc V bit */ 1422 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1423 tcg_gen_xor_tl(temp, r1, r2); 1424 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1425 /* calc SV bit */ 1426 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1427 /* Calc AV bit */ 1428 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1429 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1430 /* calc SAV bit */ 1431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1432 /* write back result */ 1433 tcg_gen_mov_tl(ret, result); 1434 } 1435 1436 static inline void 1437 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1438 { 1439 TCGv temp = tcg_temp_new(); 1440 TCGv_i64 t0 = tcg_temp_new_i64(); 1441 TCGv_i64 t1 = tcg_temp_new_i64(); 1442 TCGv_i64 result = tcg_temp_new_i64(); 1443 1444 tcg_gen_sub_i64(result, r1, r2); 1445 /* calc v bit */ 1446 tcg_gen_xor_i64(t1, result, r1); 1447 tcg_gen_xor_i64(t0, r1, r2); 1448 tcg_gen_and_i64(t1, t1, t0); 1449 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1450 /* calc SV bit */ 1451 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1452 /* calc AV/SAV bits */ 1453 tcg_gen_extrh_i64_i32(temp, result); 1454 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1455 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1456 /* calc SAV */ 1457 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1458 /* write back result */ 1459 tcg_gen_mov_i64(ret, result); 1460 } 1461 1462 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1463 { 1464 TCGv result = tcg_temp_new(); 1465 TCGv temp = tcg_temp_new(); 1466 1467 tcg_gen_sub_tl(result, r1, r2); 1468 /* calc C bit */ 1469 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1470 /* calc V bit */ 1471 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1472 tcg_gen_xor_tl(temp, r1, r2); 1473 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1474 /* calc SV bit */ 1475 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1476 /* Calc AV bit */ 1477 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1478 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1479 /* calc SAV bit */ 1480 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1481 /* write back result */ 1482 tcg_gen_mov_tl(ret, result); 1483 } 1484 1485 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1486 { 1487 TCGv temp = tcg_temp_new(); 1488 tcg_gen_not_tl(temp, r2); 1489 gen_addc_CC(ret, r1, temp); 1490 } 1491 1492 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1493 TCGv r4) 1494 { 1495 TCGv temp = tcg_temp_new(); 1496 TCGv temp2 = tcg_temp_new(); 1497 TCGv result = tcg_temp_new(); 1498 TCGv mask = tcg_temp_new(); 1499 TCGv t0 = tcg_constant_i32(0); 1500 1501 /* create mask for sticky bits */ 1502 tcg_gen_setcond_tl(cond, mask, r4, t0); 1503 tcg_gen_shli_tl(mask, mask, 31); 1504 1505 tcg_gen_sub_tl(result, r1, r2); 1506 /* Calc PSW_V */ 1507 tcg_gen_xor_tl(temp, result, r1); 1508 tcg_gen_xor_tl(temp2, r1, r2); 1509 tcg_gen_and_tl(temp, temp, temp2); 1510 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1511 /* Set PSW_SV */ 1512 tcg_gen_and_tl(temp, temp, mask); 1513 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1514 /* calc AV bit */ 1515 tcg_gen_add_tl(temp, result, result); 1516 tcg_gen_xor_tl(temp, temp, result); 1517 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1518 /* calc SAV bit */ 1519 tcg_gen_and_tl(temp, temp, mask); 1520 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1521 /* write back result */ 1522 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1523 } 1524 1525 static inline void 1526 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1527 TCGv r3, uint32_t n, uint32_t mode) 1528 { 1529 TCGv t_n = tcg_constant_i32(n); 1530 TCGv temp = tcg_temp_new(); 1531 TCGv temp2 = tcg_temp_new(); 1532 TCGv_i64 temp64 = tcg_temp_new_i64(); 1533 switch (mode) { 1534 case MODE_LL: 1535 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1536 break; 1537 case MODE_LU: 1538 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1539 break; 1540 case MODE_UL: 1541 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1542 break; 1543 case MODE_UU: 1544 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1545 break; 1546 } 1547 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1548 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1549 tcg_gen_sub_tl, tcg_gen_sub_tl); 1550 } 1551 1552 static inline void 1553 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1554 TCGv r3, uint32_t n, uint32_t mode) 1555 { 1556 TCGv t_n = tcg_constant_i32(n); 1557 TCGv temp = tcg_temp_new(); 1558 TCGv temp2 = tcg_temp_new(); 1559 TCGv temp3 = tcg_temp_new(); 1560 TCGv_i64 temp64 = tcg_temp_new_i64(); 1561 1562 switch (mode) { 1563 case MODE_LL: 1564 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1565 break; 1566 case MODE_LU: 1567 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1568 break; 1569 case MODE_UL: 1570 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1571 break; 1572 case MODE_UU: 1573 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1574 break; 1575 } 1576 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1577 gen_subs(ret_low, r1_low, temp); 1578 tcg_gen_mov_tl(temp, cpu_PSW_V); 1579 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1580 gen_subs(ret_high, r1_high, temp2); 1581 /* combine v bits */ 1582 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1583 /* combine av bits */ 1584 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1585 } 1586 1587 static inline void 1588 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1589 TCGv r3, uint32_t n, uint32_t mode) 1590 { 1591 TCGv t_n = tcg_constant_i32(n); 1592 TCGv_i64 temp64 = tcg_temp_new_i64(); 1593 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1594 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1595 switch (mode) { 1596 case MODE_LL: 1597 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1598 break; 1599 case MODE_LU: 1600 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1601 break; 1602 case MODE_UL: 1603 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1604 break; 1605 case MODE_UU: 1606 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1607 break; 1608 } 1609 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1610 gen_sub64_d(temp64_3, temp64_2, temp64); 1611 /* write back result */ 1612 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1613 } 1614 1615 static inline void 1616 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1617 TCGv r3, uint32_t n, uint32_t mode) 1618 { 1619 TCGv t_n = tcg_constant_i32(n); 1620 TCGv_i64 temp64 = tcg_temp_new_i64(); 1621 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1622 switch (mode) { 1623 case MODE_LL: 1624 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1625 break; 1626 case MODE_LU: 1627 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1628 break; 1629 case MODE_UL: 1630 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1631 break; 1632 case MODE_UU: 1633 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1634 break; 1635 } 1636 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1637 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 1638 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1639 } 1640 1641 static inline void 1642 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1643 uint32_t mode) 1644 { 1645 TCGv t_n = tcg_constant_i32(n); 1646 TCGv_i64 temp64 = tcg_temp_new_i64(); 1647 switch (mode) { 1648 case MODE_LL: 1649 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1650 break; 1651 case MODE_LU: 1652 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1653 break; 1654 case MODE_UL: 1655 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1656 break; 1657 case MODE_UU: 1658 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1659 break; 1660 } 1661 gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high); 1662 } 1663 1664 static inline void 1665 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1666 { 1667 TCGv temp = tcg_temp_new(); 1668 TCGv temp2 = tcg_temp_new(); 1669 1670 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1671 tcg_gen_shli_tl(temp, r1, 16); 1672 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1673 } 1674 1675 static inline void 1676 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1677 uint32_t n, uint32_t mode) 1678 { 1679 TCGv t_n = tcg_constant_i32(n); 1680 TCGv_i64 temp64 = tcg_temp_new_i64(); 1681 switch (mode) { 1682 case MODE_LL: 1683 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1684 break; 1685 case MODE_LU: 1686 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1687 break; 1688 case MODE_UL: 1689 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1690 break; 1691 case MODE_UU: 1692 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1693 break; 1694 } 1695 gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); 1696 } 1697 1698 static inline void 1699 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1700 { 1701 TCGv temp = tcg_temp_new(); 1702 TCGv temp2 = tcg_temp_new(); 1703 1704 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1705 tcg_gen_shli_tl(temp, r1, 16); 1706 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1707 } 1708 1709 static inline void 1710 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1711 { 1712 TCGv temp = tcg_constant_i32(n); 1713 gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); 1714 } 1715 1716 static inline void 1717 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1718 { 1719 TCGv temp = tcg_constant_i32(n); 1720 gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); 1721 } 1722 1723 static inline void 1724 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1725 uint32_t up_shift) 1726 { 1727 TCGv temp3 = tcg_temp_new(); 1728 TCGv_i64 t1 = tcg_temp_new_i64(); 1729 TCGv_i64 t2 = tcg_temp_new_i64(); 1730 TCGv_i64 t3 = tcg_temp_new_i64(); 1731 TCGv_i64 t4 = tcg_temp_new_i64(); 1732 1733 tcg_gen_ext_i32_i64(t2, arg2); 1734 tcg_gen_ext_i32_i64(t3, arg3); 1735 1736 tcg_gen_mul_i64(t2, t2, t3); 1737 1738 tcg_gen_ext_i32_i64(t1, arg1); 1739 /* if we shift part of the fraction out, we need to round up */ 1740 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1741 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1742 tcg_gen_sari_i64(t2, t2, up_shift - n); 1743 tcg_gen_add_i64(t2, t2, t4); 1744 1745 tcg_gen_sub_i64(t3, t1, t2); 1746 tcg_gen_extrl_i64_i32(temp3, t3); 1747 /* calc v bit */ 1748 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1749 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1750 tcg_gen_or_i64(t1, t1, t2); 1751 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1752 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1753 /* Calc SV bit */ 1754 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1755 /* Calc AV/SAV bits */ 1756 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1757 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1758 /* calc SAV */ 1759 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1760 /* write back result */ 1761 tcg_gen_mov_tl(ret, temp3); 1762 } 1763 1764 static inline void 1765 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1766 { 1767 TCGv temp = tcg_temp_new(); 1768 TCGv temp2 = tcg_temp_new(); 1769 if (n == 0) { 1770 tcg_gen_mul_tl(temp, arg2, arg3); 1771 } else { /* n is expected to be 1 */ 1772 tcg_gen_mul_tl(temp, arg2, arg3); 1773 tcg_gen_shli_tl(temp, temp, 1); 1774 /* catch special case r1 = r2 = 0x8000 */ 1775 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1776 tcg_gen_sub_tl(temp, temp, temp2); 1777 } 1778 gen_sub_d(ret, arg1, temp); 1779 } 1780 1781 static inline void 1782 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1783 { 1784 TCGv temp = tcg_temp_new(); 1785 TCGv temp2 = tcg_temp_new(); 1786 if (n == 0) { 1787 tcg_gen_mul_tl(temp, arg2, arg3); 1788 } else { /* n is expected to be 1 */ 1789 tcg_gen_mul_tl(temp, arg2, arg3); 1790 tcg_gen_shli_tl(temp, temp, 1); 1791 /* catch special case r1 = r2 = 0x8000 */ 1792 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1793 tcg_gen_sub_tl(temp, temp, temp2); 1794 } 1795 gen_subs(ret, arg1, temp); 1796 } 1797 1798 static inline void 1799 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1800 TCGv arg3, uint32_t n) 1801 { 1802 TCGv temp = tcg_temp_new(); 1803 TCGv temp2 = tcg_temp_new(); 1804 TCGv_i64 t1 = tcg_temp_new_i64(); 1805 TCGv_i64 t2 = tcg_temp_new_i64(); 1806 TCGv_i64 t3 = tcg_temp_new_i64(); 1807 1808 if (n == 0) { 1809 tcg_gen_mul_tl(temp, arg2, arg3); 1810 } else { /* n is expected to be 1 */ 1811 tcg_gen_mul_tl(temp, arg2, arg3); 1812 tcg_gen_shli_tl(temp, temp, 1); 1813 /* catch special case r1 = r2 = 0x8000 */ 1814 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1815 tcg_gen_sub_tl(temp, temp, temp2); 1816 } 1817 tcg_gen_ext_i32_i64(t2, temp); 1818 tcg_gen_shli_i64(t2, t2, 16); 1819 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1820 gen_sub64_d(t3, t1, t2); 1821 /* write back result */ 1822 tcg_gen_extr_i64_i32(rl, rh, t3); 1823 } 1824 1825 static inline void 1826 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1827 TCGv arg3, uint32_t n) 1828 { 1829 TCGv temp = tcg_temp_new(); 1830 TCGv temp2 = tcg_temp_new(); 1831 TCGv_i64 t1 = tcg_temp_new_i64(); 1832 TCGv_i64 t2 = tcg_temp_new_i64(); 1833 1834 if (n == 0) { 1835 tcg_gen_mul_tl(temp, arg2, arg3); 1836 } else { /* n is expected to be 1 */ 1837 tcg_gen_mul_tl(temp, arg2, arg3); 1838 tcg_gen_shli_tl(temp, temp, 1); 1839 /* catch special case r1 = r2 = 0x8000 */ 1840 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1841 tcg_gen_sub_tl(temp, temp, temp2); 1842 } 1843 tcg_gen_ext_i32_i64(t2, temp); 1844 tcg_gen_shli_i64(t2, t2, 16); 1845 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1846 1847 gen_helper_sub64_ssov(t1, tcg_env, t1, t2); 1848 tcg_gen_extr_i64_i32(rl, rh, t1); 1849 } 1850 1851 static inline void 1852 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1853 TCGv arg3, uint32_t n) 1854 { 1855 TCGv_i64 t1 = tcg_temp_new_i64(); 1856 TCGv_i64 t2 = tcg_temp_new_i64(); 1857 TCGv_i64 t3 = tcg_temp_new_i64(); 1858 TCGv_i64 t4 = tcg_temp_new_i64(); 1859 TCGv temp, temp2; 1860 1861 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1862 tcg_gen_ext_i32_i64(t2, arg2); 1863 tcg_gen_ext_i32_i64(t3, arg3); 1864 1865 tcg_gen_mul_i64(t2, t2, t3); 1866 if (n != 0) { 1867 tcg_gen_shli_i64(t2, t2, 1); 1868 } 1869 tcg_gen_sub_i64(t4, t1, t2); 1870 /* calc v bit */ 1871 tcg_gen_xor_i64(t3, t4, t1); 1872 tcg_gen_xor_i64(t2, t1, t2); 1873 tcg_gen_and_i64(t3, t3, t2); 1874 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1875 /* We produce an overflow on the host if the mul before was 1876 (0x80000000 * 0x80000000) << 1). If this is the 1877 case, we negate the ovf. */ 1878 if (n == 1) { 1879 temp = tcg_temp_new(); 1880 temp2 = tcg_temp_new(); 1881 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1882 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1883 tcg_gen_and_tl(temp, temp, temp2); 1884 tcg_gen_shli_tl(temp, temp, 31); 1885 /* negate v bit, if special condition */ 1886 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1887 } 1888 /* write back result */ 1889 tcg_gen_extr_i64_i32(rl, rh, t4); 1890 /* Calc SV bit */ 1891 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1892 /* Calc AV/SAV bits */ 1893 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1894 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1895 /* calc SAV */ 1896 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1897 } 1898 1899 static inline void 1900 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1901 uint32_t up_shift) 1902 { 1903 TCGv_i64 t1 = tcg_temp_new_i64(); 1904 TCGv_i64 t2 = tcg_temp_new_i64(); 1905 TCGv_i64 t3 = tcg_temp_new_i64(); 1906 TCGv_i64 t4 = tcg_temp_new_i64(); 1907 1908 tcg_gen_ext_i32_i64(t1, arg1); 1909 tcg_gen_ext_i32_i64(t2, arg2); 1910 tcg_gen_ext_i32_i64(t3, arg3); 1911 1912 tcg_gen_mul_i64(t2, t2, t3); 1913 /* if we shift part of the fraction out, we need to round up */ 1914 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1915 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1916 tcg_gen_sari_i64(t3, t2, up_shift - n); 1917 tcg_gen_add_i64(t3, t3, t4); 1918 1919 gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3); 1920 } 1921 1922 static inline void 1923 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1924 TCGv arg3, uint32_t n) 1925 { 1926 TCGv_i64 r1 = tcg_temp_new_i64(); 1927 TCGv t_n = tcg_constant_i32(n); 1928 1929 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1930 gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); 1931 tcg_gen_extr_i64_i32(rl, rh, r1); 1932 } 1933 1934 static inline void 1935 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1936 TCGv r3, uint32_t n, uint32_t mode) 1937 { 1938 TCGv t_n = tcg_constant_i32(n); 1939 TCGv temp = tcg_temp_new(); 1940 TCGv temp2 = tcg_temp_new(); 1941 TCGv_i64 temp64 = tcg_temp_new_i64(); 1942 switch (mode) { 1943 case MODE_LL: 1944 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1945 break; 1946 case MODE_LU: 1947 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1948 break; 1949 case MODE_UL: 1950 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1951 break; 1952 case MODE_UU: 1953 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1954 break; 1955 } 1956 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1957 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1958 tcg_gen_add_tl, tcg_gen_sub_tl); 1959 } 1960 1961 static inline void 1962 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1963 TCGv r3, uint32_t n, uint32_t mode) 1964 { 1965 TCGv t_n = tcg_constant_i32(n); 1966 TCGv_i64 temp64 = tcg_temp_new_i64(); 1967 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1968 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1969 switch (mode) { 1970 case MODE_LL: 1971 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1972 break; 1973 case MODE_LU: 1974 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1975 break; 1976 case MODE_UL: 1977 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1978 break; 1979 case MODE_UU: 1980 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1981 break; 1982 } 1983 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1984 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1985 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1986 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1987 tcg_gen_shli_i64(temp64, temp64, 16); 1988 1989 gen_sub64_d(temp64_2, temp64_3, temp64); 1990 /* write back result */ 1991 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1992 } 1993 1994 static inline void 1995 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1996 { 1997 TCGv t_n = tcg_constant_i32(n); 1998 TCGv temp = tcg_temp_new(); 1999 TCGv temp2 = tcg_temp_new(); 2000 TCGv_i64 temp64 = tcg_temp_new_i64(); 2001 switch (mode) { 2002 case MODE_LL: 2003 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2004 break; 2005 case MODE_LU: 2006 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2007 break; 2008 case MODE_UL: 2009 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2010 break; 2011 case MODE_UU: 2012 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2013 break; 2014 } 2015 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2016 tcg_gen_shli_tl(temp, r1, 16); 2017 gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2); 2018 } 2019 2020 static inline void 2021 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2022 TCGv r3, uint32_t n, uint32_t mode) 2023 { 2024 TCGv t_n = tcg_constant_i32(n); 2025 TCGv temp = tcg_temp_new(); 2026 TCGv temp2 = tcg_temp_new(); 2027 TCGv temp3 = tcg_temp_new(); 2028 TCGv_i64 temp64 = tcg_temp_new_i64(); 2029 2030 switch (mode) { 2031 case MODE_LL: 2032 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2033 break; 2034 case MODE_LU: 2035 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2036 break; 2037 case MODE_UL: 2038 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2039 break; 2040 case MODE_UU: 2041 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2042 break; 2043 } 2044 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2045 gen_adds(ret_low, r1_low, temp); 2046 tcg_gen_mov_tl(temp, cpu_PSW_V); 2047 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2048 gen_subs(ret_high, r1_high, temp2); 2049 /* combine v bits */ 2050 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2051 /* combine av bits */ 2052 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2053 } 2054 2055 static inline void 2056 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2057 TCGv r3, uint32_t n, uint32_t mode) 2058 { 2059 TCGv t_n = tcg_constant_i32(n); 2060 TCGv_i64 temp64 = tcg_temp_new_i64(); 2061 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2062 2063 switch (mode) { 2064 case MODE_LL: 2065 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2066 break; 2067 case MODE_LU: 2068 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2069 break; 2070 case MODE_UL: 2071 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2072 break; 2073 case MODE_UU: 2074 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2075 break; 2076 } 2077 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2078 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2079 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2080 tcg_gen_shli_i64(temp64, temp64, 16); 2081 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2082 2083 gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); 2084 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2085 } 2086 2087 static inline void 2088 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2089 { 2090 TCGv t_n = tcg_constant_i32(n); 2091 TCGv temp = tcg_temp_new(); 2092 TCGv temp2 = tcg_temp_new(); 2093 TCGv_i64 temp64 = tcg_temp_new_i64(); 2094 switch (mode) { 2095 case MODE_LL: 2096 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2097 break; 2098 case MODE_LU: 2099 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2100 break; 2101 case MODE_UL: 2102 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2103 break; 2104 case MODE_UU: 2105 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2106 break; 2107 } 2108 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2109 tcg_gen_shli_tl(temp, r1, 16); 2110 gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2); 2111 } 2112 2113 static inline void gen_abs(TCGv ret, TCGv r1) 2114 { 2115 tcg_gen_abs_tl(ret, r1); 2116 /* overflow can only happen, if r1 = 0x80000000 */ 2117 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2118 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2119 /* calc SV bit */ 2120 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2121 /* Calc AV bit */ 2122 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2123 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2124 /* calc SAV bit */ 2125 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2126 } 2127 2128 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2129 { 2130 TCGv temp = tcg_temp_new_i32(); 2131 TCGv result = tcg_temp_new_i32(); 2132 2133 tcg_gen_sub_tl(result, r1, r2); 2134 tcg_gen_sub_tl(temp, r2, r1); 2135 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2136 2137 /* calc V bit */ 2138 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2139 tcg_gen_xor_tl(temp, result, r2); 2140 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2141 tcg_gen_xor_tl(temp, r1, r2); 2142 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2143 /* calc SV bit */ 2144 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2145 /* Calc AV bit */ 2146 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2147 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2148 /* calc SAV bit */ 2149 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2150 /* write back result */ 2151 tcg_gen_mov_tl(ret, result); 2152 } 2153 2154 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2155 { 2156 TCGv temp = tcg_constant_i32(con); 2157 gen_absdif(ret, r1, temp); 2158 } 2159 2160 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2161 { 2162 TCGv temp = tcg_constant_i32(con); 2163 gen_helper_absdif_ssov(ret, tcg_env, r1, temp); 2164 } 2165 2166 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2167 { 2168 TCGv high = tcg_temp_new(); 2169 TCGv low = tcg_temp_new(); 2170 2171 tcg_gen_muls2_tl(low, high, r1, r2); 2172 tcg_gen_mov_tl(ret, low); 2173 /* calc V bit */ 2174 tcg_gen_sari_tl(low, low, 31); 2175 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2176 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2177 /* calc SV bit */ 2178 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2179 /* Calc AV bit */ 2180 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2181 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2182 /* calc SAV bit */ 2183 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2184 } 2185 2186 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2187 { 2188 TCGv temp = tcg_constant_i32(con); 2189 gen_mul_i32s(ret, r1, temp); 2190 } 2191 2192 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2193 { 2194 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2195 /* clear V bit */ 2196 tcg_gen_movi_tl(cpu_PSW_V, 0); 2197 /* calc SV bit */ 2198 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2199 /* Calc AV bit */ 2200 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2201 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2202 /* calc SAV bit */ 2203 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2204 } 2205 2206 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2207 int32_t con) 2208 { 2209 TCGv temp = tcg_constant_i32(con); 2210 gen_mul_i64s(ret_low, ret_high, r1, temp); 2211 } 2212 2213 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2214 { 2215 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2216 /* clear V bit */ 2217 tcg_gen_movi_tl(cpu_PSW_V, 0); 2218 /* calc SV bit */ 2219 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2220 /* Calc AV bit */ 2221 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2222 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2223 /* calc SAV bit */ 2224 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2225 } 2226 2227 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2228 int32_t con) 2229 { 2230 TCGv temp = tcg_constant_i32(con); 2231 gen_mul_i64u(ret_low, ret_high, r1, temp); 2232 } 2233 2234 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2235 { 2236 TCGv temp = tcg_constant_i32(con); 2237 gen_helper_mul_ssov(ret, tcg_env, r1, temp); 2238 } 2239 2240 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2241 { 2242 TCGv temp = tcg_constant_i32(con); 2243 gen_helper_mul_suov(ret, tcg_env, r1, temp); 2244 } 2245 2246 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2247 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2248 { 2249 TCGv temp = tcg_constant_i32(con); 2250 gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); 2251 } 2252 2253 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2254 { 2255 TCGv temp = tcg_constant_i32(con); 2256 gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); 2257 } 2258 2259 static void 2260 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2261 { 2262 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2263 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2264 2265 if (n == 0) { 2266 if (up_shift == 32) { 2267 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2268 } else if (up_shift == 16) { 2269 tcg_gen_ext_i32_i64(temp_64, arg1); 2270 tcg_gen_ext_i32_i64(temp2_64, arg2); 2271 2272 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2273 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2274 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2275 } else { 2276 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2277 } 2278 /* reset v bit */ 2279 tcg_gen_movi_tl(cpu_PSW_V, 0); 2280 } else { /* n is expected to be 1 */ 2281 tcg_gen_ext_i32_i64(temp_64, arg1); 2282 tcg_gen_ext_i32_i64(temp2_64, arg2); 2283 2284 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2285 2286 if (up_shift == 0) { 2287 tcg_gen_shli_i64(temp_64, temp_64, 1); 2288 } else { 2289 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2290 } 2291 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2292 /* overflow only occurs if r1 = r2 = 0x8000 */ 2293 if (up_shift == 0) {/* result is 64 bit */ 2294 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2295 0x80000000); 2296 } else { /* result is 32 bit */ 2297 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2298 0x80000000); 2299 } 2300 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2301 /* calc sv overflow bit */ 2302 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2303 } 2304 /* calc av overflow bit */ 2305 if (up_shift == 0) { 2306 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2307 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2308 } else { 2309 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2310 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2311 } 2312 /* calc sav overflow bit */ 2313 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2314 } 2315 2316 static void 2317 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2318 { 2319 TCGv temp = tcg_temp_new(); 2320 if (n == 0) { 2321 tcg_gen_mul_tl(ret, arg1, arg2); 2322 } else { /* n is expected to be 1 */ 2323 tcg_gen_mul_tl(ret, arg1, arg2); 2324 tcg_gen_shli_tl(ret, ret, 1); 2325 /* catch special case r1 = r2 = 0x8000 */ 2326 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2327 tcg_gen_sub_tl(ret, ret, temp); 2328 } 2329 /* reset v bit */ 2330 tcg_gen_movi_tl(cpu_PSW_V, 0); 2331 /* calc av overflow bit */ 2332 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2333 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2334 /* calc sav overflow bit */ 2335 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2336 } 2337 2338 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2339 { 2340 TCGv temp = tcg_temp_new(); 2341 if (n == 0) { 2342 tcg_gen_mul_tl(ret, arg1, arg2); 2343 tcg_gen_addi_tl(ret, ret, 0x8000); 2344 } else { 2345 tcg_gen_mul_tl(ret, arg1, arg2); 2346 tcg_gen_shli_tl(ret, ret, 1); 2347 tcg_gen_addi_tl(ret, ret, 0x8000); 2348 /* catch special case r1 = r2 = 0x8000 */ 2349 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2350 tcg_gen_muli_tl(temp, temp, 0x8001); 2351 tcg_gen_sub_tl(ret, ret, temp); 2352 } 2353 /* reset v bit */ 2354 tcg_gen_movi_tl(cpu_PSW_V, 0); 2355 /* calc av overflow bit */ 2356 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2357 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2358 /* calc sav overflow bit */ 2359 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2360 /* cut halfword off */ 2361 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2362 } 2363 2364 static inline void 2365 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2366 TCGv r3) 2367 { 2368 TCGv_i64 temp64 = tcg_temp_new_i64(); 2369 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2370 gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); 2371 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2372 } 2373 2374 static inline void 2375 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2376 int32_t con) 2377 { 2378 TCGv temp = tcg_constant_i32(con); 2379 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2380 } 2381 2382 static inline void 2383 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2384 TCGv r3) 2385 { 2386 TCGv_i64 temp64 = tcg_temp_new_i64(); 2387 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2388 gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); 2389 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2390 } 2391 2392 static inline void 2393 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2394 int32_t con) 2395 { 2396 TCGv temp = tcg_constant_i32(con); 2397 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2398 } 2399 2400 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2401 { 2402 TCGv temp = tcg_constant_i32(con); 2403 gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); 2404 } 2405 2406 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2407 { 2408 TCGv temp = tcg_constant_i32(con); 2409 gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); 2410 } 2411 2412 static inline void 2413 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2414 TCGv r3) 2415 { 2416 TCGv_i64 temp64 = tcg_temp_new_i64(); 2417 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2418 gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); 2419 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2420 } 2421 2422 static inline void 2423 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2424 int32_t con) 2425 { 2426 TCGv temp = tcg_constant_i32(con); 2427 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2428 } 2429 2430 static inline void 2431 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2432 TCGv r3) 2433 { 2434 TCGv_i64 temp64 = tcg_temp_new_i64(); 2435 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2436 gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); 2437 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2438 } 2439 2440 static inline void 2441 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2442 int32_t con) 2443 { 2444 TCGv temp = tcg_constant_i32(con); 2445 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2446 } 2447 2448 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2449 { 2450 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); 2451 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); 2452 } 2453 2454 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2455 { 2456 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); 2457 } 2458 2459 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2460 { 2461 if (shift_count == -32) { 2462 tcg_gen_movi_tl(ret, 0); 2463 } else if (shift_count >= 0) { 2464 tcg_gen_shli_tl(ret, r1, shift_count); 2465 } else { 2466 tcg_gen_shri_tl(ret, r1, -shift_count); 2467 } 2468 } 2469 2470 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2471 { 2472 TCGv temp_low, temp_high; 2473 2474 if (shiftcount == -16) { 2475 tcg_gen_movi_tl(ret, 0); 2476 } else { 2477 temp_high = tcg_temp_new(); 2478 temp_low = tcg_temp_new(); 2479 2480 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2481 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2482 gen_shi(temp_low, temp_low, shiftcount); 2483 gen_shi(ret, temp_high, shiftcount); 2484 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2485 } 2486 } 2487 2488 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2489 { 2490 uint32_t msk, msk_start; 2491 TCGv temp = tcg_temp_new(); 2492 TCGv temp2 = tcg_temp_new(); 2493 2494 if (shift_count == 0) { 2495 /* Clear PSW.C and PSW.V */ 2496 tcg_gen_movi_tl(cpu_PSW_C, 0); 2497 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2498 tcg_gen_mov_tl(ret, r1); 2499 } else if (shift_count == -32) { 2500 /* set PSW.C */ 2501 tcg_gen_mov_tl(cpu_PSW_C, r1); 2502 /* fill ret completely with sign bit */ 2503 tcg_gen_sari_tl(ret, r1, 31); 2504 /* clear PSW.V */ 2505 tcg_gen_movi_tl(cpu_PSW_V, 0); 2506 } else if (shift_count > 0) { 2507 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2508 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2509 2510 /* calc carry */ 2511 msk_start = 32 - shift_count; 2512 msk = ((1 << shift_count) - 1) << msk_start; 2513 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2514 /* calc v/sv bits */ 2515 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2516 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2517 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2518 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2519 /* calc sv */ 2520 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2521 /* do shift */ 2522 tcg_gen_shli_tl(ret, r1, shift_count); 2523 } else { 2524 /* clear PSW.V */ 2525 tcg_gen_movi_tl(cpu_PSW_V, 0); 2526 /* calc carry */ 2527 msk = (1 << -shift_count) - 1; 2528 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2529 /* do shift */ 2530 tcg_gen_sari_tl(ret, r1, -shift_count); 2531 } 2532 /* calc av overflow bit */ 2533 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2534 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2535 /* calc sav overflow bit */ 2536 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2537 } 2538 2539 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2540 { 2541 gen_helper_sha_ssov(ret, tcg_env, r1, r2); 2542 } 2543 2544 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2545 { 2546 TCGv temp = tcg_constant_i32(con); 2547 gen_shas(ret, r1, temp); 2548 } 2549 2550 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2551 { 2552 TCGv low, high; 2553 2554 if (shift_count == 0) { 2555 tcg_gen_mov_tl(ret, r1); 2556 } else if (shift_count > 0) { 2557 low = tcg_temp_new(); 2558 high = tcg_temp_new(); 2559 2560 tcg_gen_andi_tl(high, r1, 0xffff0000); 2561 tcg_gen_shli_tl(low, r1, shift_count); 2562 tcg_gen_shli_tl(ret, high, shift_count); 2563 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2564 } else { 2565 low = tcg_temp_new(); 2566 high = tcg_temp_new(); 2567 2568 tcg_gen_ext16s_tl(low, r1); 2569 tcg_gen_sari_tl(low, low, -shift_count); 2570 tcg_gen_sari_tl(ret, r1, -shift_count); 2571 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2572 } 2573 } 2574 2575 /* ret = {ret[30:0], (r1 cond r2)}; */ 2576 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2577 { 2578 TCGv temp = tcg_temp_new(); 2579 TCGv temp2 = tcg_temp_new(); 2580 2581 tcg_gen_shli_tl(temp, ret, 1); 2582 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2583 tcg_gen_or_tl(ret, temp, temp2); 2584 } 2585 2586 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2587 { 2588 TCGv temp = tcg_constant_i32(con); 2589 gen_sh_cond(cond, ret, r1, temp); 2590 } 2591 2592 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2593 { 2594 gen_helper_add_ssov(ret, tcg_env, r1, r2); 2595 } 2596 2597 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2598 { 2599 TCGv temp = tcg_constant_i32(con); 2600 gen_helper_add_ssov(ret, tcg_env, r1, temp); 2601 } 2602 2603 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2604 { 2605 TCGv temp = tcg_constant_i32(con); 2606 gen_helper_add_suov(ret, tcg_env, r1, temp); 2607 } 2608 2609 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2610 { 2611 gen_helper_sub_ssov(ret, tcg_env, r1, r2); 2612 } 2613 2614 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2615 { 2616 gen_helper_sub_suov(ret, tcg_env, r1, r2); 2617 } 2618 2619 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2620 int pos1, int pos2, 2621 void(*op1)(TCGv, TCGv, TCGv), 2622 void(*op2)(TCGv, TCGv, TCGv)) 2623 { 2624 TCGv temp1, temp2; 2625 2626 temp1 = tcg_temp_new(); 2627 temp2 = tcg_temp_new(); 2628 2629 tcg_gen_shri_tl(temp2, r2, pos2); 2630 tcg_gen_shri_tl(temp1, r1, pos1); 2631 2632 (*op1)(temp1, temp1, temp2); 2633 (*op2)(temp1 , ret, temp1); 2634 2635 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2636 } 2637 2638 /* ret = r1[pos1] op1 r2[pos2]; */ 2639 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2640 int pos1, int pos2, 2641 void(*op1)(TCGv, TCGv, TCGv)) 2642 { 2643 TCGv temp1, temp2; 2644 2645 temp1 = tcg_temp_new(); 2646 temp2 = tcg_temp_new(); 2647 2648 tcg_gen_shri_tl(temp2, r2, pos2); 2649 tcg_gen_shri_tl(temp1, r1, pos1); 2650 2651 (*op1)(ret, temp1, temp2); 2652 2653 tcg_gen_andi_tl(ret, ret, 0x1); 2654 } 2655 2656 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2657 void(*op)(TCGv, TCGv, TCGv)) 2658 { 2659 TCGv temp = tcg_temp_new(); 2660 TCGv temp2 = tcg_temp_new(); 2661 /* temp = (arg1 cond arg2 )*/ 2662 tcg_gen_setcond_tl(cond, temp, r1, r2); 2663 /* temp2 = ret[0]*/ 2664 tcg_gen_andi_tl(temp2, ret, 0x1); 2665 /* temp = temp insn temp2 */ 2666 (*op)(temp, temp, temp2); 2667 /* ret = {ret[31:1], temp} */ 2668 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2669 } 2670 2671 static inline void 2672 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2673 void(*op)(TCGv, TCGv, TCGv)) 2674 { 2675 TCGv temp = tcg_constant_i32(con); 2676 gen_accumulating_cond(cond, ret, r1, temp, op); 2677 } 2678 2679 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2680 { 2681 TCGv b0 = tcg_temp_new(); 2682 TCGv b1 = tcg_temp_new(); 2683 TCGv b2 = tcg_temp_new(); 2684 TCGv b3 = tcg_temp_new(); 2685 2686 /* byte 0 */ 2687 tcg_gen_andi_tl(b0, r1, 0xff); 2688 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2689 2690 /* byte 1 */ 2691 tcg_gen_andi_tl(b1, r1, 0xff00); 2692 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2693 2694 /* byte 2 */ 2695 tcg_gen_andi_tl(b2, r1, 0xff0000); 2696 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2697 2698 /* byte 3 */ 2699 tcg_gen_andi_tl(b3, r1, 0xff000000); 2700 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2701 2702 /* combine them */ 2703 tcg_gen_or_tl(ret, b0, b1); 2704 tcg_gen_or_tl(ret, ret, b2); 2705 tcg_gen_or_tl(ret, ret, b3); 2706 } 2707 2708 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2709 { 2710 TCGv h0 = tcg_temp_new(); 2711 TCGv h1 = tcg_temp_new(); 2712 2713 /* halfword 0 */ 2714 tcg_gen_andi_tl(h0, r1, 0xffff); 2715 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2716 2717 /* halfword 1 */ 2718 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2719 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2720 2721 /* combine them */ 2722 tcg_gen_or_tl(ret, h0, h1); 2723 } 2724 2725 /* mask = ((1 << width) -1) << pos; 2726 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2727 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2728 { 2729 TCGv mask = tcg_temp_new(); 2730 TCGv temp = tcg_temp_new(); 2731 TCGv temp2 = tcg_temp_new(); 2732 2733 tcg_gen_shl_tl(mask, tcg_constant_tl(1), width); 2734 tcg_gen_subi_tl(mask, mask, 1); 2735 tcg_gen_shl_tl(mask, mask, pos); 2736 2737 tcg_gen_shl_tl(temp, r2, pos); 2738 tcg_gen_and_tl(temp, temp, mask); 2739 tcg_gen_andc_tl(temp2, r1, mask); 2740 tcg_gen_or_tl(ret, temp, temp2); 2741 } 2742 2743 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2744 { 2745 TCGv_i64 temp = tcg_temp_new_i64(); 2746 2747 gen_helper_bsplit(temp, r1); 2748 tcg_gen_extr_i64_i32(rl, rh, temp); 2749 } 2750 2751 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2752 { 2753 TCGv_i64 temp = tcg_temp_new_i64(); 2754 2755 gen_helper_unpack(temp, r1); 2756 tcg_gen_extr_i64_i32(rl, rh, temp); 2757 } 2758 2759 static inline void 2760 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2761 { 2762 TCGv_i64 ret = tcg_temp_new_i64(); 2763 2764 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2765 gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); 2766 } else { 2767 gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); 2768 } 2769 tcg_gen_extr_i64_i32(rl, rh, ret); 2770 } 2771 2772 static inline void 2773 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2774 { 2775 TCGv_i64 ret = tcg_temp_new_i64(); 2776 2777 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2778 gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); 2779 } else { 2780 gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); 2781 } 2782 tcg_gen_extr_i64_i32(rl, rh, ret); 2783 } 2784 2785 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2786 { 2787 TCGv temp = tcg_temp_new(); 2788 /* calc AV bit */ 2789 tcg_gen_add_tl(temp, arg_low, arg_low); 2790 tcg_gen_xor_tl(temp, temp, arg_low); 2791 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2792 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2793 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2794 /* calc SAV bit */ 2795 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2796 tcg_gen_movi_tl(cpu_PSW_V, 0); 2797 } 2798 2799 static void gen_calc_usb_mulr_h(TCGv arg) 2800 { 2801 TCGv temp = tcg_temp_new(); 2802 /* calc AV bit */ 2803 tcg_gen_add_tl(temp, arg, arg); 2804 tcg_gen_xor_tl(temp, temp, arg); 2805 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2806 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2807 /* calc SAV bit */ 2808 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2809 /* clear V bit */ 2810 tcg_gen_movi_tl(cpu_PSW_V, 0); 2811 } 2812 2813 /* helpers for generating program flow micro-ops */ 2814 2815 static inline void gen_save_pc(target_ulong pc) 2816 { 2817 tcg_gen_movi_tl(cpu_PC, pc); 2818 } 2819 2820 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2821 { 2822 if (translator_use_goto_tb(&ctx->base, dest)) { 2823 tcg_gen_goto_tb(n); 2824 gen_save_pc(dest); 2825 tcg_gen_exit_tb(ctx->base.tb, n); 2826 } else { 2827 gen_save_pc(dest); 2828 tcg_gen_lookup_and_goto_ptr(); 2829 } 2830 ctx->base.is_jmp = DISAS_NORETURN; 2831 } 2832 2833 static void generate_trap(DisasContext *ctx, int class, int tin) 2834 { 2835 TCGv_i32 classtemp = tcg_constant_i32(class); 2836 TCGv_i32 tintemp = tcg_constant_i32(tin); 2837 2838 gen_save_pc(ctx->base.pc_next); 2839 gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp); 2840 ctx->base.is_jmp = DISAS_NORETURN; 2841 } 2842 2843 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2844 TCGv r2, int16_t address) 2845 { 2846 TCGLabel *jumpLabel = gen_new_label(); 2847 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2848 2849 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2850 2851 gen_set_label(jumpLabel); 2852 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2853 } 2854 2855 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2856 int r2, int16_t address) 2857 { 2858 TCGv temp = tcg_constant_i32(r2); 2859 gen_branch_cond(ctx, cond, r1, temp, address); 2860 } 2861 2862 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2863 { 2864 TCGLabel *l1 = gen_new_label(); 2865 2866 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2867 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2868 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2869 gen_set_label(l1); 2870 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2871 } 2872 2873 static void gen_fcall_save_ctx(DisasContext *ctx) 2874 { 2875 TCGv temp = tcg_temp_new(); 2876 2877 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2878 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2879 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2880 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2881 } 2882 2883 static void gen_fret(DisasContext *ctx) 2884 { 2885 TCGv temp = tcg_temp_new(); 2886 2887 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2888 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2889 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2890 tcg_gen_mov_tl(cpu_PC, temp); 2891 ctx->base.is_jmp = DISAS_EXIT; 2892 } 2893 2894 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2895 int r2 , int32_t constant , int32_t offset) 2896 { 2897 TCGv temp, temp2; 2898 int n; 2899 2900 switch (opc) { 2901 /* SB-format jumps */ 2902 case OPC1_16_SB_J: 2903 case OPC1_32_B_J: 2904 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2905 break; 2906 case OPC1_32_B_CALL: 2907 case OPC1_16_SB_CALL: 2908 gen_helper_1arg(call, ctx->pc_succ_insn); 2909 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2910 break; 2911 case OPC1_16_SB_JZ: 2912 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2913 break; 2914 case OPC1_16_SB_JNZ: 2915 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2916 break; 2917 /* SBC-format jumps */ 2918 case OPC1_16_SBC_JEQ: 2919 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2920 break; 2921 case OPC1_16_SBC_JEQ2: 2922 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2923 offset + 16); 2924 break; 2925 case OPC1_16_SBC_JNE: 2926 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2927 break; 2928 case OPC1_16_SBC_JNE2: 2929 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2930 constant, offset + 16); 2931 break; 2932 /* SBRN-format jumps */ 2933 case OPC1_16_SBRN_JZ_T: 2934 temp = tcg_temp_new(); 2935 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2936 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2937 break; 2938 case OPC1_16_SBRN_JNZ_T: 2939 temp = tcg_temp_new(); 2940 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2941 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2942 break; 2943 /* SBR-format jumps */ 2944 case OPC1_16_SBR_JEQ: 2945 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2946 offset); 2947 break; 2948 case OPC1_16_SBR_JEQ2: 2949 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2950 offset + 16); 2951 break; 2952 case OPC1_16_SBR_JNE: 2953 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2954 offset); 2955 break; 2956 case OPC1_16_SBR_JNE2: 2957 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2958 offset + 16); 2959 break; 2960 case OPC1_16_SBR_JNZ: 2961 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2962 break; 2963 case OPC1_16_SBR_JNZ_A: 2964 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2965 break; 2966 case OPC1_16_SBR_JGEZ: 2967 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2968 break; 2969 case OPC1_16_SBR_JGTZ: 2970 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2971 break; 2972 case OPC1_16_SBR_JLEZ: 2973 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2974 break; 2975 case OPC1_16_SBR_JLTZ: 2976 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2977 break; 2978 case OPC1_16_SBR_JZ: 2979 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2980 break; 2981 case OPC1_16_SBR_JZ_A: 2982 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2983 break; 2984 case OPC1_16_SBR_LOOP: 2985 gen_loop(ctx, r1, offset * 2 - 32); 2986 break; 2987 /* SR-format jumps */ 2988 case OPC1_16_SR_JI: 2989 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 2990 ctx->base.is_jmp = DISAS_EXIT; 2991 break; 2992 case OPC2_32_SYS_RET: 2993 case OPC2_16_SR_RET: 2994 gen_helper_ret(tcg_env); 2995 ctx->base.is_jmp = DISAS_EXIT; 2996 break; 2997 /* B-format */ 2998 case OPC1_32_B_CALLA: 2999 gen_helper_1arg(call, ctx->pc_succ_insn); 3000 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3001 break; 3002 case OPC1_32_B_FCALL: 3003 gen_fcall_save_ctx(ctx); 3004 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3005 break; 3006 case OPC1_32_B_FCALLA: 3007 gen_fcall_save_ctx(ctx); 3008 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3009 break; 3010 case OPC1_32_B_JLA: 3011 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3012 /* fall through */ 3013 case OPC1_32_B_JA: 3014 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3015 break; 3016 case OPC1_32_B_JL: 3017 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3018 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3019 break; 3020 /* BOL format */ 3021 case OPCM_32_BRC_EQ_NEQ: 3022 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3023 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3024 } else { 3025 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3026 } 3027 break; 3028 case OPCM_32_BRC_GE: 3029 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3030 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3031 } else { 3032 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3033 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3034 offset); 3035 } 3036 break; 3037 case OPCM_32_BRC_JLT: 3038 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3039 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3040 } else { 3041 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3042 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3043 offset); 3044 } 3045 break; 3046 case OPCM_32_BRC_JNE: 3047 temp = tcg_temp_new(); 3048 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3049 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3050 /* subi is unconditional */ 3051 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3052 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3053 } else { 3054 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3055 /* addi is unconditional */ 3056 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3057 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3058 } 3059 break; 3060 /* BRN format */ 3061 case OPCM_32_BRN_JTT: 3062 n = MASK_OP_BRN_N(ctx->opcode); 3063 3064 temp = tcg_temp_new(); 3065 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3066 3067 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3068 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3069 } else { 3070 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3071 } 3072 break; 3073 /* BRR Format */ 3074 case OPCM_32_BRR_EQ_NEQ: 3075 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3076 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3077 offset); 3078 } else { 3079 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3080 offset); 3081 } 3082 break; 3083 case OPCM_32_BRR_ADDR_EQ_NEQ: 3084 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3085 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3086 offset); 3087 } else { 3088 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3089 offset); 3090 } 3091 break; 3092 case OPCM_32_BRR_GE: 3093 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3094 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3095 offset); 3096 } else { 3097 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3098 offset); 3099 } 3100 break; 3101 case OPCM_32_BRR_JLT: 3102 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3103 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3104 offset); 3105 } else { 3106 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3107 offset); 3108 } 3109 break; 3110 case OPCM_32_BRR_LOOP: 3111 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3112 gen_loop(ctx, r2, offset * 2); 3113 } else { 3114 /* OPC2_32_BRR_LOOPU */ 3115 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3116 } 3117 break; 3118 case OPCM_32_BRR_JNE: 3119 temp = tcg_temp_new(); 3120 temp2 = tcg_temp_new(); 3121 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3122 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3123 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3124 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3125 /* subi is unconditional */ 3126 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3127 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3128 } else { 3129 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3130 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3131 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3132 /* addi is unconditional */ 3133 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3134 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3135 } 3136 break; 3137 case OPCM_32_BRR_JNZ: 3138 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3139 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3140 } else { 3141 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3142 } 3143 break; 3144 default: 3145 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3146 } 3147 } 3148 3149 3150 /* 3151 * Functions for decoding instructions 3152 */ 3153 3154 static void decode_src_opc(DisasContext *ctx, int op1) 3155 { 3156 int r1; 3157 int32_t const4; 3158 TCGv temp, temp2; 3159 3160 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3161 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3162 3163 switch (op1) { 3164 case OPC1_16_SRC_ADD: 3165 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3166 break; 3167 case OPC1_16_SRC_ADD_A15: 3168 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3169 break; 3170 case OPC1_16_SRC_ADD_15A: 3171 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3172 break; 3173 case OPC1_16_SRC_ADD_A: 3174 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3175 break; 3176 case OPC1_16_SRC_CADD: 3177 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3178 cpu_gpr_d[15]); 3179 break; 3180 case OPC1_16_SRC_CADDN: 3181 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3182 cpu_gpr_d[15]); 3183 break; 3184 case OPC1_16_SRC_CMOV: 3185 temp = tcg_constant_tl(0); 3186 temp2 = tcg_constant_tl(const4); 3187 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3188 temp2, cpu_gpr_d[r1]); 3189 break; 3190 case OPC1_16_SRC_CMOVN: 3191 temp = tcg_constant_tl(0); 3192 temp2 = tcg_constant_tl(const4); 3193 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3194 temp2, cpu_gpr_d[r1]); 3195 break; 3196 case OPC1_16_SRC_EQ: 3197 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3198 const4); 3199 break; 3200 case OPC1_16_SRC_LT: 3201 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3202 const4); 3203 break; 3204 case OPC1_16_SRC_MOV: 3205 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3206 break; 3207 case OPC1_16_SRC_MOV_A: 3208 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3209 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3210 break; 3211 case OPC1_16_SRC_MOV_E: 3212 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3213 CHECK_REG_PAIR(r1); 3214 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3215 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3216 } else { 3217 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3218 } 3219 break; 3220 case OPC1_16_SRC_SH: 3221 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3222 break; 3223 case OPC1_16_SRC_SHA: 3224 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3225 break; 3226 default: 3227 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3228 } 3229 } 3230 3231 static void decode_srr_opc(DisasContext *ctx, int op1) 3232 { 3233 int r1, r2; 3234 TCGv temp; 3235 3236 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3237 r2 = MASK_OP_SRR_S2(ctx->opcode); 3238 3239 switch (op1) { 3240 case OPC1_16_SRR_ADD: 3241 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3242 break; 3243 case OPC1_16_SRR_ADD_A15: 3244 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3245 break; 3246 case OPC1_16_SRR_ADD_15A: 3247 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3248 break; 3249 case OPC1_16_SRR_ADD_A: 3250 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3251 break; 3252 case OPC1_16_SRR_ADDS: 3253 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3254 break; 3255 case OPC1_16_SRR_AND: 3256 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3257 break; 3258 case OPC1_16_SRR_CMOV: 3259 temp = tcg_constant_tl(0); 3260 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3261 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3262 break; 3263 case OPC1_16_SRR_CMOVN: 3264 temp = tcg_constant_tl(0); 3265 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3266 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3267 break; 3268 case OPC1_16_SRR_EQ: 3269 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3270 cpu_gpr_d[r2]); 3271 break; 3272 case OPC1_16_SRR_LT: 3273 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3274 cpu_gpr_d[r2]); 3275 break; 3276 case OPC1_16_SRR_MOV: 3277 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3278 break; 3279 case OPC1_16_SRR_MOV_A: 3280 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3281 break; 3282 case OPC1_16_SRR_MOV_AA: 3283 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3284 break; 3285 case OPC1_16_SRR_MOV_D: 3286 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3287 break; 3288 case OPC1_16_SRR_MUL: 3289 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3290 break; 3291 case OPC1_16_SRR_OR: 3292 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3293 break; 3294 case OPC1_16_SRR_SUB: 3295 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3296 break; 3297 case OPC1_16_SRR_SUB_A15B: 3298 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3299 break; 3300 case OPC1_16_SRR_SUB_15AB: 3301 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3302 break; 3303 case OPC1_16_SRR_SUBS: 3304 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3305 break; 3306 case OPC1_16_SRR_XOR: 3307 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3308 break; 3309 default: 3310 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3311 } 3312 } 3313 3314 static void decode_ssr_opc(DisasContext *ctx, int op1) 3315 { 3316 int r1, r2; 3317 3318 r1 = MASK_OP_SSR_S1(ctx->opcode); 3319 r2 = MASK_OP_SSR_S2(ctx->opcode); 3320 3321 switch (op1) { 3322 case OPC1_16_SSR_ST_A: 3323 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3324 break; 3325 case OPC1_16_SSR_ST_A_POSTINC: 3326 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3327 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3328 break; 3329 case OPC1_16_SSR_ST_B: 3330 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3331 break; 3332 case OPC1_16_SSR_ST_B_POSTINC: 3333 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3334 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3335 break; 3336 case OPC1_16_SSR_ST_H: 3337 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3338 break; 3339 case OPC1_16_SSR_ST_H_POSTINC: 3340 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3341 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3342 break; 3343 case OPC1_16_SSR_ST_W: 3344 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3345 break; 3346 case OPC1_16_SSR_ST_W_POSTINC: 3347 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3348 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3349 break; 3350 default: 3351 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3352 } 3353 } 3354 3355 static void decode_sc_opc(DisasContext *ctx, int op1) 3356 { 3357 int32_t const16; 3358 3359 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3360 3361 switch (op1) { 3362 case OPC1_16_SC_AND: 3363 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3364 break; 3365 case OPC1_16_SC_BISR: 3366 if (ctx->priv == TRICORE_PRIV_SM) { 3367 gen_helper_1arg(bisr, const16 & 0xff); 3368 } else { 3369 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 3370 } 3371 break; 3372 case OPC1_16_SC_LD_A: 3373 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3374 break; 3375 case OPC1_16_SC_LD_W: 3376 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3377 break; 3378 case OPC1_16_SC_MOV: 3379 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3380 break; 3381 case OPC1_16_SC_OR: 3382 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3383 break; 3384 case OPC1_16_SC_ST_A: 3385 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3386 break; 3387 case OPC1_16_SC_ST_W: 3388 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3389 break; 3390 case OPC1_16_SC_SUB_A: 3391 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3392 break; 3393 default: 3394 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3395 } 3396 } 3397 3398 static void decode_slr_opc(DisasContext *ctx, int op1) 3399 { 3400 int r1, r2; 3401 3402 r1 = MASK_OP_SLR_D(ctx->opcode); 3403 r2 = MASK_OP_SLR_S2(ctx->opcode); 3404 3405 switch (op1) { 3406 /* SLR-format */ 3407 case OPC1_16_SLR_LD_A: 3408 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3409 break; 3410 case OPC1_16_SLR_LD_A_POSTINC: 3411 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3412 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3413 break; 3414 case OPC1_16_SLR_LD_BU: 3415 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3416 break; 3417 case OPC1_16_SLR_LD_BU_POSTINC: 3418 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3419 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3420 break; 3421 case OPC1_16_SLR_LD_H: 3422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3423 break; 3424 case OPC1_16_SLR_LD_H_POSTINC: 3425 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3426 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3427 break; 3428 case OPC1_16_SLR_LD_W: 3429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3430 break; 3431 case OPC1_16_SLR_LD_W_POSTINC: 3432 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3433 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3434 break; 3435 default: 3436 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3437 } 3438 } 3439 3440 static void decode_sro_opc(DisasContext *ctx, int op1) 3441 { 3442 int r2; 3443 int32_t address; 3444 3445 r2 = MASK_OP_SRO_S2(ctx->opcode); 3446 address = MASK_OP_SRO_OFF4(ctx->opcode); 3447 3448 /* SRO-format */ 3449 switch (op1) { 3450 case OPC1_16_SRO_LD_A: 3451 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3452 break; 3453 case OPC1_16_SRO_LD_BU: 3454 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3455 break; 3456 case OPC1_16_SRO_LD_H: 3457 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3458 break; 3459 case OPC1_16_SRO_LD_W: 3460 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3461 break; 3462 case OPC1_16_SRO_ST_A: 3463 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3464 break; 3465 case OPC1_16_SRO_ST_B: 3466 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3467 break; 3468 case OPC1_16_SRO_ST_H: 3469 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3470 break; 3471 case OPC1_16_SRO_ST_W: 3472 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3473 break; 3474 default: 3475 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3476 } 3477 } 3478 3479 static void decode_sr_system(DisasContext *ctx) 3480 { 3481 uint32_t op2; 3482 op2 = MASK_OP_SR_OP2(ctx->opcode); 3483 3484 switch (op2) { 3485 case OPC2_16_SR_NOP: 3486 break; 3487 case OPC2_16_SR_RET: 3488 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3489 break; 3490 case OPC2_16_SR_RFE: 3491 gen_helper_rfe(tcg_env); 3492 ctx->base.is_jmp = DISAS_EXIT; 3493 break; 3494 case OPC2_16_SR_DEBUG: 3495 /* raise EXCP_DEBUG */ 3496 break; 3497 case OPC2_16_SR_FRET: 3498 gen_fret(ctx); 3499 break; 3500 default: 3501 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3502 } 3503 } 3504 3505 static void decode_sr_accu(DisasContext *ctx) 3506 { 3507 uint32_t op2; 3508 uint32_t r1; 3509 3510 r1 = MASK_OP_SR_S1D(ctx->opcode); 3511 op2 = MASK_OP_SR_OP2(ctx->opcode); 3512 3513 switch (op2) { 3514 case OPC2_16_SR_RSUB: 3515 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3516 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3517 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3518 /* calc SV bit */ 3519 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3520 /* sub */ 3521 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3522 /* calc av */ 3523 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3524 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3525 /* calc sav */ 3526 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3527 break; 3528 case OPC2_16_SR_SAT_B: 3529 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3530 break; 3531 case OPC2_16_SR_SAT_BU: 3532 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3533 break; 3534 case OPC2_16_SR_SAT_H: 3535 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3536 break; 3537 case OPC2_16_SR_SAT_HU: 3538 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3539 break; 3540 default: 3541 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3542 } 3543 } 3544 3545 static void decode_16Bit_opc(DisasContext *ctx) 3546 { 3547 int op1; 3548 int r1, r2; 3549 int32_t const16; 3550 int32_t address; 3551 TCGv temp; 3552 3553 op1 = MASK_OP_MAJOR(ctx->opcode); 3554 3555 /* handle ADDSC.A opcode only being 6 bit long */ 3556 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3557 op1 = OPC1_16_SRRS_ADDSC_A; 3558 } 3559 3560 switch (op1) { 3561 case OPC1_16_SRC_ADD: 3562 case OPC1_16_SRC_ADD_A15: 3563 case OPC1_16_SRC_ADD_15A: 3564 case OPC1_16_SRC_ADD_A: 3565 case OPC1_16_SRC_CADD: 3566 case OPC1_16_SRC_CADDN: 3567 case OPC1_16_SRC_CMOV: 3568 case OPC1_16_SRC_CMOVN: 3569 case OPC1_16_SRC_EQ: 3570 case OPC1_16_SRC_LT: 3571 case OPC1_16_SRC_MOV: 3572 case OPC1_16_SRC_MOV_A: 3573 case OPC1_16_SRC_MOV_E: 3574 case OPC1_16_SRC_SH: 3575 case OPC1_16_SRC_SHA: 3576 decode_src_opc(ctx, op1); 3577 break; 3578 /* SRR-format */ 3579 case OPC1_16_SRR_ADD: 3580 case OPC1_16_SRR_ADD_A15: 3581 case OPC1_16_SRR_ADD_15A: 3582 case OPC1_16_SRR_ADD_A: 3583 case OPC1_16_SRR_ADDS: 3584 case OPC1_16_SRR_AND: 3585 case OPC1_16_SRR_CMOV: 3586 case OPC1_16_SRR_CMOVN: 3587 case OPC1_16_SRR_EQ: 3588 case OPC1_16_SRR_LT: 3589 case OPC1_16_SRR_MOV: 3590 case OPC1_16_SRR_MOV_A: 3591 case OPC1_16_SRR_MOV_AA: 3592 case OPC1_16_SRR_MOV_D: 3593 case OPC1_16_SRR_MUL: 3594 case OPC1_16_SRR_OR: 3595 case OPC1_16_SRR_SUB: 3596 case OPC1_16_SRR_SUB_A15B: 3597 case OPC1_16_SRR_SUB_15AB: 3598 case OPC1_16_SRR_SUBS: 3599 case OPC1_16_SRR_XOR: 3600 decode_srr_opc(ctx, op1); 3601 break; 3602 /* SSR-format */ 3603 case OPC1_16_SSR_ST_A: 3604 case OPC1_16_SSR_ST_A_POSTINC: 3605 case OPC1_16_SSR_ST_B: 3606 case OPC1_16_SSR_ST_B_POSTINC: 3607 case OPC1_16_SSR_ST_H: 3608 case OPC1_16_SSR_ST_H_POSTINC: 3609 case OPC1_16_SSR_ST_W: 3610 case OPC1_16_SSR_ST_W_POSTINC: 3611 decode_ssr_opc(ctx, op1); 3612 break; 3613 /* SRRS-format */ 3614 case OPC1_16_SRRS_ADDSC_A: 3615 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3616 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3617 const16 = MASK_OP_SRRS_N(ctx->opcode); 3618 temp = tcg_temp_new(); 3619 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3620 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3621 break; 3622 /* SLRO-format */ 3623 case OPC1_16_SLRO_LD_A: 3624 r1 = MASK_OP_SLRO_D(ctx->opcode); 3625 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3626 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3627 break; 3628 case OPC1_16_SLRO_LD_BU: 3629 r1 = MASK_OP_SLRO_D(ctx->opcode); 3630 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3631 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3632 break; 3633 case OPC1_16_SLRO_LD_H: 3634 r1 = MASK_OP_SLRO_D(ctx->opcode); 3635 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3636 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3637 break; 3638 case OPC1_16_SLRO_LD_W: 3639 r1 = MASK_OP_SLRO_D(ctx->opcode); 3640 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3641 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3642 break; 3643 /* SB-format */ 3644 case OPC1_16_SB_CALL: 3645 case OPC1_16_SB_J: 3646 case OPC1_16_SB_JNZ: 3647 case OPC1_16_SB_JZ: 3648 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3649 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3650 break; 3651 /* SBC-format */ 3652 case OPC1_16_SBC_JEQ: 3653 case OPC1_16_SBC_JNE: 3654 address = MASK_OP_SBC_DISP4(ctx->opcode); 3655 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3656 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3657 break; 3658 case OPC1_16_SBC_JEQ2: 3659 case OPC1_16_SBC_JNE2: 3660 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3661 address = MASK_OP_SBC_DISP4(ctx->opcode); 3662 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3663 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3664 } else { 3665 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3666 } 3667 break; 3668 /* SBRN-format */ 3669 case OPC1_16_SBRN_JNZ_T: 3670 case OPC1_16_SBRN_JZ_T: 3671 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3672 const16 = MASK_OP_SBRN_N(ctx->opcode); 3673 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3674 break; 3675 /* SBR-format */ 3676 case OPC1_16_SBR_JEQ2: 3677 case OPC1_16_SBR_JNE2: 3678 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3679 r1 = MASK_OP_SBR_S2(ctx->opcode); 3680 address = MASK_OP_SBR_DISP4(ctx->opcode); 3681 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3682 } else { 3683 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3684 } 3685 break; 3686 case OPC1_16_SBR_JEQ: 3687 case OPC1_16_SBR_JGEZ: 3688 case OPC1_16_SBR_JGTZ: 3689 case OPC1_16_SBR_JLEZ: 3690 case OPC1_16_SBR_JLTZ: 3691 case OPC1_16_SBR_JNE: 3692 case OPC1_16_SBR_JNZ: 3693 case OPC1_16_SBR_JNZ_A: 3694 case OPC1_16_SBR_JZ: 3695 case OPC1_16_SBR_JZ_A: 3696 case OPC1_16_SBR_LOOP: 3697 r1 = MASK_OP_SBR_S2(ctx->opcode); 3698 address = MASK_OP_SBR_DISP4(ctx->opcode); 3699 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3700 break; 3701 /* SC-format */ 3702 case OPC1_16_SC_AND: 3703 case OPC1_16_SC_BISR: 3704 case OPC1_16_SC_LD_A: 3705 case OPC1_16_SC_LD_W: 3706 case OPC1_16_SC_MOV: 3707 case OPC1_16_SC_OR: 3708 case OPC1_16_SC_ST_A: 3709 case OPC1_16_SC_ST_W: 3710 case OPC1_16_SC_SUB_A: 3711 decode_sc_opc(ctx, op1); 3712 break; 3713 /* SLR-format */ 3714 case OPC1_16_SLR_LD_A: 3715 case OPC1_16_SLR_LD_A_POSTINC: 3716 case OPC1_16_SLR_LD_BU: 3717 case OPC1_16_SLR_LD_BU_POSTINC: 3718 case OPC1_16_SLR_LD_H: 3719 case OPC1_16_SLR_LD_H_POSTINC: 3720 case OPC1_16_SLR_LD_W: 3721 case OPC1_16_SLR_LD_W_POSTINC: 3722 decode_slr_opc(ctx, op1); 3723 break; 3724 /* SRO-format */ 3725 case OPC1_16_SRO_LD_A: 3726 case OPC1_16_SRO_LD_BU: 3727 case OPC1_16_SRO_LD_H: 3728 case OPC1_16_SRO_LD_W: 3729 case OPC1_16_SRO_ST_A: 3730 case OPC1_16_SRO_ST_B: 3731 case OPC1_16_SRO_ST_H: 3732 case OPC1_16_SRO_ST_W: 3733 decode_sro_opc(ctx, op1); 3734 break; 3735 /* SSRO-format */ 3736 case OPC1_16_SSRO_ST_A: 3737 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3738 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3739 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3740 break; 3741 case OPC1_16_SSRO_ST_B: 3742 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3743 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3744 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3745 break; 3746 case OPC1_16_SSRO_ST_H: 3747 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3748 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3749 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3750 break; 3751 case OPC1_16_SSRO_ST_W: 3752 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3753 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3754 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3755 break; 3756 /* SR-format */ 3757 case OPCM_16_SR_SYSTEM: 3758 decode_sr_system(ctx); 3759 break; 3760 case OPCM_16_SR_ACCU: 3761 decode_sr_accu(ctx); 3762 break; 3763 case OPC1_16_SR_JI: 3764 r1 = MASK_OP_SR_S1D(ctx->opcode); 3765 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3766 break; 3767 case OPC1_16_SR_NOT: 3768 r1 = MASK_OP_SR_S1D(ctx->opcode); 3769 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3770 break; 3771 default: 3772 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3773 } 3774 } 3775 3776 /* 3777 * 32 bit instructions 3778 */ 3779 3780 /* ABS-format */ 3781 static void decode_abs_ldw(DisasContext *ctx) 3782 { 3783 int32_t op2; 3784 int32_t r1; 3785 uint32_t address; 3786 TCGv temp; 3787 3788 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3789 address = MASK_OP_ABS_OFF18(ctx->opcode); 3790 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3791 3792 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3793 3794 switch (op2) { 3795 case OPC2_32_ABS_LD_A: 3796 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3797 break; 3798 case OPC2_32_ABS_LD_D: 3799 CHECK_REG_PAIR(r1); 3800 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3801 break; 3802 case OPC2_32_ABS_LD_DA: 3803 CHECK_REG_PAIR(r1); 3804 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3805 break; 3806 case OPC2_32_ABS_LD_W: 3807 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3808 break; 3809 default: 3810 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3811 } 3812 } 3813 3814 static void decode_abs_ldb(DisasContext *ctx) 3815 { 3816 int32_t op2; 3817 int32_t r1; 3818 uint32_t address; 3819 TCGv temp; 3820 3821 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3822 address = MASK_OP_ABS_OFF18(ctx->opcode); 3823 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3824 3825 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3826 3827 switch (op2) { 3828 case OPC2_32_ABS_LD_B: 3829 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3830 break; 3831 case OPC2_32_ABS_LD_BU: 3832 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3833 break; 3834 case OPC2_32_ABS_LD_H: 3835 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3836 break; 3837 case OPC2_32_ABS_LD_HU: 3838 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3839 break; 3840 default: 3841 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3842 } 3843 } 3844 3845 static void decode_abs_ldst_swap(DisasContext *ctx) 3846 { 3847 int32_t op2; 3848 int32_t r1; 3849 uint32_t address; 3850 TCGv temp; 3851 3852 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3853 address = MASK_OP_ABS_OFF18(ctx->opcode); 3854 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3855 3856 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3857 3858 switch (op2) { 3859 case OPC2_32_ABS_LDMST: 3860 gen_ldmst(ctx, r1, temp); 3861 break; 3862 case OPC2_32_ABS_SWAP_W: 3863 gen_swap(ctx, r1, temp); 3864 break; 3865 default: 3866 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3867 } 3868 } 3869 3870 static void decode_abs_ldst_context(DisasContext *ctx) 3871 { 3872 uint32_t op2; 3873 int32_t off18; 3874 3875 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3876 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3877 3878 switch (op2) { 3879 case OPC2_32_ABS_LDLCX: 3880 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3881 break; 3882 case OPC2_32_ABS_LDUCX: 3883 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3884 break; 3885 case OPC2_32_ABS_STLCX: 3886 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3887 break; 3888 case OPC2_32_ABS_STUCX: 3889 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3890 break; 3891 default: 3892 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3893 } 3894 } 3895 3896 static void decode_abs_store(DisasContext *ctx) 3897 { 3898 int32_t op2; 3899 int32_t r1; 3900 uint32_t address; 3901 TCGv temp; 3902 3903 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3904 address = MASK_OP_ABS_OFF18(ctx->opcode); 3905 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3906 3907 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3908 3909 switch (op2) { 3910 case OPC2_32_ABS_ST_A: 3911 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3912 break; 3913 case OPC2_32_ABS_ST_D: 3914 CHECK_REG_PAIR(r1); 3915 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3916 break; 3917 case OPC2_32_ABS_ST_DA: 3918 CHECK_REG_PAIR(r1); 3919 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3920 break; 3921 case OPC2_32_ABS_ST_W: 3922 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3923 break; 3924 default: 3925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3926 } 3927 } 3928 3929 static void decode_abs_storeb_h(DisasContext *ctx) 3930 { 3931 int32_t op2; 3932 int32_t r1; 3933 uint32_t address; 3934 TCGv temp; 3935 3936 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3937 address = MASK_OP_ABS_OFF18(ctx->opcode); 3938 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3939 3940 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3941 3942 switch (op2) { 3943 case OPC2_32_ABS_ST_B: 3944 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3945 break; 3946 case OPC2_32_ABS_ST_H: 3947 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3948 break; 3949 default: 3950 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3951 } 3952 } 3953 3954 /* Bit-format */ 3955 3956 static void decode_bit_andacc(DisasContext *ctx) 3957 { 3958 uint32_t op2; 3959 int r1, r2, r3; 3960 int pos1, pos2; 3961 3962 r1 = MASK_OP_BIT_S1(ctx->opcode); 3963 r2 = MASK_OP_BIT_S2(ctx->opcode); 3964 r3 = MASK_OP_BIT_D(ctx->opcode); 3965 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3966 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3967 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3968 3969 3970 switch (op2) { 3971 case OPC2_32_BIT_AND_AND_T: 3972 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3973 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3974 break; 3975 case OPC2_32_BIT_AND_ANDN_T: 3976 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3977 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3978 break; 3979 case OPC2_32_BIT_AND_NOR_T: 3980 if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) { 3981 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3982 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3983 } else { 3984 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3985 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3986 } 3987 break; 3988 case OPC2_32_BIT_AND_OR_T: 3989 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3990 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 3991 break; 3992 default: 3993 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3994 } 3995 } 3996 3997 static void decode_bit_logical_t(DisasContext *ctx) 3998 { 3999 uint32_t op2; 4000 int r1, r2, r3; 4001 int pos1, pos2; 4002 r1 = MASK_OP_BIT_S1(ctx->opcode); 4003 r2 = MASK_OP_BIT_S2(ctx->opcode); 4004 r3 = MASK_OP_BIT_D(ctx->opcode); 4005 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4006 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4007 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4008 4009 switch (op2) { 4010 case OPC2_32_BIT_AND_T: 4011 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4012 pos1, pos2, &tcg_gen_and_tl); 4013 break; 4014 case OPC2_32_BIT_ANDN_T: 4015 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4016 pos1, pos2, &tcg_gen_andc_tl); 4017 break; 4018 case OPC2_32_BIT_NOR_T: 4019 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4020 pos1, pos2, &tcg_gen_nor_tl); 4021 break; 4022 case OPC2_32_BIT_OR_T: 4023 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4024 pos1, pos2, &tcg_gen_or_tl); 4025 break; 4026 default: 4027 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4028 } 4029 } 4030 4031 static void decode_bit_insert(DisasContext *ctx) 4032 { 4033 uint32_t op2; 4034 int r1, r2, r3; 4035 int pos1, pos2; 4036 TCGv temp; 4037 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4038 r1 = MASK_OP_BIT_S1(ctx->opcode); 4039 r2 = MASK_OP_BIT_S2(ctx->opcode); 4040 r3 = MASK_OP_BIT_D(ctx->opcode); 4041 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4042 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4043 4044 temp = tcg_temp_new(); 4045 4046 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4047 if (op2 == OPC2_32_BIT_INSN_T) { 4048 tcg_gen_not_tl(temp, temp); 4049 } 4050 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4051 } 4052 4053 static void decode_bit_logical_t2(DisasContext *ctx) 4054 { 4055 uint32_t op2; 4056 4057 int r1, r2, r3; 4058 int pos1, pos2; 4059 4060 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4061 r1 = MASK_OP_BIT_S1(ctx->opcode); 4062 r2 = MASK_OP_BIT_S2(ctx->opcode); 4063 r3 = MASK_OP_BIT_D(ctx->opcode); 4064 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4065 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4066 4067 switch (op2) { 4068 case OPC2_32_BIT_NAND_T: 4069 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4070 pos1, pos2, &tcg_gen_nand_tl); 4071 break; 4072 case OPC2_32_BIT_ORN_T: 4073 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4074 pos1, pos2, &tcg_gen_orc_tl); 4075 break; 4076 case OPC2_32_BIT_XNOR_T: 4077 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4078 pos1, pos2, &tcg_gen_eqv_tl); 4079 break; 4080 case OPC2_32_BIT_XOR_T: 4081 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4082 pos1, pos2, &tcg_gen_xor_tl); 4083 break; 4084 default: 4085 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4086 } 4087 } 4088 4089 static void decode_bit_orand(DisasContext *ctx) 4090 { 4091 uint32_t op2; 4092 4093 int r1, r2, r3; 4094 int pos1, pos2; 4095 4096 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4097 r1 = MASK_OP_BIT_S1(ctx->opcode); 4098 r2 = MASK_OP_BIT_S2(ctx->opcode); 4099 r3 = MASK_OP_BIT_D(ctx->opcode); 4100 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4101 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4102 4103 switch (op2) { 4104 case OPC2_32_BIT_OR_AND_T: 4105 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4106 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4107 break; 4108 case OPC2_32_BIT_OR_ANDN_T: 4109 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4110 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4111 break; 4112 case OPC2_32_BIT_OR_NOR_T: 4113 if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) { 4114 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4115 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4116 } else { 4117 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4118 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4119 } 4120 break; 4121 case OPC2_32_BIT_OR_OR_T: 4122 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4123 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4124 break; 4125 default: 4126 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4127 } 4128 } 4129 4130 static void decode_bit_sh_logic1(DisasContext *ctx) 4131 { 4132 uint32_t op2; 4133 int r1, r2, r3; 4134 int pos1, pos2; 4135 TCGv temp; 4136 4137 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4138 r1 = MASK_OP_BIT_S1(ctx->opcode); 4139 r2 = MASK_OP_BIT_S2(ctx->opcode); 4140 r3 = MASK_OP_BIT_D(ctx->opcode); 4141 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4142 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4143 4144 temp = tcg_temp_new(); 4145 4146 switch (op2) { 4147 case OPC2_32_BIT_SH_AND_T: 4148 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4149 pos1, pos2, &tcg_gen_and_tl); 4150 break; 4151 case OPC2_32_BIT_SH_ANDN_T: 4152 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4153 pos1, pos2, &tcg_gen_andc_tl); 4154 break; 4155 case OPC2_32_BIT_SH_NOR_T: 4156 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4157 pos1, pos2, &tcg_gen_nor_tl); 4158 break; 4159 case OPC2_32_BIT_SH_OR_T: 4160 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4161 pos1, pos2, &tcg_gen_or_tl); 4162 break; 4163 default: 4164 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4165 } 4166 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4167 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4168 } 4169 4170 static void decode_bit_sh_logic2(DisasContext *ctx) 4171 { 4172 uint32_t op2; 4173 int r1, r2, r3; 4174 int pos1, pos2; 4175 TCGv temp; 4176 4177 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4178 r1 = MASK_OP_BIT_S1(ctx->opcode); 4179 r2 = MASK_OP_BIT_S2(ctx->opcode); 4180 r3 = MASK_OP_BIT_D(ctx->opcode); 4181 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4182 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4183 4184 temp = tcg_temp_new(); 4185 4186 switch (op2) { 4187 case OPC2_32_BIT_SH_NAND_T: 4188 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4189 pos1, pos2, &tcg_gen_nand_tl); 4190 break; 4191 case OPC2_32_BIT_SH_ORN_T: 4192 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4193 pos1, pos2, &tcg_gen_orc_tl); 4194 break; 4195 case OPC2_32_BIT_SH_XNOR_T: 4196 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4197 pos1, pos2, &tcg_gen_eqv_tl); 4198 break; 4199 case OPC2_32_BIT_SH_XOR_T: 4200 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4201 pos1, pos2, &tcg_gen_xor_tl); 4202 break; 4203 default: 4204 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4205 } 4206 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4207 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4208 } 4209 4210 /* BO-format */ 4211 4212 4213 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4214 { 4215 uint32_t op2; 4216 uint32_t off10; 4217 int32_t r1, r2; 4218 TCGv temp; 4219 4220 r1 = MASK_OP_BO_S1D(ctx->opcode); 4221 r2 = MASK_OP_BO_S2(ctx->opcode); 4222 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4223 op2 = MASK_OP_BO_OP2(ctx->opcode); 4224 4225 switch (op2) { 4226 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4227 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4228 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4229 /* instruction to access the cache */ 4230 break; 4231 case OPC2_32_BO_CACHEA_WI_POSTINC: 4232 case OPC2_32_BO_CACHEA_W_POSTINC: 4233 case OPC2_32_BO_CACHEA_I_POSTINC: 4234 /* instruction to access the cache, but we still need to handle 4235 the addressing mode */ 4236 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4237 break; 4238 case OPC2_32_BO_CACHEA_WI_PREINC: 4239 case OPC2_32_BO_CACHEA_W_PREINC: 4240 case OPC2_32_BO_CACHEA_I_PREINC: 4241 /* instruction to access the cache, but we still need to handle 4242 the addressing mode */ 4243 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4244 break; 4245 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4246 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4247 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4248 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4249 } 4250 break; 4251 case OPC2_32_BO_CACHEI_W_POSTINC: 4252 case OPC2_32_BO_CACHEI_WI_POSTINC: 4253 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4254 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4255 } else { 4256 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4257 } 4258 break; 4259 case OPC2_32_BO_CACHEI_W_PREINC: 4260 case OPC2_32_BO_CACHEI_WI_PREINC: 4261 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4262 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4263 } else { 4264 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4265 } 4266 break; 4267 case OPC2_32_BO_ST_A_SHORTOFF: 4268 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4269 break; 4270 case OPC2_32_BO_ST_A_POSTINC: 4271 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4272 MO_LESL); 4273 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4274 break; 4275 case OPC2_32_BO_ST_A_PREINC: 4276 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4277 break; 4278 case OPC2_32_BO_ST_B_SHORTOFF: 4279 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4280 break; 4281 case OPC2_32_BO_ST_B_POSTINC: 4282 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4283 MO_UB); 4284 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4285 break; 4286 case OPC2_32_BO_ST_B_PREINC: 4287 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4288 break; 4289 case OPC2_32_BO_ST_D_SHORTOFF: 4290 CHECK_REG_PAIR(r1); 4291 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4292 off10, ctx); 4293 break; 4294 case OPC2_32_BO_ST_D_POSTINC: 4295 CHECK_REG_PAIR(r1); 4296 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4297 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4298 break; 4299 case OPC2_32_BO_ST_D_PREINC: 4300 CHECK_REG_PAIR(r1); 4301 temp = tcg_temp_new(); 4302 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4303 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4304 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4305 break; 4306 case OPC2_32_BO_ST_DA_SHORTOFF: 4307 CHECK_REG_PAIR(r1); 4308 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4309 off10, ctx); 4310 break; 4311 case OPC2_32_BO_ST_DA_POSTINC: 4312 CHECK_REG_PAIR(r1); 4313 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4314 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4315 break; 4316 case OPC2_32_BO_ST_DA_PREINC: 4317 CHECK_REG_PAIR(r1); 4318 temp = tcg_temp_new(); 4319 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4320 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4321 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4322 break; 4323 case OPC2_32_BO_ST_H_SHORTOFF: 4324 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4325 break; 4326 case OPC2_32_BO_ST_H_POSTINC: 4327 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4328 MO_LEUW); 4329 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4330 break; 4331 case OPC2_32_BO_ST_H_PREINC: 4332 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4333 break; 4334 case OPC2_32_BO_ST_Q_SHORTOFF: 4335 temp = tcg_temp_new(); 4336 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4337 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4338 break; 4339 case OPC2_32_BO_ST_Q_POSTINC: 4340 temp = tcg_temp_new(); 4341 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4342 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4343 MO_LEUW); 4344 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4345 break; 4346 case OPC2_32_BO_ST_Q_PREINC: 4347 temp = tcg_temp_new(); 4348 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4349 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4350 break; 4351 case OPC2_32_BO_ST_W_SHORTOFF: 4352 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4353 break; 4354 case OPC2_32_BO_ST_W_POSTINC: 4355 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4356 MO_LEUL); 4357 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4358 break; 4359 case OPC2_32_BO_ST_W_PREINC: 4360 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4361 break; 4362 default: 4363 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4364 } 4365 } 4366 4367 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4368 { 4369 uint32_t op2; 4370 uint32_t off10; 4371 int32_t r1, r2; 4372 TCGv temp, temp2, t_off10; 4373 4374 r1 = MASK_OP_BO_S1D(ctx->opcode); 4375 r2 = MASK_OP_BO_S2(ctx->opcode); 4376 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4377 op2 = MASK_OP_BO_OP2(ctx->opcode); 4378 4379 temp = tcg_temp_new(); 4380 temp2 = tcg_temp_new(); 4381 t_off10 = tcg_constant_i32(off10); 4382 CHECK_REG_PAIR(r2); 4383 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4384 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4385 4386 switch (op2) { 4387 case OPC2_32_BO_CACHEA_WI_BR: 4388 case OPC2_32_BO_CACHEA_W_BR: 4389 case OPC2_32_BO_CACHEA_I_BR: 4390 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4391 break; 4392 case OPC2_32_BO_CACHEA_WI_CIRC: 4393 case OPC2_32_BO_CACHEA_W_CIRC: 4394 case OPC2_32_BO_CACHEA_I_CIRC: 4395 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4396 break; 4397 case OPC2_32_BO_ST_A_BR: 4398 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4399 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4400 break; 4401 case OPC2_32_BO_ST_A_CIRC: 4402 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4403 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4404 break; 4405 case OPC2_32_BO_ST_B_BR: 4406 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4407 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4408 break; 4409 case OPC2_32_BO_ST_B_CIRC: 4410 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4411 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4412 break; 4413 case OPC2_32_BO_ST_D_BR: 4414 CHECK_REG_PAIR(r1); 4415 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4416 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4417 break; 4418 case OPC2_32_BO_ST_D_CIRC: 4419 CHECK_REG_PAIR(r1); 4420 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4421 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4422 tcg_gen_addi_tl(temp, temp, 4); 4423 tcg_gen_rem_tl(temp, temp, temp2); 4424 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4425 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4426 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4427 break; 4428 case OPC2_32_BO_ST_DA_BR: 4429 CHECK_REG_PAIR(r1); 4430 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4431 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4432 break; 4433 case OPC2_32_BO_ST_DA_CIRC: 4434 CHECK_REG_PAIR(r1); 4435 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4436 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4437 tcg_gen_addi_tl(temp, temp, 4); 4438 tcg_gen_rem_tl(temp, temp, temp2); 4439 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4440 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4441 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4442 break; 4443 case OPC2_32_BO_ST_H_BR: 4444 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4445 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4446 break; 4447 case OPC2_32_BO_ST_H_CIRC: 4448 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4449 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4450 break; 4451 case OPC2_32_BO_ST_Q_BR: 4452 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4453 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4454 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4455 break; 4456 case OPC2_32_BO_ST_Q_CIRC: 4457 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4458 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4459 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4460 break; 4461 case OPC2_32_BO_ST_W_BR: 4462 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4463 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4464 break; 4465 case OPC2_32_BO_ST_W_CIRC: 4466 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4467 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4468 break; 4469 default: 4470 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4471 } 4472 } 4473 4474 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4475 { 4476 uint32_t op2; 4477 uint32_t off10; 4478 int32_t r1, r2; 4479 TCGv temp; 4480 4481 r1 = MASK_OP_BO_S1D(ctx->opcode); 4482 r2 = MASK_OP_BO_S2(ctx->opcode); 4483 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4484 op2 = MASK_OP_BO_OP2(ctx->opcode); 4485 4486 switch (op2) { 4487 case OPC2_32_BO_LD_A_SHORTOFF: 4488 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4489 break; 4490 case OPC2_32_BO_LD_A_POSTINC: 4491 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4492 MO_LEUL); 4493 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4494 break; 4495 case OPC2_32_BO_LD_A_PREINC: 4496 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4497 break; 4498 case OPC2_32_BO_LD_B_SHORTOFF: 4499 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4500 break; 4501 case OPC2_32_BO_LD_B_POSTINC: 4502 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4503 MO_SB); 4504 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4505 break; 4506 case OPC2_32_BO_LD_B_PREINC: 4507 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4508 break; 4509 case OPC2_32_BO_LD_BU_SHORTOFF: 4510 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4511 break; 4512 case OPC2_32_BO_LD_BU_POSTINC: 4513 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4514 MO_UB); 4515 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4516 break; 4517 case OPC2_32_BO_LD_BU_PREINC: 4518 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4519 break; 4520 case OPC2_32_BO_LD_D_SHORTOFF: 4521 CHECK_REG_PAIR(r1); 4522 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4523 off10, ctx); 4524 break; 4525 case OPC2_32_BO_LD_D_POSTINC: 4526 CHECK_REG_PAIR(r1); 4527 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4528 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4529 break; 4530 case OPC2_32_BO_LD_D_PREINC: 4531 CHECK_REG_PAIR(r1); 4532 temp = tcg_temp_new(); 4533 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4534 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4535 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4536 break; 4537 case OPC2_32_BO_LD_DA_SHORTOFF: 4538 CHECK_REG_PAIR(r1); 4539 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4540 off10, ctx); 4541 break; 4542 case OPC2_32_BO_LD_DA_POSTINC: 4543 CHECK_REG_PAIR(r1); 4544 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4545 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4546 break; 4547 case OPC2_32_BO_LD_DA_PREINC: 4548 CHECK_REG_PAIR(r1); 4549 temp = tcg_temp_new(); 4550 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4551 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4552 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4553 break; 4554 case OPC2_32_BO_LD_H_SHORTOFF: 4555 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4556 break; 4557 case OPC2_32_BO_LD_H_POSTINC: 4558 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4559 MO_LESW); 4560 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4561 break; 4562 case OPC2_32_BO_LD_H_PREINC: 4563 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4564 break; 4565 case OPC2_32_BO_LD_HU_SHORTOFF: 4566 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4567 break; 4568 case OPC2_32_BO_LD_HU_POSTINC: 4569 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4570 MO_LEUW); 4571 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4572 break; 4573 case OPC2_32_BO_LD_HU_PREINC: 4574 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4575 break; 4576 case OPC2_32_BO_LD_Q_SHORTOFF: 4577 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4578 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4579 break; 4580 case OPC2_32_BO_LD_Q_POSTINC: 4581 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4582 MO_LEUW); 4583 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4584 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4585 break; 4586 case OPC2_32_BO_LD_Q_PREINC: 4587 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4588 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4589 break; 4590 case OPC2_32_BO_LD_W_SHORTOFF: 4591 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4592 break; 4593 case OPC2_32_BO_LD_W_POSTINC: 4594 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4595 MO_LEUL); 4596 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4597 break; 4598 case OPC2_32_BO_LD_W_PREINC: 4599 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4600 break; 4601 default: 4602 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4603 } 4604 } 4605 4606 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4607 { 4608 uint32_t op2; 4609 uint32_t off10; 4610 int r1, r2; 4611 TCGv temp, temp2, t_off10; 4612 4613 r1 = MASK_OP_BO_S1D(ctx->opcode); 4614 r2 = MASK_OP_BO_S2(ctx->opcode); 4615 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4616 op2 = MASK_OP_BO_OP2(ctx->opcode); 4617 4618 temp = tcg_temp_new(); 4619 temp2 = tcg_temp_new(); 4620 t_off10 = tcg_constant_i32(off10); 4621 CHECK_REG_PAIR(r2); 4622 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4623 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4624 4625 4626 switch (op2) { 4627 case OPC2_32_BO_LD_A_BR: 4628 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4629 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4630 break; 4631 case OPC2_32_BO_LD_A_CIRC: 4632 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4633 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4634 break; 4635 case OPC2_32_BO_LD_B_BR: 4636 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4637 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4638 break; 4639 case OPC2_32_BO_LD_B_CIRC: 4640 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4641 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4642 break; 4643 case OPC2_32_BO_LD_BU_BR: 4644 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4645 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4646 break; 4647 case OPC2_32_BO_LD_BU_CIRC: 4648 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4649 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4650 break; 4651 case OPC2_32_BO_LD_D_BR: 4652 CHECK_REG_PAIR(r1); 4653 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4654 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4655 break; 4656 case OPC2_32_BO_LD_D_CIRC: 4657 CHECK_REG_PAIR(r1); 4658 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4659 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4660 tcg_gen_addi_tl(temp, temp, 4); 4661 tcg_gen_rem_tl(temp, temp, temp2); 4662 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4663 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4664 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4665 break; 4666 case OPC2_32_BO_LD_DA_BR: 4667 CHECK_REG_PAIR(r1); 4668 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4669 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4670 break; 4671 case OPC2_32_BO_LD_DA_CIRC: 4672 CHECK_REG_PAIR(r1); 4673 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4674 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4675 tcg_gen_addi_tl(temp, temp, 4); 4676 tcg_gen_rem_tl(temp, temp, temp2); 4677 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4678 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4679 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4680 break; 4681 case OPC2_32_BO_LD_H_BR: 4682 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4683 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4684 break; 4685 case OPC2_32_BO_LD_H_CIRC: 4686 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4687 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4688 break; 4689 case OPC2_32_BO_LD_HU_BR: 4690 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4691 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4692 break; 4693 case OPC2_32_BO_LD_HU_CIRC: 4694 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4695 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4696 break; 4697 case OPC2_32_BO_LD_Q_BR: 4698 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4699 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4700 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4701 break; 4702 case OPC2_32_BO_LD_Q_CIRC: 4703 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4704 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4705 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4706 break; 4707 case OPC2_32_BO_LD_W_BR: 4708 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4709 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4710 break; 4711 case OPC2_32_BO_LD_W_CIRC: 4712 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4713 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4714 break; 4715 default: 4716 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4717 } 4718 } 4719 4720 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4721 { 4722 uint32_t op2; 4723 uint32_t off10; 4724 int r1, r2; 4725 4726 TCGv temp; 4727 4728 r1 = MASK_OP_BO_S1D(ctx->opcode); 4729 r2 = MASK_OP_BO_S2(ctx->opcode); 4730 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4731 op2 = MASK_OP_BO_OP2(ctx->opcode); 4732 4733 4734 temp = tcg_temp_new(); 4735 4736 switch (op2) { 4737 case OPC2_32_BO_LDLCX_SHORTOFF: 4738 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4739 gen_helper_ldlcx(tcg_env, temp); 4740 break; 4741 case OPC2_32_BO_LDMST_SHORTOFF: 4742 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4743 gen_ldmst(ctx, r1, temp); 4744 break; 4745 case OPC2_32_BO_LDMST_POSTINC: 4746 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4747 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4748 break; 4749 case OPC2_32_BO_LDMST_PREINC: 4750 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4751 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4752 break; 4753 case OPC2_32_BO_LDUCX_SHORTOFF: 4754 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4755 gen_helper_lducx(tcg_env, temp); 4756 break; 4757 case OPC2_32_BO_LEA_SHORTOFF: 4758 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4759 break; 4760 case OPC2_32_BO_STLCX_SHORTOFF: 4761 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4762 gen_helper_stlcx(tcg_env, temp); 4763 break; 4764 case OPC2_32_BO_STUCX_SHORTOFF: 4765 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4766 gen_helper_stucx(tcg_env, temp); 4767 break; 4768 case OPC2_32_BO_SWAP_W_SHORTOFF: 4769 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4770 gen_swap(ctx, r1, temp); 4771 break; 4772 case OPC2_32_BO_SWAP_W_POSTINC: 4773 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4774 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4775 break; 4776 case OPC2_32_BO_SWAP_W_PREINC: 4777 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4778 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4779 break; 4780 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4781 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4782 gen_cmpswap(ctx, r1, temp); 4783 break; 4784 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4785 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4786 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4787 break; 4788 case OPC2_32_BO_CMPSWAP_W_PREINC: 4789 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4790 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4791 break; 4792 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4793 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4794 gen_swapmsk(ctx, r1, temp); 4795 break; 4796 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4797 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4798 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4799 break; 4800 case OPC2_32_BO_SWAPMSK_W_PREINC: 4801 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4802 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4803 break; 4804 default: 4805 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4806 } 4807 } 4808 4809 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4810 { 4811 uint32_t op2; 4812 uint32_t off10; 4813 int r1, r2; 4814 TCGv temp, temp2, t_off10; 4815 4816 r1 = MASK_OP_BO_S1D(ctx->opcode); 4817 r2 = MASK_OP_BO_S2(ctx->opcode); 4818 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4819 op2 = MASK_OP_BO_OP2(ctx->opcode); 4820 4821 temp = tcg_temp_new(); 4822 temp2 = tcg_temp_new(); 4823 t_off10 = tcg_constant_i32(off10); 4824 CHECK_REG_PAIR(r2); 4825 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4826 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4827 4828 switch (op2) { 4829 case OPC2_32_BO_LDMST_BR: 4830 gen_ldmst(ctx, r1, temp2); 4831 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4832 break; 4833 case OPC2_32_BO_LDMST_CIRC: 4834 gen_ldmst(ctx, r1, temp2); 4835 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4836 break; 4837 case OPC2_32_BO_SWAP_W_BR: 4838 gen_swap(ctx, r1, temp2); 4839 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4840 break; 4841 case OPC2_32_BO_SWAP_W_CIRC: 4842 gen_swap(ctx, r1, temp2); 4843 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4844 break; 4845 case OPC2_32_BO_CMPSWAP_W_BR: 4846 gen_cmpswap(ctx, r1, temp2); 4847 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4848 break; 4849 case OPC2_32_BO_CMPSWAP_W_CIRC: 4850 gen_cmpswap(ctx, r1, temp2); 4851 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4852 break; 4853 case OPC2_32_BO_SWAPMSK_W_BR: 4854 gen_swapmsk(ctx, r1, temp2); 4855 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4856 break; 4857 case OPC2_32_BO_SWAPMSK_W_CIRC: 4858 gen_swapmsk(ctx, r1, temp2); 4859 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4860 break; 4861 default: 4862 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4863 } 4864 } 4865 4866 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4867 { 4868 int r1, r2; 4869 int32_t address; 4870 TCGv temp; 4871 4872 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4873 r2 = MASK_OP_BOL_S2(ctx->opcode); 4874 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4875 4876 switch (op1) { 4877 case OPC1_32_BOL_LD_A_LONGOFF: 4878 temp = tcg_temp_new(); 4879 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4880 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4881 break; 4882 case OPC1_32_BOL_LD_W_LONGOFF: 4883 temp = tcg_temp_new(); 4884 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4885 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4886 break; 4887 case OPC1_32_BOL_LEA_LONGOFF: 4888 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4889 break; 4890 case OPC1_32_BOL_ST_A_LONGOFF: 4891 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4892 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4893 } else { 4894 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4895 } 4896 break; 4897 case OPC1_32_BOL_ST_W_LONGOFF: 4898 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4899 break; 4900 case OPC1_32_BOL_LD_B_LONGOFF: 4901 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4902 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4903 } else { 4904 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4905 } 4906 break; 4907 case OPC1_32_BOL_LD_BU_LONGOFF: 4908 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4909 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4910 } else { 4911 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4912 } 4913 break; 4914 case OPC1_32_BOL_LD_H_LONGOFF: 4915 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4916 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4917 } else { 4918 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4919 } 4920 break; 4921 case OPC1_32_BOL_LD_HU_LONGOFF: 4922 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4923 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4924 } else { 4925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4926 } 4927 break; 4928 case OPC1_32_BOL_ST_B_LONGOFF: 4929 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4930 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4931 } else { 4932 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4933 } 4934 break; 4935 case OPC1_32_BOL_ST_H_LONGOFF: 4936 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4937 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4938 } else { 4939 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4940 } 4941 break; 4942 default: 4943 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4944 } 4945 } 4946 4947 /* RC format */ 4948 static void decode_rc_logical_shift(DisasContext *ctx) 4949 { 4950 uint32_t op2; 4951 int r1, r2; 4952 int32_t const9; 4953 TCGv temp; 4954 4955 r2 = MASK_OP_RC_D(ctx->opcode); 4956 r1 = MASK_OP_RC_S1(ctx->opcode); 4957 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4958 op2 = MASK_OP_RC_OP2(ctx->opcode); 4959 4960 switch (op2) { 4961 case OPC2_32_RC_AND: 4962 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4963 break; 4964 case OPC2_32_RC_ANDN: 4965 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4966 break; 4967 case OPC2_32_RC_NAND: 4968 temp = tcg_temp_new(); 4969 tcg_gen_movi_tl(temp, const9); 4970 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4971 break; 4972 case OPC2_32_RC_NOR: 4973 temp = tcg_temp_new(); 4974 tcg_gen_movi_tl(temp, const9); 4975 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4976 break; 4977 case OPC2_32_RC_OR: 4978 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4979 break; 4980 case OPC2_32_RC_ORN: 4981 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4982 break; 4983 case OPC2_32_RC_SH: 4984 const9 = sextract32(const9, 0, 6); 4985 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4986 break; 4987 case OPC2_32_RC_SH_H: 4988 const9 = sextract32(const9, 0, 5); 4989 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4990 break; 4991 case OPC2_32_RC_SHA: 4992 const9 = sextract32(const9, 0, 6); 4993 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4994 break; 4995 case OPC2_32_RC_SHA_H: 4996 const9 = sextract32(const9, 0, 5); 4997 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4998 break; 4999 case OPC2_32_RC_SHAS: 5000 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5001 break; 5002 case OPC2_32_RC_XNOR: 5003 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5004 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5005 break; 5006 case OPC2_32_RC_XOR: 5007 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5008 break; 5009 case OPC2_32_RC_SHUFFLE: 5010 if (has_feature(ctx, TRICORE_FEATURE_162)) { 5011 temp = tcg_constant_i32(const9); 5012 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5013 } else { 5014 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5015 } 5016 break; 5017 default: 5018 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5019 } 5020 } 5021 5022 static void decode_rc_accumulator(DisasContext *ctx) 5023 { 5024 uint32_t op2; 5025 int r1, r2; 5026 int16_t const9; 5027 5028 TCGv temp; 5029 5030 r2 = MASK_OP_RC_D(ctx->opcode); 5031 r1 = MASK_OP_RC_S1(ctx->opcode); 5032 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5033 5034 op2 = MASK_OP_RC_OP2(ctx->opcode); 5035 5036 temp = tcg_temp_new(); 5037 5038 switch (op2) { 5039 case OPC2_32_RC_ABSDIF: 5040 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5041 break; 5042 case OPC2_32_RC_ABSDIFS: 5043 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5044 break; 5045 case OPC2_32_RC_ADD: 5046 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5047 break; 5048 case OPC2_32_RC_ADDC: 5049 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5050 break; 5051 case OPC2_32_RC_ADDS: 5052 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5053 break; 5054 case OPC2_32_RC_ADDS_U: 5055 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5056 break; 5057 case OPC2_32_RC_ADDX: 5058 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5059 break; 5060 case OPC2_32_RC_AND_EQ: 5061 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5062 const9, &tcg_gen_and_tl); 5063 break; 5064 case OPC2_32_RC_AND_GE: 5065 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5066 const9, &tcg_gen_and_tl); 5067 break; 5068 case OPC2_32_RC_AND_GE_U: 5069 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5070 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5071 const9, &tcg_gen_and_tl); 5072 break; 5073 case OPC2_32_RC_AND_LT: 5074 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5075 const9, &tcg_gen_and_tl); 5076 break; 5077 case OPC2_32_RC_AND_LT_U: 5078 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5079 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5080 const9, &tcg_gen_and_tl); 5081 break; 5082 case OPC2_32_RC_AND_NE: 5083 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5084 const9, &tcg_gen_and_tl); 5085 break; 5086 case OPC2_32_RC_EQ: 5087 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5088 break; 5089 case OPC2_32_RC_EQANY_B: 5090 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5091 break; 5092 case OPC2_32_RC_EQANY_H: 5093 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5094 break; 5095 case OPC2_32_RC_GE: 5096 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5097 break; 5098 case OPC2_32_RC_GE_U: 5099 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5100 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5101 break; 5102 case OPC2_32_RC_LT: 5103 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5104 break; 5105 case OPC2_32_RC_LT_U: 5106 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5107 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5108 break; 5109 case OPC2_32_RC_MAX: 5110 tcg_gen_movi_tl(temp, const9); 5111 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5112 cpu_gpr_d[r1], temp); 5113 break; 5114 case OPC2_32_RC_MAX_U: 5115 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5116 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5117 cpu_gpr_d[r1], temp); 5118 break; 5119 case OPC2_32_RC_MIN: 5120 tcg_gen_movi_tl(temp, const9); 5121 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5122 cpu_gpr_d[r1], temp); 5123 break; 5124 case OPC2_32_RC_MIN_U: 5125 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5126 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5127 cpu_gpr_d[r1], temp); 5128 break; 5129 case OPC2_32_RC_NE: 5130 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5131 break; 5132 case OPC2_32_RC_OR_EQ: 5133 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5134 const9, &tcg_gen_or_tl); 5135 break; 5136 case OPC2_32_RC_OR_GE: 5137 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5138 const9, &tcg_gen_or_tl); 5139 break; 5140 case OPC2_32_RC_OR_GE_U: 5141 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5142 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5143 const9, &tcg_gen_or_tl); 5144 break; 5145 case OPC2_32_RC_OR_LT: 5146 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5147 const9, &tcg_gen_or_tl); 5148 break; 5149 case OPC2_32_RC_OR_LT_U: 5150 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5151 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5152 const9, &tcg_gen_or_tl); 5153 break; 5154 case OPC2_32_RC_OR_NE: 5155 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5156 const9, &tcg_gen_or_tl); 5157 break; 5158 case OPC2_32_RC_RSUB: 5159 tcg_gen_movi_tl(temp, const9); 5160 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5161 break; 5162 case OPC2_32_RC_RSUBS: 5163 tcg_gen_movi_tl(temp, const9); 5164 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5165 break; 5166 case OPC2_32_RC_RSUBS_U: 5167 tcg_gen_movi_tl(temp, const9); 5168 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5169 break; 5170 case OPC2_32_RC_SH_EQ: 5171 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5172 break; 5173 case OPC2_32_RC_SH_GE: 5174 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5175 break; 5176 case OPC2_32_RC_SH_GE_U: 5177 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5178 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5179 break; 5180 case OPC2_32_RC_SH_LT: 5181 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5182 break; 5183 case OPC2_32_RC_SH_LT_U: 5184 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5185 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5186 break; 5187 case OPC2_32_RC_SH_NE: 5188 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5189 break; 5190 case OPC2_32_RC_XOR_EQ: 5191 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5192 const9, &tcg_gen_xor_tl); 5193 break; 5194 case OPC2_32_RC_XOR_GE: 5195 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5196 const9, &tcg_gen_xor_tl); 5197 break; 5198 case OPC2_32_RC_XOR_GE_U: 5199 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5200 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5201 const9, &tcg_gen_xor_tl); 5202 break; 5203 case OPC2_32_RC_XOR_LT: 5204 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5205 const9, &tcg_gen_xor_tl); 5206 break; 5207 case OPC2_32_RC_XOR_LT_U: 5208 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5209 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5210 const9, &tcg_gen_xor_tl); 5211 break; 5212 case OPC2_32_RC_XOR_NE: 5213 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5214 const9, &tcg_gen_xor_tl); 5215 break; 5216 default: 5217 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5218 } 5219 } 5220 5221 static void decode_rc_serviceroutine(DisasContext *ctx) 5222 { 5223 uint32_t op2; 5224 uint32_t const9; 5225 5226 op2 = MASK_OP_RC_OP2(ctx->opcode); 5227 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5228 5229 switch (op2) { 5230 case OPC2_32_RC_BISR: 5231 if (ctx->priv == TRICORE_PRIV_SM) { 5232 gen_helper_1arg(bisr, const9); 5233 } else { 5234 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 5235 } 5236 break; 5237 case OPC2_32_RC_SYSCALL: 5238 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff); 5239 break; 5240 default: 5241 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5242 } 5243 } 5244 5245 static void decode_rc_mul(DisasContext *ctx) 5246 { 5247 uint32_t op2; 5248 int r1, r2; 5249 int16_t const9; 5250 5251 r2 = MASK_OP_RC_D(ctx->opcode); 5252 r1 = MASK_OP_RC_S1(ctx->opcode); 5253 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5254 5255 op2 = MASK_OP_RC_OP2(ctx->opcode); 5256 5257 switch (op2) { 5258 case OPC2_32_RC_MUL_32: 5259 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5260 break; 5261 case OPC2_32_RC_MUL_64: 5262 CHECK_REG_PAIR(r2); 5263 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5264 break; 5265 case OPC2_32_RC_MULS_32: 5266 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5267 break; 5268 case OPC2_32_RC_MUL_U_64: 5269 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5270 CHECK_REG_PAIR(r2); 5271 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5272 break; 5273 case OPC2_32_RC_MULS_U_32: 5274 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5275 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5276 break; 5277 default: 5278 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5279 } 5280 } 5281 5282 /* RCPW format */ 5283 static void decode_rcpw_insert(DisasContext *ctx) 5284 { 5285 uint32_t op2; 5286 int r1, r2; 5287 int32_t pos, width, const4; 5288 5289 TCGv temp; 5290 5291 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5292 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5293 r2 = MASK_OP_RCPW_D(ctx->opcode); 5294 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5295 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5296 pos = MASK_OP_RCPW_POS(ctx->opcode); 5297 5298 switch (op2) { 5299 case OPC2_32_RCPW_IMASK: 5300 CHECK_REG_PAIR(r2); 5301 /* if pos + width > 32 undefined result */ 5302 if (pos + width <= 32) { 5303 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5304 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5305 } 5306 break; 5307 case OPC2_32_RCPW_INSERT: 5308 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 5309 if (width == 0) { 5310 tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]); 5311 /* if pos + width > 32 undefined result */ 5312 } else if (pos + width <= 32) { 5313 temp = tcg_constant_i32(const4); 5314 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5315 } 5316 break; 5317 default: 5318 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5319 } 5320 } 5321 5322 /* RCRW format */ 5323 5324 static void decode_rcrw_insert(DisasContext *ctx) 5325 { 5326 uint32_t op2; 5327 int r1, r3, r4; 5328 int32_t width, const4; 5329 5330 TCGv temp, temp2, temp3; 5331 5332 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5333 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5334 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5335 r4 = MASK_OP_RCRW_D(ctx->opcode); 5336 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5337 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5338 5339 temp = tcg_temp_new(); 5340 temp2 = tcg_temp_new(); 5341 5342 switch (op2) { 5343 case OPC2_32_RCRW_IMASK: 5344 CHECK_REG_PAIR(r4); 5345 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5346 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5347 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5348 tcg_gen_movi_tl(temp2, const4); 5349 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5350 break; 5351 case OPC2_32_RCRW_INSERT: 5352 temp3 = tcg_temp_new(); 5353 5354 tcg_gen_movi_tl(temp, width); 5355 tcg_gen_movi_tl(temp2, const4); 5356 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5357 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5358 break; 5359 default: 5360 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5361 } 5362 } 5363 5364 /* RCR format */ 5365 5366 static void decode_rcr_cond_select(DisasContext *ctx) 5367 { 5368 uint32_t op2; 5369 int r1, r3, r4; 5370 int32_t const9; 5371 5372 TCGv temp, temp2; 5373 5374 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5375 r1 = MASK_OP_RCR_S1(ctx->opcode); 5376 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5377 r3 = MASK_OP_RCR_S3(ctx->opcode); 5378 r4 = MASK_OP_RCR_D(ctx->opcode); 5379 5380 switch (op2) { 5381 case OPC2_32_RCR_CADD: 5382 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5383 cpu_gpr_d[r3]); 5384 break; 5385 case OPC2_32_RCR_CADDN: 5386 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5387 cpu_gpr_d[r3]); 5388 break; 5389 case OPC2_32_RCR_SEL: 5390 temp = tcg_constant_i32(0); 5391 temp2 = tcg_constant_i32(const9); 5392 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5393 cpu_gpr_d[r1], temp2); 5394 break; 5395 case OPC2_32_RCR_SELN: 5396 temp = tcg_constant_i32(0); 5397 temp2 = tcg_constant_i32(const9); 5398 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5399 cpu_gpr_d[r1], temp2); 5400 break; 5401 default: 5402 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5403 } 5404 } 5405 5406 static void decode_rcr_madd(DisasContext *ctx) 5407 { 5408 uint32_t op2; 5409 int r1, r3, r4; 5410 int32_t const9; 5411 5412 5413 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5414 r1 = MASK_OP_RCR_S1(ctx->opcode); 5415 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5416 r3 = MASK_OP_RCR_S3(ctx->opcode); 5417 r4 = MASK_OP_RCR_D(ctx->opcode); 5418 5419 switch (op2) { 5420 case OPC2_32_RCR_MADD_32: 5421 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5422 break; 5423 case OPC2_32_RCR_MADD_64: 5424 CHECK_REG_PAIR(r4); 5425 CHECK_REG_PAIR(r3); 5426 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5427 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5428 break; 5429 case OPC2_32_RCR_MADDS_32: 5430 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5431 break; 5432 case OPC2_32_RCR_MADDS_64: 5433 CHECK_REG_PAIR(r4); 5434 CHECK_REG_PAIR(r3); 5435 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5436 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5437 break; 5438 case OPC2_32_RCR_MADD_U_64: 5439 CHECK_REG_PAIR(r4); 5440 CHECK_REG_PAIR(r3); 5441 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5442 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5443 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5444 break; 5445 case OPC2_32_RCR_MADDS_U_32: 5446 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5447 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5448 break; 5449 case OPC2_32_RCR_MADDS_U_64: 5450 CHECK_REG_PAIR(r4); 5451 CHECK_REG_PAIR(r3); 5452 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5453 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5454 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5455 break; 5456 default: 5457 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5458 } 5459 } 5460 5461 static void decode_rcr_msub(DisasContext *ctx) 5462 { 5463 uint32_t op2; 5464 int r1, r3, r4; 5465 int32_t const9; 5466 5467 5468 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5469 r1 = MASK_OP_RCR_S1(ctx->opcode); 5470 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5471 r3 = MASK_OP_RCR_S3(ctx->opcode); 5472 r4 = MASK_OP_RCR_D(ctx->opcode); 5473 5474 switch (op2) { 5475 case OPC2_32_RCR_MSUB_32: 5476 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5477 break; 5478 case OPC2_32_RCR_MSUB_64: 5479 CHECK_REG_PAIR(r4); 5480 CHECK_REG_PAIR(r3); 5481 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5482 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5483 break; 5484 case OPC2_32_RCR_MSUBS_32: 5485 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5486 break; 5487 case OPC2_32_RCR_MSUBS_64: 5488 CHECK_REG_PAIR(r4); 5489 CHECK_REG_PAIR(r3); 5490 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5491 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5492 break; 5493 case OPC2_32_RCR_MSUB_U_64: 5494 CHECK_REG_PAIR(r4); 5495 CHECK_REG_PAIR(r3); 5496 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5497 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5498 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5499 break; 5500 case OPC2_32_RCR_MSUBS_U_32: 5501 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5502 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5503 break; 5504 case OPC2_32_RCR_MSUBS_U_64: 5505 CHECK_REG_PAIR(r4); 5506 CHECK_REG_PAIR(r3); 5507 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5508 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5509 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5510 break; 5511 default: 5512 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5513 } 5514 } 5515 5516 /* RLC format */ 5517 5518 static void decode_rlc_opc(DisasContext *ctx, 5519 uint32_t op1) 5520 { 5521 int32_t const16; 5522 int r1, r2; 5523 5524 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5525 r1 = MASK_OP_RLC_S1(ctx->opcode); 5526 r2 = MASK_OP_RLC_D(ctx->opcode); 5527 5528 switch (op1) { 5529 case OPC1_32_RLC_ADDI: 5530 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5531 break; 5532 case OPC1_32_RLC_ADDIH: 5533 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5534 break; 5535 case OPC1_32_RLC_ADDIH_A: 5536 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5537 break; 5538 case OPC1_32_RLC_MFCR: 5539 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5540 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5541 break; 5542 case OPC1_32_RLC_MOV: 5543 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5544 break; 5545 case OPC1_32_RLC_MOV_64: 5546 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5547 CHECK_REG_PAIR(r2); 5548 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5549 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5550 } else { 5551 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5552 } 5553 break; 5554 case OPC1_32_RLC_MOV_U: 5555 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5556 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5557 break; 5558 case OPC1_32_RLC_MOV_H: 5559 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5560 break; 5561 case OPC1_32_RLC_MOVH_A: 5562 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5563 break; 5564 case OPC1_32_RLC_MTCR: 5565 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5566 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5567 break; 5568 default: 5569 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5570 } 5571 } 5572 5573 /* RR format */ 5574 static void decode_rr_accumulator(DisasContext *ctx) 5575 { 5576 uint32_t op2; 5577 int r3, r2, r1; 5578 5579 TCGv temp; 5580 5581 r3 = MASK_OP_RR_D(ctx->opcode); 5582 r2 = MASK_OP_RR_S2(ctx->opcode); 5583 r1 = MASK_OP_RR_S1(ctx->opcode); 5584 op2 = MASK_OP_RR_OP2(ctx->opcode); 5585 5586 switch (op2) { 5587 case OPC2_32_RR_ABS: 5588 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5589 break; 5590 case OPC2_32_RR_ABS_B: 5591 gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5592 break; 5593 case OPC2_32_RR_ABS_H: 5594 gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5595 break; 5596 case OPC2_32_RR_ABSDIF: 5597 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5598 break; 5599 case OPC2_32_RR_ABSDIF_B: 5600 gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5601 cpu_gpr_d[r2]); 5602 break; 5603 case OPC2_32_RR_ABSDIF_H: 5604 gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5605 cpu_gpr_d[r2]); 5606 break; 5607 case OPC2_32_RR_ABSDIFS: 5608 gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5609 cpu_gpr_d[r2]); 5610 break; 5611 case OPC2_32_RR_ABSDIFS_H: 5612 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5613 cpu_gpr_d[r2]); 5614 break; 5615 case OPC2_32_RR_ABSS: 5616 gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5617 break; 5618 case OPC2_32_RR_ABSS_H: 5619 gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); 5620 break; 5621 case OPC2_32_RR_ADD: 5622 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5623 break; 5624 case OPC2_32_RR_ADD_B: 5625 gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5626 break; 5627 case OPC2_32_RR_ADD_H: 5628 gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5629 break; 5630 case OPC2_32_RR_ADDC: 5631 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5632 break; 5633 case OPC2_32_RR_ADDS: 5634 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5635 break; 5636 case OPC2_32_RR_ADDS_H: 5637 gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5638 cpu_gpr_d[r2]); 5639 break; 5640 case OPC2_32_RR_ADDS_HU: 5641 gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5642 cpu_gpr_d[r2]); 5643 break; 5644 case OPC2_32_RR_ADDS_U: 5645 gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5646 cpu_gpr_d[r2]); 5647 break; 5648 case OPC2_32_RR_ADDX: 5649 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5650 break; 5651 case OPC2_32_RR_AND_EQ: 5652 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5653 cpu_gpr_d[r2], &tcg_gen_and_tl); 5654 break; 5655 case OPC2_32_RR_AND_GE: 5656 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5657 cpu_gpr_d[r2], &tcg_gen_and_tl); 5658 break; 5659 case OPC2_32_RR_AND_GE_U: 5660 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5661 cpu_gpr_d[r2], &tcg_gen_and_tl); 5662 break; 5663 case OPC2_32_RR_AND_LT: 5664 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5665 cpu_gpr_d[r2], &tcg_gen_and_tl); 5666 break; 5667 case OPC2_32_RR_AND_LT_U: 5668 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5669 cpu_gpr_d[r2], &tcg_gen_and_tl); 5670 break; 5671 case OPC2_32_RR_AND_NE: 5672 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5673 cpu_gpr_d[r2], &tcg_gen_and_tl); 5674 break; 5675 case OPC2_32_RR_EQ: 5676 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5677 cpu_gpr_d[r2]); 5678 break; 5679 case OPC2_32_RR_EQ_B: 5680 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5681 break; 5682 case OPC2_32_RR_EQ_H: 5683 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5684 break; 5685 case OPC2_32_RR_EQ_W: 5686 tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], 5687 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5688 break; 5689 case OPC2_32_RR_EQANY_B: 5690 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5691 break; 5692 case OPC2_32_RR_EQANY_H: 5693 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5694 break; 5695 case OPC2_32_RR_GE: 5696 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5697 cpu_gpr_d[r2]); 5698 break; 5699 case OPC2_32_RR_GE_U: 5700 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5701 cpu_gpr_d[r2]); 5702 break; 5703 case OPC2_32_RR_LT: 5704 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5705 cpu_gpr_d[r2]); 5706 break; 5707 case OPC2_32_RR_LT_U: 5708 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5709 cpu_gpr_d[r2]); 5710 break; 5711 case OPC2_32_RR_LT_B: 5712 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5713 break; 5714 case OPC2_32_RR_LT_BU: 5715 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5716 break; 5717 case OPC2_32_RR_LT_H: 5718 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5719 break; 5720 case OPC2_32_RR_LT_HU: 5721 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5722 break; 5723 case OPC2_32_RR_LT_W: 5724 tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3], 5725 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5726 break; 5727 case OPC2_32_RR_LT_WU: 5728 tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], 5729 cpu_gpr_d[r1], cpu_gpr_d[r2]); 5730 break; 5731 case OPC2_32_RR_MAX: 5732 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5733 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5734 break; 5735 case OPC2_32_RR_MAX_U: 5736 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5737 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5738 break; 5739 case OPC2_32_RR_MAX_B: 5740 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5741 break; 5742 case OPC2_32_RR_MAX_BU: 5743 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5744 break; 5745 case OPC2_32_RR_MAX_H: 5746 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5747 break; 5748 case OPC2_32_RR_MAX_HU: 5749 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5750 break; 5751 case OPC2_32_RR_MIN: 5752 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5753 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5754 break; 5755 case OPC2_32_RR_MIN_U: 5756 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5757 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5758 break; 5759 case OPC2_32_RR_MIN_B: 5760 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5761 break; 5762 case OPC2_32_RR_MIN_BU: 5763 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5764 break; 5765 case OPC2_32_RR_MIN_H: 5766 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5767 break; 5768 case OPC2_32_RR_MIN_HU: 5769 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5770 break; 5771 case OPC2_32_RR_MOV: 5772 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5773 break; 5774 case OPC2_32_RR_MOV_64: 5775 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5776 temp = tcg_temp_new(); 5777 5778 CHECK_REG_PAIR(r3); 5779 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5780 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5781 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5782 } else { 5783 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5784 } 5785 break; 5786 case OPC2_32_RR_MOVS_64: 5787 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5788 CHECK_REG_PAIR(r3); 5789 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5790 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5791 } else { 5792 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5793 } 5794 break; 5795 case OPC2_32_RR_NE: 5796 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5797 cpu_gpr_d[r2]); 5798 break; 5799 case OPC2_32_RR_OR_EQ: 5800 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5801 cpu_gpr_d[r2], &tcg_gen_or_tl); 5802 break; 5803 case OPC2_32_RR_OR_GE: 5804 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5805 cpu_gpr_d[r2], &tcg_gen_or_tl); 5806 break; 5807 case OPC2_32_RR_OR_GE_U: 5808 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5809 cpu_gpr_d[r2], &tcg_gen_or_tl); 5810 break; 5811 case OPC2_32_RR_OR_LT: 5812 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5813 cpu_gpr_d[r2], &tcg_gen_or_tl); 5814 break; 5815 case OPC2_32_RR_OR_LT_U: 5816 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5817 cpu_gpr_d[r2], &tcg_gen_or_tl); 5818 break; 5819 case OPC2_32_RR_OR_NE: 5820 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5821 cpu_gpr_d[r2], &tcg_gen_or_tl); 5822 break; 5823 case OPC2_32_RR_SAT_B: 5824 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5825 break; 5826 case OPC2_32_RR_SAT_BU: 5827 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5828 break; 5829 case OPC2_32_RR_SAT_H: 5830 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5831 break; 5832 case OPC2_32_RR_SAT_HU: 5833 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5834 break; 5835 case OPC2_32_RR_SH_EQ: 5836 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5837 cpu_gpr_d[r2]); 5838 break; 5839 case OPC2_32_RR_SH_GE: 5840 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5841 cpu_gpr_d[r2]); 5842 break; 5843 case OPC2_32_RR_SH_GE_U: 5844 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5845 cpu_gpr_d[r2]); 5846 break; 5847 case OPC2_32_RR_SH_LT: 5848 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5849 cpu_gpr_d[r2]); 5850 break; 5851 case OPC2_32_RR_SH_LT_U: 5852 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5853 cpu_gpr_d[r2]); 5854 break; 5855 case OPC2_32_RR_SH_NE: 5856 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5857 cpu_gpr_d[r2]); 5858 break; 5859 case OPC2_32_RR_SUB: 5860 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5861 break; 5862 case OPC2_32_RR_SUB_B: 5863 gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5864 break; 5865 case OPC2_32_RR_SUB_H: 5866 gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5867 break; 5868 case OPC2_32_RR_SUBC: 5869 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5870 break; 5871 case OPC2_32_RR_SUBS: 5872 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5873 break; 5874 case OPC2_32_RR_SUBS_U: 5875 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5876 break; 5877 case OPC2_32_RR_SUBS_H: 5878 gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5879 cpu_gpr_d[r2]); 5880 break; 5881 case OPC2_32_RR_SUBS_HU: 5882 gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 5883 cpu_gpr_d[r2]); 5884 break; 5885 case OPC2_32_RR_SUBX: 5886 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5887 break; 5888 case OPC2_32_RR_XOR_EQ: 5889 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5890 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5891 break; 5892 case OPC2_32_RR_XOR_GE: 5893 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5894 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5895 break; 5896 case OPC2_32_RR_XOR_GE_U: 5897 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5898 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5899 break; 5900 case OPC2_32_RR_XOR_LT: 5901 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5902 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5903 break; 5904 case OPC2_32_RR_XOR_LT_U: 5905 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5906 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5907 break; 5908 case OPC2_32_RR_XOR_NE: 5909 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5910 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5911 break; 5912 default: 5913 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5914 } 5915 } 5916 5917 static void decode_rr_logical_shift(DisasContext *ctx) 5918 { 5919 uint32_t op2; 5920 int r3, r2, r1; 5921 5922 r3 = MASK_OP_RR_D(ctx->opcode); 5923 r2 = MASK_OP_RR_S2(ctx->opcode); 5924 r1 = MASK_OP_RR_S1(ctx->opcode); 5925 op2 = MASK_OP_RR_OP2(ctx->opcode); 5926 5927 switch (op2) { 5928 case OPC2_32_RR_AND: 5929 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5930 break; 5931 case OPC2_32_RR_ANDN: 5932 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5933 break; 5934 case OPC2_32_RR_CLO: 5935 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5936 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5937 break; 5938 case OPC2_32_RR_CLO_H: 5939 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5940 break; 5941 case OPC2_32_RR_CLS: 5942 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5943 break; 5944 case OPC2_32_RR_CLS_H: 5945 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5946 break; 5947 case OPC2_32_RR_CLZ: 5948 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5949 break; 5950 case OPC2_32_RR_CLZ_H: 5951 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5952 break; 5953 case OPC2_32_RR_NAND: 5954 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5955 break; 5956 case OPC2_32_RR_NOR: 5957 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5958 break; 5959 case OPC2_32_RR_OR: 5960 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5961 break; 5962 case OPC2_32_RR_ORN: 5963 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5964 break; 5965 case OPC2_32_RR_SH: 5966 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5967 break; 5968 case OPC2_32_RR_SH_H: 5969 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5970 break; 5971 case OPC2_32_RR_SHA: 5972 gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5973 break; 5974 case OPC2_32_RR_SHA_H: 5975 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5976 break; 5977 case OPC2_32_RR_SHAS: 5978 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5979 break; 5980 case OPC2_32_RR_XNOR: 5981 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5982 break; 5983 case OPC2_32_RR_XOR: 5984 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5985 break; 5986 default: 5987 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5988 } 5989 } 5990 5991 static void decode_rr_address(DisasContext *ctx) 5992 { 5993 uint32_t op2, n; 5994 int r1, r2, r3; 5995 TCGv temp; 5996 5997 op2 = MASK_OP_RR_OP2(ctx->opcode); 5998 r3 = MASK_OP_RR_D(ctx->opcode); 5999 r2 = MASK_OP_RR_S2(ctx->opcode); 6000 r1 = MASK_OP_RR_S1(ctx->opcode); 6001 n = MASK_OP_RR_N(ctx->opcode); 6002 6003 switch (op2) { 6004 case OPC2_32_RR_ADD_A: 6005 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6006 break; 6007 case OPC2_32_RR_ADDSC_A: 6008 temp = tcg_temp_new(); 6009 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6010 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6011 break; 6012 case OPC2_32_RR_ADDSC_AT: 6013 temp = tcg_temp_new(); 6014 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6015 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6016 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6017 break; 6018 case OPC2_32_RR_EQ_A: 6019 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6020 cpu_gpr_a[r2]); 6021 break; 6022 case OPC2_32_RR_EQZ: 6023 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6024 break; 6025 case OPC2_32_RR_GE_A: 6026 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6027 cpu_gpr_a[r2]); 6028 break; 6029 case OPC2_32_RR_LT_A: 6030 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6031 cpu_gpr_a[r2]); 6032 break; 6033 case OPC2_32_RR_MOV_A: 6034 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6035 break; 6036 case OPC2_32_RR_MOV_AA: 6037 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6038 break; 6039 case OPC2_32_RR_MOV_D: 6040 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6041 break; 6042 case OPC2_32_RR_NE_A: 6043 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6044 cpu_gpr_a[r2]); 6045 break; 6046 case OPC2_32_RR_NEZ_A: 6047 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6048 break; 6049 case OPC2_32_RR_SUB_A: 6050 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6051 break; 6052 default: 6053 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6054 } 6055 } 6056 6057 static void decode_rr_idirect(DisasContext *ctx) 6058 { 6059 uint32_t op2; 6060 int r1; 6061 6062 op2 = MASK_OP_RR_OP2(ctx->opcode); 6063 r1 = MASK_OP_RR_S1(ctx->opcode); 6064 6065 switch (op2) { 6066 case OPC2_32_RR_JI: 6067 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6068 break; 6069 case OPC2_32_RR_JLI: 6070 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6071 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6072 break; 6073 case OPC2_32_RR_CALLI: 6074 gen_helper_1arg(call, ctx->pc_succ_insn); 6075 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6076 break; 6077 case OPC2_32_RR_FCALLI: 6078 gen_fcall_save_ctx(ctx); 6079 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6080 break; 6081 default: 6082 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6083 return; 6084 } 6085 ctx->base.is_jmp = DISAS_JUMP; 6086 } 6087 6088 static void decode_rr_divide(DisasContext *ctx) 6089 { 6090 uint32_t op2; 6091 int r1, r2, r3; 6092 6093 TCGv temp, temp2, temp3; 6094 6095 op2 = MASK_OP_RR_OP2(ctx->opcode); 6096 r3 = MASK_OP_RR_D(ctx->opcode); 6097 r2 = MASK_OP_RR_S2(ctx->opcode); 6098 r1 = MASK_OP_RR_S1(ctx->opcode); 6099 6100 switch (op2) { 6101 case OPC2_32_RR_BMERGE: 6102 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6103 break; 6104 case OPC2_32_RR_BSPLIT: 6105 CHECK_REG_PAIR(r3); 6106 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6107 break; 6108 case OPC2_32_RR_DVINIT_B: 6109 CHECK_REG_PAIR(r3); 6110 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6111 cpu_gpr_d[r2]); 6112 break; 6113 case OPC2_32_RR_DVINIT_BU: 6114 temp = tcg_temp_new(); 6115 temp2 = tcg_temp_new(); 6116 temp3 = tcg_temp_new(); 6117 CHECK_REG_PAIR(r3); 6118 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6119 /* reset av */ 6120 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6121 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6122 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6123 tcg_gen_abs_tl(temp, temp3); 6124 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6125 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6126 } else { 6127 /* overflow = (D[b] == 0) */ 6128 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6129 } 6130 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6131 /* sv */ 6132 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6133 /* write result */ 6134 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6135 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6136 break; 6137 case OPC2_32_RR_DVINIT_H: 6138 CHECK_REG_PAIR(r3); 6139 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6140 cpu_gpr_d[r2]); 6141 break; 6142 case OPC2_32_RR_DVINIT_HU: 6143 temp = tcg_temp_new(); 6144 temp2 = tcg_temp_new(); 6145 temp3 = tcg_temp_new(); 6146 CHECK_REG_PAIR(r3); 6147 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6148 /* reset av */ 6149 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6150 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6151 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6152 tcg_gen_abs_tl(temp, temp3); 6153 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6154 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6155 } else { 6156 /* overflow = (D[b] == 0) */ 6157 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6158 } 6159 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6160 /* sv */ 6161 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6162 /* write result */ 6163 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6164 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6165 break; 6166 case OPC2_32_RR_DVINIT: 6167 temp = tcg_temp_new(); 6168 temp2 = tcg_temp_new(); 6169 CHECK_REG_PAIR(r3); 6170 /* overflow = ((D[b] == 0) || 6171 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6173 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6174 tcg_gen_and_tl(temp, temp, temp2); 6175 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6176 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6177 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6178 /* sv */ 6179 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6180 /* reset av */ 6181 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6182 /* write result */ 6183 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6184 /* sign extend to high reg */ 6185 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6186 break; 6187 case OPC2_32_RR_DVINIT_U: 6188 CHECK_REG_PAIR(r3); 6189 /* overflow = (D[b] == 0) */ 6190 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6191 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6192 /* sv */ 6193 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6194 /* reset av */ 6195 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6196 /* write result */ 6197 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6198 /* zero extend to high reg*/ 6199 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6200 break; 6201 case OPC2_32_RR_PARITY: 6202 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6203 break; 6204 case OPC2_32_RR_UNPACK: 6205 CHECK_REG_PAIR(r3); 6206 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6207 break; 6208 case OPC2_32_RR_CRC32_B: 6209 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6210 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6211 } else { 6212 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6213 } 6214 break; 6215 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */ 6216 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6217 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6218 } else { 6219 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6220 } 6221 break; 6222 case OPC2_32_RR_CRC32L_W: 6223 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6224 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6225 } else { 6226 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6227 } 6228 break; 6229 6230 case OPC2_32_RR_POPCNT_W: 6231 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6232 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6233 } else { 6234 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6235 } 6236 break; 6237 case OPC2_32_RR_DIV: 6238 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6239 CHECK_REG_PAIR(r3); 6240 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6241 cpu_gpr_d[r2]); 6242 } else { 6243 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6244 } 6245 break; 6246 case OPC2_32_RR_DIV_U: 6247 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6248 CHECK_REG_PAIR(r3); 6249 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6250 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6251 } else { 6252 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6253 } 6254 break; 6255 case OPC2_32_RR_MUL_F: 6256 gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6257 break; 6258 case OPC2_32_RR_DIV_F: 6259 gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6260 break; 6261 case OPC2_32_RR_FTOHP: 6262 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6263 gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6264 } else { 6265 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6266 } 6267 break; 6268 case OPC2_32_RR_HPTOF: 6269 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6270 gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6271 } else { 6272 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6273 } 6274 break; 6275 case OPC2_32_RR_CMP_F: 6276 gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6277 break; 6278 case OPC2_32_RR_FTOI: 6279 gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6280 break; 6281 case OPC2_32_RR_ITOF: 6282 gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6283 break; 6284 case OPC2_32_RR_FTOU: 6285 gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6286 break; 6287 case OPC2_32_RR_FTOUZ: 6288 if (has_feature(ctx, TRICORE_FEATURE_131)) { 6289 gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6290 } else { 6291 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6292 } 6293 break; 6294 case OPC2_32_RR_UPDFL: 6295 gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); 6296 break; 6297 case OPC2_32_RR_UTOF: 6298 gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6299 break; 6300 case OPC2_32_RR_FTOIZ: 6301 gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6302 break; 6303 case OPC2_32_RR_QSEED_F: 6304 gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); 6305 break; 6306 default: 6307 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6308 } 6309 } 6310 6311 /* RR1 Format */ 6312 static void decode_rr1_mul(DisasContext *ctx) 6313 { 6314 uint32_t op2; 6315 6316 int r1, r2, r3; 6317 TCGv n; 6318 TCGv_i64 temp64; 6319 6320 r1 = MASK_OP_RR1_S1(ctx->opcode); 6321 r2 = MASK_OP_RR1_S2(ctx->opcode); 6322 r3 = MASK_OP_RR1_D(ctx->opcode); 6323 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6324 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6325 6326 switch (op2) { 6327 case OPC2_32_RR1_MUL_H_32_LL: 6328 temp64 = tcg_temp_new_i64(); 6329 CHECK_REG_PAIR(r3); 6330 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6331 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6332 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6333 break; 6334 case OPC2_32_RR1_MUL_H_32_LU: 6335 temp64 = tcg_temp_new_i64(); 6336 CHECK_REG_PAIR(r3); 6337 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6338 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6339 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6340 break; 6341 case OPC2_32_RR1_MUL_H_32_UL: 6342 temp64 = tcg_temp_new_i64(); 6343 CHECK_REG_PAIR(r3); 6344 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6345 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6346 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6347 break; 6348 case OPC2_32_RR1_MUL_H_32_UU: 6349 temp64 = tcg_temp_new_i64(); 6350 CHECK_REG_PAIR(r3); 6351 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6352 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6353 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6354 break; 6355 case OPC2_32_RR1_MULM_H_64_LL: 6356 temp64 = tcg_temp_new_i64(); 6357 CHECK_REG_PAIR(r3); 6358 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6359 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6360 /* reset V bit */ 6361 tcg_gen_movi_tl(cpu_PSW_V, 0); 6362 /* reset AV bit */ 6363 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6364 break; 6365 case OPC2_32_RR1_MULM_H_64_LU: 6366 temp64 = tcg_temp_new_i64(); 6367 CHECK_REG_PAIR(r3); 6368 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6369 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6370 /* reset V bit */ 6371 tcg_gen_movi_tl(cpu_PSW_V, 0); 6372 /* reset AV bit */ 6373 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6374 break; 6375 case OPC2_32_RR1_MULM_H_64_UL: 6376 temp64 = tcg_temp_new_i64(); 6377 CHECK_REG_PAIR(r3); 6378 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6379 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6380 /* reset V bit */ 6381 tcg_gen_movi_tl(cpu_PSW_V, 0); 6382 /* reset AV bit */ 6383 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6384 break; 6385 case OPC2_32_RR1_MULM_H_64_UU: 6386 temp64 = tcg_temp_new_i64(); 6387 CHECK_REG_PAIR(r3); 6388 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6389 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6390 /* reset V bit */ 6391 tcg_gen_movi_tl(cpu_PSW_V, 0); 6392 /* reset AV bit */ 6393 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6394 break; 6395 case OPC2_32_RR1_MULR_H_16_LL: 6396 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6397 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6398 break; 6399 case OPC2_32_RR1_MULR_H_16_LU: 6400 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6401 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6402 break; 6403 case OPC2_32_RR1_MULR_H_16_UL: 6404 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6405 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6406 break; 6407 case OPC2_32_RR1_MULR_H_16_UU: 6408 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6409 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6410 break; 6411 default: 6412 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6413 } 6414 } 6415 6416 static void decode_rr1_mulq(DisasContext *ctx) 6417 { 6418 uint32_t op2; 6419 int r1, r2, r3; 6420 uint32_t n; 6421 6422 TCGv temp, temp2; 6423 6424 r1 = MASK_OP_RR1_S1(ctx->opcode); 6425 r2 = MASK_OP_RR1_S2(ctx->opcode); 6426 r3 = MASK_OP_RR1_D(ctx->opcode); 6427 n = MASK_OP_RR1_N(ctx->opcode); 6428 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6429 6430 temp = tcg_temp_new(); 6431 temp2 = tcg_temp_new(); 6432 6433 switch (op2) { 6434 case OPC2_32_RR1_MUL_Q_32: 6435 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6436 break; 6437 case OPC2_32_RR1_MUL_Q_64: 6438 CHECK_REG_PAIR(r3); 6439 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6440 n, 0); 6441 break; 6442 case OPC2_32_RR1_MUL_Q_32_L: 6443 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6444 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6445 break; 6446 case OPC2_32_RR1_MUL_Q_64_L: 6447 CHECK_REG_PAIR(r3); 6448 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6449 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6450 break; 6451 case OPC2_32_RR1_MUL_Q_32_U: 6452 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6453 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6454 break; 6455 case OPC2_32_RR1_MUL_Q_64_U: 6456 CHECK_REG_PAIR(r3); 6457 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6458 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6459 break; 6460 case OPC2_32_RR1_MUL_Q_32_LL: 6461 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6462 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6463 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6464 break; 6465 case OPC2_32_RR1_MUL_Q_32_UU: 6466 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6467 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6468 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6469 break; 6470 case OPC2_32_RR1_MULR_Q_32_L: 6471 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6472 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6473 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6474 break; 6475 case OPC2_32_RR1_MULR_Q_32_U: 6476 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6477 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6478 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6479 break; 6480 default: 6481 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6482 } 6483 } 6484 6485 /* RR2 format */ 6486 static void decode_rr2_mul(DisasContext *ctx) 6487 { 6488 uint32_t op2; 6489 int r1, r2, r3; 6490 6491 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6492 r1 = MASK_OP_RR2_S1(ctx->opcode); 6493 r2 = MASK_OP_RR2_S2(ctx->opcode); 6494 r3 = MASK_OP_RR2_D(ctx->opcode); 6495 switch (op2) { 6496 case OPC2_32_RR2_MUL_32: 6497 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6498 break; 6499 case OPC2_32_RR2_MUL_64: 6500 CHECK_REG_PAIR(r3); 6501 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6502 cpu_gpr_d[r2]); 6503 break; 6504 case OPC2_32_RR2_MULS_32: 6505 gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6506 cpu_gpr_d[r2]); 6507 break; 6508 case OPC2_32_RR2_MUL_U_64: 6509 CHECK_REG_PAIR(r3); 6510 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6511 cpu_gpr_d[r2]); 6512 break; 6513 case OPC2_32_RR2_MULS_U_32: 6514 gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], 6515 cpu_gpr_d[r2]); 6516 break; 6517 default: 6518 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6519 } 6520 } 6521 6522 /* RRPW format */ 6523 static void decode_rrpw_extract_insert(DisasContext *ctx) 6524 { 6525 uint32_t op2; 6526 int r1, r2, r3; 6527 int32_t pos, width; 6528 TCGv temp; 6529 6530 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6531 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6532 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6533 r3 = MASK_OP_RRPW_D(ctx->opcode); 6534 pos = MASK_OP_RRPW_POS(ctx->opcode); 6535 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6536 6537 switch (op2) { 6538 case OPC2_32_RRPW_EXTR: 6539 if (width == 0) { 6540 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6541 } else if (pos + width <= 32) { 6542 tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6543 } 6544 break; 6545 case OPC2_32_RRPW_EXTR_U: 6546 if (width == 0) { 6547 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6548 } else { 6549 tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); 6550 } 6551 break; 6552 case OPC2_32_RRPW_IMASK: 6553 CHECK_REG_PAIR(r3); 6554 6555 if (pos + width <= 32) { 6556 temp = tcg_temp_new(); 6557 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6558 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6559 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6560 } 6561 6562 break; 6563 case OPC2_32_RRPW_INSERT: 6564 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ 6565 if (width == 0) { 6566 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6567 } else if (pos + width <= 32) { 6568 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6569 pos, width); 6570 } 6571 break; 6572 default: 6573 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6574 } 6575 } 6576 6577 /* RRR format */ 6578 static void decode_rrr_cond_select(DisasContext *ctx) 6579 { 6580 uint32_t op2; 6581 int r1, r2, r3, r4; 6582 TCGv temp; 6583 6584 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6585 r1 = MASK_OP_RRR_S1(ctx->opcode); 6586 r2 = MASK_OP_RRR_S2(ctx->opcode); 6587 r3 = MASK_OP_RRR_S3(ctx->opcode); 6588 r4 = MASK_OP_RRR_D(ctx->opcode); 6589 6590 switch (op2) { 6591 case OPC2_32_RRR_CADD: 6592 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6593 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6594 break; 6595 case OPC2_32_RRR_CADDN: 6596 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6597 cpu_gpr_d[r3]); 6598 break; 6599 case OPC2_32_RRR_CSUB: 6600 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6601 cpu_gpr_d[r3]); 6602 break; 6603 case OPC2_32_RRR_CSUBN: 6604 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6605 cpu_gpr_d[r3]); 6606 break; 6607 case OPC2_32_RRR_SEL: 6608 temp = tcg_constant_i32(0); 6609 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6610 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6611 break; 6612 case OPC2_32_RRR_SELN: 6613 temp = tcg_constant_i32(0); 6614 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6615 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6616 break; 6617 default: 6618 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6619 } 6620 } 6621 6622 static void decode_rrr_divide(DisasContext *ctx) 6623 { 6624 uint32_t op2; 6625 6626 int r1, r2, r3, r4; 6627 6628 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6629 r1 = MASK_OP_RRR_S1(ctx->opcode); 6630 r2 = MASK_OP_RRR_S2(ctx->opcode); 6631 r3 = MASK_OP_RRR_S3(ctx->opcode); 6632 r4 = MASK_OP_RRR_D(ctx->opcode); 6633 6634 switch (op2) { 6635 case OPC2_32_RRR_DVADJ: 6636 CHECK_REG_PAIR(r3); 6637 CHECK_REG_PAIR(r4); 6638 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6639 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6640 break; 6641 case OPC2_32_RRR_DVSTEP: 6642 CHECK_REG_PAIR(r3); 6643 CHECK_REG_PAIR(r4); 6644 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6645 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6646 break; 6647 case OPC2_32_RRR_DVSTEP_U: 6648 CHECK_REG_PAIR(r3); 6649 CHECK_REG_PAIR(r4); 6650 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6651 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6652 break; 6653 case OPC2_32_RRR_IXMAX: 6654 CHECK_REG_PAIR(r3); 6655 CHECK_REG_PAIR(r4); 6656 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6657 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6658 break; 6659 case OPC2_32_RRR_IXMAX_U: 6660 CHECK_REG_PAIR(r3); 6661 CHECK_REG_PAIR(r4); 6662 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6663 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6664 break; 6665 case OPC2_32_RRR_IXMIN: 6666 CHECK_REG_PAIR(r3); 6667 CHECK_REG_PAIR(r4); 6668 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6669 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6670 break; 6671 case OPC2_32_RRR_IXMIN_U: 6672 CHECK_REG_PAIR(r3); 6673 CHECK_REG_PAIR(r4); 6674 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6675 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6676 break; 6677 case OPC2_32_RRR_PACK: 6678 CHECK_REG_PAIR(r3); 6679 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6680 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6681 break; 6682 case OPC2_32_RRR_CRCN: 6683 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6684 gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], 6685 cpu_gpr_d[r3]); 6686 } else { 6687 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6688 } 6689 break; 6690 case OPC2_32_RRR_ADD_F: 6691 gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6692 break; 6693 case OPC2_32_RRR_SUB_F: 6694 gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6695 break; 6696 case OPC2_32_RRR_MADD_F: 6697 gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6698 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6699 break; 6700 case OPC2_32_RRR_MSUB_F: 6701 gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6702 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6703 break; 6704 default: 6705 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6706 } 6707 } 6708 6709 /* RRR2 format */ 6710 static void decode_rrr2_madd(DisasContext *ctx) 6711 { 6712 uint32_t op2; 6713 uint32_t r1, r2, r3, r4; 6714 6715 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6716 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6717 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6718 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6719 r4 = MASK_OP_RRR2_D(ctx->opcode); 6720 switch (op2) { 6721 case OPC2_32_RRR2_MADD_32: 6722 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6723 cpu_gpr_d[r2]); 6724 break; 6725 case OPC2_32_RRR2_MADD_64: 6726 CHECK_REG_PAIR(r4); 6727 CHECK_REG_PAIR(r3); 6728 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6729 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6730 break; 6731 case OPC2_32_RRR2_MADDS_32: 6732 gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6733 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6734 break; 6735 case OPC2_32_RRR2_MADDS_64: 6736 CHECK_REG_PAIR(r4); 6737 CHECK_REG_PAIR(r3); 6738 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6739 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6740 break; 6741 case OPC2_32_RRR2_MADD_U_64: 6742 CHECK_REG_PAIR(r4); 6743 CHECK_REG_PAIR(r3); 6744 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6745 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6746 break; 6747 case OPC2_32_RRR2_MADDS_U_32: 6748 gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6749 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6750 break; 6751 case OPC2_32_RRR2_MADDS_U_64: 6752 CHECK_REG_PAIR(r4); 6753 CHECK_REG_PAIR(r3); 6754 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6755 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6756 break; 6757 default: 6758 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6759 } 6760 } 6761 6762 static void decode_rrr2_msub(DisasContext *ctx) 6763 { 6764 uint32_t op2; 6765 uint32_t r1, r2, r3, r4; 6766 6767 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6768 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6769 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6770 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6771 r4 = MASK_OP_RRR2_D(ctx->opcode); 6772 6773 switch (op2) { 6774 case OPC2_32_RRR2_MSUB_32: 6775 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6776 cpu_gpr_d[r2]); 6777 break; 6778 case OPC2_32_RRR2_MSUB_64: 6779 CHECK_REG_PAIR(r4); 6780 CHECK_REG_PAIR(r3); 6781 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6782 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6783 break; 6784 case OPC2_32_RRR2_MSUBS_32: 6785 gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6786 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6787 break; 6788 case OPC2_32_RRR2_MSUBS_64: 6789 CHECK_REG_PAIR(r4); 6790 CHECK_REG_PAIR(r3); 6791 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6792 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6793 break; 6794 case OPC2_32_RRR2_MSUB_U_64: 6795 CHECK_REG_PAIR(r4); 6796 CHECK_REG_PAIR(r3); 6797 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6798 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6799 break; 6800 case OPC2_32_RRR2_MSUBS_U_32: 6801 gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], 6802 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6803 break; 6804 case OPC2_32_RRR2_MSUBS_U_64: 6805 CHECK_REG_PAIR(r4); 6806 CHECK_REG_PAIR(r3); 6807 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6808 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6809 break; 6810 default: 6811 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6812 } 6813 } 6814 6815 /* RRR1 format */ 6816 static void decode_rrr1_madd(DisasContext *ctx) 6817 { 6818 uint32_t op2; 6819 uint32_t r1, r2, r3, r4, n; 6820 6821 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6822 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6823 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6824 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6825 r4 = MASK_OP_RRR1_D(ctx->opcode); 6826 n = MASK_OP_RRR1_N(ctx->opcode); 6827 6828 switch (op2) { 6829 case OPC2_32_RRR1_MADD_H_LL: 6830 CHECK_REG_PAIR(r4); 6831 CHECK_REG_PAIR(r3); 6832 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6833 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6834 break; 6835 case OPC2_32_RRR1_MADD_H_LU: 6836 CHECK_REG_PAIR(r4); 6837 CHECK_REG_PAIR(r3); 6838 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6839 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6840 break; 6841 case OPC2_32_RRR1_MADD_H_UL: 6842 CHECK_REG_PAIR(r4); 6843 CHECK_REG_PAIR(r3); 6844 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6845 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6846 break; 6847 case OPC2_32_RRR1_MADD_H_UU: 6848 CHECK_REG_PAIR(r4); 6849 CHECK_REG_PAIR(r3); 6850 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6851 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6852 break; 6853 case OPC2_32_RRR1_MADDS_H_LL: 6854 CHECK_REG_PAIR(r4); 6855 CHECK_REG_PAIR(r3); 6856 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6857 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6858 break; 6859 case OPC2_32_RRR1_MADDS_H_LU: 6860 CHECK_REG_PAIR(r4); 6861 CHECK_REG_PAIR(r3); 6862 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6863 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6864 break; 6865 case OPC2_32_RRR1_MADDS_H_UL: 6866 CHECK_REG_PAIR(r4); 6867 CHECK_REG_PAIR(r3); 6868 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6869 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6870 break; 6871 case OPC2_32_RRR1_MADDS_H_UU: 6872 CHECK_REG_PAIR(r4); 6873 CHECK_REG_PAIR(r3); 6874 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6875 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6876 break; 6877 case OPC2_32_RRR1_MADDM_H_LL: 6878 CHECK_REG_PAIR(r4); 6879 CHECK_REG_PAIR(r3); 6880 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6881 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6882 break; 6883 case OPC2_32_RRR1_MADDM_H_LU: 6884 CHECK_REG_PAIR(r4); 6885 CHECK_REG_PAIR(r3); 6886 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6887 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6888 break; 6889 case OPC2_32_RRR1_MADDM_H_UL: 6890 CHECK_REG_PAIR(r4); 6891 CHECK_REG_PAIR(r3); 6892 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6893 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6894 break; 6895 case OPC2_32_RRR1_MADDM_H_UU: 6896 CHECK_REG_PAIR(r4); 6897 CHECK_REG_PAIR(r3); 6898 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6899 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6900 break; 6901 case OPC2_32_RRR1_MADDMS_H_LL: 6902 CHECK_REG_PAIR(r4); 6903 CHECK_REG_PAIR(r3); 6904 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6905 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6906 break; 6907 case OPC2_32_RRR1_MADDMS_H_LU: 6908 CHECK_REG_PAIR(r4); 6909 CHECK_REG_PAIR(r3); 6910 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6911 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6912 break; 6913 case OPC2_32_RRR1_MADDMS_H_UL: 6914 CHECK_REG_PAIR(r4); 6915 CHECK_REG_PAIR(r3); 6916 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6917 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6918 break; 6919 case OPC2_32_RRR1_MADDMS_H_UU: 6920 CHECK_REG_PAIR(r4); 6921 CHECK_REG_PAIR(r3); 6922 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6923 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6924 break; 6925 case OPC2_32_RRR1_MADDR_H_LL: 6926 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6927 cpu_gpr_d[r2], n, MODE_LL); 6928 break; 6929 case OPC2_32_RRR1_MADDR_H_LU: 6930 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6931 cpu_gpr_d[r2], n, MODE_LU); 6932 break; 6933 case OPC2_32_RRR1_MADDR_H_UL: 6934 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6935 cpu_gpr_d[r2], n, MODE_UL); 6936 break; 6937 case OPC2_32_RRR1_MADDR_H_UU: 6938 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6939 cpu_gpr_d[r2], n, MODE_UU); 6940 break; 6941 case OPC2_32_RRR1_MADDRS_H_LL: 6942 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6943 cpu_gpr_d[r2], n, MODE_LL); 6944 break; 6945 case OPC2_32_RRR1_MADDRS_H_LU: 6946 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6947 cpu_gpr_d[r2], n, MODE_LU); 6948 break; 6949 case OPC2_32_RRR1_MADDRS_H_UL: 6950 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6951 cpu_gpr_d[r2], n, MODE_UL); 6952 break; 6953 case OPC2_32_RRR1_MADDRS_H_UU: 6954 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6955 cpu_gpr_d[r2], n, MODE_UU); 6956 break; 6957 default: 6958 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6959 } 6960 } 6961 6962 static void decode_rrr1_maddq_h(DisasContext *ctx) 6963 { 6964 uint32_t op2; 6965 uint32_t r1, r2, r3, r4, n; 6966 TCGv temp, temp2; 6967 6968 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6969 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6970 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6971 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6972 r4 = MASK_OP_RRR1_D(ctx->opcode); 6973 n = MASK_OP_RRR1_N(ctx->opcode); 6974 6975 temp = tcg_temp_new(); 6976 temp2 = tcg_temp_new(); 6977 6978 switch (op2) { 6979 case OPC2_32_RRR1_MADD_Q_32: 6980 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6981 cpu_gpr_d[r2], n, 32); 6982 break; 6983 case OPC2_32_RRR1_MADD_Q_64: 6984 CHECK_REG_PAIR(r4); 6985 CHECK_REG_PAIR(r3); 6986 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6987 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6988 n); 6989 break; 6990 case OPC2_32_RRR1_MADD_Q_32_L: 6991 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6992 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6993 temp, n, 16); 6994 break; 6995 case OPC2_32_RRR1_MADD_Q_64_L: 6996 CHECK_REG_PAIR(r4); 6997 CHECK_REG_PAIR(r3); 6998 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6999 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7000 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7001 n); 7002 break; 7003 case OPC2_32_RRR1_MADD_Q_32_U: 7004 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7005 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7006 temp, n, 16); 7007 break; 7008 case OPC2_32_RRR1_MADD_Q_64_U: 7009 CHECK_REG_PAIR(r4); 7010 CHECK_REG_PAIR(r3); 7011 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7012 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7013 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7014 n); 7015 break; 7016 case OPC2_32_RRR1_MADD_Q_32_LL: 7017 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7018 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7019 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7020 break; 7021 case OPC2_32_RRR1_MADD_Q_64_LL: 7022 CHECK_REG_PAIR(r4); 7023 CHECK_REG_PAIR(r3); 7024 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7025 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7026 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7027 cpu_gpr_d[r3+1], temp, temp2, n); 7028 break; 7029 case OPC2_32_RRR1_MADD_Q_32_UU: 7030 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7031 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7032 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7033 break; 7034 case OPC2_32_RRR1_MADD_Q_64_UU: 7035 CHECK_REG_PAIR(r4); 7036 CHECK_REG_PAIR(r3); 7037 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7038 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7039 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7040 cpu_gpr_d[r3+1], temp, temp2, n); 7041 break; 7042 case OPC2_32_RRR1_MADDS_Q_32: 7043 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7044 cpu_gpr_d[r2], n, 32); 7045 break; 7046 case OPC2_32_RRR1_MADDS_Q_64: 7047 CHECK_REG_PAIR(r4); 7048 CHECK_REG_PAIR(r3); 7049 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7050 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7051 n); 7052 break; 7053 case OPC2_32_RRR1_MADDS_Q_32_L: 7054 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7055 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7056 temp, n, 16); 7057 break; 7058 case OPC2_32_RRR1_MADDS_Q_64_L: 7059 CHECK_REG_PAIR(r4); 7060 CHECK_REG_PAIR(r3); 7061 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7062 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7063 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7064 n); 7065 break; 7066 case OPC2_32_RRR1_MADDS_Q_32_U: 7067 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7068 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7069 temp, n, 16); 7070 break; 7071 case OPC2_32_RRR1_MADDS_Q_64_U: 7072 CHECK_REG_PAIR(r4); 7073 CHECK_REG_PAIR(r3); 7074 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7075 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7076 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7077 n); 7078 break; 7079 case OPC2_32_RRR1_MADDS_Q_32_LL: 7080 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7081 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7082 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7083 break; 7084 case OPC2_32_RRR1_MADDS_Q_64_LL: 7085 CHECK_REG_PAIR(r4); 7086 CHECK_REG_PAIR(r3); 7087 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7088 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7089 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7090 cpu_gpr_d[r3+1], temp, temp2, n); 7091 break; 7092 case OPC2_32_RRR1_MADDS_Q_32_UU: 7093 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7094 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7095 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7096 break; 7097 case OPC2_32_RRR1_MADDS_Q_64_UU: 7098 CHECK_REG_PAIR(r4); 7099 CHECK_REG_PAIR(r3); 7100 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7101 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7102 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7103 cpu_gpr_d[r3+1], temp, temp2, n); 7104 break; 7105 case OPC2_32_RRR1_MADDR_H_64_UL: 7106 CHECK_REG_PAIR(r3); 7107 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7108 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7109 break; 7110 case OPC2_32_RRR1_MADDRS_H_64_UL: 7111 CHECK_REG_PAIR(r3); 7112 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7113 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7114 break; 7115 case OPC2_32_RRR1_MADDR_Q_32_LL: 7116 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7117 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7118 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7119 break; 7120 case OPC2_32_RRR1_MADDR_Q_32_UU: 7121 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7122 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7123 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7124 break; 7125 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7126 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7127 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7128 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7129 break; 7130 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7131 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7132 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7133 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7134 break; 7135 default: 7136 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7137 } 7138 } 7139 7140 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7141 { 7142 uint32_t op2; 7143 uint32_t r1, r2, r3, r4, n; 7144 7145 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7146 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7147 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7148 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7149 r4 = MASK_OP_RRR1_D(ctx->opcode); 7150 n = MASK_OP_RRR1_N(ctx->opcode); 7151 7152 switch (op2) { 7153 case OPC2_32_RRR1_MADDSU_H_32_LL: 7154 CHECK_REG_PAIR(r4); 7155 CHECK_REG_PAIR(r3); 7156 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7157 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7158 break; 7159 case OPC2_32_RRR1_MADDSU_H_32_LU: 7160 CHECK_REG_PAIR(r4); 7161 CHECK_REG_PAIR(r3); 7162 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7163 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7164 break; 7165 case OPC2_32_RRR1_MADDSU_H_32_UL: 7166 CHECK_REG_PAIR(r4); 7167 CHECK_REG_PAIR(r3); 7168 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7169 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7170 break; 7171 case OPC2_32_RRR1_MADDSU_H_32_UU: 7172 CHECK_REG_PAIR(r4); 7173 CHECK_REG_PAIR(r3); 7174 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7175 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7176 break; 7177 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7178 CHECK_REG_PAIR(r4); 7179 CHECK_REG_PAIR(r3); 7180 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7181 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7182 n, MODE_LL); 7183 break; 7184 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7185 CHECK_REG_PAIR(r4); 7186 CHECK_REG_PAIR(r3); 7187 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7188 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7189 n, MODE_LU); 7190 break; 7191 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7192 CHECK_REG_PAIR(r4); 7193 CHECK_REG_PAIR(r3); 7194 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7195 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7196 n, MODE_UL); 7197 break; 7198 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7199 CHECK_REG_PAIR(r4); 7200 CHECK_REG_PAIR(r3); 7201 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7202 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7203 n, MODE_UU); 7204 break; 7205 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7206 CHECK_REG_PAIR(r4); 7207 CHECK_REG_PAIR(r3); 7208 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7209 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7210 n, MODE_LL); 7211 break; 7212 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7213 CHECK_REG_PAIR(r4); 7214 CHECK_REG_PAIR(r3); 7215 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7216 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7217 n, MODE_LU); 7218 break; 7219 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7220 CHECK_REG_PAIR(r4); 7221 CHECK_REG_PAIR(r3); 7222 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7223 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7224 n, MODE_UL); 7225 break; 7226 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7227 CHECK_REG_PAIR(r4); 7228 CHECK_REG_PAIR(r3); 7229 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7230 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7231 n, MODE_UU); 7232 break; 7233 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7234 CHECK_REG_PAIR(r4); 7235 CHECK_REG_PAIR(r3); 7236 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7237 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7238 n, MODE_LL); 7239 break; 7240 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7241 CHECK_REG_PAIR(r4); 7242 CHECK_REG_PAIR(r3); 7243 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7244 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7245 n, MODE_LU); 7246 break; 7247 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7248 CHECK_REG_PAIR(r4); 7249 CHECK_REG_PAIR(r3); 7250 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7251 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7252 n, MODE_UL); 7253 break; 7254 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7255 CHECK_REG_PAIR(r4); 7256 CHECK_REG_PAIR(r3); 7257 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7258 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7259 n, MODE_UU); 7260 break; 7261 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7262 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7263 cpu_gpr_d[r2], n, MODE_LL); 7264 break; 7265 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7266 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7267 cpu_gpr_d[r2], n, MODE_LU); 7268 break; 7269 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7270 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7271 cpu_gpr_d[r2], n, MODE_UL); 7272 break; 7273 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7274 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7275 cpu_gpr_d[r2], n, MODE_UU); 7276 break; 7277 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7278 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7279 cpu_gpr_d[r2], n, MODE_LL); 7280 break; 7281 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7282 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7283 cpu_gpr_d[r2], n, MODE_LU); 7284 break; 7285 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7286 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7287 cpu_gpr_d[r2], n, MODE_UL); 7288 break; 7289 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7290 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7291 cpu_gpr_d[r2], n, MODE_UU); 7292 break; 7293 default: 7294 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7295 } 7296 } 7297 7298 static void decode_rrr1_msub(DisasContext *ctx) 7299 { 7300 uint32_t op2; 7301 uint32_t r1, r2, r3, r4, n; 7302 7303 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7304 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7305 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7306 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7307 r4 = MASK_OP_RRR1_D(ctx->opcode); 7308 n = MASK_OP_RRR1_N(ctx->opcode); 7309 7310 switch (op2) { 7311 case OPC2_32_RRR1_MSUB_H_LL: 7312 CHECK_REG_PAIR(r4); 7313 CHECK_REG_PAIR(r3); 7314 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7315 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7316 break; 7317 case OPC2_32_RRR1_MSUB_H_LU: 7318 CHECK_REG_PAIR(r4); 7319 CHECK_REG_PAIR(r3); 7320 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7321 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7322 break; 7323 case OPC2_32_RRR1_MSUB_H_UL: 7324 CHECK_REG_PAIR(r4); 7325 CHECK_REG_PAIR(r3); 7326 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7327 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7328 break; 7329 case OPC2_32_RRR1_MSUB_H_UU: 7330 CHECK_REG_PAIR(r4); 7331 CHECK_REG_PAIR(r3); 7332 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7333 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7334 break; 7335 case OPC2_32_RRR1_MSUBS_H_LL: 7336 CHECK_REG_PAIR(r4); 7337 CHECK_REG_PAIR(r3); 7338 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7339 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7340 break; 7341 case OPC2_32_RRR1_MSUBS_H_LU: 7342 CHECK_REG_PAIR(r4); 7343 CHECK_REG_PAIR(r3); 7344 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7345 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7346 break; 7347 case OPC2_32_RRR1_MSUBS_H_UL: 7348 CHECK_REG_PAIR(r4); 7349 CHECK_REG_PAIR(r3); 7350 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7351 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7352 break; 7353 case OPC2_32_RRR1_MSUBS_H_UU: 7354 CHECK_REG_PAIR(r4); 7355 CHECK_REG_PAIR(r3); 7356 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7357 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7358 break; 7359 case OPC2_32_RRR1_MSUBM_H_LL: 7360 CHECK_REG_PAIR(r4); 7361 CHECK_REG_PAIR(r3); 7362 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7363 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7364 break; 7365 case OPC2_32_RRR1_MSUBM_H_LU: 7366 CHECK_REG_PAIR(r4); 7367 CHECK_REG_PAIR(r3); 7368 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7369 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7370 break; 7371 case OPC2_32_RRR1_MSUBM_H_UL: 7372 CHECK_REG_PAIR(r4); 7373 CHECK_REG_PAIR(r3); 7374 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7375 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7376 break; 7377 case OPC2_32_RRR1_MSUBM_H_UU: 7378 CHECK_REG_PAIR(r4); 7379 CHECK_REG_PAIR(r3); 7380 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7381 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7382 break; 7383 case OPC2_32_RRR1_MSUBMS_H_LL: 7384 CHECK_REG_PAIR(r4); 7385 CHECK_REG_PAIR(r3); 7386 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7387 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7388 break; 7389 case OPC2_32_RRR1_MSUBMS_H_LU: 7390 CHECK_REG_PAIR(r4); 7391 CHECK_REG_PAIR(r3); 7392 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7393 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7394 break; 7395 case OPC2_32_RRR1_MSUBMS_H_UL: 7396 CHECK_REG_PAIR(r4); 7397 CHECK_REG_PAIR(r3); 7398 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7399 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7400 break; 7401 case OPC2_32_RRR1_MSUBMS_H_UU: 7402 CHECK_REG_PAIR(r4); 7403 CHECK_REG_PAIR(r3); 7404 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7405 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7406 break; 7407 case OPC2_32_RRR1_MSUBR_H_LL: 7408 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7409 cpu_gpr_d[r2], n, MODE_LL); 7410 break; 7411 case OPC2_32_RRR1_MSUBR_H_LU: 7412 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7413 cpu_gpr_d[r2], n, MODE_LU); 7414 break; 7415 case OPC2_32_RRR1_MSUBR_H_UL: 7416 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7417 cpu_gpr_d[r2], n, MODE_UL); 7418 break; 7419 case OPC2_32_RRR1_MSUBR_H_UU: 7420 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7421 cpu_gpr_d[r2], n, MODE_UU); 7422 break; 7423 case OPC2_32_RRR1_MSUBRS_H_LL: 7424 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7425 cpu_gpr_d[r2], n, MODE_LL); 7426 break; 7427 case OPC2_32_RRR1_MSUBRS_H_LU: 7428 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7429 cpu_gpr_d[r2], n, MODE_LU); 7430 break; 7431 case OPC2_32_RRR1_MSUBRS_H_UL: 7432 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7433 cpu_gpr_d[r2], n, MODE_UL); 7434 break; 7435 case OPC2_32_RRR1_MSUBRS_H_UU: 7436 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7437 cpu_gpr_d[r2], n, MODE_UU); 7438 break; 7439 default: 7440 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7441 } 7442 } 7443 7444 static void decode_rrr1_msubq_h(DisasContext *ctx) 7445 { 7446 uint32_t op2; 7447 uint32_t r1, r2, r3, r4, n; 7448 TCGv temp, temp2; 7449 7450 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7451 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7452 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7453 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7454 r4 = MASK_OP_RRR1_D(ctx->opcode); 7455 n = MASK_OP_RRR1_N(ctx->opcode); 7456 7457 temp = tcg_temp_new(); 7458 temp2 = tcg_temp_new(); 7459 7460 switch (op2) { 7461 case OPC2_32_RRR1_MSUB_Q_32: 7462 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7463 cpu_gpr_d[r2], n, 32); 7464 break; 7465 case OPC2_32_RRR1_MSUB_Q_64: 7466 CHECK_REG_PAIR(r4); 7467 CHECK_REG_PAIR(r3); 7468 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7469 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7470 n); 7471 break; 7472 case OPC2_32_RRR1_MSUB_Q_32_L: 7473 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7474 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7475 temp, n, 16); 7476 break; 7477 case OPC2_32_RRR1_MSUB_Q_64_L: 7478 CHECK_REG_PAIR(r4); 7479 CHECK_REG_PAIR(r3); 7480 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7481 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7482 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7483 n); 7484 break; 7485 case OPC2_32_RRR1_MSUB_Q_32_U: 7486 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7487 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7488 temp, n, 16); 7489 break; 7490 case OPC2_32_RRR1_MSUB_Q_64_U: 7491 CHECK_REG_PAIR(r4); 7492 CHECK_REG_PAIR(r3); 7493 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7494 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7495 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7496 n); 7497 break; 7498 case OPC2_32_RRR1_MSUB_Q_32_LL: 7499 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7500 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7501 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7502 break; 7503 case OPC2_32_RRR1_MSUB_Q_64_LL: 7504 CHECK_REG_PAIR(r4); 7505 CHECK_REG_PAIR(r3); 7506 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7507 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7508 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7509 cpu_gpr_d[r3+1], temp, temp2, n); 7510 break; 7511 case OPC2_32_RRR1_MSUB_Q_32_UU: 7512 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7513 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7514 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7515 break; 7516 case OPC2_32_RRR1_MSUB_Q_64_UU: 7517 CHECK_REG_PAIR(r4); 7518 CHECK_REG_PAIR(r3); 7519 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7520 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7521 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7522 cpu_gpr_d[r3+1], temp, temp2, n); 7523 break; 7524 case OPC2_32_RRR1_MSUBS_Q_32: 7525 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7526 cpu_gpr_d[r2], n, 32); 7527 break; 7528 case OPC2_32_RRR1_MSUBS_Q_64: 7529 CHECK_REG_PAIR(r4); 7530 CHECK_REG_PAIR(r3); 7531 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7532 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7533 n); 7534 break; 7535 case OPC2_32_RRR1_MSUBS_Q_32_L: 7536 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7537 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7538 temp, n, 16); 7539 break; 7540 case OPC2_32_RRR1_MSUBS_Q_64_L: 7541 CHECK_REG_PAIR(r4); 7542 CHECK_REG_PAIR(r3); 7543 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7544 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7545 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7546 n); 7547 break; 7548 case OPC2_32_RRR1_MSUBS_Q_32_U: 7549 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7550 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7551 temp, n, 16); 7552 break; 7553 case OPC2_32_RRR1_MSUBS_Q_64_U: 7554 CHECK_REG_PAIR(r4); 7555 CHECK_REG_PAIR(r3); 7556 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7557 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7558 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7559 n); 7560 break; 7561 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7562 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7563 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7564 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7565 break; 7566 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7567 CHECK_REG_PAIR(r4); 7568 CHECK_REG_PAIR(r3); 7569 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7570 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7571 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7572 cpu_gpr_d[r3+1], temp, temp2, n); 7573 break; 7574 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7575 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7576 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7577 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7578 break; 7579 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7580 CHECK_REG_PAIR(r4); 7581 CHECK_REG_PAIR(r3); 7582 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7583 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7584 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7585 cpu_gpr_d[r3+1], temp, temp2, n); 7586 break; 7587 case OPC2_32_RRR1_MSUBR_H_64_UL: 7588 CHECK_REG_PAIR(r3); 7589 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7590 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7591 break; 7592 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7593 CHECK_REG_PAIR(r3); 7594 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7595 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7596 break; 7597 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7598 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7599 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7600 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7601 break; 7602 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7603 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7604 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7605 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7606 break; 7607 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7608 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7609 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7610 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7611 break; 7612 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7613 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7614 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7615 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7616 break; 7617 default: 7618 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7619 } 7620 } 7621 7622 static void decode_rrr1_msubad_h(DisasContext *ctx) 7623 { 7624 uint32_t op2; 7625 uint32_t r1, r2, r3, r4, n; 7626 7627 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7628 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7629 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7630 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7631 r4 = MASK_OP_RRR1_D(ctx->opcode); 7632 n = MASK_OP_RRR1_N(ctx->opcode); 7633 7634 switch (op2) { 7635 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7636 CHECK_REG_PAIR(r4); 7637 CHECK_REG_PAIR(r3); 7638 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7639 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7640 break; 7641 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7642 CHECK_REG_PAIR(r4); 7643 CHECK_REG_PAIR(r3); 7644 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7645 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7646 break; 7647 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7648 CHECK_REG_PAIR(r4); 7649 CHECK_REG_PAIR(r3); 7650 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7651 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7652 break; 7653 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7654 CHECK_REG_PAIR(r4); 7655 CHECK_REG_PAIR(r3); 7656 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7657 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7658 break; 7659 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7660 CHECK_REG_PAIR(r4); 7661 CHECK_REG_PAIR(r3); 7662 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7663 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7664 n, MODE_LL); 7665 break; 7666 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7667 CHECK_REG_PAIR(r4); 7668 CHECK_REG_PAIR(r3); 7669 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7670 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7671 n, MODE_LU); 7672 break; 7673 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7674 CHECK_REG_PAIR(r4); 7675 CHECK_REG_PAIR(r3); 7676 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7677 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7678 n, MODE_UL); 7679 break; 7680 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7681 CHECK_REG_PAIR(r4); 7682 CHECK_REG_PAIR(r3); 7683 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7684 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7685 n, MODE_UU); 7686 break; 7687 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7688 CHECK_REG_PAIR(r4); 7689 CHECK_REG_PAIR(r3); 7690 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7691 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7692 n, MODE_LL); 7693 break; 7694 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7695 CHECK_REG_PAIR(r4); 7696 CHECK_REG_PAIR(r3); 7697 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7698 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7699 n, MODE_LU); 7700 break; 7701 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7702 CHECK_REG_PAIR(r4); 7703 CHECK_REG_PAIR(r3); 7704 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7705 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7706 n, MODE_UL); 7707 break; 7708 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7709 CHECK_REG_PAIR(r4); 7710 CHECK_REG_PAIR(r3); 7711 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7712 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7713 n, MODE_UU); 7714 break; 7715 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7716 CHECK_REG_PAIR(r4); 7717 CHECK_REG_PAIR(r3); 7718 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7719 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7720 n, MODE_LL); 7721 break; 7722 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7723 CHECK_REG_PAIR(r4); 7724 CHECK_REG_PAIR(r3); 7725 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7726 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7727 n, MODE_LU); 7728 break; 7729 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7730 CHECK_REG_PAIR(r4); 7731 CHECK_REG_PAIR(r3); 7732 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7733 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7734 n, MODE_UL); 7735 break; 7736 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7737 CHECK_REG_PAIR(r4); 7738 CHECK_REG_PAIR(r3); 7739 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7740 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7741 n, MODE_UU); 7742 break; 7743 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7744 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7745 cpu_gpr_d[r2], n, MODE_LL); 7746 break; 7747 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7748 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7749 cpu_gpr_d[r2], n, MODE_LU); 7750 break; 7751 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7752 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7753 cpu_gpr_d[r2], n, MODE_UL); 7754 break; 7755 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7756 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7757 cpu_gpr_d[r2], n, MODE_UU); 7758 break; 7759 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7760 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7761 cpu_gpr_d[r2], n, MODE_LL); 7762 break; 7763 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7764 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7765 cpu_gpr_d[r2], n, MODE_LU); 7766 break; 7767 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7768 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7769 cpu_gpr_d[r2], n, MODE_UL); 7770 break; 7771 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7772 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7773 cpu_gpr_d[r2], n, MODE_UU); 7774 break; 7775 default: 7776 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7777 } 7778 } 7779 7780 /* RRRR format */ 7781 static void decode_rrrr_extract_insert(DisasContext *ctx) 7782 { 7783 uint32_t op2; 7784 int r1, r2, r3, r4; 7785 TCGv tmp_width, tmp_pos; 7786 7787 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7788 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7789 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7790 r4 = MASK_OP_RRRR_D(ctx->opcode); 7791 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7792 7793 tmp_pos = tcg_temp_new(); 7794 tmp_width = tcg_temp_new(); 7795 7796 switch (op2) { 7797 case OPC2_32_RRRR_DEXTR: 7798 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7799 if (r1 == r2) { 7800 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7801 } else { 7802 TCGv msw = tcg_temp_new(); 7803 TCGv zero = tcg_constant_tl(0); 7804 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7805 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7806 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7807 /* 7808 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7809 * behaviour. So check that case here and set the low bits to zero 7810 * which effectivly returns cpu_gpr_d[r1] 7811 */ 7812 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7813 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7814 } 7815 break; 7816 case OPC2_32_RRRR_EXTR: 7817 case OPC2_32_RRRR_EXTR_U: 7818 CHECK_REG_PAIR(r3); 7819 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7820 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7821 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7822 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7823 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7824 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7825 if (op2 == OPC2_32_RRRR_EXTR) { 7826 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7827 } else { 7828 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7829 } 7830 break; 7831 case OPC2_32_RRRR_INSERT: 7832 CHECK_REG_PAIR(r3); 7833 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7834 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7835 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7836 tmp_pos); 7837 break; 7838 default: 7839 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7840 } 7841 } 7842 7843 /* RRRW format */ 7844 static void decode_rrrw_extract_insert(DisasContext *ctx) 7845 { 7846 uint32_t op2; 7847 int r1, r2, r3, r4; 7848 int32_t width; 7849 7850 TCGv temp, temp2; 7851 7852 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7853 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7854 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7855 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7856 r4 = MASK_OP_RRRW_D(ctx->opcode); 7857 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7858 7859 temp = tcg_temp_new(); 7860 7861 switch (op2) { 7862 case OPC2_32_RRRW_EXTR: 7863 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7864 tcg_gen_addi_tl(temp, temp, width); 7865 tcg_gen_subfi_tl(temp, 32, temp); 7866 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7867 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7868 break; 7869 case OPC2_32_RRRW_EXTR_U: 7870 if (width == 0) { 7871 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7872 } else { 7873 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7874 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7875 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7876 } 7877 break; 7878 case OPC2_32_RRRW_IMASK: 7879 temp2 = tcg_temp_new(); 7880 CHECK_REG_PAIR(r4); 7881 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7882 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7883 tcg_gen_shl_tl(temp2, temp2, temp); 7884 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7885 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7886 break; 7887 case OPC2_32_RRRW_INSERT: 7888 temp2 = tcg_temp_new(); 7889 7890 tcg_gen_movi_tl(temp, width); 7891 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7892 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7893 break; 7894 default: 7895 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7896 } 7897 } 7898 7899 /* SYS Format*/ 7900 static void decode_sys_interrupts(DisasContext *ctx) 7901 { 7902 uint32_t op2; 7903 uint32_t r1; 7904 TCGLabel *l1; 7905 TCGv tmp; 7906 7907 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7908 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7909 7910 switch (op2) { 7911 case OPC2_32_SYS_DEBUG: 7912 /* raise EXCP_DEBUG */ 7913 break; 7914 case OPC2_32_SYS_DISABLE: 7915 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7916 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7917 } else { 7918 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7919 } 7920 break; 7921 case OPC2_32_SYS_DISABLE_D: 7922 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7923 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7924 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, 7925 ctx->icr_ie_offset, 1); 7926 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7927 } else { 7928 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7929 } 7930 } else { 7931 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7932 } 7933 case OPC2_32_SYS_DSYNC: 7934 break; 7935 case OPC2_32_SYS_ENABLE: 7936 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7937 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); 7938 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7939 } else { 7940 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7941 } 7942 break; 7943 case OPC2_32_SYS_ISYNC: 7944 break; 7945 case OPC2_32_SYS_NOP: 7946 break; 7947 case OPC2_32_SYS_RET: 7948 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7949 break; 7950 case OPC2_32_SYS_FRET: 7951 gen_fret(ctx); 7952 break; 7953 case OPC2_32_SYS_RFE: 7954 gen_helper_rfe(tcg_env); 7955 ctx->base.is_jmp = DISAS_EXIT; 7956 break; 7957 case OPC2_32_SYS_RFM: 7958 if (ctx->priv == TRICORE_PRIV_SM) { 7959 tmp = tcg_temp_new(); 7960 l1 = gen_new_label(); 7961 7962 tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR)); 7963 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7964 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7965 gen_helper_rfm(tcg_env); 7966 gen_set_label(l1); 7967 ctx->base.is_jmp = DISAS_EXIT; 7968 } else { 7969 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7970 } 7971 break; 7972 case OPC2_32_SYS_RSLCX: 7973 gen_helper_rslcx(tcg_env); 7974 break; 7975 case OPC2_32_SYS_SVLCX: 7976 gen_helper_svlcx(tcg_env); 7977 break; 7978 case OPC2_32_SYS_RESTORE: 7979 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7980 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7981 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 7982 ctx->icr_ie_offset, 1); 7983 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7984 } else { 7985 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7986 } 7987 } else { 7988 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7989 } 7990 break; 7991 case OPC2_32_SYS_TRAPSV: 7992 l1 = gen_new_label(); 7993 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7994 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7995 gen_set_label(l1); 7996 break; 7997 case OPC2_32_SYS_TRAPV: 7998 l1 = gen_new_label(); 7999 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 8000 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8001 gen_set_label(l1); 8002 break; 8003 default: 8004 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8005 } 8006 } 8007 8008 static void decode_32Bit_opc(DisasContext *ctx) 8009 { 8010 int op1, op2; 8011 int32_t r1, r2, r3; 8012 int32_t address, const16; 8013 int8_t b, const4; 8014 int32_t bpos; 8015 TCGv temp, temp2, temp3; 8016 8017 op1 = MASK_OP_MAJOR(ctx->opcode); 8018 8019 /* handle JNZ.T opcode only being 7 bit long */ 8020 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8021 op1 = OPCM_32_BRN_JTT; 8022 } 8023 8024 switch (op1) { 8025 /* ABS-format */ 8026 case OPCM_32_ABS_LDW: 8027 decode_abs_ldw(ctx); 8028 break; 8029 case OPCM_32_ABS_LDB: 8030 decode_abs_ldb(ctx); 8031 break; 8032 case OPCM_32_ABS_LDMST_SWAP: 8033 decode_abs_ldst_swap(ctx); 8034 break; 8035 case OPCM_32_ABS_LDST_CONTEXT: 8036 decode_abs_ldst_context(ctx); 8037 break; 8038 case OPCM_32_ABS_STORE: 8039 decode_abs_store(ctx); 8040 break; 8041 case OPCM_32_ABS_STOREB_H: 8042 decode_abs_storeb_h(ctx); 8043 break; 8044 case OPC1_32_ABS_STOREQ: 8045 address = MASK_OP_ABS_OFF18(ctx->opcode); 8046 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8047 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8048 temp2 = tcg_temp_new(); 8049 8050 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8051 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8052 break; 8053 case OPC1_32_ABS_LD_Q: 8054 address = MASK_OP_ABS_OFF18(ctx->opcode); 8055 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8056 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8057 8058 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8059 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8060 break; 8061 case OPCM_32_ABS_LEA_LHA: 8062 address = MASK_OP_ABS_OFF18(ctx->opcode); 8063 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8064 8065 if (has_feature(ctx, TRICORE_FEATURE_162)) { 8066 op2 = MASK_OP_ABS_OP2(ctx->opcode); 8067 if (op2 == OPC2_32_ABS_LHA) { 8068 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); 8069 break; 8070 } 8071 /* otherwise translate regular LEA */ 8072 } 8073 8074 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8075 break; 8076 /* ABSB-format */ 8077 case OPC1_32_ABSB_ST_T: 8078 address = MASK_OP_ABS_OFF18(ctx->opcode); 8079 b = MASK_OP_ABSB_B(ctx->opcode); 8080 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8081 8082 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8083 temp2 = tcg_temp_new(); 8084 8085 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8086 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8087 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8088 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8089 break; 8090 /* B-format */ 8091 case OPC1_32_B_CALL: 8092 case OPC1_32_B_CALLA: 8093 case OPC1_32_B_FCALL: 8094 case OPC1_32_B_FCALLA: 8095 case OPC1_32_B_J: 8096 case OPC1_32_B_JA: 8097 case OPC1_32_B_JL: 8098 case OPC1_32_B_JLA: 8099 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8100 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8101 break; 8102 /* Bit-format */ 8103 case OPCM_32_BIT_ANDACC: 8104 decode_bit_andacc(ctx); 8105 break; 8106 case OPCM_32_BIT_LOGICAL_T1: 8107 decode_bit_logical_t(ctx); 8108 break; 8109 case OPCM_32_BIT_INSERT: 8110 decode_bit_insert(ctx); 8111 break; 8112 case OPCM_32_BIT_LOGICAL_T2: 8113 decode_bit_logical_t2(ctx); 8114 break; 8115 case OPCM_32_BIT_ORAND: 8116 decode_bit_orand(ctx); 8117 break; 8118 case OPCM_32_BIT_SH_LOGIC1: 8119 decode_bit_sh_logic1(ctx); 8120 break; 8121 case OPCM_32_BIT_SH_LOGIC2: 8122 decode_bit_sh_logic2(ctx); 8123 break; 8124 /* BO Format */ 8125 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8126 decode_bo_addrmode_post_pre_base(ctx); 8127 break; 8128 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8129 decode_bo_addrmode_bitreverse_circular(ctx); 8130 break; 8131 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8132 decode_bo_addrmode_ld_post_pre_base(ctx); 8133 break; 8134 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8135 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8136 break; 8137 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8138 decode_bo_addrmode_stctx_post_pre_base(ctx); 8139 break; 8140 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8141 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8142 break; 8143 /* BOL-format */ 8144 case OPC1_32_BOL_LD_A_LONGOFF: 8145 case OPC1_32_BOL_LD_W_LONGOFF: 8146 case OPC1_32_BOL_LEA_LONGOFF: 8147 case OPC1_32_BOL_ST_W_LONGOFF: 8148 case OPC1_32_BOL_ST_A_LONGOFF: 8149 case OPC1_32_BOL_LD_B_LONGOFF: 8150 case OPC1_32_BOL_LD_BU_LONGOFF: 8151 case OPC1_32_BOL_LD_H_LONGOFF: 8152 case OPC1_32_BOL_LD_HU_LONGOFF: 8153 case OPC1_32_BOL_ST_B_LONGOFF: 8154 case OPC1_32_BOL_ST_H_LONGOFF: 8155 decode_bol_opc(ctx, op1); 8156 break; 8157 /* BRC Format */ 8158 case OPCM_32_BRC_EQ_NEQ: 8159 case OPCM_32_BRC_GE: 8160 case OPCM_32_BRC_JLT: 8161 case OPCM_32_BRC_JNE: 8162 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8163 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8164 r1 = MASK_OP_BRC_S1(ctx->opcode); 8165 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8166 break; 8167 /* BRN Format */ 8168 case OPCM_32_BRN_JTT: 8169 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8170 r1 = MASK_OP_BRN_S1(ctx->opcode); 8171 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8172 break; 8173 /* BRR Format */ 8174 case OPCM_32_BRR_EQ_NEQ: 8175 case OPCM_32_BRR_ADDR_EQ_NEQ: 8176 case OPCM_32_BRR_GE: 8177 case OPCM_32_BRR_JLT: 8178 case OPCM_32_BRR_JNE: 8179 case OPCM_32_BRR_JNZ: 8180 case OPCM_32_BRR_LOOP: 8181 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8182 r2 = MASK_OP_BRR_S2(ctx->opcode); 8183 r1 = MASK_OP_BRR_S1(ctx->opcode); 8184 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8185 break; 8186 /* RC Format */ 8187 case OPCM_32_RC_LOGICAL_SHIFT: 8188 decode_rc_logical_shift(ctx); 8189 break; 8190 case OPCM_32_RC_ACCUMULATOR: 8191 decode_rc_accumulator(ctx); 8192 break; 8193 case OPCM_32_RC_SERVICEROUTINE: 8194 decode_rc_serviceroutine(ctx); 8195 break; 8196 case OPCM_32_RC_MUL: 8197 decode_rc_mul(ctx); 8198 break; 8199 /* RCPW Format */ 8200 case OPCM_32_RCPW_MASK_INSERT: 8201 decode_rcpw_insert(ctx); 8202 break; 8203 /* RCRR Format */ 8204 case OPC1_32_RCRR_INSERT: 8205 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8206 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8207 r3 = MASK_OP_RCRR_D(ctx->opcode); 8208 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8209 temp = tcg_constant_i32(const16); 8210 temp2 = tcg_temp_new(); /* width*/ 8211 temp3 = tcg_temp_new(); /* pos */ 8212 8213 CHECK_REG_PAIR(r2); 8214 8215 tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f); 8216 tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f); 8217 8218 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); 8219 break; 8220 /* RCRW Format */ 8221 case OPCM_32_RCRW_MASK_INSERT: 8222 decode_rcrw_insert(ctx); 8223 break; 8224 /* RCR Format */ 8225 case OPCM_32_RCR_COND_SELECT: 8226 decode_rcr_cond_select(ctx); 8227 break; 8228 case OPCM_32_RCR_MADD: 8229 decode_rcr_madd(ctx); 8230 break; 8231 case OPCM_32_RCR_MSUB: 8232 decode_rcr_msub(ctx); 8233 break; 8234 /* RLC Format */ 8235 case OPC1_32_RLC_ADDI: 8236 case OPC1_32_RLC_ADDIH: 8237 case OPC1_32_RLC_ADDIH_A: 8238 case OPC1_32_RLC_MFCR: 8239 case OPC1_32_RLC_MOV: 8240 case OPC1_32_RLC_MOV_64: 8241 case OPC1_32_RLC_MOV_U: 8242 case OPC1_32_RLC_MOV_H: 8243 case OPC1_32_RLC_MOVH_A: 8244 case OPC1_32_RLC_MTCR: 8245 decode_rlc_opc(ctx, op1); 8246 break; 8247 /* RR Format */ 8248 case OPCM_32_RR_ACCUMULATOR: 8249 decode_rr_accumulator(ctx); 8250 break; 8251 case OPCM_32_RR_LOGICAL_SHIFT: 8252 decode_rr_logical_shift(ctx); 8253 break; 8254 case OPCM_32_RR_ADDRESS: 8255 decode_rr_address(ctx); 8256 break; 8257 case OPCM_32_RR_IDIRECT: 8258 decode_rr_idirect(ctx); 8259 break; 8260 case OPCM_32_RR_DIVIDE: 8261 decode_rr_divide(ctx); 8262 break; 8263 /* RR1 Format */ 8264 case OPCM_32_RR1_MUL: 8265 decode_rr1_mul(ctx); 8266 break; 8267 case OPCM_32_RR1_MULQ: 8268 decode_rr1_mulq(ctx); 8269 break; 8270 /* RR2 format */ 8271 case OPCM_32_RR2_MUL: 8272 decode_rr2_mul(ctx); 8273 break; 8274 /* RRPW format */ 8275 case OPCM_32_RRPW_EXTRACT_INSERT: 8276 decode_rrpw_extract_insert(ctx); 8277 break; 8278 case OPC1_32_RRPW_DEXTR: 8279 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8280 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8281 r3 = MASK_OP_RRPW_D(ctx->opcode); 8282 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8283 8284 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8285 32 - const16); 8286 break; 8287 /* RRR Format */ 8288 case OPCM_32_RRR_COND_SELECT: 8289 decode_rrr_cond_select(ctx); 8290 break; 8291 case OPCM_32_RRR_DIVIDE: 8292 decode_rrr_divide(ctx); 8293 break; 8294 /* RRR2 Format */ 8295 case OPCM_32_RRR2_MADD: 8296 decode_rrr2_madd(ctx); 8297 break; 8298 case OPCM_32_RRR2_MSUB: 8299 decode_rrr2_msub(ctx); 8300 break; 8301 /* RRR1 format */ 8302 case OPCM_32_RRR1_MADD: 8303 decode_rrr1_madd(ctx); 8304 break; 8305 case OPCM_32_RRR1_MADDQ_H: 8306 decode_rrr1_maddq_h(ctx); 8307 break; 8308 case OPCM_32_RRR1_MADDSU_H: 8309 decode_rrr1_maddsu_h(ctx); 8310 break; 8311 case OPCM_32_RRR1_MSUB_H: 8312 decode_rrr1_msub(ctx); 8313 break; 8314 case OPCM_32_RRR1_MSUB_Q: 8315 decode_rrr1_msubq_h(ctx); 8316 break; 8317 case OPCM_32_RRR1_MSUBAD_H: 8318 decode_rrr1_msubad_h(ctx); 8319 break; 8320 /* RRRR format */ 8321 case OPCM_32_RRRR_EXTRACT_INSERT: 8322 decode_rrrr_extract_insert(ctx); 8323 break; 8324 /* RRRW format */ 8325 case OPCM_32_RRRW_EXTRACT_INSERT: 8326 decode_rrrw_extract_insert(ctx); 8327 break; 8328 /* SYS format */ 8329 case OPCM_32_SYS_INTERRUPTS: 8330 decode_sys_interrupts(ctx); 8331 break; 8332 case OPC1_32_SYS_RSTV: 8333 tcg_gen_movi_tl(cpu_PSW_V, 0); 8334 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8335 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8336 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8337 break; 8338 default: 8339 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8340 } 8341 } 8342 8343 static bool tricore_insn_is_16bit(uint32_t insn) 8344 { 8345 return (insn & 0x1) == 0; 8346 } 8347 8348 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8349 CPUState *cs) 8350 { 8351 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8352 CPUTriCoreState *env = cpu_env(cs); 8353 ctx->mem_idx = cpu_mmu_index(cs, false); 8354 8355 uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; 8356 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 8357 8358 ctx->features = env->features; 8359 if (has_feature(ctx, TRICORE_FEATURE_161)) { 8360 ctx->icr_ie_mask = R_ICR_IE_161_MASK; 8361 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; 8362 } else { 8363 ctx->icr_ie_mask = R_ICR_IE_13_MASK; 8364 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; 8365 } 8366 } 8367 8368 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8369 { 8370 } 8371 8372 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8373 { 8374 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8375 8376 tcg_gen_insn_start(ctx->base.pc_next); 8377 } 8378 8379 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8380 { 8381 /* 8382 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8383 * (False positives are OK, false negatives are not.) 8384 * Our caller ensures we are only called if dc->base.pc_next is less than 8385 * 4 bytes from the page boundary, so we cross the page if the first 8386 * 16 bits indicate that this is a 32 bit insn. 8387 */ 8388 uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8389 8390 return !tricore_insn_is_16bit(insn); 8391 } 8392 8393 8394 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8395 { 8396 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8397 CPUTriCoreState *env = cpu_env(cpu); 8398 uint16_t insn_lo; 8399 bool is_16bit; 8400 8401 insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next); 8402 is_16bit = tricore_insn_is_16bit(insn_lo); 8403 if (is_16bit) { 8404 ctx->opcode = insn_lo; 8405 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8406 decode_16Bit_opc(ctx); 8407 } else { 8408 uint32_t insn_hi = translator_lduw(env, &ctx->base, 8409 ctx->base.pc_next + 2); 8410 ctx->opcode = insn_hi << 16 | insn_lo; 8411 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8412 decode_32Bit_opc(ctx); 8413 } 8414 ctx->base.pc_next = ctx->pc_succ_insn; 8415 8416 if (ctx->base.is_jmp == DISAS_NEXT) { 8417 target_ulong page_start; 8418 8419 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8420 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8421 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8422 && insn_crosses_page(env, ctx))) { 8423 ctx->base.is_jmp = DISAS_TOO_MANY; 8424 } 8425 } 8426 } 8427 8428 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8429 { 8430 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8431 8432 switch (ctx->base.is_jmp) { 8433 case DISAS_TOO_MANY: 8434 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8435 break; 8436 case DISAS_EXIT_UPDATE: 8437 gen_save_pc(ctx->base.pc_next); 8438 /* fall through */ 8439 case DISAS_EXIT: 8440 tcg_gen_exit_tb(NULL, 0); 8441 break; 8442 case DISAS_JUMP: 8443 tcg_gen_lookup_and_goto_ptr(); 8444 break; 8445 case DISAS_NORETURN: 8446 break; 8447 default: 8448 g_assert_not_reached(); 8449 } 8450 } 8451 8452 static const TranslatorOps tricore_tr_ops = { 8453 .init_disas_context = tricore_tr_init_disas_context, 8454 .tb_start = tricore_tr_tb_start, 8455 .insn_start = tricore_tr_insn_start, 8456 .translate_insn = tricore_tr_translate_insn, 8457 .tb_stop = tricore_tr_tb_stop, 8458 }; 8459 8460 void tricore_translate_code(CPUState *cs, TranslationBlock *tb, 8461 int *max_insns, vaddr pc, void *host_pc) 8462 { 8463 DisasContext ctx; 8464 translator_loop(cs, tb, max_insns, pc, host_pc, 8465 &tricore_tr_ops, &ctx.base); 8466 } 8467 8468 /* 8469 * 8470 * Initialization 8471 * 8472 */ 8473 8474 void cpu_state_reset(CPUTriCoreState *env) 8475 { 8476 /* Reset Regs to Default Value */ 8477 env->PSW = 0xb80; 8478 fpu_set_state(env); 8479 } 8480 8481 static void tricore_tcg_init_csfr(void) 8482 { 8483 cpu_PCXI = tcg_global_mem_new(tcg_env, 8484 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8485 cpu_PSW = tcg_global_mem_new(tcg_env, 8486 offsetof(CPUTriCoreState, PSW), "PSW"); 8487 cpu_PC = tcg_global_mem_new(tcg_env, 8488 offsetof(CPUTriCoreState, PC), "PC"); 8489 cpu_ICR = tcg_global_mem_new(tcg_env, 8490 offsetof(CPUTriCoreState, ICR), "ICR"); 8491 } 8492 8493 void tricore_tcg_init(void) 8494 { 8495 int i; 8496 8497 /* reg init */ 8498 for (i = 0 ; i < 16 ; i++) { 8499 cpu_gpr_a[i] = tcg_global_mem_new(tcg_env, 8500 offsetof(CPUTriCoreState, gpr_a[i]), 8501 regnames_a[i]); 8502 } 8503 for (i = 0 ; i < 16 ; i++) { 8504 cpu_gpr_d[i] = tcg_global_mem_new(tcg_env, 8505 offsetof(CPUTriCoreState, gpr_d[i]), 8506 regnames_d[i]); 8507 } 8508 tricore_tcg_init_csfr(); 8509 /* init PSW flag cache */ 8510 cpu_PSW_C = tcg_global_mem_new(tcg_env, 8511 offsetof(CPUTriCoreState, PSW_USB_C), 8512 "PSW_C"); 8513 cpu_PSW_V = tcg_global_mem_new(tcg_env, 8514 offsetof(CPUTriCoreState, PSW_USB_V), 8515 "PSW_V"); 8516 cpu_PSW_SV = tcg_global_mem_new(tcg_env, 8517 offsetof(CPUTriCoreState, PSW_USB_SV), 8518 "PSW_SV"); 8519 cpu_PSW_AV = tcg_global_mem_new(tcg_env, 8520 offsetof(CPUTriCoreState, PSW_USB_AV), 8521 "PSW_AV"); 8522 cpu_PSW_SAV = tcg_global_mem_new(tcg_env, 8523 offsetof(CPUTriCoreState, PSW_USB_SAV), 8524 "PSW_SAV"); 8525 } 8526