1 /* 2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "hw/registerfields.h" 21 #include "cpu.h" 22 #include "exec/cputlb.h" 23 #include "accel/tcg/cpu-mmu-index.h" 24 #include "exec/page-protection.h" 25 #include "exec/target_page.h" 26 #include "fpu/softfloat-helpers.h" 27 #include "qemu/qemu-print.h" 28 29 enum { 30 TLBRET_DIRTY = -4, 31 TLBRET_INVALID = -3, 32 TLBRET_NOMATCH = -2, 33 TLBRET_BADADDR = -1, 34 TLBRET_MATCH = 0 35 }; 36 37 static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, 38 int *prot, target_ulong address, 39 MMUAccessType access_type, int mmu_idx) 40 { 41 int ret = TLBRET_MATCH; 42 43 *physical = address & 0xFFFFFFFF; 44 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 45 46 return ret; 47 } 48 49 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 50 { 51 TriCoreCPU *cpu = TRICORE_CPU(cs); 52 hwaddr phys_addr; 53 int prot; 54 int mmu_idx = cpu_mmu_index(cs, false); 55 56 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 57 MMU_DATA_LOAD, mmu_idx)) { 58 return -1; 59 } 60 return phys_addr; 61 } 62 63 /* TODO: Add exception support */ 64 static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, 65 int rw, int tlb_error) 66 { 67 } 68 69 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 70 MMUAccessType rw, int mmu_idx, 71 bool probe, uintptr_t retaddr) 72 { 73 CPUTriCoreState *env = cpu_env(cs); 74 hwaddr physical; 75 int prot; 76 int ret = 0; 77 78 rw &= 1; 79 ret = get_physical_address(env, &physical, &prot, 80 address, rw, mmu_idx); 81 82 qemu_log_mask(CPU_LOG_MMU, "%s address=0x%" VADDR_PRIx " ret %d physical " 83 HWADDR_FMT_plx " prot %d\n", 84 __func__, address, ret, physical, prot); 85 86 if (ret == TLBRET_MATCH) { 87 tlb_set_page(cs, address & TARGET_PAGE_MASK, 88 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, 89 mmu_idx, TARGET_PAGE_SIZE); 90 return true; 91 } else { 92 assert(ret < 0); 93 if (probe) { 94 return false; 95 } 96 raise_mmu_exception(env, address, rw, ret); 97 cpu_loop_exit_restore(cs, retaddr); 98 } 99 } 100 101 void fpu_set_state(CPUTriCoreState *env) 102 { 103 switch (extract32(env->PSW, 24, 2)) { 104 case 0: 105 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 106 break; 107 case 1: 108 set_float_rounding_mode(float_round_up, &env->fp_status); 109 break; 110 case 2: 111 set_float_rounding_mode(float_round_down, &env->fp_status); 112 break; 113 case 3: 114 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 115 break; 116 } 117 118 set_flush_inputs_to_zero(1, &env->fp_status); 119 set_flush_to_zero(1, &env->fp_status); 120 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 121 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 122 set_default_nan_mode(1, &env->fp_status); 123 /* Default NaN pattern: sign bit clear, frac msb set */ 124 set_float_default_nan_pattern(0b01000000, &env->fp_status); 125 } 126 127 uint32_t psw_read(CPUTriCoreState *env) 128 { 129 /* clear all USB bits */ 130 env->PSW &= 0x7ffffff; 131 /* now set them from the cache */ 132 env->PSW |= ((env->PSW_USB_C != 0) << 31); 133 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); 134 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2); 135 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3); 136 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4); 137 138 return env->PSW; 139 } 140 141 void psw_write(CPUTriCoreState *env, uint32_t val) 142 { 143 env->PSW_USB_C = (val & MASK_USB_C); 144 env->PSW_USB_V = (val & MASK_USB_V) << 1; 145 env->PSW_USB_SV = (val & MASK_USB_SV) << 2; 146 env->PSW_USB_AV = (val & MASK_USB_AV) << 3; 147 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4; 148 env->PSW = val; 149 150 fpu_set_state(env); 151 } 152 153 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 154 uint32_t NAME(CPUTriCoreState *env) \ 155 { \ 156 if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 157 return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \ 158 } \ 159 return FIELD_EX32(env->REG, REG, FIELD ## _13); \ 160 } 161 162 #define FIELD_GETTER(NAME, REG, FIELD) \ 163 uint32_t NAME(CPUTriCoreState *env) \ 164 { \ 165 return FIELD_EX32(env->REG, REG, FIELD); \ 166 } 167 168 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 169 void NAME(CPUTriCoreState *env, uint32_t val) \ 170 { \ 171 if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 172 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \ 173 } \ 174 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \ 175 } 176 177 #define FIELD_SETTER(NAME, REG, FIELD) \ 178 void NAME(CPUTriCoreState *env, uint32_t val) \ 179 { \ 180 env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \ 181 } 182 183 FIELD_GETTER_WITH_FEATURE(pcxi_get_pcpn, PCXI, PCPN, 161) 184 FIELD_SETTER_WITH_FEATURE(pcxi_set_pcpn, PCXI, PCPN, 161) 185 FIELD_GETTER_WITH_FEATURE(pcxi_get_pie, PCXI, PIE, 161) 186 FIELD_SETTER_WITH_FEATURE(pcxi_set_pie, PCXI, PIE, 161) 187 FIELD_GETTER_WITH_FEATURE(pcxi_get_ul, PCXI, UL, 161) 188 FIELD_SETTER_WITH_FEATURE(pcxi_set_ul, PCXI, UL, 161) 189 FIELD_GETTER(pcxi_get_pcxs, PCXI, PCXS) 190 FIELD_GETTER(pcxi_get_pcxo, PCXI, PCXO) 191 192 FIELD_GETTER_WITH_FEATURE(icr_get_ie, ICR, IE, 161) 193 FIELD_SETTER_WITH_FEATURE(icr_set_ie, ICR, IE, 161) 194 FIELD_GETTER(icr_get_ccpn, ICR, CCPN) 195 FIELD_SETTER(icr_set_ccpn, ICR, CCPN) 196