1 /* 2 * TriCore emulation for qemu: main CPU struct. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef TRICORE_CPU_H 21 #define TRICORE_CPU_H 22 23 #include "cpu-qom.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-common.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "tricore-defs.h" 29 30 #ifdef CONFIG_USER_ONLY 31 #error "TriCore does not support user mode emulation" 32 #endif 33 34 typedef struct CPUArchState { 35 /* GPR Register */ 36 uint32_t gpr_a[16]; 37 uint32_t gpr_d[16]; 38 /* Frequently accessed PSW_USB bits are stored separately for efficiency. 39 This contains all the other bits. Use psw_{read,write} to access 40 the whole PSW. */ 41 uint32_t PSW; 42 /* PSW flag cache for faster execution */ 43 uint32_t PSW_USB_C; 44 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ 45 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ 46 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ 47 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ 48 49 #define R(ADDR, NAME, FEATURE) uint32_t NAME; 50 #define A(ADDR, NAME, FEATURE) uint32_t NAME; 51 #define E(ADDR, NAME, FEATURE) uint32_t NAME; 52 #include "csfr.h.inc" 53 #undef R 54 #undef A 55 #undef E 56 57 /* Floating Point Registers */ 58 float_status fp_status; 59 60 /* Internal CPU feature flags. */ 61 uint64_t features; 62 } CPUTriCoreState; 63 64 /** 65 * TriCoreCPU: 66 * @env: #CPUTriCoreState 67 * 68 * A TriCore CPU. 69 */ 70 struct ArchCPU { 71 CPUState parent_obj; 72 73 CPUTriCoreState env; 74 }; 75 76 struct TriCoreCPUClass { 77 CPUClass parent_class; 78 79 DeviceRealize parent_realize; 80 ResettablePhases parent_phases; 81 }; 82 83 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 84 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 85 86 FIELD(PCXI, PCPN_13, 24, 8) 87 FIELD(PCXI, PCPN_161, 22, 8) 88 FIELD(PCXI, PIE_13, 23, 1) 89 FIELD(PCXI, PIE_161, 21, 1) 90 FIELD(PCXI, UL_13, 22, 1) 91 FIELD(PCXI, UL_161, 20, 1) 92 FIELD(PCXI, PCXS, 16, 4) 93 FIELD(PCXI, PCXO, 0, 16) 94 uint32_t pcxi_get_ul(CPUTriCoreState *env); 95 uint32_t pcxi_get_pie(CPUTriCoreState *env); 96 uint32_t pcxi_get_pcpn(CPUTriCoreState *env); 97 uint32_t pcxi_get_pcxs(CPUTriCoreState *env); 98 uint32_t pcxi_get_pcxo(CPUTriCoreState *env); 99 void pcxi_set_ul(CPUTriCoreState *env, uint32_t val); 100 void pcxi_set_pie(CPUTriCoreState *env, uint32_t val); 101 void pcxi_set_pcpn(CPUTriCoreState *env, uint32_t val); 102 103 FIELD(ICR, IE_161, 15, 1) 104 FIELD(ICR, IE_13, 8, 1) 105 FIELD(ICR, PIPN, 16, 8) 106 FIELD(ICR, CCPN, 0, 8) 107 108 uint32_t icr_get_ie(CPUTriCoreState *env); 109 uint32_t icr_get_ccpn(CPUTriCoreState *env); 110 111 void icr_set_ccpn(CPUTriCoreState *env, uint32_t val); 112 void icr_set_ie(CPUTriCoreState *env, uint32_t val); 113 114 #define MASK_PSW_USB 0xff000000 115 #define MASK_USB_C 0x80000000 116 #define MASK_USB_V 0x40000000 117 #define MASK_USB_SV 0x20000000 118 #define MASK_USB_AV 0x10000000 119 #define MASK_USB_SAV 0x08000000 120 #define MASK_PSW_PRS 0x00003000 121 #define MASK_PSW_IO 0x00000c00 122 #define MASK_PSW_IS 0x00000200 123 #define MASK_PSW_GW 0x00000100 124 #define MASK_PSW_CDE 0x00000080 125 #define MASK_PSW_CDC 0x0000007f 126 #define MASK_PSW_FPU_RM 0x3000000 127 128 #define MASK_SYSCON_PRO_TEN 0x2 129 #define MASK_SYSCON_FCD_SF 0x1 130 131 #define MASK_CPUID_MOD 0xffff0000 132 #define MASK_CPUID_MOD_32B 0x0000ff00 133 #define MASK_CPUID_REV 0x000000ff 134 135 136 #define MASK_FCX_FCXS 0x000f0000 137 #define MASK_FCX_FCXO 0x0000ffff 138 139 #define MASK_LCX_LCXS 0x000f0000 140 #define MASK_LCX_LCX0 0x0000ffff 141 142 #define MASK_DBGSR_DE 0x1 143 #define MASK_DBGSR_HALT 0x6 144 #define MASK_DBGSR_SUSP 0x10 145 #define MASK_DBGSR_PREVSUSP 0x20 146 #define MASK_DBGSR_PEVT 0x40 147 #define MASK_DBGSR_EVTSRC 0x1f00 148 149 enum tricore_priv_levels { 150 TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */ 151 TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */ 152 TRICORE_PRIV_SM = 0x2, /* kernel mode flag */ 153 }; 154 155 enum tricore_features { 156 TRICORE_FEATURE_13, 157 TRICORE_FEATURE_131, 158 TRICORE_FEATURE_16, 159 TRICORE_FEATURE_161, 160 TRICORE_FEATURE_162, 161 }; 162 163 static inline int tricore_has_feature(CPUTriCoreState *env, int feature) 164 { 165 return (env->features & (1ULL << feature)) != 0; 166 } 167 168 /* TriCore Traps Classes*/ 169 enum { 170 TRAPC_NONE = -1, 171 TRAPC_MMU = 0, 172 TRAPC_PROT = 1, 173 TRAPC_INSN_ERR = 2, 174 TRAPC_CTX_MNG = 3, 175 TRAPC_SYSBUS = 4, 176 TRAPC_ASSERT = 5, 177 TRAPC_SYSCALL = 6, 178 TRAPC_NMI = 7, 179 TRAPC_IRQ = 8 180 }; 181 182 /* Class 0 TIN */ 183 enum { 184 TIN0_VAF = 0, 185 TIN0_VAP = 1, 186 }; 187 188 /* Class 1 TIN */ 189 enum { 190 TIN1_PRIV = 1, 191 TIN1_MPR = 2, 192 TIN1_MPW = 3, 193 TIN1_MPX = 4, 194 TIN1_MPP = 5, 195 TIN1_MPN = 6, 196 TIN1_GRWP = 7, 197 }; 198 199 /* Class 2 TIN */ 200 enum { 201 TIN2_IOPC = 1, 202 TIN2_UOPC = 2, 203 TIN2_OPD = 3, 204 TIN2_ALN = 4, 205 TIN2_MEM = 5, 206 }; 207 208 /* Class 3 TIN */ 209 enum { 210 TIN3_FCD = 1, 211 TIN3_CDO = 2, 212 TIN3_CDU = 3, 213 TIN3_FCU = 4, 214 TIN3_CSU = 5, 215 TIN3_CTYP = 6, 216 TIN3_NEST = 7, 217 }; 218 219 /* Class 4 TIN */ 220 enum { 221 TIN4_PSE = 1, 222 TIN4_DSE = 2, 223 TIN4_DAE = 3, 224 TIN4_CAE = 4, 225 TIN4_PIE = 5, 226 TIN4_DIE = 6, 227 }; 228 229 /* Class 5 TIN */ 230 enum { 231 TIN5_OVF = 1, 232 TIN5_SOVF = 1, 233 }; 234 235 /* Class 6 TIN 236 * 237 * Is always TIN6_SYS 238 */ 239 240 /* Class 7 TIN */ 241 enum { 242 TIN7_NMI = 0, 243 }; 244 245 uint32_t psw_read(CPUTriCoreState *env); 246 void psw_write(CPUTriCoreState *env, uint32_t val); 247 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); 248 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); 249 250 void fpu_set_state(CPUTriCoreState *env); 251 252 #define MMU_USER_IDX 2 253 254 FIELD(TB_FLAGS, PRIV, 0, 2) 255 256 void cpu_state_reset(CPUTriCoreState *s); 257 void tricore_tcg_init(void); 258 void tricore_translate_code(CPUState *cs, TranslationBlock *tb, 259 int *max_insns, vaddr pc, void *host_pc); 260 261 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, 262 uint64_t *cs_base, uint32_t *flags) 263 { 264 uint32_t new_flags = 0; 265 *pc = env->PC; 266 *cs_base = 0; 267 268 new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, 269 extract32(env->PSW, 10, 2)); 270 *flags = new_flags; 271 } 272 273 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU 274 275 /* helpers.c */ 276 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 277 MMUAccessType access_type, int mmu_idx, 278 bool probe, uintptr_t retaddr); 279 280 #endif /* TRICORE_CPU_H */ 281