1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/range.h" 23 #include "cpu.h" 24 #include "tcg/tcg.h" 25 #include "exec/helper-proto.h" 26 #include "exec/exec-all.h" 27 #include "exec/cputlb.h" 28 #include "exec/page-protection.h" 29 #include "exec/target_page.h" 30 #include "accel/tcg/cpu-ldst.h" 31 #include "system/memory.h" 32 #ifdef CONFIG_USER_ONLY 33 #include "user/page-protection.h" 34 #endif 35 #include "asi.h" 36 37 //#define DEBUG_MMU 38 //#define DEBUG_MXCC 39 //#define DEBUG_UNASSIGNED 40 //#define DEBUG_ASI 41 //#define DEBUG_CACHE_CONTROL 42 43 #ifdef DEBUG_MMU 44 #define DPRINTF_MMU(fmt, ...) \ 45 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 46 #else 47 #define DPRINTF_MMU(fmt, ...) do {} while (0) 48 #endif 49 50 #ifdef DEBUG_MXCC 51 #define DPRINTF_MXCC(fmt, ...) \ 52 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 53 #else 54 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 55 #endif 56 57 #ifdef DEBUG_ASI 58 #define DPRINTF_ASI(fmt, ...) \ 59 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 60 #endif 61 62 #ifdef DEBUG_CACHE_CONTROL 63 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 64 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 65 #else 66 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 67 #endif 68 69 #ifdef TARGET_SPARC64 70 #ifndef TARGET_ABI32 71 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 72 #else 73 #define AM_CHECK(env1) (1) 74 #endif 75 #endif 76 77 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 78 /* Calculates TSB pointer value for fault page size 79 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 80 * UA2005 holds the page size configuration in mmu_ctx registers */ 81 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 82 const SparcV9MMU *mmu, const int idx) 83 { 84 uint64_t tsb_register; 85 int page_size; 86 if (cpu_has_hypervisor(env)) { 87 int tsb_index = 0; 88 int ctx = mmu->tag_access & 0x1fffULL; 89 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 90 tsb_index = idx; 91 tsb_index |= ctx ? 2 : 0; 92 page_size = idx ? ctx_register >> 8 : ctx_register; 93 page_size &= 7; 94 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 95 } else { 96 page_size = idx; 97 tsb_register = mmu->tsb; 98 } 99 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 100 int tsb_size = tsb_register & 0xf; 101 102 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 103 104 /* move va bits to correct position, 105 * the context bits will be masked out later */ 106 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 107 108 /* calculate tsb_base mask and adjust va if split is in use */ 109 if (tsb_split) { 110 if (idx == 0) { 111 va &= ~(1ULL << (13 + tsb_size)); 112 } else { 113 va |= (1ULL << (13 + tsb_size)); 114 } 115 tsb_base_mask <<= 1; 116 } 117 118 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 119 } 120 121 /* Calculates tag target register value by reordering bits 122 in tag access register */ 123 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 124 { 125 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 126 } 127 128 static void replace_tlb_entry(SparcTLBEntry *tlb, 129 uint64_t tlb_tag, uint64_t tlb_tte, 130 CPUSPARCState *env) 131 { 132 target_ulong mask, size, va, offset; 133 134 /* flush page range if translation is valid */ 135 if (TTE_IS_VALID(tlb->tte)) { 136 CPUState *cs = env_cpu(env); 137 138 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 139 mask = 1ULL + ~size; 140 141 va = tlb->tag & mask; 142 143 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 144 tlb_flush_page(cs, va + offset); 145 } 146 } 147 148 tlb->tag = tlb_tag; 149 tlb->tte = tlb_tte; 150 } 151 152 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 153 const char *strmmu, CPUSPARCState *env1) 154 { 155 unsigned int i; 156 target_ulong mask; 157 uint64_t context; 158 159 int is_demap_context = (demap_addr >> 6) & 1; 160 161 /* demap context */ 162 switch ((demap_addr >> 4) & 3) { 163 case 0: /* primary */ 164 context = env1->dmmu.mmu_primary_context; 165 break; 166 case 1: /* secondary */ 167 context = env1->dmmu.mmu_secondary_context; 168 break; 169 case 2: /* nucleus */ 170 context = 0; 171 break; 172 case 3: /* reserved */ 173 default: 174 return; 175 } 176 177 for (i = 0; i < 64; i++) { 178 if (TTE_IS_VALID(tlb[i].tte)) { 179 180 if (is_demap_context) { 181 /* will remove non-global entries matching context value */ 182 if (TTE_IS_GLOBAL(tlb[i].tte) || 183 !tlb_compare_context(&tlb[i], context)) { 184 continue; 185 } 186 } else { 187 /* demap page 188 will remove any entry matching VA */ 189 mask = 0xffffffffffffe000ULL; 190 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 191 192 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 193 continue; 194 } 195 196 /* entry should be global or matching context value */ 197 if (!TTE_IS_GLOBAL(tlb[i].tte) && 198 !tlb_compare_context(&tlb[i], context)) { 199 continue; 200 } 201 } 202 203 replace_tlb_entry(&tlb[i], 0, 0, env1); 204 #ifdef DEBUG_MMU 205 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 206 dump_mmu(env1); 207 #endif 208 } 209 } 210 } 211 212 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 213 uint64_t sun4v_tte) 214 { 215 uint64_t sun4u_tte; 216 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 217 /* is already in the sun4u format */ 218 return sun4v_tte; 219 } 220 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 221 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 222 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 223 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 224 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 225 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 226 TTE_SIDEEFFECT_BIT); 227 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 228 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 229 return sun4u_tte; 230 } 231 232 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 233 uint64_t tlb_tag, uint64_t tlb_tte, 234 const char *strmmu, CPUSPARCState *env1, 235 uint64_t addr) 236 { 237 unsigned int i, replace_used; 238 239 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 240 if (cpu_has_hypervisor(env1)) { 241 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 242 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 243 uint32_t new_ctx = tlb_tag & 0x1fffU; 244 for (i = 0; i < 64; i++) { 245 uint32_t ctx = tlb[i].tag & 0x1fffU; 246 /* check if new mapping overlaps an existing one */ 247 if (new_ctx == ctx) { 248 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 249 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 250 if (ranges_overlap(new_vaddr, new_size, vaddr, size)) { 251 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 252 new_vaddr); 253 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 254 return; 255 } 256 } 257 258 } 259 } 260 /* Try replacing invalid entry */ 261 for (i = 0; i < 64; i++) { 262 if (!TTE_IS_VALID(tlb[i].tte)) { 263 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 264 #ifdef DEBUG_MMU 265 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 266 dump_mmu(env1); 267 #endif 268 return; 269 } 270 } 271 272 /* All entries are valid, try replacing unlocked entry */ 273 274 for (replace_used = 0; replace_used < 2; ++replace_used) { 275 276 /* Used entries are not replaced on first pass */ 277 278 for (i = 0; i < 64; i++) { 279 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 280 281 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 282 #ifdef DEBUG_MMU 283 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 284 strmmu, (replace_used ? "used" : "unused"), i); 285 dump_mmu(env1); 286 #endif 287 return; 288 } 289 } 290 291 /* Now reset used bit and search for unused entries again */ 292 293 for (i = 0; i < 64; i++) { 294 TTE_SET_UNUSED(tlb[i].tte); 295 } 296 } 297 298 #ifdef DEBUG_MMU 299 DPRINTF_MMU("%s lru replacement: no free entries available, " 300 "replacing the last one\n", strmmu); 301 #endif 302 /* corner case: the last entry is replaced anyway */ 303 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 304 } 305 306 #endif 307 308 #ifdef TARGET_SPARC64 309 /* returns true if access using this ASI is to have address translated by MMU 310 otherwise access is to raw physical address */ 311 /* TODO: check sparc32 bits */ 312 static inline int is_translating_asi(int asi) 313 { 314 /* Ultrasparc IIi translating asi 315 - note this list is defined by cpu implementation 316 */ 317 switch (asi) { 318 case 0x04 ... 0x11: 319 case 0x16 ... 0x19: 320 case 0x1E ... 0x1F: 321 case 0x24 ... 0x2C: 322 case 0x70 ... 0x73: 323 case 0x78 ... 0x79: 324 case 0x80 ... 0xFF: 325 return 1; 326 327 default: 328 return 0; 329 } 330 } 331 332 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 333 { 334 if (AM_CHECK(env1)) { 335 addr &= 0xffffffffULL; 336 } 337 return addr; 338 } 339 340 static inline target_ulong asi_address_mask(CPUSPARCState *env, 341 int asi, target_ulong addr) 342 { 343 if (is_translating_asi(asi)) { 344 addr = address_mask(env, addr); 345 } 346 return addr; 347 } 348 349 #ifndef CONFIG_USER_ONLY 350 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 351 { 352 /* ASIs >= 0x80 are user mode. 353 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 354 * ASIs <= 0x2f are super mode. 355 */ 356 if (asi < 0x80 357 && !cpu_hypervisor_mode(env) 358 && (!cpu_supervisor_mode(env) 359 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 360 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 361 } 362 } 363 #endif /* !CONFIG_USER_ONLY */ 364 #endif 365 366 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 367 static void do_check_align(CPUSPARCState *env, target_ulong addr, 368 uint32_t align, uintptr_t ra) 369 { 370 if (addr & align) { 371 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 372 } 373 } 374 #endif 375 376 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 377 defined(DEBUG_MXCC) 378 static void dump_mxcc(CPUSPARCState *env) 379 { 380 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 381 "\n", 382 env->mxccdata[0], env->mxccdata[1], 383 env->mxccdata[2], env->mxccdata[3]); 384 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 385 "\n" 386 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 387 "\n", 388 env->mxccregs[0], env->mxccregs[1], 389 env->mxccregs[2], env->mxccregs[3], 390 env->mxccregs[4], env->mxccregs[5], 391 env->mxccregs[6], env->mxccregs[7]); 392 } 393 #endif 394 395 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 396 && defined(DEBUG_ASI) 397 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 398 uint64_t r1) 399 { 400 switch (size) { 401 case 1: 402 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 403 addr, asi, r1 & 0xff); 404 break; 405 case 2: 406 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 407 addr, asi, r1 & 0xffff); 408 break; 409 case 4: 410 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 411 addr, asi, r1 & 0xffffffff); 412 break; 413 case 8: 414 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 415 addr, asi, r1); 416 break; 417 } 418 } 419 #endif 420 421 #ifndef CONFIG_USER_ONLY 422 #ifndef TARGET_SPARC64 423 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 424 bool is_write, bool is_exec, int is_asi, 425 unsigned size, uintptr_t retaddr) 426 { 427 CPUSPARCState *env = cpu_env(cs); 428 int fault_type; 429 430 #ifdef DEBUG_UNASSIGNED 431 if (is_asi) { 432 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 433 " asi 0x%02x from " TARGET_FMT_lx "\n", 434 is_exec ? "exec" : is_write ? "write" : "read", size, 435 size == 1 ? "" : "s", addr, is_asi, env->pc); 436 } else { 437 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 438 " from " TARGET_FMT_lx "\n", 439 is_exec ? "exec" : is_write ? "write" : "read", size, 440 size == 1 ? "" : "s", addr, env->pc); 441 } 442 #endif 443 /* Don't overwrite translation and access faults */ 444 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 445 if ((fault_type > 4) || (fault_type == 0)) { 446 env->mmuregs[3] = 0; /* Fault status register */ 447 if (is_asi) { 448 env->mmuregs[3] |= 1 << 16; 449 } 450 if (env->psrs) { 451 env->mmuregs[3] |= 1 << 5; 452 } 453 if (is_exec) { 454 env->mmuregs[3] |= 1 << 6; 455 } 456 if (is_write) { 457 env->mmuregs[3] |= 1 << 7; 458 } 459 env->mmuregs[3] |= (5 << 2) | 2; 460 /* SuperSPARC will never place instruction fault addresses in the FAR */ 461 if (!is_exec) { 462 env->mmuregs[4] = addr; /* Fault address register */ 463 } 464 } 465 /* overflow (same type fault was not read before another fault) */ 466 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 467 env->mmuregs[3] |= 1; 468 } 469 470 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 471 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 472 cpu_raise_exception_ra(env, tt, retaddr); 473 } 474 475 /* 476 * flush neverland mappings created during no-fault mode, 477 * so the sequential MMU faults report proper fault types 478 */ 479 if (env->mmuregs[0] & MMU_NF) { 480 tlb_flush(cs); 481 } 482 } 483 #else 484 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 485 bool is_write, bool is_exec, int is_asi, 486 unsigned size, uintptr_t retaddr) 487 { 488 CPUSPARCState *env = cpu_env(cs); 489 490 #ifdef DEBUG_UNASSIGNED 491 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 492 "\n", addr, env->pc); 493 #endif 494 495 if (is_exec) { /* XXX has_hypervisor */ 496 if (env->lsu & (IMMU_E)) { 497 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 498 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 499 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 500 } 501 } else { 502 if (env->lsu & (DMMU_E)) { 503 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 504 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 505 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 506 } 507 } 508 } 509 #endif 510 #endif 511 512 #ifndef TARGET_SPARC64 513 #ifndef CONFIG_USER_ONLY 514 515 516 /* Leon3 cache control */ 517 518 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 519 uint64_t val, int size) 520 { 521 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 522 addr, val, size); 523 524 if (size != 4) { 525 DPRINTF_CACHE_CONTROL("32bits only\n"); 526 return; 527 } 528 529 switch (addr) { 530 case 0x00: /* Cache control */ 531 532 /* These values must always be read as zeros */ 533 val &= ~CACHE_CTRL_FD; 534 val &= ~CACHE_CTRL_FI; 535 val &= ~CACHE_CTRL_IB; 536 val &= ~CACHE_CTRL_IP; 537 val &= ~CACHE_CTRL_DP; 538 539 env->cache_control = val; 540 break; 541 case 0x04: /* Instruction cache configuration */ 542 case 0x08: /* Data cache configuration */ 543 /* Read Only */ 544 break; 545 default: 546 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 547 break; 548 }; 549 } 550 551 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 552 int size) 553 { 554 uint64_t ret = 0; 555 556 if (size != 4) { 557 DPRINTF_CACHE_CONTROL("32bits only\n"); 558 return 0; 559 } 560 561 switch (addr) { 562 case 0x00: /* Cache control */ 563 ret = env->cache_control; 564 break; 565 566 /* Configuration registers are read and only always keep those 567 predefined values */ 568 569 case 0x04: /* Instruction cache configuration */ 570 ret = 0x10220000; 571 break; 572 case 0x08: /* Data cache configuration */ 573 ret = 0x18220000; 574 break; 575 default: 576 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 577 break; 578 }; 579 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 580 addr, ret, size); 581 return ret; 582 } 583 584 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 585 int asi, uint32_t memop) 586 { 587 int size = 1 << (memop & MO_SIZE); 588 int sign = memop & MO_SIGN; 589 CPUState *cs = env_cpu(env); 590 uint64_t ret = 0; 591 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 592 uint32_t last_addr = addr; 593 #endif 594 595 do_check_align(env, addr, size - 1, GETPC()); 596 switch (asi) { 597 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 598 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 599 switch (addr) { 600 case 0x00: /* Leon3 Cache Control */ 601 case 0x08: /* Leon3 Instruction Cache config */ 602 case 0x0C: /* Leon3 Date Cache config */ 603 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 604 ret = leon3_cache_control_ld(env, addr, size); 605 } else { 606 qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented" 607 " address, size: %d\n", addr, size); 608 } 609 break; 610 case 0x01c00a00: /* MXCC control register */ 611 if (size == 8) { 612 ret = env->mxccregs[3]; 613 } else { 614 qemu_log_mask(LOG_UNIMP, 615 "%08x: unimplemented access size: %d\n", addr, 616 size); 617 } 618 break; 619 case 0x01c00a04: /* MXCC control register */ 620 if (size == 4) { 621 ret = env->mxccregs[3]; 622 } else { 623 qemu_log_mask(LOG_UNIMP, 624 "%08x: unimplemented access size: %d\n", addr, 625 size); 626 } 627 break; 628 case 0x01c00c00: /* Module reset register */ 629 if (size == 8) { 630 ret = env->mxccregs[5]; 631 /* should we do something here? */ 632 } else { 633 qemu_log_mask(LOG_UNIMP, 634 "%08x: unimplemented access size: %d\n", addr, 635 size); 636 } 637 break; 638 case 0x01c00f00: /* MBus port address register */ 639 if (size == 8) { 640 ret = env->mxccregs[7]; 641 } else { 642 qemu_log_mask(LOG_UNIMP, 643 "%08x: unimplemented access size: %d\n", addr, 644 size); 645 } 646 break; 647 default: 648 qemu_log_mask(LOG_UNIMP, 649 "%08x: unimplemented address, size: %d\n", addr, 650 size); 651 break; 652 } 653 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 654 "addr = %08x -> ret = %" PRIx64 "," 655 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 656 #ifdef DEBUG_MXCC 657 dump_mxcc(env); 658 #endif 659 break; 660 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 661 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 662 { 663 int mmulev; 664 665 mmulev = (addr >> 8) & 15; 666 if (mmulev > 4) { 667 ret = 0; 668 } else { 669 ret = mmu_probe(env, addr, mmulev); 670 } 671 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 672 addr, mmulev, ret); 673 } 674 break; 675 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 676 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 677 { 678 int reg = (addr >> 8) & 0x1f; 679 680 ret = env->mmuregs[reg]; 681 if (reg == 3) { /* Fault status cleared on read */ 682 env->mmuregs[3] = 0; 683 } else if (reg == 0x13) { /* Fault status read */ 684 ret = env->mmuregs[3]; 685 } else if (reg == 0x14) { /* Fault address read */ 686 ret = env->mmuregs[4]; 687 } 688 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 689 } 690 break; 691 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 692 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 693 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 694 break; 695 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 696 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 697 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 698 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 699 break; 700 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 701 { 702 MemTxResult result; 703 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 704 705 switch (size) { 706 case 1: 707 ret = address_space_ldub(cs->as, access_addr, 708 MEMTXATTRS_UNSPECIFIED, &result); 709 break; 710 case 2: 711 ret = address_space_lduw(cs->as, access_addr, 712 MEMTXATTRS_UNSPECIFIED, &result); 713 break; 714 default: 715 case 4: 716 ret = address_space_ldl(cs->as, access_addr, 717 MEMTXATTRS_UNSPECIFIED, &result); 718 break; 719 case 8: 720 ret = address_space_ldq(cs->as, access_addr, 721 MEMTXATTRS_UNSPECIFIED, &result); 722 break; 723 } 724 725 if (result != MEMTX_OK) { 726 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 727 size, GETPC()); 728 } 729 break; 730 } 731 case 0x30: /* Turbosparc secondary cache diagnostic */ 732 case 0x31: /* Turbosparc RAM snoop */ 733 case 0x32: /* Turbosparc page table descriptor diagnostic */ 734 case 0x39: /* data cache diagnostic register */ 735 ret = 0; 736 break; 737 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 738 { 739 int reg = (addr >> 8) & 3; 740 741 switch (reg) { 742 case 0: /* Breakpoint Value (Addr) */ 743 ret = env->mmubpregs[reg]; 744 break; 745 case 1: /* Breakpoint Mask */ 746 ret = env->mmubpregs[reg]; 747 break; 748 case 2: /* Breakpoint Control */ 749 ret = env->mmubpregs[reg]; 750 break; 751 case 3: /* Breakpoint Status */ 752 ret = env->mmubpregs[reg]; 753 env->mmubpregs[reg] = 0ULL; 754 break; 755 } 756 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 757 ret); 758 } 759 break; 760 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 761 ret = env->mmubpctrv; 762 break; 763 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 764 ret = env->mmubpctrc; 765 break; 766 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 767 ret = env->mmubpctrs; 768 break; 769 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 770 ret = env->mmubpaction; 771 break; 772 default: 773 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 774 ret = 0; 775 break; 776 777 case ASI_USERDATA: /* User data access */ 778 case ASI_KERNELDATA: /* Supervisor data access */ 779 case ASI_USERTXT: /* User code access */ 780 case ASI_KERNELTXT: /* Supervisor code access */ 781 case ASI_P: /* Implicit primary context data access (v9 only?) */ 782 case ASI_M_BYPASS: /* MMU passthrough */ 783 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 784 /* These are always handled inline. */ 785 g_assert_not_reached(); 786 } 787 if (sign) { 788 switch (size) { 789 case 1: 790 ret = (int8_t) ret; 791 break; 792 case 2: 793 ret = (int16_t) ret; 794 break; 795 case 4: 796 ret = (int32_t) ret; 797 break; 798 default: 799 break; 800 } 801 } 802 #ifdef DEBUG_ASI 803 dump_asi("read ", last_addr, asi, size, ret); 804 #endif 805 return ret; 806 } 807 808 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 809 int asi, uint32_t memop) 810 { 811 int size = 1 << (memop & MO_SIZE); 812 CPUState *cs = env_cpu(env); 813 814 do_check_align(env, addr, size - 1, GETPC()); 815 switch (asi) { 816 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 817 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 818 switch (addr) { 819 case 0x00: /* Leon3 Cache Control */ 820 case 0x08: /* Leon3 Instruction Cache config */ 821 case 0x0C: /* Leon3 Date Cache config */ 822 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 823 leon3_cache_control_st(env, addr, val, size); 824 } else { 825 qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented" 826 " address, size: %d\n", addr, size); 827 } 828 break; 829 830 case 0x01c00000: /* MXCC stream data register 0 */ 831 if (size == 8) { 832 env->mxccdata[0] = val; 833 } else { 834 qemu_log_mask(LOG_UNIMP, 835 "%08x: unimplemented access size: %d\n", addr, 836 size); 837 } 838 break; 839 case 0x01c00008: /* MXCC stream data register 1 */ 840 if (size == 8) { 841 env->mxccdata[1] = val; 842 } else { 843 qemu_log_mask(LOG_UNIMP, 844 "%08x: unimplemented access size: %d\n", addr, 845 size); 846 } 847 break; 848 case 0x01c00010: /* MXCC stream data register 2 */ 849 if (size == 8) { 850 env->mxccdata[2] = val; 851 } else { 852 qemu_log_mask(LOG_UNIMP, 853 "%08x: unimplemented access size: %d\n", addr, 854 size); 855 } 856 break; 857 case 0x01c00018: /* MXCC stream data register 3 */ 858 if (size == 8) { 859 env->mxccdata[3] = val; 860 } else { 861 qemu_log_mask(LOG_UNIMP, 862 "%08x: unimplemented access size: %d\n", addr, 863 size); 864 } 865 break; 866 case 0x01c00100: /* MXCC stream source */ 867 { 868 int i; 869 870 if (size == 8) { 871 env->mxccregs[0] = val; 872 } else { 873 qemu_log_mask(LOG_UNIMP, 874 "%08x: unimplemented access size: %d\n", addr, 875 size); 876 } 877 878 for (i = 0; i < 4; i++) { 879 MemTxResult result; 880 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 881 882 env->mxccdata[i] = address_space_ldq(cs->as, 883 access_addr, 884 MEMTXATTRS_UNSPECIFIED, 885 &result); 886 if (result != MEMTX_OK) { 887 /* TODO: investigate whether this is the right behaviour */ 888 sparc_raise_mmu_fault(cs, access_addr, false, false, 889 false, size, GETPC()); 890 } 891 } 892 break; 893 } 894 case 0x01c00200: /* MXCC stream destination */ 895 { 896 int i; 897 898 if (size == 8) { 899 env->mxccregs[1] = val; 900 } else { 901 qemu_log_mask(LOG_UNIMP, 902 "%08x: unimplemented access size: %d\n", addr, 903 size); 904 } 905 906 for (i = 0; i < 4; i++) { 907 MemTxResult result; 908 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 909 910 address_space_stq(cs->as, access_addr, env->mxccdata[i], 911 MEMTXATTRS_UNSPECIFIED, &result); 912 913 if (result != MEMTX_OK) { 914 /* TODO: investigate whether this is the right behaviour */ 915 sparc_raise_mmu_fault(cs, access_addr, true, false, 916 false, size, GETPC()); 917 } 918 } 919 break; 920 } 921 case 0x01c00a00: /* MXCC control register */ 922 if (size == 8) { 923 env->mxccregs[3] = val; 924 } else { 925 qemu_log_mask(LOG_UNIMP, 926 "%08x: unimplemented access size: %d\n", addr, 927 size); 928 } 929 break; 930 case 0x01c00a04: /* MXCC control register */ 931 if (size == 4) { 932 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 933 | val; 934 } else { 935 qemu_log_mask(LOG_UNIMP, 936 "%08x: unimplemented access size: %d\n", addr, 937 size); 938 } 939 break; 940 case 0x01c00e00: /* MXCC error register */ 941 /* writing a 1 bit clears the error */ 942 if (size == 8) { 943 env->mxccregs[6] &= ~val; 944 } else { 945 qemu_log_mask(LOG_UNIMP, 946 "%08x: unimplemented access size: %d\n", addr, 947 size); 948 } 949 break; 950 case 0x01c00f00: /* MBus port address register */ 951 if (size == 8) { 952 env->mxccregs[7] = val; 953 } else { 954 qemu_log_mask(LOG_UNIMP, 955 "%08x: unimplemented access size: %d\n", addr, 956 size); 957 } 958 break; 959 default: 960 qemu_log_mask(LOG_UNIMP, 961 "%08x: unimplemented address, size: %d\n", addr, 962 size); 963 break; 964 } 965 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 966 asi, size, addr, val); 967 #ifdef DEBUG_MXCC 968 dump_mxcc(env); 969 #endif 970 break; 971 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 972 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 973 { 974 int mmulev; 975 976 mmulev = (addr >> 8) & 15; 977 DPRINTF_MMU("mmu flush level %d\n", mmulev); 978 switch (mmulev) { 979 case 0: /* flush page */ 980 tlb_flush_page(cs, addr & 0xfffff000); 981 break; 982 case 1: /* flush segment (256k) */ 983 case 2: /* flush region (16M) */ 984 case 3: /* flush context (4G) */ 985 case 4: /* flush entire */ 986 tlb_flush(cs); 987 break; 988 default: 989 break; 990 } 991 #ifdef DEBUG_MMU 992 dump_mmu(env); 993 #endif 994 } 995 break; 996 case ASI_M_MMUREGS: /* write MMU regs */ 997 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 998 { 999 int reg = (addr >> 8) & 0x1f; 1000 uint32_t oldreg; 1001 1002 oldreg = env->mmuregs[reg]; 1003 switch (reg) { 1004 case 0: /* Control Register */ 1005 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 1006 (val & 0x00ffffff); 1007 /* Mappings generated during no-fault mode 1008 are invalid in normal mode. */ 1009 if ((oldreg ^ env->mmuregs[reg]) 1010 & (MMU_NF | env->def.mmu_bm)) { 1011 tlb_flush(cs); 1012 } 1013 break; 1014 case 1: /* Context Table Pointer Register */ 1015 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1016 break; 1017 case 2: /* Context Register */ 1018 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1019 if (oldreg != env->mmuregs[reg]) { 1020 /* we flush when the MMU context changes because 1021 QEMU has no MMU context support */ 1022 tlb_flush(cs); 1023 } 1024 break; 1025 case 3: /* Synchronous Fault Status Register with Clear */ 1026 case 4: /* Synchronous Fault Address Register */ 1027 break; 1028 case 0x10: /* TLB Replacement Control Register */ 1029 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1030 break; 1031 case 0x13: /* Synchronous Fault Status Register with Read 1032 and Clear */ 1033 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1034 break; 1035 case 0x14: /* Synchronous Fault Address Register */ 1036 env->mmuregs[4] = val; 1037 break; 1038 default: 1039 env->mmuregs[reg] = val; 1040 break; 1041 } 1042 if (oldreg != env->mmuregs[reg]) { 1043 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1044 reg, oldreg, env->mmuregs[reg]); 1045 } 1046 #ifdef DEBUG_MMU 1047 dump_mmu(env); 1048 #endif 1049 } 1050 break; 1051 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1052 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1053 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1054 break; 1055 case ASI_M_TXTC_TAG: /* I-cache tag */ 1056 case ASI_M_TXTC_DATA: /* I-cache data */ 1057 case ASI_M_DATAC_TAG: /* D-cache tag */ 1058 case ASI_M_DATAC_DATA: /* D-cache data */ 1059 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1060 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1061 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1062 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1063 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1064 break; 1065 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1066 { 1067 MemTxResult result; 1068 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1069 1070 switch (size) { 1071 case 1: 1072 address_space_stb(cs->as, access_addr, val, 1073 MEMTXATTRS_UNSPECIFIED, &result); 1074 break; 1075 case 2: 1076 address_space_stw(cs->as, access_addr, val, 1077 MEMTXATTRS_UNSPECIFIED, &result); 1078 break; 1079 case 4: 1080 default: 1081 address_space_stl(cs->as, access_addr, val, 1082 MEMTXATTRS_UNSPECIFIED, &result); 1083 break; 1084 case 8: 1085 address_space_stq(cs->as, access_addr, val, 1086 MEMTXATTRS_UNSPECIFIED, &result); 1087 break; 1088 } 1089 if (result != MEMTX_OK) { 1090 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1091 size, GETPC()); 1092 } 1093 } 1094 break; 1095 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1096 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1097 Turbosparc snoop RAM */ 1098 case 0x32: /* store buffer control or Turbosparc page table 1099 descriptor diagnostic */ 1100 case 0x36: /* I-cache flash clear */ 1101 case 0x37: /* D-cache flash clear */ 1102 break; 1103 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1104 { 1105 int reg = (addr >> 8) & 3; 1106 1107 switch (reg) { 1108 case 0: /* Breakpoint Value (Addr) */ 1109 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1110 break; 1111 case 1: /* Breakpoint Mask */ 1112 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1113 break; 1114 case 2: /* Breakpoint Control */ 1115 env->mmubpregs[reg] = (val & 0x7fULL); 1116 break; 1117 case 3: /* Breakpoint Status */ 1118 env->mmubpregs[reg] = (val & 0xfULL); 1119 break; 1120 } 1121 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1122 env->mmuregs[reg]); 1123 } 1124 break; 1125 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1126 env->mmubpctrv = val & 0xffffffff; 1127 break; 1128 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1129 env->mmubpctrc = val & 0x3; 1130 break; 1131 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1132 env->mmubpctrs = val & 0x3; 1133 break; 1134 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1135 env->mmubpaction = val & 0x1fff; 1136 break; 1137 case ASI_USERTXT: /* User code access, XXX */ 1138 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1139 default: 1140 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1141 break; 1142 1143 case ASI_USERDATA: /* User data access */ 1144 case ASI_KERNELDATA: /* Supervisor data access */ 1145 case ASI_P: 1146 case ASI_M_BYPASS: /* MMU passthrough */ 1147 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1148 case ASI_M_BCOPY: /* Block copy, sta access */ 1149 case ASI_M_BFILL: /* Block fill, stda access */ 1150 /* These are always handled inline. */ 1151 g_assert_not_reached(); 1152 } 1153 #ifdef DEBUG_ASI 1154 dump_asi("write", addr, asi, size, val); 1155 #endif 1156 } 1157 1158 uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi) 1159 { 1160 MemOp mop = get_memop(oi); 1161 uintptr_t ra = GETPC(); 1162 uint64_t ret; 1163 1164 switch (mop & MO_SIZE) { 1165 case MO_8: 1166 ret = cpu_ldb_code_mmu(env, addr, oi, ra); 1167 if (mop & MO_SIGN) { 1168 ret = (int8_t)ret; 1169 } 1170 break; 1171 case MO_16: 1172 ret = cpu_ldw_code_mmu(env, addr, oi, ra); 1173 if ((mop & MO_BSWAP) != MO_TE) { 1174 ret = bswap16(ret); 1175 } 1176 if (mop & MO_SIGN) { 1177 ret = (int16_t)ret; 1178 } 1179 break; 1180 case MO_32: 1181 ret = cpu_ldl_code_mmu(env, addr, oi, ra); 1182 if ((mop & MO_BSWAP) != MO_TE) { 1183 ret = bswap32(ret); 1184 } 1185 if (mop & MO_SIGN) { 1186 ret = (int32_t)ret; 1187 } 1188 break; 1189 case MO_64: 1190 ret = cpu_ldq_code_mmu(env, addr, oi, ra); 1191 if ((mop & MO_BSWAP) != MO_TE) { 1192 ret = bswap64(ret); 1193 } 1194 break; 1195 default: 1196 g_assert_not_reached(); 1197 } 1198 return ret; 1199 } 1200 1201 #endif /* CONFIG_USER_ONLY */ 1202 #else /* TARGET_SPARC64 */ 1203 1204 #ifdef CONFIG_USER_ONLY 1205 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1206 int asi, uint32_t memop) 1207 { 1208 int size = 1 << (memop & MO_SIZE); 1209 int sign = memop & MO_SIGN; 1210 uint64_t ret = 0; 1211 1212 if (asi < 0x80) { 1213 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1214 } 1215 do_check_align(env, addr, size - 1, GETPC()); 1216 addr = asi_address_mask(env, asi, addr); 1217 1218 switch (asi) { 1219 case ASI_PNF: /* Primary no-fault */ 1220 case ASI_PNFL: /* Primary no-fault LE */ 1221 case ASI_SNF: /* Secondary no-fault */ 1222 case ASI_SNFL: /* Secondary no-fault LE */ 1223 if (!page_check_range(addr, size, PAGE_READ)) { 1224 ret = 0; 1225 break; 1226 } 1227 switch (size) { 1228 case 1: 1229 ret = cpu_ldub_data(env, addr); 1230 break; 1231 case 2: 1232 ret = cpu_lduw_data(env, addr); 1233 break; 1234 case 4: 1235 ret = cpu_ldl_data(env, addr); 1236 break; 1237 case 8: 1238 ret = cpu_ldq_data(env, addr); 1239 break; 1240 default: 1241 g_assert_not_reached(); 1242 } 1243 break; 1244 break; 1245 1246 case ASI_P: /* Primary */ 1247 case ASI_PL: /* Primary LE */ 1248 case ASI_S: /* Secondary */ 1249 case ASI_SL: /* Secondary LE */ 1250 /* These are always handled inline. */ 1251 g_assert_not_reached(); 1252 1253 default: 1254 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1255 } 1256 1257 /* Convert from little endian */ 1258 switch (asi) { 1259 case ASI_PNFL: /* Primary no-fault LE */ 1260 case ASI_SNFL: /* Secondary no-fault LE */ 1261 switch (size) { 1262 case 2: 1263 ret = bswap16(ret); 1264 break; 1265 case 4: 1266 ret = bswap32(ret); 1267 break; 1268 case 8: 1269 ret = bswap64(ret); 1270 break; 1271 } 1272 } 1273 1274 /* Convert to signed number */ 1275 if (sign) { 1276 switch (size) { 1277 case 1: 1278 ret = (int8_t) ret; 1279 break; 1280 case 2: 1281 ret = (int16_t) ret; 1282 break; 1283 case 4: 1284 ret = (int32_t) ret; 1285 break; 1286 } 1287 } 1288 #ifdef DEBUG_ASI 1289 dump_asi("read", addr, asi, size, ret); 1290 #endif 1291 return ret; 1292 } 1293 1294 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1295 int asi, uint32_t memop) 1296 { 1297 int size = 1 << (memop & MO_SIZE); 1298 #ifdef DEBUG_ASI 1299 dump_asi("write", addr, asi, size, val); 1300 #endif 1301 if (asi < 0x80) { 1302 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1303 } 1304 do_check_align(env, addr, size - 1, GETPC()); 1305 1306 switch (asi) { 1307 case ASI_P: /* Primary */ 1308 case ASI_PL: /* Primary LE */ 1309 case ASI_S: /* Secondary */ 1310 case ASI_SL: /* Secondary LE */ 1311 /* These are always handled inline. */ 1312 g_assert_not_reached(); 1313 1314 case ASI_PNF: /* Primary no-fault, RO */ 1315 case ASI_SNF: /* Secondary no-fault, RO */ 1316 case ASI_PNFL: /* Primary no-fault LE, RO */ 1317 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1318 default: 1319 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1320 } 1321 } 1322 1323 #else /* CONFIG_USER_ONLY */ 1324 1325 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1326 int asi, uint32_t memop) 1327 { 1328 int size = 1 << (memop & MO_SIZE); 1329 int sign = memop & MO_SIGN; 1330 CPUState *cs = env_cpu(env); 1331 uint64_t ret = 0; 1332 #if defined(DEBUG_ASI) 1333 target_ulong last_addr = addr; 1334 #endif 1335 1336 asi &= 0xff; 1337 1338 do_check_asi(env, asi, GETPC()); 1339 do_check_align(env, addr, size - 1, GETPC()); 1340 addr = asi_address_mask(env, asi, addr); 1341 1342 switch (asi) { 1343 case ASI_PNF: 1344 case ASI_PNFL: 1345 case ASI_SNF: 1346 case ASI_SNFL: 1347 { 1348 MemOpIdx oi; 1349 int idx = (env->pstate & PS_PRIV 1350 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1351 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1352 1353 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1354 #ifdef DEBUG_ASI 1355 dump_asi("read ", last_addr, asi, size, ret); 1356 #endif 1357 /* exception_index is set in get_physical_address_data. */ 1358 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1359 } 1360 oi = make_memop_idx(memop, idx); 1361 switch (size) { 1362 case 1: 1363 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1364 break; 1365 case 2: 1366 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1367 break; 1368 case 4: 1369 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1370 break; 1371 case 8: 1372 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1373 break; 1374 default: 1375 g_assert_not_reached(); 1376 } 1377 } 1378 break; 1379 1380 case ASI_AIUP: /* As if user primary */ 1381 case ASI_AIUS: /* As if user secondary */ 1382 case ASI_AIUPL: /* As if user primary LE */ 1383 case ASI_AIUSL: /* As if user secondary LE */ 1384 case ASI_P: /* Primary */ 1385 case ASI_S: /* Secondary */ 1386 case ASI_PL: /* Primary LE */ 1387 case ASI_SL: /* Secondary LE */ 1388 case ASI_REAL: /* Bypass */ 1389 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1390 case ASI_REAL_L: /* Bypass LE */ 1391 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1392 case ASI_N: /* Nucleus */ 1393 case ASI_NL: /* Nucleus Little Endian (LE) */ 1394 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1395 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1396 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1397 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1398 case ASI_TWINX_REAL: /* Real address, twinx */ 1399 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1400 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1401 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1402 case ASI_TWINX_N: /* Nucleus, twinx */ 1403 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1404 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1405 case ASI_TWINX_P: /* Primary, twinx */ 1406 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1407 case ASI_TWINX_S: /* Secondary, twinx */ 1408 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1409 case ASI_MON_P: 1410 case ASI_MON_S: 1411 case ASI_MON_AIUP: 1412 case ASI_MON_AIUS: 1413 /* These are always handled inline. */ 1414 g_assert_not_reached(); 1415 1416 case ASI_UPA_CONFIG: /* UPA config */ 1417 /* XXX */ 1418 break; 1419 case ASI_LSU_CONTROL: /* LSU */ 1420 ret = env->lsu; 1421 break; 1422 case ASI_IMMU: /* I-MMU regs */ 1423 { 1424 int reg = (addr >> 3) & 0xf; 1425 switch (reg) { 1426 case 0: 1427 /* 0x00 I-TSB Tag Target register */ 1428 ret = ultrasparc_tag_target(env->immu.tag_access); 1429 break; 1430 case 3: /* SFSR */ 1431 ret = env->immu.sfsr; 1432 break; 1433 case 5: /* TSB access */ 1434 ret = env->immu.tsb; 1435 break; 1436 case 6: 1437 /* 0x30 I-TSB Tag Access register */ 1438 ret = env->immu.tag_access; 1439 break; 1440 default: 1441 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1442 ret = 0; 1443 } 1444 break; 1445 } 1446 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1447 { 1448 /* env->immuregs[5] holds I-MMU TSB register value 1449 env->immuregs[6] holds I-MMU Tag Access register value */ 1450 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1451 break; 1452 } 1453 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1454 { 1455 /* env->immuregs[5] holds I-MMU TSB register value 1456 env->immuregs[6] holds I-MMU Tag Access register value */ 1457 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1458 break; 1459 } 1460 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1461 { 1462 int reg = (addr >> 3) & 0x3f; 1463 1464 ret = env->itlb[reg].tte; 1465 break; 1466 } 1467 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1468 { 1469 int reg = (addr >> 3) & 0x3f; 1470 1471 ret = env->itlb[reg].tag; 1472 break; 1473 } 1474 case ASI_DMMU: /* D-MMU regs */ 1475 { 1476 int reg = (addr >> 3) & 0xf; 1477 switch (reg) { 1478 case 0: 1479 /* 0x00 D-TSB Tag Target register */ 1480 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1481 break; 1482 case 1: /* 0x08 Primary Context */ 1483 ret = env->dmmu.mmu_primary_context; 1484 break; 1485 case 2: /* 0x10 Secondary Context */ 1486 ret = env->dmmu.mmu_secondary_context; 1487 break; 1488 case 3: /* SFSR */ 1489 ret = env->dmmu.sfsr; 1490 break; 1491 case 4: /* 0x20 SFAR */ 1492 ret = env->dmmu.sfar; 1493 break; 1494 case 5: /* 0x28 TSB access */ 1495 ret = env->dmmu.tsb; 1496 break; 1497 case 6: /* 0x30 D-TSB Tag Access register */ 1498 ret = env->dmmu.tag_access; 1499 break; 1500 case 7: 1501 ret = env->dmmu.virtual_watchpoint; 1502 break; 1503 case 8: 1504 ret = env->dmmu.physical_watchpoint; 1505 break; 1506 default: 1507 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1508 ret = 0; 1509 } 1510 break; 1511 } 1512 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1513 { 1514 /* env->dmmuregs[5] holds D-MMU TSB register value 1515 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1516 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1517 break; 1518 } 1519 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1520 { 1521 /* env->dmmuregs[5] holds D-MMU TSB register value 1522 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1523 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1524 break; 1525 } 1526 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1527 { 1528 int reg = (addr >> 3) & 0x3f; 1529 1530 ret = env->dtlb[reg].tte; 1531 break; 1532 } 1533 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1534 { 1535 int reg = (addr >> 3) & 0x3f; 1536 1537 ret = env->dtlb[reg].tag; 1538 break; 1539 } 1540 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1541 break; 1542 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1543 ret = env->ivec_status; 1544 break; 1545 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1546 { 1547 int reg = (addr >> 4) & 0x3; 1548 if (reg < 3) { 1549 ret = env->ivec_data[reg]; 1550 } 1551 break; 1552 } 1553 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1554 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1555 /* Hyperprivileged access only */ 1556 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1557 } 1558 /* fall through */ 1559 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1560 { 1561 unsigned int i = (addr >> 3) & 0x7; 1562 ret = env->scratch[i]; 1563 break; 1564 } 1565 case ASI_MMU: /* UA2005 Context ID registers */ 1566 switch ((addr >> 3) & 0x3) { 1567 case 1: 1568 ret = env->dmmu.mmu_primary_context; 1569 break; 1570 case 2: 1571 ret = env->dmmu.mmu_secondary_context; 1572 break; 1573 default: 1574 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1575 } 1576 break; 1577 case ASI_DCACHE_DATA: /* D-cache data */ 1578 case ASI_DCACHE_TAG: /* D-cache tag access */ 1579 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1580 case ASI_AFSR: /* E-cache asynchronous fault status */ 1581 case ASI_AFAR: /* E-cache asynchronous fault address */ 1582 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1583 case ASI_IC_INSTR: /* I-cache instruction access */ 1584 case ASI_IC_TAG: /* I-cache tag access */ 1585 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1586 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1587 case ASI_EC_W: /* E-cache tag */ 1588 case ASI_EC_R: /* E-cache tag */ 1589 break; 1590 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1591 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1592 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1593 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1594 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1595 case ASI_INTR_W: /* Interrupt vector, WO */ 1596 default: 1597 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1598 ret = 0; 1599 break; 1600 } 1601 1602 /* Convert to signed number */ 1603 if (sign) { 1604 switch (size) { 1605 case 1: 1606 ret = (int8_t) ret; 1607 break; 1608 case 2: 1609 ret = (int16_t) ret; 1610 break; 1611 case 4: 1612 ret = (int32_t) ret; 1613 break; 1614 default: 1615 break; 1616 } 1617 } 1618 #ifdef DEBUG_ASI 1619 dump_asi("read ", last_addr, asi, size, ret); 1620 #endif 1621 return ret; 1622 } 1623 1624 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1625 int asi, uint32_t memop) 1626 { 1627 int size = 1 << (memop & MO_SIZE); 1628 CPUState *cs = env_cpu(env); 1629 1630 #ifdef DEBUG_ASI 1631 dump_asi("write", addr, asi, size, val); 1632 #endif 1633 1634 asi &= 0xff; 1635 1636 do_check_asi(env, asi, GETPC()); 1637 do_check_align(env, addr, size - 1, GETPC()); 1638 addr = asi_address_mask(env, asi, addr); 1639 1640 switch (asi) { 1641 case ASI_AIUP: /* As if user primary */ 1642 case ASI_AIUS: /* As if user secondary */ 1643 case ASI_AIUPL: /* As if user primary LE */ 1644 case ASI_AIUSL: /* As if user secondary LE */ 1645 case ASI_P: /* Primary */ 1646 case ASI_S: /* Secondary */ 1647 case ASI_PL: /* Primary LE */ 1648 case ASI_SL: /* Secondary LE */ 1649 case ASI_REAL: /* Bypass */ 1650 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1651 case ASI_REAL_L: /* Bypass LE */ 1652 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1653 case ASI_N: /* Nucleus */ 1654 case ASI_NL: /* Nucleus Little Endian (LE) */ 1655 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1656 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1657 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1658 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1659 case ASI_TWINX_REAL: /* Real address, twinx */ 1660 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1661 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1662 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1663 case ASI_TWINX_N: /* Nucleus, twinx */ 1664 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1665 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1666 case ASI_TWINX_P: /* Primary, twinx */ 1667 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1668 case ASI_TWINX_S: /* Secondary, twinx */ 1669 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1670 /* These are always handled inline. */ 1671 g_assert_not_reached(); 1672 /* these ASIs have different functions on UltraSPARC-IIIi 1673 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1674 */ 1675 case 0x31: 1676 case 0x32: 1677 case 0x39: 1678 case 0x3a: 1679 if (cpu_has_hypervisor(env)) { 1680 /* UA2005 1681 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1682 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1683 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1684 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1685 */ 1686 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1687 env->dmmu.sun4v_tsb_pointers[idx] = val; 1688 } else { 1689 goto illegal_insn; 1690 } 1691 break; 1692 case 0x33: 1693 case 0x3b: 1694 if (cpu_has_hypervisor(env)) { 1695 /* UA2005 1696 * ASI_DMMU_CTX_ZERO_CONFIG 1697 * ASI_DMMU_CTX_NONZERO_CONFIG 1698 */ 1699 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1700 } else { 1701 goto illegal_insn; 1702 } 1703 break; 1704 case 0x35: 1705 case 0x36: 1706 case 0x3d: 1707 case 0x3e: 1708 if (cpu_has_hypervisor(env)) { 1709 /* UA2005 1710 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1711 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1712 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1713 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1714 */ 1715 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1716 env->immu.sun4v_tsb_pointers[idx] = val; 1717 } else { 1718 goto illegal_insn; 1719 } 1720 break; 1721 case 0x37: 1722 case 0x3f: 1723 if (cpu_has_hypervisor(env)) { 1724 /* UA2005 1725 * ASI_IMMU_CTX_ZERO_CONFIG 1726 * ASI_IMMU_CTX_NONZERO_CONFIG 1727 */ 1728 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1729 } else { 1730 goto illegal_insn; 1731 } 1732 break; 1733 case ASI_UPA_CONFIG: /* UPA config */ 1734 /* XXX */ 1735 return; 1736 case ASI_LSU_CONTROL: /* LSU */ 1737 env->lsu = val & (DMMU_E | IMMU_E); 1738 return; 1739 case ASI_IMMU: /* I-MMU regs */ 1740 { 1741 int reg = (addr >> 3) & 0xf; 1742 uint64_t oldreg; 1743 1744 oldreg = env->immu.mmuregs[reg]; 1745 switch (reg) { 1746 case 0: /* RO */ 1747 return; 1748 case 1: /* Not in I-MMU */ 1749 case 2: 1750 return; 1751 case 3: /* SFSR */ 1752 if ((val & 1) == 0) { 1753 val = 0; /* Clear SFSR */ 1754 } 1755 env->immu.sfsr = val; 1756 break; 1757 case 4: /* RO */ 1758 return; 1759 case 5: /* TSB access */ 1760 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1761 PRIx64 "\n", env->immu.tsb, val); 1762 env->immu.tsb = val; 1763 break; 1764 case 6: /* Tag access */ 1765 env->immu.tag_access = val; 1766 break; 1767 case 7: 1768 case 8: 1769 return; 1770 default: 1771 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1772 break; 1773 } 1774 1775 if (oldreg != env->immu.mmuregs[reg]) { 1776 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1777 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1778 } 1779 #ifdef DEBUG_MMU 1780 dump_mmu(env); 1781 #endif 1782 return; 1783 } 1784 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1785 /* ignore real translation entries */ 1786 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1787 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1788 val, "immu", env, addr); 1789 } 1790 return; 1791 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1792 { 1793 /* TODO: auto demap */ 1794 1795 unsigned int i = (addr >> 3) & 0x3f; 1796 1797 /* ignore real translation entries */ 1798 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1799 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1800 sun4v_tte_to_sun4u(env, addr, val), env); 1801 } 1802 #ifdef DEBUG_MMU 1803 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1804 dump_mmu(env); 1805 #endif 1806 return; 1807 } 1808 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1809 demap_tlb(env->itlb, addr, "immu", env); 1810 return; 1811 case ASI_DMMU: /* D-MMU regs */ 1812 { 1813 int reg = (addr >> 3) & 0xf; 1814 uint64_t oldreg; 1815 1816 oldreg = env->dmmu.mmuregs[reg]; 1817 switch (reg) { 1818 case 0: /* RO */ 1819 case 4: 1820 return; 1821 case 3: /* SFSR */ 1822 if ((val & 1) == 0) { 1823 val = 0; /* Clear SFSR, Fault address */ 1824 env->dmmu.sfar = 0; 1825 } 1826 env->dmmu.sfsr = val; 1827 break; 1828 case 1: /* Primary context */ 1829 env->dmmu.mmu_primary_context = val; 1830 /* can be optimized to only flush MMU_USER_IDX 1831 and MMU_KERNEL_IDX entries */ 1832 tlb_flush(cs); 1833 break; 1834 case 2: /* Secondary context */ 1835 env->dmmu.mmu_secondary_context = val; 1836 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1837 and MMU_KERNEL_SECONDARY_IDX entries */ 1838 tlb_flush(cs); 1839 break; 1840 case 5: /* TSB access */ 1841 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1842 PRIx64 "\n", env->dmmu.tsb, val); 1843 env->dmmu.tsb = val; 1844 break; 1845 case 6: /* Tag access */ 1846 env->dmmu.tag_access = val; 1847 break; 1848 case 7: /* Virtual Watchpoint */ 1849 env->dmmu.virtual_watchpoint = val; 1850 break; 1851 case 8: /* Physical Watchpoint */ 1852 env->dmmu.physical_watchpoint = val; 1853 break; 1854 default: 1855 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1856 break; 1857 } 1858 1859 if (oldreg != env->dmmu.mmuregs[reg]) { 1860 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1861 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1862 } 1863 #ifdef DEBUG_MMU 1864 dump_mmu(env); 1865 #endif 1866 return; 1867 } 1868 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1869 /* ignore real translation entries */ 1870 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1871 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1872 val, "dmmu", env, addr); 1873 } 1874 return; 1875 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1876 { 1877 unsigned int i = (addr >> 3) & 0x3f; 1878 1879 /* ignore real translation entries */ 1880 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1881 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1882 sun4v_tte_to_sun4u(env, addr, val), env); 1883 } 1884 #ifdef DEBUG_MMU 1885 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1886 dump_mmu(env); 1887 #endif 1888 return; 1889 } 1890 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1891 demap_tlb(env->dtlb, addr, "dmmu", env); 1892 return; 1893 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1894 env->ivec_status = val & 0x20; 1895 return; 1896 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1897 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1898 /* Hyperprivileged access only */ 1899 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1900 } 1901 /* fall through */ 1902 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1903 { 1904 unsigned int i = (addr >> 3) & 0x7; 1905 env->scratch[i] = val; 1906 return; 1907 } 1908 case ASI_MMU: /* UA2005 Context ID registers */ 1909 { 1910 switch ((addr >> 3) & 0x3) { 1911 case 1: 1912 env->dmmu.mmu_primary_context = val; 1913 env->immu.mmu_primary_context = val; 1914 tlb_flush_by_mmuidx(cs, 1915 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1916 break; 1917 case 2: 1918 env->dmmu.mmu_secondary_context = val; 1919 env->immu.mmu_secondary_context = val; 1920 tlb_flush_by_mmuidx(cs, 1921 (1 << MMU_USER_SECONDARY_IDX) | 1922 (1 << MMU_KERNEL_SECONDARY_IDX)); 1923 break; 1924 default: 1925 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1926 } 1927 } 1928 return; 1929 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1930 case ASI_DCACHE_DATA: /* D-cache data */ 1931 case ASI_DCACHE_TAG: /* D-cache tag access */ 1932 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1933 case ASI_AFSR: /* E-cache asynchronous fault status */ 1934 case ASI_AFAR: /* E-cache asynchronous fault address */ 1935 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1936 case ASI_IC_INSTR: /* I-cache instruction access */ 1937 case ASI_IC_TAG: /* I-cache tag access */ 1938 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1939 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1940 case ASI_EC_W: /* E-cache tag */ 1941 case ASI_EC_R: /* E-cache tag */ 1942 return; 1943 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1944 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1945 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1946 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1947 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1948 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1949 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1950 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1951 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1952 case ASI_PNF: /* Primary no-fault, RO */ 1953 case ASI_SNF: /* Secondary no-fault, RO */ 1954 case ASI_PNFL: /* Primary no-fault LE, RO */ 1955 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1956 default: 1957 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1958 return; 1959 illegal_insn: 1960 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1961 } 1962 } 1963 #endif /* CONFIG_USER_ONLY */ 1964 #endif /* TARGET_SPARC64 */ 1965 1966 #if !defined(CONFIG_USER_ONLY) 1967 1968 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1969 vaddr addr, unsigned size, 1970 MMUAccessType access_type, 1971 int mmu_idx, MemTxAttrs attrs, 1972 MemTxResult response, uintptr_t retaddr) 1973 { 1974 bool is_write = access_type == MMU_DATA_STORE; 1975 bool is_exec = access_type == MMU_INST_FETCH; 1976 bool is_asi = false; 1977 1978 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1979 is_asi, size, retaddr); 1980 } 1981 #endif 1982