1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/range.h" 23 #include "cpu.h" 24 #include "tcg/tcg.h" 25 #include "exec/helper-proto.h" 26 #include "exec/exec-all.h" 27 #include "exec/cputlb.h" 28 #include "exec/page-protection.h" 29 #include "exec/cpu_ldst.h" 30 #ifdef CONFIG_USER_ONLY 31 #include "user/page-protection.h" 32 #endif 33 #include "asi.h" 34 35 //#define DEBUG_MMU 36 //#define DEBUG_MXCC 37 //#define DEBUG_UNASSIGNED 38 //#define DEBUG_ASI 39 //#define DEBUG_CACHE_CONTROL 40 41 #ifdef DEBUG_MMU 42 #define DPRINTF_MMU(fmt, ...) \ 43 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 44 #else 45 #define DPRINTF_MMU(fmt, ...) do {} while (0) 46 #endif 47 48 #ifdef DEBUG_MXCC 49 #define DPRINTF_MXCC(fmt, ...) \ 50 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 51 #else 52 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 53 #endif 54 55 #ifdef DEBUG_ASI 56 #define DPRINTF_ASI(fmt, ...) \ 57 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 58 #endif 59 60 #ifdef DEBUG_CACHE_CONTROL 61 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 62 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 63 #else 64 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 65 #endif 66 67 #ifdef TARGET_SPARC64 68 #ifndef TARGET_ABI32 69 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 70 #else 71 #define AM_CHECK(env1) (1) 72 #endif 73 #endif 74 75 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 76 /* Calculates TSB pointer value for fault page size 77 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 78 * UA2005 holds the page size configuration in mmu_ctx registers */ 79 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 80 const SparcV9MMU *mmu, const int idx) 81 { 82 uint64_t tsb_register; 83 int page_size; 84 if (cpu_has_hypervisor(env)) { 85 int tsb_index = 0; 86 int ctx = mmu->tag_access & 0x1fffULL; 87 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 88 tsb_index = idx; 89 tsb_index |= ctx ? 2 : 0; 90 page_size = idx ? ctx_register >> 8 : ctx_register; 91 page_size &= 7; 92 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 93 } else { 94 page_size = idx; 95 tsb_register = mmu->tsb; 96 } 97 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 98 int tsb_size = tsb_register & 0xf; 99 100 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 101 102 /* move va bits to correct position, 103 * the context bits will be masked out later */ 104 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 105 106 /* calculate tsb_base mask and adjust va if split is in use */ 107 if (tsb_split) { 108 if (idx == 0) { 109 va &= ~(1ULL << (13 + tsb_size)); 110 } else { 111 va |= (1ULL << (13 + tsb_size)); 112 } 113 tsb_base_mask <<= 1; 114 } 115 116 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 117 } 118 119 /* Calculates tag target register value by reordering bits 120 in tag access register */ 121 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 122 { 123 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 124 } 125 126 static void replace_tlb_entry(SparcTLBEntry *tlb, 127 uint64_t tlb_tag, uint64_t tlb_tte, 128 CPUSPARCState *env) 129 { 130 target_ulong mask, size, va, offset; 131 132 /* flush page range if translation is valid */ 133 if (TTE_IS_VALID(tlb->tte)) { 134 CPUState *cs = env_cpu(env); 135 136 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 137 mask = 1ULL + ~size; 138 139 va = tlb->tag & mask; 140 141 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 142 tlb_flush_page(cs, va + offset); 143 } 144 } 145 146 tlb->tag = tlb_tag; 147 tlb->tte = tlb_tte; 148 } 149 150 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 151 const char *strmmu, CPUSPARCState *env1) 152 { 153 unsigned int i; 154 target_ulong mask; 155 uint64_t context; 156 157 int is_demap_context = (demap_addr >> 6) & 1; 158 159 /* demap context */ 160 switch ((demap_addr >> 4) & 3) { 161 case 0: /* primary */ 162 context = env1->dmmu.mmu_primary_context; 163 break; 164 case 1: /* secondary */ 165 context = env1->dmmu.mmu_secondary_context; 166 break; 167 case 2: /* nucleus */ 168 context = 0; 169 break; 170 case 3: /* reserved */ 171 default: 172 return; 173 } 174 175 for (i = 0; i < 64; i++) { 176 if (TTE_IS_VALID(tlb[i].tte)) { 177 178 if (is_demap_context) { 179 /* will remove non-global entries matching context value */ 180 if (TTE_IS_GLOBAL(tlb[i].tte) || 181 !tlb_compare_context(&tlb[i], context)) { 182 continue; 183 } 184 } else { 185 /* demap page 186 will remove any entry matching VA */ 187 mask = 0xffffffffffffe000ULL; 188 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 189 190 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 191 continue; 192 } 193 194 /* entry should be global or matching context value */ 195 if (!TTE_IS_GLOBAL(tlb[i].tte) && 196 !tlb_compare_context(&tlb[i], context)) { 197 continue; 198 } 199 } 200 201 replace_tlb_entry(&tlb[i], 0, 0, env1); 202 #ifdef DEBUG_MMU 203 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 204 dump_mmu(env1); 205 #endif 206 } 207 } 208 } 209 210 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 211 uint64_t sun4v_tte) 212 { 213 uint64_t sun4u_tte; 214 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 215 /* is already in the sun4u format */ 216 return sun4v_tte; 217 } 218 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 219 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 221 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 222 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 223 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 224 TTE_SIDEEFFECT_BIT); 225 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 226 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 227 return sun4u_tte; 228 } 229 230 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 231 uint64_t tlb_tag, uint64_t tlb_tte, 232 const char *strmmu, CPUSPARCState *env1, 233 uint64_t addr) 234 { 235 unsigned int i, replace_used; 236 237 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 238 if (cpu_has_hypervisor(env1)) { 239 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 240 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 241 uint32_t new_ctx = tlb_tag & 0x1fffU; 242 for (i = 0; i < 64; i++) { 243 uint32_t ctx = tlb[i].tag & 0x1fffU; 244 /* check if new mapping overlaps an existing one */ 245 if (new_ctx == ctx) { 246 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 247 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 248 if (ranges_overlap(new_vaddr, new_size, vaddr, size)) { 249 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 250 new_vaddr); 251 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 252 return; 253 } 254 } 255 256 } 257 } 258 /* Try replacing invalid entry */ 259 for (i = 0; i < 64; i++) { 260 if (!TTE_IS_VALID(tlb[i].tte)) { 261 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 262 #ifdef DEBUG_MMU 263 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 264 dump_mmu(env1); 265 #endif 266 return; 267 } 268 } 269 270 /* All entries are valid, try replacing unlocked entry */ 271 272 for (replace_used = 0; replace_used < 2; ++replace_used) { 273 274 /* Used entries are not replaced on first pass */ 275 276 for (i = 0; i < 64; i++) { 277 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 278 279 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 280 #ifdef DEBUG_MMU 281 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 282 strmmu, (replace_used ? "used" : "unused"), i); 283 dump_mmu(env1); 284 #endif 285 return; 286 } 287 } 288 289 /* Now reset used bit and search for unused entries again */ 290 291 for (i = 0; i < 64; i++) { 292 TTE_SET_UNUSED(tlb[i].tte); 293 } 294 } 295 296 #ifdef DEBUG_MMU 297 DPRINTF_MMU("%s lru replacement: no free entries available, " 298 "replacing the last one\n", strmmu); 299 #endif 300 /* corner case: the last entry is replaced anyway */ 301 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 302 } 303 304 #endif 305 306 #ifdef TARGET_SPARC64 307 /* returns true if access using this ASI is to have address translated by MMU 308 otherwise access is to raw physical address */ 309 /* TODO: check sparc32 bits */ 310 static inline int is_translating_asi(int asi) 311 { 312 /* Ultrasparc IIi translating asi 313 - note this list is defined by cpu implementation 314 */ 315 switch (asi) { 316 case 0x04 ... 0x11: 317 case 0x16 ... 0x19: 318 case 0x1E ... 0x1F: 319 case 0x24 ... 0x2C: 320 case 0x70 ... 0x73: 321 case 0x78 ... 0x79: 322 case 0x80 ... 0xFF: 323 return 1; 324 325 default: 326 return 0; 327 } 328 } 329 330 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 331 { 332 if (AM_CHECK(env1)) { 333 addr &= 0xffffffffULL; 334 } 335 return addr; 336 } 337 338 static inline target_ulong asi_address_mask(CPUSPARCState *env, 339 int asi, target_ulong addr) 340 { 341 if (is_translating_asi(asi)) { 342 addr = address_mask(env, addr); 343 } 344 return addr; 345 } 346 347 #ifndef CONFIG_USER_ONLY 348 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 349 { 350 /* ASIs >= 0x80 are user mode. 351 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 352 * ASIs <= 0x2f are super mode. 353 */ 354 if (asi < 0x80 355 && !cpu_hypervisor_mode(env) 356 && (!cpu_supervisor_mode(env) 357 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 358 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 359 } 360 } 361 #endif /* !CONFIG_USER_ONLY */ 362 #endif 363 364 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 365 static void do_check_align(CPUSPARCState *env, target_ulong addr, 366 uint32_t align, uintptr_t ra) 367 { 368 if (addr & align) { 369 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 370 } 371 } 372 #endif 373 374 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 375 defined(DEBUG_MXCC) 376 static void dump_mxcc(CPUSPARCState *env) 377 { 378 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 379 "\n", 380 env->mxccdata[0], env->mxccdata[1], 381 env->mxccdata[2], env->mxccdata[3]); 382 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 383 "\n" 384 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 385 "\n", 386 env->mxccregs[0], env->mxccregs[1], 387 env->mxccregs[2], env->mxccregs[3], 388 env->mxccregs[4], env->mxccregs[5], 389 env->mxccregs[6], env->mxccregs[7]); 390 } 391 #endif 392 393 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 394 && defined(DEBUG_ASI) 395 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 396 uint64_t r1) 397 { 398 switch (size) { 399 case 1: 400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 401 addr, asi, r1 & 0xff); 402 break; 403 case 2: 404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 405 addr, asi, r1 & 0xffff); 406 break; 407 case 4: 408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 409 addr, asi, r1 & 0xffffffff); 410 break; 411 case 8: 412 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 413 addr, asi, r1); 414 break; 415 } 416 } 417 #endif 418 419 #ifndef CONFIG_USER_ONLY 420 #ifndef TARGET_SPARC64 421 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 422 bool is_write, bool is_exec, int is_asi, 423 unsigned size, uintptr_t retaddr) 424 { 425 CPUSPARCState *env = cpu_env(cs); 426 int fault_type; 427 428 #ifdef DEBUG_UNASSIGNED 429 if (is_asi) { 430 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 431 " asi 0x%02x from " TARGET_FMT_lx "\n", 432 is_exec ? "exec" : is_write ? "write" : "read", size, 433 size == 1 ? "" : "s", addr, is_asi, env->pc); 434 } else { 435 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 436 " from " TARGET_FMT_lx "\n", 437 is_exec ? "exec" : is_write ? "write" : "read", size, 438 size == 1 ? "" : "s", addr, env->pc); 439 } 440 #endif 441 /* Don't overwrite translation and access faults */ 442 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 443 if ((fault_type > 4) || (fault_type == 0)) { 444 env->mmuregs[3] = 0; /* Fault status register */ 445 if (is_asi) { 446 env->mmuregs[3] |= 1 << 16; 447 } 448 if (env->psrs) { 449 env->mmuregs[3] |= 1 << 5; 450 } 451 if (is_exec) { 452 env->mmuregs[3] |= 1 << 6; 453 } 454 if (is_write) { 455 env->mmuregs[3] |= 1 << 7; 456 } 457 env->mmuregs[3] |= (5 << 2) | 2; 458 /* SuperSPARC will never place instruction fault addresses in the FAR */ 459 if (!is_exec) { 460 env->mmuregs[4] = addr; /* Fault address register */ 461 } 462 } 463 /* overflow (same type fault was not read before another fault) */ 464 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 465 env->mmuregs[3] |= 1; 466 } 467 468 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 469 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 470 cpu_raise_exception_ra(env, tt, retaddr); 471 } 472 473 /* 474 * flush neverland mappings created during no-fault mode, 475 * so the sequential MMU faults report proper fault types 476 */ 477 if (env->mmuregs[0] & MMU_NF) { 478 tlb_flush(cs); 479 } 480 } 481 #else 482 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 483 bool is_write, bool is_exec, int is_asi, 484 unsigned size, uintptr_t retaddr) 485 { 486 CPUSPARCState *env = cpu_env(cs); 487 488 #ifdef DEBUG_UNASSIGNED 489 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 490 "\n", addr, env->pc); 491 #endif 492 493 if (is_exec) { /* XXX has_hypervisor */ 494 if (env->lsu & (IMMU_E)) { 495 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 496 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 497 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 498 } 499 } else { 500 if (env->lsu & (DMMU_E)) { 501 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 502 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 503 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 504 } 505 } 506 } 507 #endif 508 #endif 509 510 #ifndef TARGET_SPARC64 511 #ifndef CONFIG_USER_ONLY 512 513 514 /* Leon3 cache control */ 515 516 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 517 uint64_t val, int size) 518 { 519 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 520 addr, val, size); 521 522 if (size != 4) { 523 DPRINTF_CACHE_CONTROL("32bits only\n"); 524 return; 525 } 526 527 switch (addr) { 528 case 0x00: /* Cache control */ 529 530 /* These values must always be read as zeros */ 531 val &= ~CACHE_CTRL_FD; 532 val &= ~CACHE_CTRL_FI; 533 val &= ~CACHE_CTRL_IB; 534 val &= ~CACHE_CTRL_IP; 535 val &= ~CACHE_CTRL_DP; 536 537 env->cache_control = val; 538 break; 539 case 0x04: /* Instruction cache configuration */ 540 case 0x08: /* Data cache configuration */ 541 /* Read Only */ 542 break; 543 default: 544 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 545 break; 546 }; 547 } 548 549 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 550 int size) 551 { 552 uint64_t ret = 0; 553 554 if (size != 4) { 555 DPRINTF_CACHE_CONTROL("32bits only\n"); 556 return 0; 557 } 558 559 switch (addr) { 560 case 0x00: /* Cache control */ 561 ret = env->cache_control; 562 break; 563 564 /* Configuration registers are read and only always keep those 565 predefined values */ 566 567 case 0x04: /* Instruction cache configuration */ 568 ret = 0x10220000; 569 break; 570 case 0x08: /* Data cache configuration */ 571 ret = 0x18220000; 572 break; 573 default: 574 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 575 break; 576 }; 577 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 578 addr, ret, size); 579 return ret; 580 } 581 582 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 583 int asi, uint32_t memop) 584 { 585 int size = 1 << (memop & MO_SIZE); 586 int sign = memop & MO_SIGN; 587 CPUState *cs = env_cpu(env); 588 uint64_t ret = 0; 589 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 590 uint32_t last_addr = addr; 591 #endif 592 593 do_check_align(env, addr, size - 1, GETPC()); 594 switch (asi) { 595 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 596 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 597 switch (addr) { 598 case 0x00: /* Leon3 Cache Control */ 599 case 0x08: /* Leon3 Instruction Cache config */ 600 case 0x0C: /* Leon3 Date Cache config */ 601 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 602 ret = leon3_cache_control_ld(env, addr, size); 603 } 604 break; 605 case 0x01c00a00: /* MXCC control register */ 606 if (size == 8) { 607 ret = env->mxccregs[3]; 608 } else { 609 qemu_log_mask(LOG_UNIMP, 610 "%08x: unimplemented access size: %d\n", addr, 611 size); 612 } 613 break; 614 case 0x01c00a04: /* MXCC control register */ 615 if (size == 4) { 616 ret = env->mxccregs[3]; 617 } else { 618 qemu_log_mask(LOG_UNIMP, 619 "%08x: unimplemented access size: %d\n", addr, 620 size); 621 } 622 break; 623 case 0x01c00c00: /* Module reset register */ 624 if (size == 8) { 625 ret = env->mxccregs[5]; 626 /* should we do something here? */ 627 } else { 628 qemu_log_mask(LOG_UNIMP, 629 "%08x: unimplemented access size: %d\n", addr, 630 size); 631 } 632 break; 633 case 0x01c00f00: /* MBus port address register */ 634 if (size == 8) { 635 ret = env->mxccregs[7]; 636 } else { 637 qemu_log_mask(LOG_UNIMP, 638 "%08x: unimplemented access size: %d\n", addr, 639 size); 640 } 641 break; 642 default: 643 qemu_log_mask(LOG_UNIMP, 644 "%08x: unimplemented address, size: %d\n", addr, 645 size); 646 break; 647 } 648 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 649 "addr = %08x -> ret = %" PRIx64 "," 650 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 651 #ifdef DEBUG_MXCC 652 dump_mxcc(env); 653 #endif 654 break; 655 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 656 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 657 { 658 int mmulev; 659 660 mmulev = (addr >> 8) & 15; 661 if (mmulev > 4) { 662 ret = 0; 663 } else { 664 ret = mmu_probe(env, addr, mmulev); 665 } 666 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 667 addr, mmulev, ret); 668 } 669 break; 670 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 671 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 672 { 673 int reg = (addr >> 8) & 0x1f; 674 675 ret = env->mmuregs[reg]; 676 if (reg == 3) { /* Fault status cleared on read */ 677 env->mmuregs[3] = 0; 678 } else if (reg == 0x13) { /* Fault status read */ 679 ret = env->mmuregs[3]; 680 } else if (reg == 0x14) { /* Fault address read */ 681 ret = env->mmuregs[4]; 682 } 683 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 684 } 685 break; 686 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 687 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 688 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 689 break; 690 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 691 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 692 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 693 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 694 break; 695 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 696 { 697 MemTxResult result; 698 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 699 700 switch (size) { 701 case 1: 702 ret = address_space_ldub(cs->as, access_addr, 703 MEMTXATTRS_UNSPECIFIED, &result); 704 break; 705 case 2: 706 ret = address_space_lduw(cs->as, access_addr, 707 MEMTXATTRS_UNSPECIFIED, &result); 708 break; 709 default: 710 case 4: 711 ret = address_space_ldl(cs->as, access_addr, 712 MEMTXATTRS_UNSPECIFIED, &result); 713 break; 714 case 8: 715 ret = address_space_ldq(cs->as, access_addr, 716 MEMTXATTRS_UNSPECIFIED, &result); 717 break; 718 } 719 720 if (result != MEMTX_OK) { 721 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 722 size, GETPC()); 723 } 724 break; 725 } 726 case 0x30: /* Turbosparc secondary cache diagnostic */ 727 case 0x31: /* Turbosparc RAM snoop */ 728 case 0x32: /* Turbosparc page table descriptor diagnostic */ 729 case 0x39: /* data cache diagnostic register */ 730 ret = 0; 731 break; 732 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 733 { 734 int reg = (addr >> 8) & 3; 735 736 switch (reg) { 737 case 0: /* Breakpoint Value (Addr) */ 738 ret = env->mmubpregs[reg]; 739 break; 740 case 1: /* Breakpoint Mask */ 741 ret = env->mmubpregs[reg]; 742 break; 743 case 2: /* Breakpoint Control */ 744 ret = env->mmubpregs[reg]; 745 break; 746 case 3: /* Breakpoint Status */ 747 ret = env->mmubpregs[reg]; 748 env->mmubpregs[reg] = 0ULL; 749 break; 750 } 751 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 752 ret); 753 } 754 break; 755 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 756 ret = env->mmubpctrv; 757 break; 758 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 759 ret = env->mmubpctrc; 760 break; 761 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 762 ret = env->mmubpctrs; 763 break; 764 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 765 ret = env->mmubpaction; 766 break; 767 default: 768 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 769 ret = 0; 770 break; 771 772 case ASI_USERDATA: /* User data access */ 773 case ASI_KERNELDATA: /* Supervisor data access */ 774 case ASI_USERTXT: /* User code access */ 775 case ASI_KERNELTXT: /* Supervisor code access */ 776 case ASI_P: /* Implicit primary context data access (v9 only?) */ 777 case ASI_M_BYPASS: /* MMU passthrough */ 778 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 779 /* These are always handled inline. */ 780 g_assert_not_reached(); 781 } 782 if (sign) { 783 switch (size) { 784 case 1: 785 ret = (int8_t) ret; 786 break; 787 case 2: 788 ret = (int16_t) ret; 789 break; 790 case 4: 791 ret = (int32_t) ret; 792 break; 793 default: 794 break; 795 } 796 } 797 #ifdef DEBUG_ASI 798 dump_asi("read ", last_addr, asi, size, ret); 799 #endif 800 return ret; 801 } 802 803 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 804 int asi, uint32_t memop) 805 { 806 int size = 1 << (memop & MO_SIZE); 807 CPUState *cs = env_cpu(env); 808 809 do_check_align(env, addr, size - 1, GETPC()); 810 switch (asi) { 811 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 812 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 813 switch (addr) { 814 case 0x00: /* Leon3 Cache Control */ 815 case 0x08: /* Leon3 Instruction Cache config */ 816 case 0x0C: /* Leon3 Date Cache config */ 817 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 818 leon3_cache_control_st(env, addr, val, size); 819 } 820 break; 821 822 case 0x01c00000: /* MXCC stream data register 0 */ 823 if (size == 8) { 824 env->mxccdata[0] = val; 825 } else { 826 qemu_log_mask(LOG_UNIMP, 827 "%08x: unimplemented access size: %d\n", addr, 828 size); 829 } 830 break; 831 case 0x01c00008: /* MXCC stream data register 1 */ 832 if (size == 8) { 833 env->mxccdata[1] = val; 834 } else { 835 qemu_log_mask(LOG_UNIMP, 836 "%08x: unimplemented access size: %d\n", addr, 837 size); 838 } 839 break; 840 case 0x01c00010: /* MXCC stream data register 2 */ 841 if (size == 8) { 842 env->mxccdata[2] = val; 843 } else { 844 qemu_log_mask(LOG_UNIMP, 845 "%08x: unimplemented access size: %d\n", addr, 846 size); 847 } 848 break; 849 case 0x01c00018: /* MXCC stream data register 3 */ 850 if (size == 8) { 851 env->mxccdata[3] = val; 852 } else { 853 qemu_log_mask(LOG_UNIMP, 854 "%08x: unimplemented access size: %d\n", addr, 855 size); 856 } 857 break; 858 case 0x01c00100: /* MXCC stream source */ 859 { 860 int i; 861 862 if (size == 8) { 863 env->mxccregs[0] = val; 864 } else { 865 qemu_log_mask(LOG_UNIMP, 866 "%08x: unimplemented access size: %d\n", addr, 867 size); 868 } 869 870 for (i = 0; i < 4; i++) { 871 MemTxResult result; 872 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 873 874 env->mxccdata[i] = address_space_ldq(cs->as, 875 access_addr, 876 MEMTXATTRS_UNSPECIFIED, 877 &result); 878 if (result != MEMTX_OK) { 879 /* TODO: investigate whether this is the right behaviour */ 880 sparc_raise_mmu_fault(cs, access_addr, false, false, 881 false, size, GETPC()); 882 } 883 } 884 break; 885 } 886 case 0x01c00200: /* MXCC stream destination */ 887 { 888 int i; 889 890 if (size == 8) { 891 env->mxccregs[1] = val; 892 } else { 893 qemu_log_mask(LOG_UNIMP, 894 "%08x: unimplemented access size: %d\n", addr, 895 size); 896 } 897 898 for (i = 0; i < 4; i++) { 899 MemTxResult result; 900 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 901 902 address_space_stq(cs->as, access_addr, env->mxccdata[i], 903 MEMTXATTRS_UNSPECIFIED, &result); 904 905 if (result != MEMTX_OK) { 906 /* TODO: investigate whether this is the right behaviour */ 907 sparc_raise_mmu_fault(cs, access_addr, true, false, 908 false, size, GETPC()); 909 } 910 } 911 break; 912 } 913 case 0x01c00a00: /* MXCC control register */ 914 if (size == 8) { 915 env->mxccregs[3] = val; 916 } else { 917 qemu_log_mask(LOG_UNIMP, 918 "%08x: unimplemented access size: %d\n", addr, 919 size); 920 } 921 break; 922 case 0x01c00a04: /* MXCC control register */ 923 if (size == 4) { 924 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 925 | val; 926 } else { 927 qemu_log_mask(LOG_UNIMP, 928 "%08x: unimplemented access size: %d\n", addr, 929 size); 930 } 931 break; 932 case 0x01c00e00: /* MXCC error register */ 933 /* writing a 1 bit clears the error */ 934 if (size == 8) { 935 env->mxccregs[6] &= ~val; 936 } else { 937 qemu_log_mask(LOG_UNIMP, 938 "%08x: unimplemented access size: %d\n", addr, 939 size); 940 } 941 break; 942 case 0x01c00f00: /* MBus port address register */ 943 if (size == 8) { 944 env->mxccregs[7] = val; 945 } else { 946 qemu_log_mask(LOG_UNIMP, 947 "%08x: unimplemented access size: %d\n", addr, 948 size); 949 } 950 break; 951 default: 952 qemu_log_mask(LOG_UNIMP, 953 "%08x: unimplemented address, size: %d\n", addr, 954 size); 955 break; 956 } 957 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 958 asi, size, addr, val); 959 #ifdef DEBUG_MXCC 960 dump_mxcc(env); 961 #endif 962 break; 963 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 964 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 965 { 966 int mmulev; 967 968 mmulev = (addr >> 8) & 15; 969 DPRINTF_MMU("mmu flush level %d\n", mmulev); 970 switch (mmulev) { 971 case 0: /* flush page */ 972 tlb_flush_page(cs, addr & 0xfffff000); 973 break; 974 case 1: /* flush segment (256k) */ 975 case 2: /* flush region (16M) */ 976 case 3: /* flush context (4G) */ 977 case 4: /* flush entire */ 978 tlb_flush(cs); 979 break; 980 default: 981 break; 982 } 983 #ifdef DEBUG_MMU 984 dump_mmu(env); 985 #endif 986 } 987 break; 988 case ASI_M_MMUREGS: /* write MMU regs */ 989 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 990 { 991 int reg = (addr >> 8) & 0x1f; 992 uint32_t oldreg; 993 994 oldreg = env->mmuregs[reg]; 995 switch (reg) { 996 case 0: /* Control Register */ 997 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 998 (val & 0x00ffffff); 999 /* Mappings generated during no-fault mode 1000 are invalid in normal mode. */ 1001 if ((oldreg ^ env->mmuregs[reg]) 1002 & (MMU_NF | env->def.mmu_bm)) { 1003 tlb_flush(cs); 1004 } 1005 break; 1006 case 1: /* Context Table Pointer Register */ 1007 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1008 break; 1009 case 2: /* Context Register */ 1010 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1011 if (oldreg != env->mmuregs[reg]) { 1012 /* we flush when the MMU context changes because 1013 QEMU has no MMU context support */ 1014 tlb_flush(cs); 1015 } 1016 break; 1017 case 3: /* Synchronous Fault Status Register with Clear */ 1018 case 4: /* Synchronous Fault Address Register */ 1019 break; 1020 case 0x10: /* TLB Replacement Control Register */ 1021 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1022 break; 1023 case 0x13: /* Synchronous Fault Status Register with Read 1024 and Clear */ 1025 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1026 break; 1027 case 0x14: /* Synchronous Fault Address Register */ 1028 env->mmuregs[4] = val; 1029 break; 1030 default: 1031 env->mmuregs[reg] = val; 1032 break; 1033 } 1034 if (oldreg != env->mmuregs[reg]) { 1035 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1036 reg, oldreg, env->mmuregs[reg]); 1037 } 1038 #ifdef DEBUG_MMU 1039 dump_mmu(env); 1040 #endif 1041 } 1042 break; 1043 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1044 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1045 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1046 break; 1047 case ASI_M_TXTC_TAG: /* I-cache tag */ 1048 case ASI_M_TXTC_DATA: /* I-cache data */ 1049 case ASI_M_DATAC_TAG: /* D-cache tag */ 1050 case ASI_M_DATAC_DATA: /* D-cache data */ 1051 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1052 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1053 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1054 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1055 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1056 break; 1057 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1058 { 1059 MemTxResult result; 1060 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1061 1062 switch (size) { 1063 case 1: 1064 address_space_stb(cs->as, access_addr, val, 1065 MEMTXATTRS_UNSPECIFIED, &result); 1066 break; 1067 case 2: 1068 address_space_stw(cs->as, access_addr, val, 1069 MEMTXATTRS_UNSPECIFIED, &result); 1070 break; 1071 case 4: 1072 default: 1073 address_space_stl(cs->as, access_addr, val, 1074 MEMTXATTRS_UNSPECIFIED, &result); 1075 break; 1076 case 8: 1077 address_space_stq(cs->as, access_addr, val, 1078 MEMTXATTRS_UNSPECIFIED, &result); 1079 break; 1080 } 1081 if (result != MEMTX_OK) { 1082 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1083 size, GETPC()); 1084 } 1085 } 1086 break; 1087 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1088 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1089 Turbosparc snoop RAM */ 1090 case 0x32: /* store buffer control or Turbosparc page table 1091 descriptor diagnostic */ 1092 case 0x36: /* I-cache flash clear */ 1093 case 0x37: /* D-cache flash clear */ 1094 break; 1095 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1096 { 1097 int reg = (addr >> 8) & 3; 1098 1099 switch (reg) { 1100 case 0: /* Breakpoint Value (Addr) */ 1101 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1102 break; 1103 case 1: /* Breakpoint Mask */ 1104 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1105 break; 1106 case 2: /* Breakpoint Control */ 1107 env->mmubpregs[reg] = (val & 0x7fULL); 1108 break; 1109 case 3: /* Breakpoint Status */ 1110 env->mmubpregs[reg] = (val & 0xfULL); 1111 break; 1112 } 1113 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1114 env->mmuregs[reg]); 1115 } 1116 break; 1117 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1118 env->mmubpctrv = val & 0xffffffff; 1119 break; 1120 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1121 env->mmubpctrc = val & 0x3; 1122 break; 1123 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1124 env->mmubpctrs = val & 0x3; 1125 break; 1126 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1127 env->mmubpaction = val & 0x1fff; 1128 break; 1129 case ASI_USERTXT: /* User code access, XXX */ 1130 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1131 default: 1132 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1133 break; 1134 1135 case ASI_USERDATA: /* User data access */ 1136 case ASI_KERNELDATA: /* Supervisor data access */ 1137 case ASI_P: 1138 case ASI_M_BYPASS: /* MMU passthrough */ 1139 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1140 case ASI_M_BCOPY: /* Block copy, sta access */ 1141 case ASI_M_BFILL: /* Block fill, stda access */ 1142 /* These are always handled inline. */ 1143 g_assert_not_reached(); 1144 } 1145 #ifdef DEBUG_ASI 1146 dump_asi("write", addr, asi, size, val); 1147 #endif 1148 } 1149 1150 uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi) 1151 { 1152 MemOp mop = get_memop(oi); 1153 uintptr_t ra = GETPC(); 1154 uint64_t ret; 1155 1156 switch (mop & MO_SIZE) { 1157 case MO_8: 1158 ret = cpu_ldb_code_mmu(env, addr, oi, ra); 1159 if (mop & MO_SIGN) { 1160 ret = (int8_t)ret; 1161 } 1162 break; 1163 case MO_16: 1164 ret = cpu_ldw_code_mmu(env, addr, oi, ra); 1165 if ((mop & MO_BSWAP) != MO_TE) { 1166 ret = bswap16(ret); 1167 } 1168 if (mop & MO_SIGN) { 1169 ret = (int16_t)ret; 1170 } 1171 break; 1172 case MO_32: 1173 ret = cpu_ldl_code_mmu(env, addr, oi, ra); 1174 if ((mop & MO_BSWAP) != MO_TE) { 1175 ret = bswap32(ret); 1176 } 1177 if (mop & MO_SIGN) { 1178 ret = (int32_t)ret; 1179 } 1180 break; 1181 case MO_64: 1182 ret = cpu_ldq_code_mmu(env, addr, oi, ra); 1183 if ((mop & MO_BSWAP) != MO_TE) { 1184 ret = bswap64(ret); 1185 } 1186 break; 1187 default: 1188 g_assert_not_reached(); 1189 } 1190 return ret; 1191 } 1192 1193 #endif /* CONFIG_USER_ONLY */ 1194 #else /* TARGET_SPARC64 */ 1195 1196 #ifdef CONFIG_USER_ONLY 1197 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1198 int asi, uint32_t memop) 1199 { 1200 int size = 1 << (memop & MO_SIZE); 1201 int sign = memop & MO_SIGN; 1202 uint64_t ret = 0; 1203 1204 if (asi < 0x80) { 1205 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1206 } 1207 do_check_align(env, addr, size - 1, GETPC()); 1208 addr = asi_address_mask(env, asi, addr); 1209 1210 switch (asi) { 1211 case ASI_PNF: /* Primary no-fault */ 1212 case ASI_PNFL: /* Primary no-fault LE */ 1213 case ASI_SNF: /* Secondary no-fault */ 1214 case ASI_SNFL: /* Secondary no-fault LE */ 1215 if (!page_check_range(addr, size, PAGE_READ)) { 1216 ret = 0; 1217 break; 1218 } 1219 switch (size) { 1220 case 1: 1221 ret = cpu_ldub_data(env, addr); 1222 break; 1223 case 2: 1224 ret = cpu_lduw_data(env, addr); 1225 break; 1226 case 4: 1227 ret = cpu_ldl_data(env, addr); 1228 break; 1229 case 8: 1230 ret = cpu_ldq_data(env, addr); 1231 break; 1232 default: 1233 g_assert_not_reached(); 1234 } 1235 break; 1236 break; 1237 1238 case ASI_P: /* Primary */ 1239 case ASI_PL: /* Primary LE */ 1240 case ASI_S: /* Secondary */ 1241 case ASI_SL: /* Secondary LE */ 1242 /* These are always handled inline. */ 1243 g_assert_not_reached(); 1244 1245 default: 1246 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1247 } 1248 1249 /* Convert from little endian */ 1250 switch (asi) { 1251 case ASI_PNFL: /* Primary no-fault LE */ 1252 case ASI_SNFL: /* Secondary no-fault LE */ 1253 switch (size) { 1254 case 2: 1255 ret = bswap16(ret); 1256 break; 1257 case 4: 1258 ret = bswap32(ret); 1259 break; 1260 case 8: 1261 ret = bswap64(ret); 1262 break; 1263 } 1264 } 1265 1266 /* Convert to signed number */ 1267 if (sign) { 1268 switch (size) { 1269 case 1: 1270 ret = (int8_t) ret; 1271 break; 1272 case 2: 1273 ret = (int16_t) ret; 1274 break; 1275 case 4: 1276 ret = (int32_t) ret; 1277 break; 1278 } 1279 } 1280 #ifdef DEBUG_ASI 1281 dump_asi("read", addr, asi, size, ret); 1282 #endif 1283 return ret; 1284 } 1285 1286 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1287 int asi, uint32_t memop) 1288 { 1289 int size = 1 << (memop & MO_SIZE); 1290 #ifdef DEBUG_ASI 1291 dump_asi("write", addr, asi, size, val); 1292 #endif 1293 if (asi < 0x80) { 1294 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1295 } 1296 do_check_align(env, addr, size - 1, GETPC()); 1297 1298 switch (asi) { 1299 case ASI_P: /* Primary */ 1300 case ASI_PL: /* Primary LE */ 1301 case ASI_S: /* Secondary */ 1302 case ASI_SL: /* Secondary LE */ 1303 /* These are always handled inline. */ 1304 g_assert_not_reached(); 1305 1306 case ASI_PNF: /* Primary no-fault, RO */ 1307 case ASI_SNF: /* Secondary no-fault, RO */ 1308 case ASI_PNFL: /* Primary no-fault LE, RO */ 1309 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1310 default: 1311 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1312 } 1313 } 1314 1315 #else /* CONFIG_USER_ONLY */ 1316 1317 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1318 int asi, uint32_t memop) 1319 { 1320 int size = 1 << (memop & MO_SIZE); 1321 int sign = memop & MO_SIGN; 1322 CPUState *cs = env_cpu(env); 1323 uint64_t ret = 0; 1324 #if defined(DEBUG_ASI) 1325 target_ulong last_addr = addr; 1326 #endif 1327 1328 asi &= 0xff; 1329 1330 do_check_asi(env, asi, GETPC()); 1331 do_check_align(env, addr, size - 1, GETPC()); 1332 addr = asi_address_mask(env, asi, addr); 1333 1334 switch (asi) { 1335 case ASI_PNF: 1336 case ASI_PNFL: 1337 case ASI_SNF: 1338 case ASI_SNFL: 1339 { 1340 MemOpIdx oi; 1341 int idx = (env->pstate & PS_PRIV 1342 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1343 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1344 1345 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1346 #ifdef DEBUG_ASI 1347 dump_asi("read ", last_addr, asi, size, ret); 1348 #endif 1349 /* exception_index is set in get_physical_address_data. */ 1350 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1351 } 1352 oi = make_memop_idx(memop, idx); 1353 switch (size) { 1354 case 1: 1355 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1356 break; 1357 case 2: 1358 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1359 break; 1360 case 4: 1361 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1362 break; 1363 case 8: 1364 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1365 break; 1366 default: 1367 g_assert_not_reached(); 1368 } 1369 } 1370 break; 1371 1372 case ASI_AIUP: /* As if user primary */ 1373 case ASI_AIUS: /* As if user secondary */ 1374 case ASI_AIUPL: /* As if user primary LE */ 1375 case ASI_AIUSL: /* As if user secondary LE */ 1376 case ASI_P: /* Primary */ 1377 case ASI_S: /* Secondary */ 1378 case ASI_PL: /* Primary LE */ 1379 case ASI_SL: /* Secondary LE */ 1380 case ASI_REAL: /* Bypass */ 1381 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1382 case ASI_REAL_L: /* Bypass LE */ 1383 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1384 case ASI_N: /* Nucleus */ 1385 case ASI_NL: /* Nucleus Little Endian (LE) */ 1386 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1387 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1388 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1389 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1390 case ASI_TWINX_REAL: /* Real address, twinx */ 1391 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1392 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1393 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1394 case ASI_TWINX_N: /* Nucleus, twinx */ 1395 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1396 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1397 case ASI_TWINX_P: /* Primary, twinx */ 1398 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1399 case ASI_TWINX_S: /* Secondary, twinx */ 1400 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1401 case ASI_MON_P: 1402 case ASI_MON_S: 1403 case ASI_MON_AIUP: 1404 case ASI_MON_AIUS: 1405 /* These are always handled inline. */ 1406 g_assert_not_reached(); 1407 1408 case ASI_UPA_CONFIG: /* UPA config */ 1409 /* XXX */ 1410 break; 1411 case ASI_LSU_CONTROL: /* LSU */ 1412 ret = env->lsu; 1413 break; 1414 case ASI_IMMU: /* I-MMU regs */ 1415 { 1416 int reg = (addr >> 3) & 0xf; 1417 switch (reg) { 1418 case 0: 1419 /* 0x00 I-TSB Tag Target register */ 1420 ret = ultrasparc_tag_target(env->immu.tag_access); 1421 break; 1422 case 3: /* SFSR */ 1423 ret = env->immu.sfsr; 1424 break; 1425 case 5: /* TSB access */ 1426 ret = env->immu.tsb; 1427 break; 1428 case 6: 1429 /* 0x30 I-TSB Tag Access register */ 1430 ret = env->immu.tag_access; 1431 break; 1432 default: 1433 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1434 ret = 0; 1435 } 1436 break; 1437 } 1438 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1439 { 1440 /* env->immuregs[5] holds I-MMU TSB register value 1441 env->immuregs[6] holds I-MMU Tag Access register value */ 1442 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1443 break; 1444 } 1445 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1446 { 1447 /* env->immuregs[5] holds I-MMU TSB register value 1448 env->immuregs[6] holds I-MMU Tag Access register value */ 1449 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1450 break; 1451 } 1452 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1453 { 1454 int reg = (addr >> 3) & 0x3f; 1455 1456 ret = env->itlb[reg].tte; 1457 break; 1458 } 1459 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1460 { 1461 int reg = (addr >> 3) & 0x3f; 1462 1463 ret = env->itlb[reg].tag; 1464 break; 1465 } 1466 case ASI_DMMU: /* D-MMU regs */ 1467 { 1468 int reg = (addr >> 3) & 0xf; 1469 switch (reg) { 1470 case 0: 1471 /* 0x00 D-TSB Tag Target register */ 1472 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1473 break; 1474 case 1: /* 0x08 Primary Context */ 1475 ret = env->dmmu.mmu_primary_context; 1476 break; 1477 case 2: /* 0x10 Secondary Context */ 1478 ret = env->dmmu.mmu_secondary_context; 1479 break; 1480 case 3: /* SFSR */ 1481 ret = env->dmmu.sfsr; 1482 break; 1483 case 4: /* 0x20 SFAR */ 1484 ret = env->dmmu.sfar; 1485 break; 1486 case 5: /* 0x28 TSB access */ 1487 ret = env->dmmu.tsb; 1488 break; 1489 case 6: /* 0x30 D-TSB Tag Access register */ 1490 ret = env->dmmu.tag_access; 1491 break; 1492 case 7: 1493 ret = env->dmmu.virtual_watchpoint; 1494 break; 1495 case 8: 1496 ret = env->dmmu.physical_watchpoint; 1497 break; 1498 default: 1499 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1500 ret = 0; 1501 } 1502 break; 1503 } 1504 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1505 { 1506 /* env->dmmuregs[5] holds D-MMU TSB register value 1507 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1508 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1509 break; 1510 } 1511 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1512 { 1513 /* env->dmmuregs[5] holds D-MMU TSB register value 1514 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1515 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1516 break; 1517 } 1518 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1519 { 1520 int reg = (addr >> 3) & 0x3f; 1521 1522 ret = env->dtlb[reg].tte; 1523 break; 1524 } 1525 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1526 { 1527 int reg = (addr >> 3) & 0x3f; 1528 1529 ret = env->dtlb[reg].tag; 1530 break; 1531 } 1532 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1533 break; 1534 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1535 ret = env->ivec_status; 1536 break; 1537 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1538 { 1539 int reg = (addr >> 4) & 0x3; 1540 if (reg < 3) { 1541 ret = env->ivec_data[reg]; 1542 } 1543 break; 1544 } 1545 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1546 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1547 /* Hyperprivileged access only */ 1548 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1549 } 1550 /* fall through */ 1551 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1552 { 1553 unsigned int i = (addr >> 3) & 0x7; 1554 ret = env->scratch[i]; 1555 break; 1556 } 1557 case ASI_MMU: /* UA2005 Context ID registers */ 1558 switch ((addr >> 3) & 0x3) { 1559 case 1: 1560 ret = env->dmmu.mmu_primary_context; 1561 break; 1562 case 2: 1563 ret = env->dmmu.mmu_secondary_context; 1564 break; 1565 default: 1566 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1567 } 1568 break; 1569 case ASI_DCACHE_DATA: /* D-cache data */ 1570 case ASI_DCACHE_TAG: /* D-cache tag access */ 1571 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1572 case ASI_AFSR: /* E-cache asynchronous fault status */ 1573 case ASI_AFAR: /* E-cache asynchronous fault address */ 1574 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1575 case ASI_IC_INSTR: /* I-cache instruction access */ 1576 case ASI_IC_TAG: /* I-cache tag access */ 1577 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1578 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1579 case ASI_EC_W: /* E-cache tag */ 1580 case ASI_EC_R: /* E-cache tag */ 1581 break; 1582 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1583 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1584 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1585 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1586 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1587 case ASI_INTR_W: /* Interrupt vector, WO */ 1588 default: 1589 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1590 ret = 0; 1591 break; 1592 } 1593 1594 /* Convert to signed number */ 1595 if (sign) { 1596 switch (size) { 1597 case 1: 1598 ret = (int8_t) ret; 1599 break; 1600 case 2: 1601 ret = (int16_t) ret; 1602 break; 1603 case 4: 1604 ret = (int32_t) ret; 1605 break; 1606 default: 1607 break; 1608 } 1609 } 1610 #ifdef DEBUG_ASI 1611 dump_asi("read ", last_addr, asi, size, ret); 1612 #endif 1613 return ret; 1614 } 1615 1616 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1617 int asi, uint32_t memop) 1618 { 1619 int size = 1 << (memop & MO_SIZE); 1620 CPUState *cs = env_cpu(env); 1621 1622 #ifdef DEBUG_ASI 1623 dump_asi("write", addr, asi, size, val); 1624 #endif 1625 1626 asi &= 0xff; 1627 1628 do_check_asi(env, asi, GETPC()); 1629 do_check_align(env, addr, size - 1, GETPC()); 1630 addr = asi_address_mask(env, asi, addr); 1631 1632 switch (asi) { 1633 case ASI_AIUP: /* As if user primary */ 1634 case ASI_AIUS: /* As if user secondary */ 1635 case ASI_AIUPL: /* As if user primary LE */ 1636 case ASI_AIUSL: /* As if user secondary LE */ 1637 case ASI_P: /* Primary */ 1638 case ASI_S: /* Secondary */ 1639 case ASI_PL: /* Primary LE */ 1640 case ASI_SL: /* Secondary LE */ 1641 case ASI_REAL: /* Bypass */ 1642 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1643 case ASI_REAL_L: /* Bypass LE */ 1644 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1645 case ASI_N: /* Nucleus */ 1646 case ASI_NL: /* Nucleus Little Endian (LE) */ 1647 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1648 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1649 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1650 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1651 case ASI_TWINX_REAL: /* Real address, twinx */ 1652 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1653 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1654 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1655 case ASI_TWINX_N: /* Nucleus, twinx */ 1656 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1657 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1658 case ASI_TWINX_P: /* Primary, twinx */ 1659 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1660 case ASI_TWINX_S: /* Secondary, twinx */ 1661 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1662 /* These are always handled inline. */ 1663 g_assert_not_reached(); 1664 /* these ASIs have different functions on UltraSPARC-IIIi 1665 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1666 */ 1667 case 0x31: 1668 case 0x32: 1669 case 0x39: 1670 case 0x3a: 1671 if (cpu_has_hypervisor(env)) { 1672 /* UA2005 1673 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1674 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1675 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1676 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1677 */ 1678 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1679 env->dmmu.sun4v_tsb_pointers[idx] = val; 1680 } else { 1681 goto illegal_insn; 1682 } 1683 break; 1684 case 0x33: 1685 case 0x3b: 1686 if (cpu_has_hypervisor(env)) { 1687 /* UA2005 1688 * ASI_DMMU_CTX_ZERO_CONFIG 1689 * ASI_DMMU_CTX_NONZERO_CONFIG 1690 */ 1691 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1692 } else { 1693 goto illegal_insn; 1694 } 1695 break; 1696 case 0x35: 1697 case 0x36: 1698 case 0x3d: 1699 case 0x3e: 1700 if (cpu_has_hypervisor(env)) { 1701 /* UA2005 1702 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1703 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1704 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1705 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1706 */ 1707 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1708 env->immu.sun4v_tsb_pointers[idx] = val; 1709 } else { 1710 goto illegal_insn; 1711 } 1712 break; 1713 case 0x37: 1714 case 0x3f: 1715 if (cpu_has_hypervisor(env)) { 1716 /* UA2005 1717 * ASI_IMMU_CTX_ZERO_CONFIG 1718 * ASI_IMMU_CTX_NONZERO_CONFIG 1719 */ 1720 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1721 } else { 1722 goto illegal_insn; 1723 } 1724 break; 1725 case ASI_UPA_CONFIG: /* UPA config */ 1726 /* XXX */ 1727 return; 1728 case ASI_LSU_CONTROL: /* LSU */ 1729 env->lsu = val & (DMMU_E | IMMU_E); 1730 return; 1731 case ASI_IMMU: /* I-MMU regs */ 1732 { 1733 int reg = (addr >> 3) & 0xf; 1734 uint64_t oldreg; 1735 1736 oldreg = env->immu.mmuregs[reg]; 1737 switch (reg) { 1738 case 0: /* RO */ 1739 return; 1740 case 1: /* Not in I-MMU */ 1741 case 2: 1742 return; 1743 case 3: /* SFSR */ 1744 if ((val & 1) == 0) { 1745 val = 0; /* Clear SFSR */ 1746 } 1747 env->immu.sfsr = val; 1748 break; 1749 case 4: /* RO */ 1750 return; 1751 case 5: /* TSB access */ 1752 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1753 PRIx64 "\n", env->immu.tsb, val); 1754 env->immu.tsb = val; 1755 break; 1756 case 6: /* Tag access */ 1757 env->immu.tag_access = val; 1758 break; 1759 case 7: 1760 case 8: 1761 return; 1762 default: 1763 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1764 break; 1765 } 1766 1767 if (oldreg != env->immu.mmuregs[reg]) { 1768 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1769 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1770 } 1771 #ifdef DEBUG_MMU 1772 dump_mmu(env); 1773 #endif 1774 return; 1775 } 1776 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1777 /* ignore real translation entries */ 1778 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1779 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1780 val, "immu", env, addr); 1781 } 1782 return; 1783 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1784 { 1785 /* TODO: auto demap */ 1786 1787 unsigned int i = (addr >> 3) & 0x3f; 1788 1789 /* ignore real translation entries */ 1790 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1791 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1792 sun4v_tte_to_sun4u(env, addr, val), env); 1793 } 1794 #ifdef DEBUG_MMU 1795 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1796 dump_mmu(env); 1797 #endif 1798 return; 1799 } 1800 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1801 demap_tlb(env->itlb, addr, "immu", env); 1802 return; 1803 case ASI_DMMU: /* D-MMU regs */ 1804 { 1805 int reg = (addr >> 3) & 0xf; 1806 uint64_t oldreg; 1807 1808 oldreg = env->dmmu.mmuregs[reg]; 1809 switch (reg) { 1810 case 0: /* RO */ 1811 case 4: 1812 return; 1813 case 3: /* SFSR */ 1814 if ((val & 1) == 0) { 1815 val = 0; /* Clear SFSR, Fault address */ 1816 env->dmmu.sfar = 0; 1817 } 1818 env->dmmu.sfsr = val; 1819 break; 1820 case 1: /* Primary context */ 1821 env->dmmu.mmu_primary_context = val; 1822 /* can be optimized to only flush MMU_USER_IDX 1823 and MMU_KERNEL_IDX entries */ 1824 tlb_flush(cs); 1825 break; 1826 case 2: /* Secondary context */ 1827 env->dmmu.mmu_secondary_context = val; 1828 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1829 and MMU_KERNEL_SECONDARY_IDX entries */ 1830 tlb_flush(cs); 1831 break; 1832 case 5: /* TSB access */ 1833 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1834 PRIx64 "\n", env->dmmu.tsb, val); 1835 env->dmmu.tsb = val; 1836 break; 1837 case 6: /* Tag access */ 1838 env->dmmu.tag_access = val; 1839 break; 1840 case 7: /* Virtual Watchpoint */ 1841 env->dmmu.virtual_watchpoint = val; 1842 break; 1843 case 8: /* Physical Watchpoint */ 1844 env->dmmu.physical_watchpoint = val; 1845 break; 1846 default: 1847 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1848 break; 1849 } 1850 1851 if (oldreg != env->dmmu.mmuregs[reg]) { 1852 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1853 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1854 } 1855 #ifdef DEBUG_MMU 1856 dump_mmu(env); 1857 #endif 1858 return; 1859 } 1860 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1861 /* ignore real translation entries */ 1862 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1863 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1864 val, "dmmu", env, addr); 1865 } 1866 return; 1867 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1868 { 1869 unsigned int i = (addr >> 3) & 0x3f; 1870 1871 /* ignore real translation entries */ 1872 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1873 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1874 sun4v_tte_to_sun4u(env, addr, val), env); 1875 } 1876 #ifdef DEBUG_MMU 1877 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1878 dump_mmu(env); 1879 #endif 1880 return; 1881 } 1882 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1883 demap_tlb(env->dtlb, addr, "dmmu", env); 1884 return; 1885 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1886 env->ivec_status = val & 0x20; 1887 return; 1888 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1889 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1890 /* Hyperprivileged access only */ 1891 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1892 } 1893 /* fall through */ 1894 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1895 { 1896 unsigned int i = (addr >> 3) & 0x7; 1897 env->scratch[i] = val; 1898 return; 1899 } 1900 case ASI_MMU: /* UA2005 Context ID registers */ 1901 { 1902 switch ((addr >> 3) & 0x3) { 1903 case 1: 1904 env->dmmu.mmu_primary_context = val; 1905 env->immu.mmu_primary_context = val; 1906 tlb_flush_by_mmuidx(cs, 1907 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1908 break; 1909 case 2: 1910 env->dmmu.mmu_secondary_context = val; 1911 env->immu.mmu_secondary_context = val; 1912 tlb_flush_by_mmuidx(cs, 1913 (1 << MMU_USER_SECONDARY_IDX) | 1914 (1 << MMU_KERNEL_SECONDARY_IDX)); 1915 break; 1916 default: 1917 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1918 } 1919 } 1920 return; 1921 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1922 case ASI_DCACHE_DATA: /* D-cache data */ 1923 case ASI_DCACHE_TAG: /* D-cache tag access */ 1924 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1925 case ASI_AFSR: /* E-cache asynchronous fault status */ 1926 case ASI_AFAR: /* E-cache asynchronous fault address */ 1927 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1928 case ASI_IC_INSTR: /* I-cache instruction access */ 1929 case ASI_IC_TAG: /* I-cache tag access */ 1930 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1931 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1932 case ASI_EC_W: /* E-cache tag */ 1933 case ASI_EC_R: /* E-cache tag */ 1934 return; 1935 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1936 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1937 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1938 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1939 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1940 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1941 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1942 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1943 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1944 case ASI_PNF: /* Primary no-fault, RO */ 1945 case ASI_SNF: /* Secondary no-fault, RO */ 1946 case ASI_PNFL: /* Primary no-fault LE, RO */ 1947 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1948 default: 1949 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1950 return; 1951 illegal_insn: 1952 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1953 } 1954 } 1955 #endif /* CONFIG_USER_ONLY */ 1956 #endif /* TARGET_SPARC64 */ 1957 1958 #if !defined(CONFIG_USER_ONLY) 1959 1960 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1961 vaddr addr, unsigned size, 1962 MMUAccessType access_type, 1963 int mmu_idx, MemTxAttrs attrs, 1964 MemTxResult response, uintptr_t retaddr) 1965 { 1966 bool is_write = access_type == MMU_DATA_STORE; 1967 bool is_exec = access_type == MMU_INST_FETCH; 1968 bool is_asi = false; 1969 1970 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1971 is_asi, size, retaddr); 1972 } 1973 #endif 1974