1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/range.h" 23 #include "cpu.h" 24 #include "tcg/tcg.h" 25 #include "exec/helper-proto.h" 26 #include "exec/exec-all.h" 27 #include "exec/page-protection.h" 28 #include "exec/cpu_ldst.h" 29 #ifdef CONFIG_USER_ONLY 30 #include "user/page-protection.h" 31 #endif 32 #include "asi.h" 33 34 //#define DEBUG_MMU 35 //#define DEBUG_MXCC 36 //#define DEBUG_UNASSIGNED 37 //#define DEBUG_ASI 38 //#define DEBUG_CACHE_CONTROL 39 40 #ifdef DEBUG_MMU 41 #define DPRINTF_MMU(fmt, ...) \ 42 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 43 #else 44 #define DPRINTF_MMU(fmt, ...) do {} while (0) 45 #endif 46 47 #ifdef DEBUG_MXCC 48 #define DPRINTF_MXCC(fmt, ...) \ 49 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 50 #else 51 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 52 #endif 53 54 #ifdef DEBUG_ASI 55 #define DPRINTF_ASI(fmt, ...) \ 56 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 57 #endif 58 59 #ifdef DEBUG_CACHE_CONTROL 60 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 61 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 62 #else 63 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 64 #endif 65 66 #ifdef TARGET_SPARC64 67 #ifndef TARGET_ABI32 68 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 69 #else 70 #define AM_CHECK(env1) (1) 71 #endif 72 #endif 73 74 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 75 /* Calculates TSB pointer value for fault page size 76 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 77 * UA2005 holds the page size configuration in mmu_ctx registers */ 78 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 79 const SparcV9MMU *mmu, const int idx) 80 { 81 uint64_t tsb_register; 82 int page_size; 83 if (cpu_has_hypervisor(env)) { 84 int tsb_index = 0; 85 int ctx = mmu->tag_access & 0x1fffULL; 86 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 87 tsb_index = idx; 88 tsb_index |= ctx ? 2 : 0; 89 page_size = idx ? ctx_register >> 8 : ctx_register; 90 page_size &= 7; 91 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 92 } else { 93 page_size = idx; 94 tsb_register = mmu->tsb; 95 } 96 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 97 int tsb_size = tsb_register & 0xf; 98 99 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 100 101 /* move va bits to correct position, 102 * the context bits will be masked out later */ 103 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 104 105 /* calculate tsb_base mask and adjust va if split is in use */ 106 if (tsb_split) { 107 if (idx == 0) { 108 va &= ~(1ULL << (13 + tsb_size)); 109 } else { 110 va |= (1ULL << (13 + tsb_size)); 111 } 112 tsb_base_mask <<= 1; 113 } 114 115 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 116 } 117 118 /* Calculates tag target register value by reordering bits 119 in tag access register */ 120 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 121 { 122 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 123 } 124 125 static void replace_tlb_entry(SparcTLBEntry *tlb, 126 uint64_t tlb_tag, uint64_t tlb_tte, 127 CPUSPARCState *env) 128 { 129 target_ulong mask, size, va, offset; 130 131 /* flush page range if translation is valid */ 132 if (TTE_IS_VALID(tlb->tte)) { 133 CPUState *cs = env_cpu(env); 134 135 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 136 mask = 1ULL + ~size; 137 138 va = tlb->tag & mask; 139 140 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 141 tlb_flush_page(cs, va + offset); 142 } 143 } 144 145 tlb->tag = tlb_tag; 146 tlb->tte = tlb_tte; 147 } 148 149 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 150 const char *strmmu, CPUSPARCState *env1) 151 { 152 unsigned int i; 153 target_ulong mask; 154 uint64_t context; 155 156 int is_demap_context = (demap_addr >> 6) & 1; 157 158 /* demap context */ 159 switch ((demap_addr >> 4) & 3) { 160 case 0: /* primary */ 161 context = env1->dmmu.mmu_primary_context; 162 break; 163 case 1: /* secondary */ 164 context = env1->dmmu.mmu_secondary_context; 165 break; 166 case 2: /* nucleus */ 167 context = 0; 168 break; 169 case 3: /* reserved */ 170 default: 171 return; 172 } 173 174 for (i = 0; i < 64; i++) { 175 if (TTE_IS_VALID(tlb[i].tte)) { 176 177 if (is_demap_context) { 178 /* will remove non-global entries matching context value */ 179 if (TTE_IS_GLOBAL(tlb[i].tte) || 180 !tlb_compare_context(&tlb[i], context)) { 181 continue; 182 } 183 } else { 184 /* demap page 185 will remove any entry matching VA */ 186 mask = 0xffffffffffffe000ULL; 187 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 188 189 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 190 continue; 191 } 192 193 /* entry should be global or matching context value */ 194 if (!TTE_IS_GLOBAL(tlb[i].tte) && 195 !tlb_compare_context(&tlb[i], context)) { 196 continue; 197 } 198 } 199 200 replace_tlb_entry(&tlb[i], 0, 0, env1); 201 #ifdef DEBUG_MMU 202 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 203 dump_mmu(env1); 204 #endif 205 } 206 } 207 } 208 209 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 210 uint64_t sun4v_tte) 211 { 212 uint64_t sun4u_tte; 213 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 214 /* is already in the sun4u format */ 215 return sun4v_tte; 216 } 217 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 218 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 221 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 222 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 223 TTE_SIDEEFFECT_BIT); 224 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 225 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 226 return sun4u_tte; 227 } 228 229 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 230 uint64_t tlb_tag, uint64_t tlb_tte, 231 const char *strmmu, CPUSPARCState *env1, 232 uint64_t addr) 233 { 234 unsigned int i, replace_used; 235 236 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 237 if (cpu_has_hypervisor(env1)) { 238 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 239 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 240 uint32_t new_ctx = tlb_tag & 0x1fffU; 241 for (i = 0; i < 64; i++) { 242 uint32_t ctx = tlb[i].tag & 0x1fffU; 243 /* check if new mapping overlaps an existing one */ 244 if (new_ctx == ctx) { 245 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 246 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 247 if (ranges_overlap(new_vaddr, new_size, vaddr, size)) { 248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 249 new_vaddr); 250 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 251 return; 252 } 253 } 254 255 } 256 } 257 /* Try replacing invalid entry */ 258 for (i = 0; i < 64; i++) { 259 if (!TTE_IS_VALID(tlb[i].tte)) { 260 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 261 #ifdef DEBUG_MMU 262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 263 dump_mmu(env1); 264 #endif 265 return; 266 } 267 } 268 269 /* All entries are valid, try replacing unlocked entry */ 270 271 for (replace_used = 0; replace_used < 2; ++replace_used) { 272 273 /* Used entries are not replaced on first pass */ 274 275 for (i = 0; i < 64; i++) { 276 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 277 278 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 279 #ifdef DEBUG_MMU 280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 281 strmmu, (replace_used ? "used" : "unused"), i); 282 dump_mmu(env1); 283 #endif 284 return; 285 } 286 } 287 288 /* Now reset used bit and search for unused entries again */ 289 290 for (i = 0; i < 64; i++) { 291 TTE_SET_UNUSED(tlb[i].tte); 292 } 293 } 294 295 #ifdef DEBUG_MMU 296 DPRINTF_MMU("%s lru replacement: no free entries available, " 297 "replacing the last one\n", strmmu); 298 #endif 299 /* corner case: the last entry is replaced anyway */ 300 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 301 } 302 303 #endif 304 305 #ifdef TARGET_SPARC64 306 /* returns true if access using this ASI is to have address translated by MMU 307 otherwise access is to raw physical address */ 308 /* TODO: check sparc32 bits */ 309 static inline int is_translating_asi(int asi) 310 { 311 /* Ultrasparc IIi translating asi 312 - note this list is defined by cpu implementation 313 */ 314 switch (asi) { 315 case 0x04 ... 0x11: 316 case 0x16 ... 0x19: 317 case 0x1E ... 0x1F: 318 case 0x24 ... 0x2C: 319 case 0x70 ... 0x73: 320 case 0x78 ... 0x79: 321 case 0x80 ... 0xFF: 322 return 1; 323 324 default: 325 return 0; 326 } 327 } 328 329 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 330 { 331 if (AM_CHECK(env1)) { 332 addr &= 0xffffffffULL; 333 } 334 return addr; 335 } 336 337 static inline target_ulong asi_address_mask(CPUSPARCState *env, 338 int asi, target_ulong addr) 339 { 340 if (is_translating_asi(asi)) { 341 addr = address_mask(env, addr); 342 } 343 return addr; 344 } 345 346 #ifndef CONFIG_USER_ONLY 347 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 348 { 349 /* ASIs >= 0x80 are user mode. 350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 351 * ASIs <= 0x2f are super mode. 352 */ 353 if (asi < 0x80 354 && !cpu_hypervisor_mode(env) 355 && (!cpu_supervisor_mode(env) 356 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 357 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 358 } 359 } 360 #endif /* !CONFIG_USER_ONLY */ 361 #endif 362 363 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 364 static void do_check_align(CPUSPARCState *env, target_ulong addr, 365 uint32_t align, uintptr_t ra) 366 { 367 if (addr & align) { 368 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 369 } 370 } 371 #endif 372 373 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 374 defined(DEBUG_MXCC) 375 static void dump_mxcc(CPUSPARCState *env) 376 { 377 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 378 "\n", 379 env->mxccdata[0], env->mxccdata[1], 380 env->mxccdata[2], env->mxccdata[3]); 381 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 382 "\n" 383 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 384 "\n", 385 env->mxccregs[0], env->mxccregs[1], 386 env->mxccregs[2], env->mxccregs[3], 387 env->mxccregs[4], env->mxccregs[5], 388 env->mxccregs[6], env->mxccregs[7]); 389 } 390 #endif 391 392 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 393 && defined(DEBUG_ASI) 394 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 395 uint64_t r1) 396 { 397 switch (size) { 398 case 1: 399 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 400 addr, asi, r1 & 0xff); 401 break; 402 case 2: 403 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 404 addr, asi, r1 & 0xffff); 405 break; 406 case 4: 407 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 408 addr, asi, r1 & 0xffffffff); 409 break; 410 case 8: 411 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 412 addr, asi, r1); 413 break; 414 } 415 } 416 #endif 417 418 #ifndef CONFIG_USER_ONLY 419 #ifndef TARGET_SPARC64 420 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 421 bool is_write, bool is_exec, int is_asi, 422 unsigned size, uintptr_t retaddr) 423 { 424 CPUSPARCState *env = cpu_env(cs); 425 int fault_type; 426 427 #ifdef DEBUG_UNASSIGNED 428 if (is_asi) { 429 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 430 " asi 0x%02x from " TARGET_FMT_lx "\n", 431 is_exec ? "exec" : is_write ? "write" : "read", size, 432 size == 1 ? "" : "s", addr, is_asi, env->pc); 433 } else { 434 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 435 " from " TARGET_FMT_lx "\n", 436 is_exec ? "exec" : is_write ? "write" : "read", size, 437 size == 1 ? "" : "s", addr, env->pc); 438 } 439 #endif 440 /* Don't overwrite translation and access faults */ 441 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 442 if ((fault_type > 4) || (fault_type == 0)) { 443 env->mmuregs[3] = 0; /* Fault status register */ 444 if (is_asi) { 445 env->mmuregs[3] |= 1 << 16; 446 } 447 if (env->psrs) { 448 env->mmuregs[3] |= 1 << 5; 449 } 450 if (is_exec) { 451 env->mmuregs[3] |= 1 << 6; 452 } 453 if (is_write) { 454 env->mmuregs[3] |= 1 << 7; 455 } 456 env->mmuregs[3] |= (5 << 2) | 2; 457 /* SuperSPARC will never place instruction fault addresses in the FAR */ 458 if (!is_exec) { 459 env->mmuregs[4] = addr; /* Fault address register */ 460 } 461 } 462 /* overflow (same type fault was not read before another fault) */ 463 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 464 env->mmuregs[3] |= 1; 465 } 466 467 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 468 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 469 cpu_raise_exception_ra(env, tt, retaddr); 470 } 471 472 /* 473 * flush neverland mappings created during no-fault mode, 474 * so the sequential MMU faults report proper fault types 475 */ 476 if (env->mmuregs[0] & MMU_NF) { 477 tlb_flush(cs); 478 } 479 } 480 #else 481 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 482 bool is_write, bool is_exec, int is_asi, 483 unsigned size, uintptr_t retaddr) 484 { 485 CPUSPARCState *env = cpu_env(cs); 486 487 #ifdef DEBUG_UNASSIGNED 488 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 489 "\n", addr, env->pc); 490 #endif 491 492 if (is_exec) { /* XXX has_hypervisor */ 493 if (env->lsu & (IMMU_E)) { 494 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 495 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 496 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 497 } 498 } else { 499 if (env->lsu & (DMMU_E)) { 500 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 501 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 502 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 503 } 504 } 505 } 506 #endif 507 #endif 508 509 #ifndef TARGET_SPARC64 510 #ifndef CONFIG_USER_ONLY 511 512 513 /* Leon3 cache control */ 514 515 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 516 uint64_t val, int size) 517 { 518 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 519 addr, val, size); 520 521 if (size != 4) { 522 DPRINTF_CACHE_CONTROL("32bits only\n"); 523 return; 524 } 525 526 switch (addr) { 527 case 0x00: /* Cache control */ 528 529 /* These values must always be read as zeros */ 530 val &= ~CACHE_CTRL_FD; 531 val &= ~CACHE_CTRL_FI; 532 val &= ~CACHE_CTRL_IB; 533 val &= ~CACHE_CTRL_IP; 534 val &= ~CACHE_CTRL_DP; 535 536 env->cache_control = val; 537 break; 538 case 0x04: /* Instruction cache configuration */ 539 case 0x08: /* Data cache configuration */ 540 /* Read Only */ 541 break; 542 default: 543 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 544 break; 545 }; 546 } 547 548 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 549 int size) 550 { 551 uint64_t ret = 0; 552 553 if (size != 4) { 554 DPRINTF_CACHE_CONTROL("32bits only\n"); 555 return 0; 556 } 557 558 switch (addr) { 559 case 0x00: /* Cache control */ 560 ret = env->cache_control; 561 break; 562 563 /* Configuration registers are read and only always keep those 564 predefined values */ 565 566 case 0x04: /* Instruction cache configuration */ 567 ret = 0x10220000; 568 break; 569 case 0x08: /* Data cache configuration */ 570 ret = 0x18220000; 571 break; 572 default: 573 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 574 break; 575 }; 576 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 577 addr, ret, size); 578 return ret; 579 } 580 581 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 582 int asi, uint32_t memop) 583 { 584 int size = 1 << (memop & MO_SIZE); 585 int sign = memop & MO_SIGN; 586 CPUState *cs = env_cpu(env); 587 uint64_t ret = 0; 588 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 589 uint32_t last_addr = addr; 590 #endif 591 592 do_check_align(env, addr, size - 1, GETPC()); 593 switch (asi) { 594 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 595 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 596 switch (addr) { 597 case 0x00: /* Leon3 Cache Control */ 598 case 0x08: /* Leon3 Instruction Cache config */ 599 case 0x0C: /* Leon3 Date Cache config */ 600 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 601 ret = leon3_cache_control_ld(env, addr, size); 602 } 603 break; 604 case 0x01c00a00: /* MXCC control register */ 605 if (size == 8) { 606 ret = env->mxccregs[3]; 607 } else { 608 qemu_log_mask(LOG_UNIMP, 609 "%08x: unimplemented access size: %d\n", addr, 610 size); 611 } 612 break; 613 case 0x01c00a04: /* MXCC control register */ 614 if (size == 4) { 615 ret = env->mxccregs[3]; 616 } else { 617 qemu_log_mask(LOG_UNIMP, 618 "%08x: unimplemented access size: %d\n", addr, 619 size); 620 } 621 break; 622 case 0x01c00c00: /* Module reset register */ 623 if (size == 8) { 624 ret = env->mxccregs[5]; 625 /* should we do something here? */ 626 } else { 627 qemu_log_mask(LOG_UNIMP, 628 "%08x: unimplemented access size: %d\n", addr, 629 size); 630 } 631 break; 632 case 0x01c00f00: /* MBus port address register */ 633 if (size == 8) { 634 ret = env->mxccregs[7]; 635 } else { 636 qemu_log_mask(LOG_UNIMP, 637 "%08x: unimplemented access size: %d\n", addr, 638 size); 639 } 640 break; 641 default: 642 qemu_log_mask(LOG_UNIMP, 643 "%08x: unimplemented address, size: %d\n", addr, 644 size); 645 break; 646 } 647 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 648 "addr = %08x -> ret = %" PRIx64 "," 649 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 650 #ifdef DEBUG_MXCC 651 dump_mxcc(env); 652 #endif 653 break; 654 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 655 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 656 { 657 int mmulev; 658 659 mmulev = (addr >> 8) & 15; 660 if (mmulev > 4) { 661 ret = 0; 662 } else { 663 ret = mmu_probe(env, addr, mmulev); 664 } 665 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 666 addr, mmulev, ret); 667 } 668 break; 669 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 670 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 671 { 672 int reg = (addr >> 8) & 0x1f; 673 674 ret = env->mmuregs[reg]; 675 if (reg == 3) { /* Fault status cleared on read */ 676 env->mmuregs[3] = 0; 677 } else if (reg == 0x13) { /* Fault status read */ 678 ret = env->mmuregs[3]; 679 } else if (reg == 0x14) { /* Fault address read */ 680 ret = env->mmuregs[4]; 681 } 682 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 683 } 684 break; 685 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 686 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 687 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 688 break; 689 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 690 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 691 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 692 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 693 break; 694 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 695 { 696 MemTxResult result; 697 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 698 699 switch (size) { 700 case 1: 701 ret = address_space_ldub(cs->as, access_addr, 702 MEMTXATTRS_UNSPECIFIED, &result); 703 break; 704 case 2: 705 ret = address_space_lduw(cs->as, access_addr, 706 MEMTXATTRS_UNSPECIFIED, &result); 707 break; 708 default: 709 case 4: 710 ret = address_space_ldl(cs->as, access_addr, 711 MEMTXATTRS_UNSPECIFIED, &result); 712 break; 713 case 8: 714 ret = address_space_ldq(cs->as, access_addr, 715 MEMTXATTRS_UNSPECIFIED, &result); 716 break; 717 } 718 719 if (result != MEMTX_OK) { 720 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 721 size, GETPC()); 722 } 723 break; 724 } 725 case 0x30: /* Turbosparc secondary cache diagnostic */ 726 case 0x31: /* Turbosparc RAM snoop */ 727 case 0x32: /* Turbosparc page table descriptor diagnostic */ 728 case 0x39: /* data cache diagnostic register */ 729 ret = 0; 730 break; 731 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 732 { 733 int reg = (addr >> 8) & 3; 734 735 switch (reg) { 736 case 0: /* Breakpoint Value (Addr) */ 737 ret = env->mmubpregs[reg]; 738 break; 739 case 1: /* Breakpoint Mask */ 740 ret = env->mmubpregs[reg]; 741 break; 742 case 2: /* Breakpoint Control */ 743 ret = env->mmubpregs[reg]; 744 break; 745 case 3: /* Breakpoint Status */ 746 ret = env->mmubpregs[reg]; 747 env->mmubpregs[reg] = 0ULL; 748 break; 749 } 750 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 751 ret); 752 } 753 break; 754 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 755 ret = env->mmubpctrv; 756 break; 757 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 758 ret = env->mmubpctrc; 759 break; 760 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 761 ret = env->mmubpctrs; 762 break; 763 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 764 ret = env->mmubpaction; 765 break; 766 default: 767 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 768 ret = 0; 769 break; 770 771 case ASI_USERDATA: /* User data access */ 772 case ASI_KERNELDATA: /* Supervisor data access */ 773 case ASI_USERTXT: /* User code access */ 774 case ASI_KERNELTXT: /* Supervisor code access */ 775 case ASI_P: /* Implicit primary context data access (v9 only?) */ 776 case ASI_M_BYPASS: /* MMU passthrough */ 777 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 778 /* These are always handled inline. */ 779 g_assert_not_reached(); 780 } 781 if (sign) { 782 switch (size) { 783 case 1: 784 ret = (int8_t) ret; 785 break; 786 case 2: 787 ret = (int16_t) ret; 788 break; 789 case 4: 790 ret = (int32_t) ret; 791 break; 792 default: 793 break; 794 } 795 } 796 #ifdef DEBUG_ASI 797 dump_asi("read ", last_addr, asi, size, ret); 798 #endif 799 return ret; 800 } 801 802 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 803 int asi, uint32_t memop) 804 { 805 int size = 1 << (memop & MO_SIZE); 806 CPUState *cs = env_cpu(env); 807 808 do_check_align(env, addr, size - 1, GETPC()); 809 switch (asi) { 810 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 811 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 812 switch (addr) { 813 case 0x00: /* Leon3 Cache Control */ 814 case 0x08: /* Leon3 Instruction Cache config */ 815 case 0x0C: /* Leon3 Date Cache config */ 816 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 817 leon3_cache_control_st(env, addr, val, size); 818 } 819 break; 820 821 case 0x01c00000: /* MXCC stream data register 0 */ 822 if (size == 8) { 823 env->mxccdata[0] = val; 824 } else { 825 qemu_log_mask(LOG_UNIMP, 826 "%08x: unimplemented access size: %d\n", addr, 827 size); 828 } 829 break; 830 case 0x01c00008: /* MXCC stream data register 1 */ 831 if (size == 8) { 832 env->mxccdata[1] = val; 833 } else { 834 qemu_log_mask(LOG_UNIMP, 835 "%08x: unimplemented access size: %d\n", addr, 836 size); 837 } 838 break; 839 case 0x01c00010: /* MXCC stream data register 2 */ 840 if (size == 8) { 841 env->mxccdata[2] = val; 842 } else { 843 qemu_log_mask(LOG_UNIMP, 844 "%08x: unimplemented access size: %d\n", addr, 845 size); 846 } 847 break; 848 case 0x01c00018: /* MXCC stream data register 3 */ 849 if (size == 8) { 850 env->mxccdata[3] = val; 851 } else { 852 qemu_log_mask(LOG_UNIMP, 853 "%08x: unimplemented access size: %d\n", addr, 854 size); 855 } 856 break; 857 case 0x01c00100: /* MXCC stream source */ 858 { 859 int i; 860 861 if (size == 8) { 862 env->mxccregs[0] = val; 863 } else { 864 qemu_log_mask(LOG_UNIMP, 865 "%08x: unimplemented access size: %d\n", addr, 866 size); 867 } 868 869 for (i = 0; i < 4; i++) { 870 MemTxResult result; 871 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 872 873 env->mxccdata[i] = address_space_ldq(cs->as, 874 access_addr, 875 MEMTXATTRS_UNSPECIFIED, 876 &result); 877 if (result != MEMTX_OK) { 878 /* TODO: investigate whether this is the right behaviour */ 879 sparc_raise_mmu_fault(cs, access_addr, false, false, 880 false, size, GETPC()); 881 } 882 } 883 break; 884 } 885 case 0x01c00200: /* MXCC stream destination */ 886 { 887 int i; 888 889 if (size == 8) { 890 env->mxccregs[1] = val; 891 } else { 892 qemu_log_mask(LOG_UNIMP, 893 "%08x: unimplemented access size: %d\n", addr, 894 size); 895 } 896 897 for (i = 0; i < 4; i++) { 898 MemTxResult result; 899 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 900 901 address_space_stq(cs->as, access_addr, env->mxccdata[i], 902 MEMTXATTRS_UNSPECIFIED, &result); 903 904 if (result != MEMTX_OK) { 905 /* TODO: investigate whether this is the right behaviour */ 906 sparc_raise_mmu_fault(cs, access_addr, true, false, 907 false, size, GETPC()); 908 } 909 } 910 break; 911 } 912 case 0x01c00a00: /* MXCC control register */ 913 if (size == 8) { 914 env->mxccregs[3] = val; 915 } else { 916 qemu_log_mask(LOG_UNIMP, 917 "%08x: unimplemented access size: %d\n", addr, 918 size); 919 } 920 break; 921 case 0x01c00a04: /* MXCC control register */ 922 if (size == 4) { 923 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 924 | val; 925 } else { 926 qemu_log_mask(LOG_UNIMP, 927 "%08x: unimplemented access size: %d\n", addr, 928 size); 929 } 930 break; 931 case 0x01c00e00: /* MXCC error register */ 932 /* writing a 1 bit clears the error */ 933 if (size == 8) { 934 env->mxccregs[6] &= ~val; 935 } else { 936 qemu_log_mask(LOG_UNIMP, 937 "%08x: unimplemented access size: %d\n", addr, 938 size); 939 } 940 break; 941 case 0x01c00f00: /* MBus port address register */ 942 if (size == 8) { 943 env->mxccregs[7] = val; 944 } else { 945 qemu_log_mask(LOG_UNIMP, 946 "%08x: unimplemented access size: %d\n", addr, 947 size); 948 } 949 break; 950 default: 951 qemu_log_mask(LOG_UNIMP, 952 "%08x: unimplemented address, size: %d\n", addr, 953 size); 954 break; 955 } 956 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 957 asi, size, addr, val); 958 #ifdef DEBUG_MXCC 959 dump_mxcc(env); 960 #endif 961 break; 962 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 963 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 964 { 965 int mmulev; 966 967 mmulev = (addr >> 8) & 15; 968 DPRINTF_MMU("mmu flush level %d\n", mmulev); 969 switch (mmulev) { 970 case 0: /* flush page */ 971 tlb_flush_page(cs, addr & 0xfffff000); 972 break; 973 case 1: /* flush segment (256k) */ 974 case 2: /* flush region (16M) */ 975 case 3: /* flush context (4G) */ 976 case 4: /* flush entire */ 977 tlb_flush(cs); 978 break; 979 default: 980 break; 981 } 982 #ifdef DEBUG_MMU 983 dump_mmu(env); 984 #endif 985 } 986 break; 987 case ASI_M_MMUREGS: /* write MMU regs */ 988 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 989 { 990 int reg = (addr >> 8) & 0x1f; 991 uint32_t oldreg; 992 993 oldreg = env->mmuregs[reg]; 994 switch (reg) { 995 case 0: /* Control Register */ 996 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 997 (val & 0x00ffffff); 998 /* Mappings generated during no-fault mode 999 are invalid in normal mode. */ 1000 if ((oldreg ^ env->mmuregs[reg]) 1001 & (MMU_NF | env->def.mmu_bm)) { 1002 tlb_flush(cs); 1003 } 1004 break; 1005 case 1: /* Context Table Pointer Register */ 1006 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1007 break; 1008 case 2: /* Context Register */ 1009 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1010 if (oldreg != env->mmuregs[reg]) { 1011 /* we flush when the MMU context changes because 1012 QEMU has no MMU context support */ 1013 tlb_flush(cs); 1014 } 1015 break; 1016 case 3: /* Synchronous Fault Status Register with Clear */ 1017 case 4: /* Synchronous Fault Address Register */ 1018 break; 1019 case 0x10: /* TLB Replacement Control Register */ 1020 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1021 break; 1022 case 0x13: /* Synchronous Fault Status Register with Read 1023 and Clear */ 1024 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1025 break; 1026 case 0x14: /* Synchronous Fault Address Register */ 1027 env->mmuregs[4] = val; 1028 break; 1029 default: 1030 env->mmuregs[reg] = val; 1031 break; 1032 } 1033 if (oldreg != env->mmuregs[reg]) { 1034 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1035 reg, oldreg, env->mmuregs[reg]); 1036 } 1037 #ifdef DEBUG_MMU 1038 dump_mmu(env); 1039 #endif 1040 } 1041 break; 1042 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1043 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1044 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1045 break; 1046 case ASI_M_TXTC_TAG: /* I-cache tag */ 1047 case ASI_M_TXTC_DATA: /* I-cache data */ 1048 case ASI_M_DATAC_TAG: /* D-cache tag */ 1049 case ASI_M_DATAC_DATA: /* D-cache data */ 1050 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1051 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1052 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1053 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1054 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1055 break; 1056 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1057 { 1058 MemTxResult result; 1059 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1060 1061 switch (size) { 1062 case 1: 1063 address_space_stb(cs->as, access_addr, val, 1064 MEMTXATTRS_UNSPECIFIED, &result); 1065 break; 1066 case 2: 1067 address_space_stw(cs->as, access_addr, val, 1068 MEMTXATTRS_UNSPECIFIED, &result); 1069 break; 1070 case 4: 1071 default: 1072 address_space_stl(cs->as, access_addr, val, 1073 MEMTXATTRS_UNSPECIFIED, &result); 1074 break; 1075 case 8: 1076 address_space_stq(cs->as, access_addr, val, 1077 MEMTXATTRS_UNSPECIFIED, &result); 1078 break; 1079 } 1080 if (result != MEMTX_OK) { 1081 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1082 size, GETPC()); 1083 } 1084 } 1085 break; 1086 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1087 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1088 Turbosparc snoop RAM */ 1089 case 0x32: /* store buffer control or Turbosparc page table 1090 descriptor diagnostic */ 1091 case 0x36: /* I-cache flash clear */ 1092 case 0x37: /* D-cache flash clear */ 1093 break; 1094 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1095 { 1096 int reg = (addr >> 8) & 3; 1097 1098 switch (reg) { 1099 case 0: /* Breakpoint Value (Addr) */ 1100 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1101 break; 1102 case 1: /* Breakpoint Mask */ 1103 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1104 break; 1105 case 2: /* Breakpoint Control */ 1106 env->mmubpregs[reg] = (val & 0x7fULL); 1107 break; 1108 case 3: /* Breakpoint Status */ 1109 env->mmubpregs[reg] = (val & 0xfULL); 1110 break; 1111 } 1112 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1113 env->mmuregs[reg]); 1114 } 1115 break; 1116 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1117 env->mmubpctrv = val & 0xffffffff; 1118 break; 1119 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1120 env->mmubpctrc = val & 0x3; 1121 break; 1122 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1123 env->mmubpctrs = val & 0x3; 1124 break; 1125 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1126 env->mmubpaction = val & 0x1fff; 1127 break; 1128 case ASI_USERTXT: /* User code access, XXX */ 1129 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1130 default: 1131 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1132 break; 1133 1134 case ASI_USERDATA: /* User data access */ 1135 case ASI_KERNELDATA: /* Supervisor data access */ 1136 case ASI_P: 1137 case ASI_M_BYPASS: /* MMU passthrough */ 1138 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1139 case ASI_M_BCOPY: /* Block copy, sta access */ 1140 case ASI_M_BFILL: /* Block fill, stda access */ 1141 /* These are always handled inline. */ 1142 g_assert_not_reached(); 1143 } 1144 #ifdef DEBUG_ASI 1145 dump_asi("write", addr, asi, size, val); 1146 #endif 1147 } 1148 1149 uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi) 1150 { 1151 MemOp mop = get_memop(oi); 1152 uintptr_t ra = GETPC(); 1153 uint64_t ret; 1154 1155 switch (mop & MO_SIZE) { 1156 case MO_8: 1157 ret = cpu_ldb_code_mmu(env, addr, oi, ra); 1158 if (mop & MO_SIGN) { 1159 ret = (int8_t)ret; 1160 } 1161 break; 1162 case MO_16: 1163 ret = cpu_ldw_code_mmu(env, addr, oi, ra); 1164 if ((mop & MO_BSWAP) != MO_TE) { 1165 ret = bswap16(ret); 1166 } 1167 if (mop & MO_SIGN) { 1168 ret = (int16_t)ret; 1169 } 1170 break; 1171 case MO_32: 1172 ret = cpu_ldl_code_mmu(env, addr, oi, ra); 1173 if ((mop & MO_BSWAP) != MO_TE) { 1174 ret = bswap32(ret); 1175 } 1176 if (mop & MO_SIGN) { 1177 ret = (int32_t)ret; 1178 } 1179 break; 1180 case MO_64: 1181 ret = cpu_ldq_code_mmu(env, addr, oi, ra); 1182 if ((mop & MO_BSWAP) != MO_TE) { 1183 ret = bswap64(ret); 1184 } 1185 break; 1186 default: 1187 g_assert_not_reached(); 1188 } 1189 return ret; 1190 } 1191 1192 #endif /* CONFIG_USER_ONLY */ 1193 #else /* TARGET_SPARC64 */ 1194 1195 #ifdef CONFIG_USER_ONLY 1196 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1197 int asi, uint32_t memop) 1198 { 1199 int size = 1 << (memop & MO_SIZE); 1200 int sign = memop & MO_SIGN; 1201 uint64_t ret = 0; 1202 1203 if (asi < 0x80) { 1204 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1205 } 1206 do_check_align(env, addr, size - 1, GETPC()); 1207 addr = asi_address_mask(env, asi, addr); 1208 1209 switch (asi) { 1210 case ASI_PNF: /* Primary no-fault */ 1211 case ASI_PNFL: /* Primary no-fault LE */ 1212 case ASI_SNF: /* Secondary no-fault */ 1213 case ASI_SNFL: /* Secondary no-fault LE */ 1214 if (!page_check_range(addr, size, PAGE_READ)) { 1215 ret = 0; 1216 break; 1217 } 1218 switch (size) { 1219 case 1: 1220 ret = cpu_ldub_data(env, addr); 1221 break; 1222 case 2: 1223 ret = cpu_lduw_data(env, addr); 1224 break; 1225 case 4: 1226 ret = cpu_ldl_data(env, addr); 1227 break; 1228 case 8: 1229 ret = cpu_ldq_data(env, addr); 1230 break; 1231 default: 1232 g_assert_not_reached(); 1233 } 1234 break; 1235 break; 1236 1237 case ASI_P: /* Primary */ 1238 case ASI_PL: /* Primary LE */ 1239 case ASI_S: /* Secondary */ 1240 case ASI_SL: /* Secondary LE */ 1241 /* These are always handled inline. */ 1242 g_assert_not_reached(); 1243 1244 default: 1245 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1246 } 1247 1248 /* Convert from little endian */ 1249 switch (asi) { 1250 case ASI_PNFL: /* Primary no-fault LE */ 1251 case ASI_SNFL: /* Secondary no-fault LE */ 1252 switch (size) { 1253 case 2: 1254 ret = bswap16(ret); 1255 break; 1256 case 4: 1257 ret = bswap32(ret); 1258 break; 1259 case 8: 1260 ret = bswap64(ret); 1261 break; 1262 } 1263 } 1264 1265 /* Convert to signed number */ 1266 if (sign) { 1267 switch (size) { 1268 case 1: 1269 ret = (int8_t) ret; 1270 break; 1271 case 2: 1272 ret = (int16_t) ret; 1273 break; 1274 case 4: 1275 ret = (int32_t) ret; 1276 break; 1277 } 1278 } 1279 #ifdef DEBUG_ASI 1280 dump_asi("read", addr, asi, size, ret); 1281 #endif 1282 return ret; 1283 } 1284 1285 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1286 int asi, uint32_t memop) 1287 { 1288 int size = 1 << (memop & MO_SIZE); 1289 #ifdef DEBUG_ASI 1290 dump_asi("write", addr, asi, size, val); 1291 #endif 1292 if (asi < 0x80) { 1293 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1294 } 1295 do_check_align(env, addr, size - 1, GETPC()); 1296 1297 switch (asi) { 1298 case ASI_P: /* Primary */ 1299 case ASI_PL: /* Primary LE */ 1300 case ASI_S: /* Secondary */ 1301 case ASI_SL: /* Secondary LE */ 1302 /* These are always handled inline. */ 1303 g_assert_not_reached(); 1304 1305 case ASI_PNF: /* Primary no-fault, RO */ 1306 case ASI_SNF: /* Secondary no-fault, RO */ 1307 case ASI_PNFL: /* Primary no-fault LE, RO */ 1308 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1309 default: 1310 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1311 } 1312 } 1313 1314 #else /* CONFIG_USER_ONLY */ 1315 1316 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1317 int asi, uint32_t memop) 1318 { 1319 int size = 1 << (memop & MO_SIZE); 1320 int sign = memop & MO_SIGN; 1321 CPUState *cs = env_cpu(env); 1322 uint64_t ret = 0; 1323 #if defined(DEBUG_ASI) 1324 target_ulong last_addr = addr; 1325 #endif 1326 1327 asi &= 0xff; 1328 1329 do_check_asi(env, asi, GETPC()); 1330 do_check_align(env, addr, size - 1, GETPC()); 1331 addr = asi_address_mask(env, asi, addr); 1332 1333 switch (asi) { 1334 case ASI_PNF: 1335 case ASI_PNFL: 1336 case ASI_SNF: 1337 case ASI_SNFL: 1338 { 1339 MemOpIdx oi; 1340 int idx = (env->pstate & PS_PRIV 1341 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1342 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1343 1344 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1345 #ifdef DEBUG_ASI 1346 dump_asi("read ", last_addr, asi, size, ret); 1347 #endif 1348 /* exception_index is set in get_physical_address_data. */ 1349 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1350 } 1351 oi = make_memop_idx(memop, idx); 1352 switch (size) { 1353 case 1: 1354 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1355 break; 1356 case 2: 1357 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1358 break; 1359 case 4: 1360 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1361 break; 1362 case 8: 1363 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1364 break; 1365 default: 1366 g_assert_not_reached(); 1367 } 1368 } 1369 break; 1370 1371 case ASI_AIUP: /* As if user primary */ 1372 case ASI_AIUS: /* As if user secondary */ 1373 case ASI_AIUPL: /* As if user primary LE */ 1374 case ASI_AIUSL: /* As if user secondary LE */ 1375 case ASI_P: /* Primary */ 1376 case ASI_S: /* Secondary */ 1377 case ASI_PL: /* Primary LE */ 1378 case ASI_SL: /* Secondary LE */ 1379 case ASI_REAL: /* Bypass */ 1380 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1381 case ASI_REAL_L: /* Bypass LE */ 1382 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1383 case ASI_N: /* Nucleus */ 1384 case ASI_NL: /* Nucleus Little Endian (LE) */ 1385 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1386 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1387 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1388 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1389 case ASI_TWINX_REAL: /* Real address, twinx */ 1390 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1391 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1392 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1393 case ASI_TWINX_N: /* Nucleus, twinx */ 1394 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1395 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1396 case ASI_TWINX_P: /* Primary, twinx */ 1397 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1398 case ASI_TWINX_S: /* Secondary, twinx */ 1399 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1400 case ASI_MON_P: 1401 case ASI_MON_S: 1402 case ASI_MON_AIUP: 1403 case ASI_MON_AIUS: 1404 /* These are always handled inline. */ 1405 g_assert_not_reached(); 1406 1407 case ASI_UPA_CONFIG: /* UPA config */ 1408 /* XXX */ 1409 break; 1410 case ASI_LSU_CONTROL: /* LSU */ 1411 ret = env->lsu; 1412 break; 1413 case ASI_IMMU: /* I-MMU regs */ 1414 { 1415 int reg = (addr >> 3) & 0xf; 1416 switch (reg) { 1417 case 0: 1418 /* 0x00 I-TSB Tag Target register */ 1419 ret = ultrasparc_tag_target(env->immu.tag_access); 1420 break; 1421 case 3: /* SFSR */ 1422 ret = env->immu.sfsr; 1423 break; 1424 case 5: /* TSB access */ 1425 ret = env->immu.tsb; 1426 break; 1427 case 6: 1428 /* 0x30 I-TSB Tag Access register */ 1429 ret = env->immu.tag_access; 1430 break; 1431 default: 1432 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1433 ret = 0; 1434 } 1435 break; 1436 } 1437 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1438 { 1439 /* env->immuregs[5] holds I-MMU TSB register value 1440 env->immuregs[6] holds I-MMU Tag Access register value */ 1441 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1442 break; 1443 } 1444 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1445 { 1446 /* env->immuregs[5] holds I-MMU TSB register value 1447 env->immuregs[6] holds I-MMU Tag Access register value */ 1448 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1449 break; 1450 } 1451 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1452 { 1453 int reg = (addr >> 3) & 0x3f; 1454 1455 ret = env->itlb[reg].tte; 1456 break; 1457 } 1458 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1459 { 1460 int reg = (addr >> 3) & 0x3f; 1461 1462 ret = env->itlb[reg].tag; 1463 break; 1464 } 1465 case ASI_DMMU: /* D-MMU regs */ 1466 { 1467 int reg = (addr >> 3) & 0xf; 1468 switch (reg) { 1469 case 0: 1470 /* 0x00 D-TSB Tag Target register */ 1471 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1472 break; 1473 case 1: /* 0x08 Primary Context */ 1474 ret = env->dmmu.mmu_primary_context; 1475 break; 1476 case 2: /* 0x10 Secondary Context */ 1477 ret = env->dmmu.mmu_secondary_context; 1478 break; 1479 case 3: /* SFSR */ 1480 ret = env->dmmu.sfsr; 1481 break; 1482 case 4: /* 0x20 SFAR */ 1483 ret = env->dmmu.sfar; 1484 break; 1485 case 5: /* 0x28 TSB access */ 1486 ret = env->dmmu.tsb; 1487 break; 1488 case 6: /* 0x30 D-TSB Tag Access register */ 1489 ret = env->dmmu.tag_access; 1490 break; 1491 case 7: 1492 ret = env->dmmu.virtual_watchpoint; 1493 break; 1494 case 8: 1495 ret = env->dmmu.physical_watchpoint; 1496 break; 1497 default: 1498 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1499 ret = 0; 1500 } 1501 break; 1502 } 1503 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1504 { 1505 /* env->dmmuregs[5] holds D-MMU TSB register value 1506 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1507 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1508 break; 1509 } 1510 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1511 { 1512 /* env->dmmuregs[5] holds D-MMU TSB register value 1513 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1514 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1515 break; 1516 } 1517 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1518 { 1519 int reg = (addr >> 3) & 0x3f; 1520 1521 ret = env->dtlb[reg].tte; 1522 break; 1523 } 1524 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1525 { 1526 int reg = (addr >> 3) & 0x3f; 1527 1528 ret = env->dtlb[reg].tag; 1529 break; 1530 } 1531 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1532 break; 1533 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1534 ret = env->ivec_status; 1535 break; 1536 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1537 { 1538 int reg = (addr >> 4) & 0x3; 1539 if (reg < 3) { 1540 ret = env->ivec_data[reg]; 1541 } 1542 break; 1543 } 1544 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1545 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1546 /* Hyperprivileged access only */ 1547 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1548 } 1549 /* fall through */ 1550 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1551 { 1552 unsigned int i = (addr >> 3) & 0x7; 1553 ret = env->scratch[i]; 1554 break; 1555 } 1556 case ASI_MMU: /* UA2005 Context ID registers */ 1557 switch ((addr >> 3) & 0x3) { 1558 case 1: 1559 ret = env->dmmu.mmu_primary_context; 1560 break; 1561 case 2: 1562 ret = env->dmmu.mmu_secondary_context; 1563 break; 1564 default: 1565 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1566 } 1567 break; 1568 case ASI_DCACHE_DATA: /* D-cache data */ 1569 case ASI_DCACHE_TAG: /* D-cache tag access */ 1570 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1571 case ASI_AFSR: /* E-cache asynchronous fault status */ 1572 case ASI_AFAR: /* E-cache asynchronous fault address */ 1573 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1574 case ASI_IC_INSTR: /* I-cache instruction access */ 1575 case ASI_IC_TAG: /* I-cache tag access */ 1576 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1577 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1578 case ASI_EC_W: /* E-cache tag */ 1579 case ASI_EC_R: /* E-cache tag */ 1580 break; 1581 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1582 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1583 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1584 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1585 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1586 case ASI_INTR_W: /* Interrupt vector, WO */ 1587 default: 1588 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1589 ret = 0; 1590 break; 1591 } 1592 1593 /* Convert to signed number */ 1594 if (sign) { 1595 switch (size) { 1596 case 1: 1597 ret = (int8_t) ret; 1598 break; 1599 case 2: 1600 ret = (int16_t) ret; 1601 break; 1602 case 4: 1603 ret = (int32_t) ret; 1604 break; 1605 default: 1606 break; 1607 } 1608 } 1609 #ifdef DEBUG_ASI 1610 dump_asi("read ", last_addr, asi, size, ret); 1611 #endif 1612 return ret; 1613 } 1614 1615 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1616 int asi, uint32_t memop) 1617 { 1618 int size = 1 << (memop & MO_SIZE); 1619 CPUState *cs = env_cpu(env); 1620 1621 #ifdef DEBUG_ASI 1622 dump_asi("write", addr, asi, size, val); 1623 #endif 1624 1625 asi &= 0xff; 1626 1627 do_check_asi(env, asi, GETPC()); 1628 do_check_align(env, addr, size - 1, GETPC()); 1629 addr = asi_address_mask(env, asi, addr); 1630 1631 switch (asi) { 1632 case ASI_AIUP: /* As if user primary */ 1633 case ASI_AIUS: /* As if user secondary */ 1634 case ASI_AIUPL: /* As if user primary LE */ 1635 case ASI_AIUSL: /* As if user secondary LE */ 1636 case ASI_P: /* Primary */ 1637 case ASI_S: /* Secondary */ 1638 case ASI_PL: /* Primary LE */ 1639 case ASI_SL: /* Secondary LE */ 1640 case ASI_REAL: /* Bypass */ 1641 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1642 case ASI_REAL_L: /* Bypass LE */ 1643 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1644 case ASI_N: /* Nucleus */ 1645 case ASI_NL: /* Nucleus Little Endian (LE) */ 1646 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1647 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1648 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1649 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1650 case ASI_TWINX_REAL: /* Real address, twinx */ 1651 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1652 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1653 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1654 case ASI_TWINX_N: /* Nucleus, twinx */ 1655 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1656 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1657 case ASI_TWINX_P: /* Primary, twinx */ 1658 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1659 case ASI_TWINX_S: /* Secondary, twinx */ 1660 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1661 /* These are always handled inline. */ 1662 g_assert_not_reached(); 1663 /* these ASIs have different functions on UltraSPARC-IIIi 1664 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1665 */ 1666 case 0x31: 1667 case 0x32: 1668 case 0x39: 1669 case 0x3a: 1670 if (cpu_has_hypervisor(env)) { 1671 /* UA2005 1672 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1673 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1674 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1675 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1676 */ 1677 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1678 env->dmmu.sun4v_tsb_pointers[idx] = val; 1679 } else { 1680 goto illegal_insn; 1681 } 1682 break; 1683 case 0x33: 1684 case 0x3b: 1685 if (cpu_has_hypervisor(env)) { 1686 /* UA2005 1687 * ASI_DMMU_CTX_ZERO_CONFIG 1688 * ASI_DMMU_CTX_NONZERO_CONFIG 1689 */ 1690 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1691 } else { 1692 goto illegal_insn; 1693 } 1694 break; 1695 case 0x35: 1696 case 0x36: 1697 case 0x3d: 1698 case 0x3e: 1699 if (cpu_has_hypervisor(env)) { 1700 /* UA2005 1701 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1702 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1703 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1704 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1705 */ 1706 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1707 env->immu.sun4v_tsb_pointers[idx] = val; 1708 } else { 1709 goto illegal_insn; 1710 } 1711 break; 1712 case 0x37: 1713 case 0x3f: 1714 if (cpu_has_hypervisor(env)) { 1715 /* UA2005 1716 * ASI_IMMU_CTX_ZERO_CONFIG 1717 * ASI_IMMU_CTX_NONZERO_CONFIG 1718 */ 1719 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1720 } else { 1721 goto illegal_insn; 1722 } 1723 break; 1724 case ASI_UPA_CONFIG: /* UPA config */ 1725 /* XXX */ 1726 return; 1727 case ASI_LSU_CONTROL: /* LSU */ 1728 env->lsu = val & (DMMU_E | IMMU_E); 1729 return; 1730 case ASI_IMMU: /* I-MMU regs */ 1731 { 1732 int reg = (addr >> 3) & 0xf; 1733 uint64_t oldreg; 1734 1735 oldreg = env->immu.mmuregs[reg]; 1736 switch (reg) { 1737 case 0: /* RO */ 1738 return; 1739 case 1: /* Not in I-MMU */ 1740 case 2: 1741 return; 1742 case 3: /* SFSR */ 1743 if ((val & 1) == 0) { 1744 val = 0; /* Clear SFSR */ 1745 } 1746 env->immu.sfsr = val; 1747 break; 1748 case 4: /* RO */ 1749 return; 1750 case 5: /* TSB access */ 1751 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1752 PRIx64 "\n", env->immu.tsb, val); 1753 env->immu.tsb = val; 1754 break; 1755 case 6: /* Tag access */ 1756 env->immu.tag_access = val; 1757 break; 1758 case 7: 1759 case 8: 1760 return; 1761 default: 1762 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1763 break; 1764 } 1765 1766 if (oldreg != env->immu.mmuregs[reg]) { 1767 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1768 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1769 } 1770 #ifdef DEBUG_MMU 1771 dump_mmu(env); 1772 #endif 1773 return; 1774 } 1775 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1776 /* ignore real translation entries */ 1777 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1778 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1779 val, "immu", env, addr); 1780 } 1781 return; 1782 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1783 { 1784 /* TODO: auto demap */ 1785 1786 unsigned int i = (addr >> 3) & 0x3f; 1787 1788 /* ignore real translation entries */ 1789 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1790 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1791 sun4v_tte_to_sun4u(env, addr, val), env); 1792 } 1793 #ifdef DEBUG_MMU 1794 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1795 dump_mmu(env); 1796 #endif 1797 return; 1798 } 1799 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1800 demap_tlb(env->itlb, addr, "immu", env); 1801 return; 1802 case ASI_DMMU: /* D-MMU regs */ 1803 { 1804 int reg = (addr >> 3) & 0xf; 1805 uint64_t oldreg; 1806 1807 oldreg = env->dmmu.mmuregs[reg]; 1808 switch (reg) { 1809 case 0: /* RO */ 1810 case 4: 1811 return; 1812 case 3: /* SFSR */ 1813 if ((val & 1) == 0) { 1814 val = 0; /* Clear SFSR, Fault address */ 1815 env->dmmu.sfar = 0; 1816 } 1817 env->dmmu.sfsr = val; 1818 break; 1819 case 1: /* Primary context */ 1820 env->dmmu.mmu_primary_context = val; 1821 /* can be optimized to only flush MMU_USER_IDX 1822 and MMU_KERNEL_IDX entries */ 1823 tlb_flush(cs); 1824 break; 1825 case 2: /* Secondary context */ 1826 env->dmmu.mmu_secondary_context = val; 1827 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1828 and MMU_KERNEL_SECONDARY_IDX entries */ 1829 tlb_flush(cs); 1830 break; 1831 case 5: /* TSB access */ 1832 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1833 PRIx64 "\n", env->dmmu.tsb, val); 1834 env->dmmu.tsb = val; 1835 break; 1836 case 6: /* Tag access */ 1837 env->dmmu.tag_access = val; 1838 break; 1839 case 7: /* Virtual Watchpoint */ 1840 env->dmmu.virtual_watchpoint = val; 1841 break; 1842 case 8: /* Physical Watchpoint */ 1843 env->dmmu.physical_watchpoint = val; 1844 break; 1845 default: 1846 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1847 break; 1848 } 1849 1850 if (oldreg != env->dmmu.mmuregs[reg]) { 1851 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1852 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1853 } 1854 #ifdef DEBUG_MMU 1855 dump_mmu(env); 1856 #endif 1857 return; 1858 } 1859 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1860 /* ignore real translation entries */ 1861 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1862 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1863 val, "dmmu", env, addr); 1864 } 1865 return; 1866 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1867 { 1868 unsigned int i = (addr >> 3) & 0x3f; 1869 1870 /* ignore real translation entries */ 1871 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1872 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1873 sun4v_tte_to_sun4u(env, addr, val), env); 1874 } 1875 #ifdef DEBUG_MMU 1876 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1877 dump_mmu(env); 1878 #endif 1879 return; 1880 } 1881 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1882 demap_tlb(env->dtlb, addr, "dmmu", env); 1883 return; 1884 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1885 env->ivec_status = val & 0x20; 1886 return; 1887 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1888 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1889 /* Hyperprivileged access only */ 1890 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1891 } 1892 /* fall through */ 1893 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1894 { 1895 unsigned int i = (addr >> 3) & 0x7; 1896 env->scratch[i] = val; 1897 return; 1898 } 1899 case ASI_MMU: /* UA2005 Context ID registers */ 1900 { 1901 switch ((addr >> 3) & 0x3) { 1902 case 1: 1903 env->dmmu.mmu_primary_context = val; 1904 env->immu.mmu_primary_context = val; 1905 tlb_flush_by_mmuidx(cs, 1906 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1907 break; 1908 case 2: 1909 env->dmmu.mmu_secondary_context = val; 1910 env->immu.mmu_secondary_context = val; 1911 tlb_flush_by_mmuidx(cs, 1912 (1 << MMU_USER_SECONDARY_IDX) | 1913 (1 << MMU_KERNEL_SECONDARY_IDX)); 1914 break; 1915 default: 1916 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1917 } 1918 } 1919 return; 1920 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1921 case ASI_DCACHE_DATA: /* D-cache data */ 1922 case ASI_DCACHE_TAG: /* D-cache tag access */ 1923 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1924 case ASI_AFSR: /* E-cache asynchronous fault status */ 1925 case ASI_AFAR: /* E-cache asynchronous fault address */ 1926 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1927 case ASI_IC_INSTR: /* I-cache instruction access */ 1928 case ASI_IC_TAG: /* I-cache tag access */ 1929 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1930 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1931 case ASI_EC_W: /* E-cache tag */ 1932 case ASI_EC_R: /* E-cache tag */ 1933 return; 1934 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1935 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1936 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1937 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1938 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1939 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1940 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1941 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1942 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1943 case ASI_PNF: /* Primary no-fault, RO */ 1944 case ASI_SNF: /* Secondary no-fault, RO */ 1945 case ASI_PNFL: /* Primary no-fault LE, RO */ 1946 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1947 default: 1948 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1949 return; 1950 illegal_insn: 1951 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1952 } 1953 } 1954 #endif /* CONFIG_USER_ONLY */ 1955 #endif /* TARGET_SPARC64 */ 1956 1957 #if !defined(CONFIG_USER_ONLY) 1958 1959 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1960 vaddr addr, unsigned size, 1961 MMUAccessType access_type, 1962 int mmu_idx, MemTxAttrs attrs, 1963 MemTxResult response, uintptr_t retaddr) 1964 { 1965 bool is_write = access_type == MMU_DATA_STORE; 1966 bool is_exec = access_type == MMU_INST_FETCH; 1967 bool is_asi = false; 1968 1969 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1970 is_asi, size, retaddr); 1971 } 1972 #endif 1973