1878cc677SRichard Henderson# SPDX-License-Identifier: LGPL-2.0+ 2878cc677SRichard Henderson# 3878cc677SRichard Henderson# Sparc instruction decode definitions. 4878cc677SRichard Henderson# Copyright (c) 2023 Richard Henderson <rth@twiddle.net> 5878cc677SRichard Henderson 66d2a0768SRichard Henderson## 76d2a0768SRichard Henderson## Major Opcodes 00 and 01 -- branches, call, and sethi. 86d2a0768SRichard Henderson## 96d2a0768SRichard Henderson 10276567aaSRichard Henderson&bcc i a cond cc 11276567aaSRichard HendersonBPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc 12276567aaSRichard HendersonBicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 1345196ea4SRichard HendersonFBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc 1445196ea4SRichard HendersonFBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0 15276567aaSRichard Henderson 16ab9ffe98SRichard Henderson%d16 20:s2 0:14 17ab9ffe98SRichard HendersonBPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 18ab9ffe98SRichard Henderson 1945196ea4SRichard HendersonNCP 00 - ---- 111 ---------------------- # CBcc 2045196ea4SRichard Henderson 216d2a0768SRichard HendersonSETHI 00 rd:5 100 i:22 226d2a0768SRichard Henderson 2323ada1b1SRichard HendersonCALL 01 i:s30 2430376636SRichard Henderson 25*0faef01bSRichard Henderson## 26*0faef01bSRichard Henderson## Major Opcode 10 -- integer, floating-point, vis, and system insns. 27*0faef01bSRichard Henderson## 28*0faef01bSRichard Henderson 29*0faef01bSRichard Henderson&r_r_ri rd rs1 rs2_or_imm imm:bool 30*0faef01bSRichard Henderson@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 31*0faef01bSRichard Henderson 32af25071cSRichard Henderson{ 33af25071cSRichard Henderson [ 34af25071cSRichard Henderson STBAR 10 00000 101000 01111 0 0000000000000 35af25071cSRichard Henderson MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 36af25071cSRichard Henderson 37af25071cSRichard Henderson RDCCR 10 rd:5 101000 00010 0 0000000000000 38af25071cSRichard Henderson RDASI 10 rd:5 101000 00011 0 0000000000000 39af25071cSRichard Henderson RDTICK 10 rd:5 101000 00100 0 0000000000000 40af25071cSRichard Henderson RDPC 10 rd:5 101000 00101 0 0000000000000 41af25071cSRichard Henderson RDFPRS 10 rd:5 101000 00110 0 0000000000000 42af25071cSRichard Henderson RDASR17 10 rd:5 101000 10001 0 0000000000000 43af25071cSRichard Henderson RDGSR 10 rd:5 101000 10011 0 0000000000000 44af25071cSRichard Henderson RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 45af25071cSRichard Henderson RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 46af25071cSRichard Henderson RDSTICK 10 rd:5 101000 11000 0 0000000000000 47af25071cSRichard Henderson RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 48af25071cSRichard Henderson RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 49af25071cSRichard Henderson ] 50af25071cSRichard Henderson # Before v8, all rs1 accepted; otherwise rs1==0. 51af25071cSRichard Henderson RDY 10 rd:5 101000 rs1:5 0 0000000000000 52af25071cSRichard Henderson} 53af25071cSRichard Henderson 54668bb9b7SRichard Henderson{ 55*0faef01bSRichard Henderson [ 56*0faef01bSRichard Henderson WRY 10 00000 110000 ..... . ............. @n_r_ri 57*0faef01bSRichard Henderson WRCCR 10 00010 110000 ..... . ............. @n_r_ri 58*0faef01bSRichard Henderson WRASI 10 00011 110000 ..... . ............. @n_r_ri 59*0faef01bSRichard Henderson WRFPRS 10 00110 110000 ..... . ............. @n_r_ri 60*0faef01bSRichard Henderson { 61*0faef01bSRichard Henderson WRGSR 10 10011 110000 ..... . ............. @n_r_ri 62*0faef01bSRichard Henderson WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri 63*0faef01bSRichard Henderson } 64*0faef01bSRichard Henderson WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri 65*0faef01bSRichard Henderson WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri 66*0faef01bSRichard Henderson WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri 67*0faef01bSRichard Henderson WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri 68*0faef01bSRichard Henderson WRSTICK 10 11000 110000 ..... . ............. @n_r_ri 69*0faef01bSRichard Henderson WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri 70*0faef01bSRichard Henderson ] 71*0faef01bSRichard Henderson # Before v8, rs1==0 was WRY, and the rest executed as nop. 72*0faef01bSRichard Henderson [ 73*0faef01bSRichard Henderson NOP_v7 10 ----- 110000 ----- 0 00000000 ----- 74*0faef01bSRichard Henderson NOP_v7 10 ----- 110000 ----- 1 -------- ----- 75*0faef01bSRichard Henderson ] 76*0faef01bSRichard Henderson} 77*0faef01bSRichard Henderson 78*0faef01bSRichard Henderson{ 79668bb9b7SRichard Henderson RDPSR 10 rd:5 101001 00000 0 0000000000000 80668bb9b7SRichard Henderson RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 81668bb9b7SRichard Henderson} 82668bb9b7SRichard HendersonRDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 83668bb9b7SRichard HendersonRDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 84668bb9b7SRichard HendersonRDHPR_htba 10 rd:5 101001 00101 0 0000000000000 85668bb9b7SRichard HendersonRDHPR_hver 10 rd:5 101001 00110 0 0000000000000 86668bb9b7SRichard HendersonRDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 87668bb9b7SRichard Henderson 885d617bfbSRichard Henderson{ 895d617bfbSRichard Henderson RDWIM 10 rd:5 101010 00000 0 0000000000000 905d617bfbSRichard Henderson RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 915d617bfbSRichard Henderson} 925d617bfbSRichard HendersonRDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 935d617bfbSRichard HendersonRDPR_tstate 10 rd:5 101010 00010 0 0000000000000 945d617bfbSRichard HendersonRDPR_tt 10 rd:5 101010 00011 0 0000000000000 955d617bfbSRichard HendersonRDPR_tick 10 rd:5 101010 00100 0 0000000000000 965d617bfbSRichard HendersonRDPR_tba 10 rd:5 101010 00101 0 0000000000000 975d617bfbSRichard HendersonRDPR_pstate 10 rd:5 101010 00110 0 0000000000000 985d617bfbSRichard HendersonRDPR_tl 10 rd:5 101010 00111 0 0000000000000 995d617bfbSRichard HendersonRDPR_pil 10 rd:5 101010 01000 0 0000000000000 1005d617bfbSRichard HendersonRDPR_cwp 10 rd:5 101010 01001 0 0000000000000 1015d617bfbSRichard HendersonRDPR_cansave 10 rd:5 101010 01010 0 0000000000000 1025d617bfbSRichard HendersonRDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 1035d617bfbSRichard HendersonRDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 1045d617bfbSRichard HendersonRDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 1055d617bfbSRichard HendersonRDPR_wstate 10 rd:5 101010 01110 0 0000000000000 1065d617bfbSRichard HendersonRDPR_gl 10 rd:5 101010 10000 0 0000000000000 1075d617bfbSRichard HendersonRDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 1085d617bfbSRichard HendersonRDPR_ver 10 rd:5 101010 11111 0 0000000000000 1095d617bfbSRichard Henderson 110e8325dc0SRichard Henderson{ 111e8325dc0SRichard Henderson FLUSHW 10 00000 101011 00000 0 0000000000000 112e8325dc0SRichard Henderson RDTBR 10 rd:5 101011 00000 0 0000000000000 113e8325dc0SRichard Henderson} 114e8325dc0SRichard Henderson 11530376636SRichard HendersonTcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 11630376636SRichard Henderson{ 11730376636SRichard Henderson # For v7, the entire simm13 field is present, but masked to 7 bits. 11830376636SRichard Henderson # For v8, [12:7] are reserved. However, a compatibility note for 11930376636SRichard Henderson # the Tcc insn in the v9 manual suggests that the v8 reserved field 12030376636SRichard Henderson # was ignored and did not produce traps. 12130376636SRichard Henderson Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7 12230376636SRichard Henderson 12330376636SRichard Henderson # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0). 12430376636SRichard Henderson # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. 12530376636SRichard Henderson Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 12630376636SRichard Henderson} 127