1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/module.h" 24 #include "qemu/qemu-print.h" 25 #include "exec/exec-all.h" 26 #include "exec/translation-block.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/visitor.h" 29 #include "tcg/tcg.h" 30 #include "fpu/softfloat.h" 31 #include "target/sparc/translate.h" 32 33 //#define DEBUG_FEATURES 34 35 static void sparc_cpu_reset_hold(Object *obj, ResetType type) 36 { 37 CPUState *cs = CPU(obj); 38 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 39 CPUSPARCState *env = cpu_env(cs); 40 41 if (scc->parent_phases.hold) { 42 scc->parent_phases.hold(obj, type); 43 } 44 45 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 46 env->cwp = 0; 47 #ifndef TARGET_SPARC64 48 env->wim = 1; 49 #endif 50 env->regwptr = env->regbase + (env->cwp * 16); 51 #if defined(CONFIG_USER_ONLY) 52 #ifdef TARGET_SPARC64 53 env->cleanwin = env->nwindows - 2; 54 env->cansave = env->nwindows - 2; 55 env->pstate = PS_RMO | PS_PEF | PS_IE; 56 env->asi = 0x82; /* Primary no-fault */ 57 #endif 58 #else 59 #if !defined(TARGET_SPARC64) 60 env->psret = 0; 61 env->psrs = 1; 62 env->psrps = 1; 63 #endif 64 #ifdef TARGET_SPARC64 65 env->pstate = PS_PRIV | PS_RED | PS_PEF; 66 if (!cpu_has_hypervisor(env)) { 67 env->pstate |= PS_AG; 68 } 69 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 70 env->tl = env->maxtl; 71 env->gl = 2; 72 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 73 env->lsu = 0; 74 #else 75 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 76 env->mmuregs[0] |= env->def.mmu_bm; 77 #endif 78 env->pc = 0; 79 env->npc = env->pc + 4; 80 #endif 81 env->cache_control = 0; 82 cpu_put_fsr(env, 0); 83 } 84 85 #ifndef CONFIG_USER_ONLY 86 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 87 { 88 if (interrupt_request & CPU_INTERRUPT_HARD) { 89 CPUSPARCState *env = cpu_env(cs); 90 91 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 92 int pil = env->interrupt_index & 0xf; 93 int type = env->interrupt_index & 0xf0; 94 95 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 96 cs->exception_index = env->interrupt_index; 97 sparc_cpu_do_interrupt(cs); 98 return true; 99 } 100 } 101 } 102 return false; 103 } 104 #endif /* !CONFIG_USER_ONLY */ 105 106 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 107 { 108 info->print_insn = print_insn_sparc; 109 info->endian = BFD_ENDIAN_BIG; 110 #ifdef TARGET_SPARC64 111 info->mach = bfd_mach_sparc_v9b; 112 #endif 113 } 114 115 static void 116 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) 117 { 118 GlobalProperty *prop = g_new0(typeof(*prop), 1); 119 prop->driver = typename; 120 prop->property = g_strdup(name); 121 prop->value = g_strdup(val); 122 qdev_prop_register_global(prop); 123 } 124 125 /* Parse "+feature,-feature,feature=foo" CPU feature string */ 126 static void sparc_cpu_parse_features(const char *typename, char *features, 127 Error **errp) 128 { 129 GList *l, *plus_features = NULL, *minus_features = NULL; 130 char *featurestr; /* Single 'key=value" string being parsed */ 131 static bool cpu_globals_initialized; 132 133 if (cpu_globals_initialized) { 134 return; 135 } 136 cpu_globals_initialized = true; 137 138 if (!features) { 139 return; 140 } 141 142 for (featurestr = strtok(features, ","); 143 featurestr; 144 featurestr = strtok(NULL, ",")) { 145 const char *name; 146 const char *val = NULL; 147 char *eq = NULL; 148 149 /* Compatibility syntax: */ 150 if (featurestr[0] == '+') { 151 plus_features = g_list_append(plus_features, 152 g_strdup(featurestr + 1)); 153 continue; 154 } else if (featurestr[0] == '-') { 155 minus_features = g_list_append(minus_features, 156 g_strdup(featurestr + 1)); 157 continue; 158 } 159 160 eq = strchr(featurestr, '='); 161 name = featurestr; 162 if (eq) { 163 *eq++ = 0; 164 val = eq; 165 166 /* 167 * Temporarily, only +feat/-feat will be supported 168 * for boolean properties until we remove the 169 * minus-overrides-plus semantics and just follow 170 * the order options appear on the command-line. 171 * 172 * TODO: warn if user is relying on minus-override-plus semantics 173 * TODO: remove minus-override-plus semantics after 174 * warning for a few releases 175 */ 176 if (!strcasecmp(val, "on") || 177 !strcasecmp(val, "off") || 178 !strcasecmp(val, "true") || 179 !strcasecmp(val, "false")) { 180 error_setg(errp, "Boolean properties in format %s=%s" 181 " are not supported", name, val); 182 return; 183 } 184 } else { 185 error_setg(errp, "Unsupported property format: %s", name); 186 return; 187 } 188 cpu_add_feat_as_prop(typename, name, val); 189 } 190 191 for (l = plus_features; l; l = l->next) { 192 const char *name = l->data; 193 cpu_add_feat_as_prop(typename, name, "on"); 194 } 195 g_list_free_full(plus_features, g_free); 196 197 for (l = minus_features; l; l = l->next) { 198 const char *name = l->data; 199 cpu_add_feat_as_prop(typename, name, "off"); 200 } 201 g_list_free_full(minus_features, g_free); 202 } 203 204 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 205 { 206 #if !defined(TARGET_SPARC64) 207 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 208 #endif 209 } 210 211 static const sparc_def_t sparc_defs[] = { 212 #ifdef TARGET_SPARC64 213 { 214 .name = "Fujitsu-Sparc64", 215 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 216 .fpu_version = 0x00000000, 217 .mmu_version = mmu_us_12, 218 .nwindows = 4, 219 .maxtl = 4, 220 .features = CPU_DEFAULT_FEATURES, 221 }, 222 { 223 .name = "Fujitsu-Sparc64-III", 224 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 225 .fpu_version = 0x00000000, 226 .mmu_version = mmu_us_12, 227 .nwindows = 5, 228 .maxtl = 4, 229 .features = CPU_DEFAULT_FEATURES, 230 }, 231 { 232 .name = "Fujitsu-Sparc64-IV", 233 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 234 .fpu_version = 0x00000000, 235 .mmu_version = mmu_us_12, 236 .nwindows = 8, 237 .maxtl = 5, 238 .features = CPU_DEFAULT_FEATURES, 239 }, 240 { 241 .name = "Fujitsu-Sparc64-V", 242 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 243 .fpu_version = 0x00000000, 244 .mmu_version = mmu_us_12, 245 .nwindows = 8, 246 .maxtl = 5, 247 .features = CPU_DEFAULT_FEATURES, 248 }, 249 { 250 .name = "TI-UltraSparc-I", 251 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 252 .fpu_version = 0x00000000, 253 .mmu_version = mmu_us_12, 254 .nwindows = 8, 255 .maxtl = 5, 256 .features = CPU_DEFAULT_FEATURES, 257 }, 258 { 259 .name = "TI-UltraSparc-II", 260 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 261 .fpu_version = 0x00000000, 262 .mmu_version = mmu_us_12, 263 .nwindows = 8, 264 .maxtl = 5, 265 .features = CPU_DEFAULT_FEATURES, 266 }, 267 { 268 .name = "TI-UltraSparc-IIi", 269 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 270 .fpu_version = 0x00000000, 271 .mmu_version = mmu_us_12, 272 .nwindows = 8, 273 .maxtl = 5, 274 .features = CPU_DEFAULT_FEATURES, 275 }, 276 { 277 .name = "TI-UltraSparc-IIe", 278 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 279 .fpu_version = 0x00000000, 280 .mmu_version = mmu_us_12, 281 .nwindows = 8, 282 .maxtl = 5, 283 .features = CPU_DEFAULT_FEATURES, 284 }, 285 { 286 .name = "Sun-UltraSparc-III", 287 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 288 .fpu_version = 0x00000000, 289 .mmu_version = mmu_us_12, 290 .nwindows = 8, 291 .maxtl = 5, 292 .features = CPU_DEFAULT_FEATURES, 293 }, 294 { 295 .name = "Sun-UltraSparc-III-Cu", 296 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 297 .fpu_version = 0x00000000, 298 .mmu_version = mmu_us_3, 299 .nwindows = 8, 300 .maxtl = 5, 301 .features = CPU_DEFAULT_FEATURES, 302 }, 303 { 304 .name = "Sun-UltraSparc-IIIi", 305 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 306 .fpu_version = 0x00000000, 307 .mmu_version = mmu_us_12, 308 .nwindows = 8, 309 .maxtl = 5, 310 .features = CPU_DEFAULT_FEATURES, 311 }, 312 { 313 .name = "Sun-UltraSparc-IV", 314 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 315 .fpu_version = 0x00000000, 316 .mmu_version = mmu_us_4, 317 .nwindows = 8, 318 .maxtl = 5, 319 .features = CPU_DEFAULT_FEATURES, 320 }, 321 { 322 .name = "Sun-UltraSparc-IV-plus", 323 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 324 .fpu_version = 0x00000000, 325 .mmu_version = mmu_us_12, 326 .nwindows = 8, 327 .maxtl = 5, 328 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 329 }, 330 { 331 .name = "Sun-UltraSparc-IIIi-plus", 332 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 333 .fpu_version = 0x00000000, 334 .mmu_version = mmu_us_3, 335 .nwindows = 8, 336 .maxtl = 5, 337 .features = CPU_DEFAULT_FEATURES, 338 }, 339 { 340 .name = "Sun-UltraSparc-T1", 341 /* defined in sparc_ifu_fdp.v and ctu.h */ 342 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 343 .fpu_version = 0x00000000, 344 .mmu_version = mmu_sun4v, 345 .nwindows = 8, 346 .maxtl = 6, 347 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 348 | CPU_FEATURE_GL, 349 }, 350 { 351 .name = "Sun-UltraSparc-T2", 352 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 353 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 354 .fpu_version = 0x00000000, 355 .mmu_version = mmu_sun4v, 356 .nwindows = 8, 357 .maxtl = 6, 358 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 359 | CPU_FEATURE_GL, 360 }, 361 { 362 .name = "NEC-UltraSparc-I", 363 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 364 .fpu_version = 0x00000000, 365 .mmu_version = mmu_us_12, 366 .nwindows = 8, 367 .maxtl = 5, 368 .features = CPU_DEFAULT_FEATURES, 369 }, 370 #else 371 { 372 .name = "Fujitsu-MB86904", 373 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 374 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 375 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 376 .mmu_bm = 0x00004000, 377 .mmu_ctpr_mask = 0x00ffffc0, 378 .mmu_cxr_mask = 0x000000ff, 379 .mmu_sfsr_mask = 0x00016fff, 380 .mmu_trcr_mask = 0x00ffffff, 381 .nwindows = 8, 382 .features = CPU_DEFAULT_FEATURES, 383 }, 384 { 385 .name = "Fujitsu-MB86907", 386 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 387 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 388 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 389 .mmu_bm = 0x00004000, 390 .mmu_ctpr_mask = 0xffffffc0, 391 .mmu_cxr_mask = 0x000000ff, 392 .mmu_sfsr_mask = 0x00016fff, 393 .mmu_trcr_mask = 0xffffffff, 394 .nwindows = 8, 395 .features = CPU_DEFAULT_FEATURES, 396 }, 397 { 398 .name = "TI-MicroSparc-I", 399 .iu_version = 0x41000000, 400 .fpu_version = 4 << FSR_VER_SHIFT, 401 .mmu_version = 0x41000000, 402 .mmu_bm = 0x00004000, 403 .mmu_ctpr_mask = 0x007ffff0, 404 .mmu_cxr_mask = 0x0000003f, 405 .mmu_sfsr_mask = 0x00016fff, 406 .mmu_trcr_mask = 0x0000003f, 407 .nwindows = 7, 408 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV, 409 }, 410 { 411 .name = "TI-MicroSparc-II", 412 .iu_version = 0x42000000, 413 .fpu_version = 4 << FSR_VER_SHIFT, 414 .mmu_version = 0x02000000, 415 .mmu_bm = 0x00004000, 416 .mmu_ctpr_mask = 0x00ffffc0, 417 .mmu_cxr_mask = 0x000000ff, 418 .mmu_sfsr_mask = 0x00016fff, 419 .mmu_trcr_mask = 0x00ffffff, 420 .nwindows = 8, 421 .features = CPU_DEFAULT_FEATURES, 422 }, 423 { 424 .name = "TI-MicroSparc-IIep", 425 .iu_version = 0x42000000, 426 .fpu_version = 4 << FSR_VER_SHIFT, 427 .mmu_version = 0x04000000, 428 .mmu_bm = 0x00004000, 429 .mmu_ctpr_mask = 0x00ffffc0, 430 .mmu_cxr_mask = 0x000000ff, 431 .mmu_sfsr_mask = 0x00016bff, 432 .mmu_trcr_mask = 0x00ffffff, 433 .nwindows = 8, 434 .features = CPU_DEFAULT_FEATURES, 435 }, 436 { 437 .name = "TI-SuperSparc-40", /* STP1020NPGA */ 438 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 439 .fpu_version = 0 << FSR_VER_SHIFT, 440 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 441 .mmu_bm = 0x00002000, 442 .mmu_ctpr_mask = 0xffffffc0, 443 .mmu_cxr_mask = 0x0000ffff, 444 .mmu_sfsr_mask = 0xffffffff, 445 .mmu_trcr_mask = 0xffffffff, 446 .nwindows = 8, 447 .features = CPU_DEFAULT_FEATURES, 448 }, 449 { 450 .name = "TI-SuperSparc-50", /* STP1020PGA */ 451 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 452 .fpu_version = 0 << FSR_VER_SHIFT, 453 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 454 .mmu_bm = 0x00002000, 455 .mmu_ctpr_mask = 0xffffffc0, 456 .mmu_cxr_mask = 0x0000ffff, 457 .mmu_sfsr_mask = 0xffffffff, 458 .mmu_trcr_mask = 0xffffffff, 459 .nwindows = 8, 460 .features = CPU_DEFAULT_FEATURES, 461 }, 462 { 463 .name = "TI-SuperSparc-51", 464 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 465 .fpu_version = 0 << FSR_VER_SHIFT, 466 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 467 .mmu_bm = 0x00002000, 468 .mmu_ctpr_mask = 0xffffffc0, 469 .mmu_cxr_mask = 0x0000ffff, 470 .mmu_sfsr_mask = 0xffffffff, 471 .mmu_trcr_mask = 0xffffffff, 472 .mxcc_version = 0x00000104, 473 .nwindows = 8, 474 .features = CPU_DEFAULT_FEATURES, 475 }, 476 { 477 .name = "TI-SuperSparc-60", /* STP1020APGA */ 478 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 479 .fpu_version = 0 << FSR_VER_SHIFT, 480 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 481 .mmu_bm = 0x00002000, 482 .mmu_ctpr_mask = 0xffffffc0, 483 .mmu_cxr_mask = 0x0000ffff, 484 .mmu_sfsr_mask = 0xffffffff, 485 .mmu_trcr_mask = 0xffffffff, 486 .nwindows = 8, 487 .features = CPU_DEFAULT_FEATURES, 488 }, 489 { 490 .name = "TI-SuperSparc-61", 491 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 492 .fpu_version = 0 << FSR_VER_SHIFT, 493 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 494 .mmu_bm = 0x00002000, 495 .mmu_ctpr_mask = 0xffffffc0, 496 .mmu_cxr_mask = 0x0000ffff, 497 .mmu_sfsr_mask = 0xffffffff, 498 .mmu_trcr_mask = 0xffffffff, 499 .mxcc_version = 0x00000104, 500 .nwindows = 8, 501 .features = CPU_DEFAULT_FEATURES, 502 }, 503 { 504 .name = "TI-SuperSparc-II", 505 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 506 .fpu_version = 0 << FSR_VER_SHIFT, 507 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 508 .mmu_bm = 0x00002000, 509 .mmu_ctpr_mask = 0xffffffc0, 510 .mmu_cxr_mask = 0x0000ffff, 511 .mmu_sfsr_mask = 0xffffffff, 512 .mmu_trcr_mask = 0xffffffff, 513 .mxcc_version = 0x00000104, 514 .nwindows = 8, 515 .features = CPU_DEFAULT_FEATURES, 516 }, 517 { 518 .name = "LEON2", 519 .iu_version = 0xf2000000, 520 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 521 .mmu_version = 0xf2000000, 522 .mmu_bm = 0x00004000, 523 .mmu_ctpr_mask = 0x007ffff0, 524 .mmu_cxr_mask = 0x0000003f, 525 .mmu_sfsr_mask = 0xffffffff, 526 .mmu_trcr_mask = 0xffffffff, 527 .nwindows = 8, 528 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 529 }, 530 { 531 .name = "LEON3", 532 .iu_version = 0xf3000000, 533 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 534 .mmu_version = 0xf3000000, 535 .mmu_bm = 0x00000000, 536 .mmu_ctpr_mask = 0xfffffffc, 537 .mmu_cxr_mask = 0x000000ff, 538 .mmu_sfsr_mask = 0xffffffff, 539 .mmu_trcr_mask = 0xffffffff, 540 .nwindows = 8, 541 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 542 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 543 CPU_FEATURE_CASA, 544 }, 545 #endif 546 }; 547 548 /* This must match sparc_cpu_properties[]. */ 549 static const char * const feature_name[] = { 550 [CPU_FEATURE_BIT_FLOAT128] = "float128", 551 #ifdef TARGET_SPARC64 552 [CPU_FEATURE_BIT_CMT] = "cmt", 553 [CPU_FEATURE_BIT_GL] = "gl", 554 [CPU_FEATURE_BIT_HYPV] = "hypv", 555 [CPU_FEATURE_BIT_VIS1] = "vis1", 556 [CPU_FEATURE_BIT_VIS2] = "vis2", 557 [CPU_FEATURE_BIT_FMAF] = "fmaf", 558 [CPU_FEATURE_BIT_VIS3] = "vis3", 559 [CPU_FEATURE_BIT_IMA] = "ima", 560 [CPU_FEATURE_BIT_VIS4] = "vis4", 561 #else 562 [CPU_FEATURE_BIT_MUL] = "mul", 563 [CPU_FEATURE_BIT_DIV] = "div", 564 [CPU_FEATURE_BIT_FSMULD] = "fsmuld", 565 #endif 566 }; 567 568 static void print_features(uint32_t features, const char *prefix) 569 { 570 unsigned int i; 571 572 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 573 if (feature_name[i] && (features & (1 << i))) { 574 if (prefix) { 575 qemu_printf("%s", prefix); 576 } 577 qemu_printf("%s ", feature_name[i]); 578 } 579 } 580 } 581 582 void sparc_cpu_list(void) 583 { 584 unsigned int i; 585 586 qemu_printf("Available CPU types:\n"); 587 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 588 qemu_printf(" %-20s (IU " TARGET_FMT_lx 589 " FPU %08x MMU %08x NWINS %d) ", 590 sparc_defs[i].name, 591 sparc_defs[i].iu_version, 592 sparc_defs[i].fpu_version, 593 sparc_defs[i].mmu_version, 594 sparc_defs[i].nwindows); 595 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); 596 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); 597 qemu_printf("\n"); 598 } 599 qemu_printf("Default CPU feature flags (use '-' to remove): "); 600 print_features(CPU_DEFAULT_FEATURES, NULL); 601 qemu_printf("\n"); 602 qemu_printf("Available CPU feature flags (use '+' to add): "); 603 print_features(~CPU_DEFAULT_FEATURES, NULL); 604 qemu_printf("\n"); 605 qemu_printf("Numerical features (use '=' to set): iu_version " 606 "fpu_version mmu_version nwindows\n"); 607 } 608 609 static void cpu_print_cc(FILE *f, uint32_t cc) 610 { 611 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 612 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 613 cc & PSR_CARRY ? 'C' : '-'); 614 } 615 616 #ifdef TARGET_SPARC64 617 #define REGS_PER_LINE 4 618 #else 619 #define REGS_PER_LINE 8 620 #endif 621 622 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 623 { 624 CPUSPARCState *env = cpu_env(cs); 625 int i, x; 626 627 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 628 env->npc); 629 630 for (i = 0; i < 8; i++) { 631 if (i % REGS_PER_LINE == 0) { 632 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 633 } 634 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 635 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 636 qemu_fprintf(f, "\n"); 637 } 638 } 639 for (x = 0; x < 3; x++) { 640 for (i = 0; i < 8; i++) { 641 if (i % REGS_PER_LINE == 0) { 642 qemu_fprintf(f, "%%%c%d-%d: ", 643 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 644 i, i + REGS_PER_LINE - 1); 645 } 646 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 647 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 648 qemu_fprintf(f, "\n"); 649 } 650 } 651 } 652 653 if (flags & CPU_DUMP_FPU) { 654 for (i = 0; i < TARGET_DPREGS; i++) { 655 if ((i & 3) == 0) { 656 qemu_fprintf(f, "%%f%02d: ", i * 2); 657 } 658 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 659 if ((i & 3) == 3) { 660 qemu_fprintf(f, "\n"); 661 } 662 } 663 } 664 665 #ifdef TARGET_SPARC64 666 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 667 (unsigned)cpu_get_ccr(env)); 668 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 669 qemu_fprintf(f, " xcc: "); 670 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 671 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 672 env->psrpil, env->gl); 673 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 674 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 675 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 676 "cleanwin: %d cwp: %d\n", 677 env->cansave, env->canrestore, env->otherwin, env->wstate, 678 env->cleanwin, env->nwindows - 1 - env->cwp); 679 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", 680 cpu_get_fsr(env), env->y, env->fprs); 681 682 #else 683 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 684 cpu_print_cc(f, cpu_get_psr(env)); 685 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 686 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 687 env->wim); 688 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 689 cpu_get_fsr(env), env->y); 690 #endif 691 qemu_fprintf(f, "\n"); 692 } 693 694 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 695 { 696 SPARCCPU *cpu = SPARC_CPU(cs); 697 698 cpu->env.pc = value; 699 cpu->env.npc = value + 4; 700 } 701 702 static vaddr sparc_cpu_get_pc(CPUState *cs) 703 { 704 SPARCCPU *cpu = SPARC_CPU(cs); 705 706 return cpu->env.pc; 707 } 708 709 static void sparc_cpu_synchronize_from_tb(CPUState *cs, 710 const TranslationBlock *tb) 711 { 712 SPARCCPU *cpu = SPARC_CPU(cs); 713 714 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 715 cpu->env.pc = tb->pc; 716 cpu->env.npc = tb->cs_base; 717 } 718 719 void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 720 uint64_t *cs_base, uint32_t *pflags) 721 { 722 uint32_t flags; 723 *pc = env->pc; 724 *cs_base = env->npc; 725 flags = cpu_mmu_index(env_cpu(env), false); 726 #ifndef CONFIG_USER_ONLY 727 if (cpu_supervisor_mode(env)) { 728 flags |= TB_FLAG_SUPER; 729 } 730 #endif 731 #ifdef TARGET_SPARC64 732 #ifndef CONFIG_USER_ONLY 733 if (cpu_hypervisor_mode(env)) { 734 flags |= TB_FLAG_HYPER; 735 } 736 #endif 737 if (env->pstate & PS_AM) { 738 flags |= TB_FLAG_AM_ENABLED; 739 } 740 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 741 flags |= TB_FLAG_FPU_ENABLED; 742 } 743 flags |= env->asi << TB_FLAG_ASI_SHIFT; 744 #else 745 if (env->psref) { 746 flags |= TB_FLAG_FPU_ENABLED; 747 } 748 #ifndef CONFIG_USER_ONLY 749 if (env->fsr_qne) { 750 flags |= TB_FLAG_FSR_QNE; 751 } 752 #endif /* !CONFIG_USER_ONLY */ 753 #endif /* TARGET_SPARC64 */ 754 *pflags = flags; 755 } 756 757 static void sparc_restore_state_to_opc(CPUState *cs, 758 const TranslationBlock *tb, 759 const uint64_t *data) 760 { 761 CPUSPARCState *env = cpu_env(cs); 762 target_ulong pc = data[0]; 763 target_ulong npc = data[1]; 764 765 env->pc = pc; 766 if (npc == DYNAMIC_PC) { 767 /* dynamic NPC: already stored */ 768 } else if (npc & JUMP_PC) { 769 /* jump PC: use 'cond' and the jump targets of the translation */ 770 if (env->cond) { 771 env->npc = npc & ~3; 772 } else { 773 env->npc = pc + 4; 774 } 775 } else { 776 env->npc = npc; 777 } 778 } 779 780 #ifndef CONFIG_USER_ONLY 781 static bool sparc_cpu_has_work(CPUState *cs) 782 { 783 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 784 cpu_interrupts_enabled(cpu_env(cs)); 785 } 786 #endif /* !CONFIG_USER_ONLY */ 787 788 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) 789 { 790 CPUSPARCState *env = cpu_env(cs); 791 792 #ifndef TARGET_SPARC64 793 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 794 return MMU_PHYS_IDX; 795 } else { 796 return env->psrs; 797 } 798 #else 799 /* IMMU or DMMU disabled. */ 800 if (ifetch 801 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 802 : (env->lsu & DMMU_E) == 0) { 803 return MMU_PHYS_IDX; 804 } else if (cpu_hypervisor_mode(env)) { 805 return MMU_PHYS_IDX; 806 } else if (env->tl > 0) { 807 return MMU_NUCLEUS_IDX; 808 } else if (cpu_supervisor_mode(env)) { 809 return MMU_KERNEL_IDX; 810 } else { 811 return MMU_USER_IDX; 812 } 813 #endif 814 } 815 816 static char *sparc_cpu_type_name(const char *cpu_model) 817 { 818 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); 819 char *s = name; 820 821 /* SPARC cpu model names happen to have whitespaces, 822 * as type names shouldn't have spaces replace them with '-' 823 */ 824 while ((s = strchr(s, ' '))) { 825 *s = '-'; 826 } 827 828 return name; 829 } 830 831 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 832 { 833 ObjectClass *oc; 834 char *typename; 835 836 typename = sparc_cpu_type_name(cpu_model); 837 838 /* Fix up legacy names with '+' in it */ 839 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { 840 g_free(typename); 841 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus")); 842 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) { 843 g_free(typename); 844 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus")); 845 } 846 847 oc = object_class_by_name(typename); 848 g_free(typename); 849 return oc; 850 } 851 852 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 853 { 854 CPUState *cs = CPU(dev); 855 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 856 Error *local_err = NULL; 857 CPUSPARCState *env = cpu_env(cs); 858 859 #if defined(CONFIG_USER_ONLY) 860 /* We are emulating the kernel, which will trap and emulate float128. */ 861 env->def.features |= CPU_FEATURE_FLOAT128; 862 #endif 863 864 env->version = env->def.iu_version; 865 env->nwindows = env->def.nwindows; 866 #if !defined(TARGET_SPARC64) 867 env->mmuregs[0] |= env->def.mmu_version; 868 cpu_sparc_set_id(env, 0); 869 env->mxccregs[7] |= env->def.mxcc_version; 870 #else 871 env->mmu_version = env->def.mmu_version; 872 env->maxtl = env->def.maxtl; 873 env->version |= env->def.maxtl << 8; 874 env->version |= env->def.nwindows - 1; 875 #endif 876 877 /* 878 * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize 879 * rather than reset, because fp_status is after 'end_reset_fields' in 880 * the CPU state struct so it won't get zeroed on reset. 881 */ 882 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); 883 /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ 884 set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); 885 /* For inf * 0 + NaN, return the input NaN */ 886 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 887 /* Default NaN value: sign bit clear, all frac bits set */ 888 set_float_default_nan_pattern(0b01111111, &env->fp_status); 889 890 cpu_exec_realizefn(cs, &local_err); 891 if (local_err != NULL) { 892 error_propagate(errp, local_err); 893 return; 894 } 895 896 qemu_init_vcpu(cs); 897 898 scc->parent_realize(dev, errp); 899 } 900 901 static void sparc_cpu_initfn(Object *obj) 902 { 903 SPARCCPU *cpu = SPARC_CPU(obj); 904 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 905 CPUSPARCState *env = &cpu->env; 906 907 if (scc->cpu_def) { 908 env->def = *scc->cpu_def; 909 } 910 } 911 912 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, 913 void *opaque, Error **errp) 914 { 915 SPARCCPU *cpu = SPARC_CPU(obj); 916 int64_t value = cpu->env.def.nwindows; 917 918 visit_type_int(v, name, &value, errp); 919 } 920 921 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, 922 void *opaque, Error **errp) 923 { 924 const int64_t min = MIN_NWINDOWS; 925 const int64_t max = MAX_NWINDOWS; 926 SPARCCPU *cpu = SPARC_CPU(obj); 927 int64_t value; 928 929 if (!visit_type_int(v, name, &value, errp)) { 930 return; 931 } 932 933 if (value < min || value > max) { 934 error_setg(errp, "Property %s.%s doesn't take value %" PRId64 935 " (minimum: %" PRId64 ", maximum: %" PRId64 ")", 936 object_get_typename(obj), name ? name : "null", 937 value, min, max); 938 return; 939 } 940 cpu->env.def.nwindows = value; 941 } 942 943 static const PropertyInfo qdev_prop_nwindows = { 944 .type = "int", 945 .description = "Number of register windows", 946 .get = sparc_get_nwindows, 947 .set = sparc_set_nwindows, 948 }; 949 950 /* This must match feature_name[]. */ 951 static const Property sparc_cpu_properties[] = { 952 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 953 CPU_FEATURE_BIT_FLOAT128, false), 954 #ifdef TARGET_SPARC64 955 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 956 CPU_FEATURE_BIT_CMT, false), 957 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 958 CPU_FEATURE_BIT_GL, false), 959 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 960 CPU_FEATURE_BIT_HYPV, false), 961 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 962 CPU_FEATURE_BIT_VIS1, false), 963 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 964 CPU_FEATURE_BIT_VIS2, false), 965 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, 966 CPU_FEATURE_BIT_FMAF, false), 967 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, 968 CPU_FEATURE_BIT_VIS3, false), 969 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, 970 CPU_FEATURE_BIT_IMA, false), 971 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, 972 CPU_FEATURE_BIT_VIS4, false), 973 #else 974 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 975 CPU_FEATURE_BIT_MUL, false), 976 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 977 CPU_FEATURE_BIT_DIV, false), 978 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 979 CPU_FEATURE_BIT_FSMULD, false), 980 #endif 981 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, 982 qdev_prop_uint64, target_ulong), 983 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), 984 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), 985 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, 986 qdev_prop_nwindows, uint32_t), 987 }; 988 989 #ifndef CONFIG_USER_ONLY 990 #include "hw/core/sysemu-cpu-ops.h" 991 992 static const struct SysemuCPUOps sparc_sysemu_ops = { 993 .has_work = sparc_cpu_has_work, 994 .get_phys_page_debug = sparc_cpu_get_phys_page_debug, 995 .legacy_vmsd = &vmstate_sparc_cpu, 996 }; 997 #endif 998 999 #ifdef CONFIG_TCG 1000 #include "accel/tcg/cpu-ops.h" 1001 1002 static const TCGCPUOps sparc_tcg_ops = { 1003 .initialize = sparc_tcg_init, 1004 .translate_code = sparc_translate_code, 1005 .synchronize_from_tb = sparc_cpu_synchronize_from_tb, 1006 .restore_state_to_opc = sparc_restore_state_to_opc, 1007 1008 #ifndef CONFIG_USER_ONLY 1009 .tlb_fill = sparc_cpu_tlb_fill, 1010 .cpu_exec_interrupt = sparc_cpu_exec_interrupt, 1011 .cpu_exec_halt = sparc_cpu_has_work, 1012 .do_interrupt = sparc_cpu_do_interrupt, 1013 .do_transaction_failed = sparc_cpu_do_transaction_failed, 1014 .do_unaligned_access = sparc_cpu_do_unaligned_access, 1015 #endif /* !CONFIG_USER_ONLY */ 1016 }; 1017 #endif /* CONFIG_TCG */ 1018 1019 static void sparc_cpu_class_init(ObjectClass *oc, void *data) 1020 { 1021 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1022 CPUClass *cc = CPU_CLASS(oc); 1023 DeviceClass *dc = DEVICE_CLASS(oc); 1024 ResettableClass *rc = RESETTABLE_CLASS(oc); 1025 1026 device_class_set_parent_realize(dc, sparc_cpu_realizefn, 1027 &scc->parent_realize); 1028 device_class_set_props(dc, sparc_cpu_properties); 1029 1030 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, 1031 &scc->parent_phases); 1032 1033 cc->class_by_name = sparc_cpu_class_by_name; 1034 cc->parse_features = sparc_cpu_parse_features; 1035 cc->mmu_index = sparc_cpu_mmu_index; 1036 cc->dump_state = sparc_cpu_dump_state; 1037 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 1038 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 1039 #endif 1040 cc->set_pc = sparc_cpu_set_pc; 1041 cc->get_pc = sparc_cpu_get_pc; 1042 cc->gdb_read_register = sparc_cpu_gdb_read_register; 1043 cc->gdb_write_register = sparc_cpu_gdb_write_register; 1044 #ifndef CONFIG_USER_ONLY 1045 cc->sysemu_ops = &sparc_sysemu_ops; 1046 #endif 1047 cc->disas_set_info = cpu_sparc_disas_set_info; 1048 1049 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1050 cc->gdb_num_core_regs = 86; 1051 #else 1052 cc->gdb_num_core_regs = 72; 1053 #endif 1054 cc->tcg_ops = &sparc_tcg_ops; 1055 } 1056 1057 static const TypeInfo sparc_cpu_type_info = { 1058 .name = TYPE_SPARC_CPU, 1059 .parent = TYPE_CPU, 1060 .instance_size = sizeof(SPARCCPU), 1061 .instance_align = __alignof(SPARCCPU), 1062 .instance_init = sparc_cpu_initfn, 1063 .abstract = true, 1064 .class_size = sizeof(SPARCCPUClass), 1065 .class_init = sparc_cpu_class_init, 1066 }; 1067 1068 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) 1069 { 1070 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1071 scc->cpu_def = data; 1072 } 1073 1074 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 1075 { 1076 char *typename = sparc_cpu_type_name(def->name); 1077 TypeInfo ti = { 1078 .name = typename, 1079 .parent = TYPE_SPARC_CPU, 1080 .class_init = sparc_cpu_cpudef_class_init, 1081 .class_data = (void *)def, 1082 }; 1083 1084 type_register_static(&ti); 1085 g_free(typename); 1086 } 1087 1088 static void sparc_cpu_register_types(void) 1089 { 1090 int i; 1091 1092 type_register_static(&sparc_cpu_type_info); 1093 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 1094 sparc_register_cpudef_type(&sparc_defs[i]); 1095 } 1096 } 1097 1098 type_init(sparc_cpu_register_types) 1099