1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/module.h" 24 #include "qemu/qemu-print.h" 25 #include "exec/exec-all.h" 26 #include "exec/translation-block.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/visitor.h" 29 #include "tcg/tcg.h" 30 #include "fpu/softfloat.h" 31 #include "target/sparc/translate.h" 32 33 //#define DEBUG_FEATURES 34 35 static void sparc_cpu_reset_hold(Object *obj, ResetType type) 36 { 37 CPUState *cs = CPU(obj); 38 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 39 CPUSPARCState *env = cpu_env(cs); 40 41 if (scc->parent_phases.hold) { 42 scc->parent_phases.hold(obj, type); 43 } 44 45 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 46 env->cwp = 0; 47 #ifndef TARGET_SPARC64 48 env->wim = 1; 49 #endif 50 env->regwptr = env->regbase + (env->cwp * 16); 51 #if defined(CONFIG_USER_ONLY) 52 #ifdef TARGET_SPARC64 53 env->cleanwin = env->nwindows - 2; 54 env->cansave = env->nwindows - 2; 55 env->pstate = PS_RMO | PS_PEF | PS_IE; 56 env->asi = 0x82; /* Primary no-fault */ 57 #endif 58 #else 59 #if !defined(TARGET_SPARC64) 60 env->psret = 0; 61 env->psrs = 1; 62 env->psrps = 1; 63 #endif 64 #ifdef TARGET_SPARC64 65 env->pstate = PS_PRIV | PS_RED | PS_PEF; 66 if (!cpu_has_hypervisor(env)) { 67 env->pstate |= PS_AG; 68 } 69 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 70 env->tl = env->maxtl; 71 env->gl = 2; 72 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 73 env->lsu = 0; 74 #else 75 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 76 env->mmuregs[0] |= env->def.mmu_bm; 77 #endif 78 env->pc = 0; 79 env->npc = env->pc + 4; 80 #endif 81 env->cache_control = 0; 82 cpu_put_fsr(env, 0); 83 } 84 85 #ifndef CONFIG_USER_ONLY 86 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 87 { 88 if (interrupt_request & CPU_INTERRUPT_HARD) { 89 CPUSPARCState *env = cpu_env(cs); 90 91 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 92 int pil = env->interrupt_index & 0xf; 93 int type = env->interrupt_index & 0xf0; 94 95 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 96 cs->exception_index = env->interrupt_index; 97 sparc_cpu_do_interrupt(cs); 98 return true; 99 } 100 } 101 } 102 return false; 103 } 104 #endif /* !CONFIG_USER_ONLY */ 105 106 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 107 { 108 info->print_insn = print_insn_sparc; 109 #ifdef TARGET_SPARC64 110 info->mach = bfd_mach_sparc_v9b; 111 #endif 112 } 113 114 static void 115 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) 116 { 117 GlobalProperty *prop = g_new0(typeof(*prop), 1); 118 prop->driver = typename; 119 prop->property = g_strdup(name); 120 prop->value = g_strdup(val); 121 qdev_prop_register_global(prop); 122 } 123 124 /* Parse "+feature,-feature,feature=foo" CPU feature string */ 125 static void sparc_cpu_parse_features(const char *typename, char *features, 126 Error **errp) 127 { 128 GList *l, *plus_features = NULL, *minus_features = NULL; 129 char *featurestr; /* Single 'key=value" string being parsed */ 130 static bool cpu_globals_initialized; 131 132 if (cpu_globals_initialized) { 133 return; 134 } 135 cpu_globals_initialized = true; 136 137 if (!features) { 138 return; 139 } 140 141 for (featurestr = strtok(features, ","); 142 featurestr; 143 featurestr = strtok(NULL, ",")) { 144 const char *name; 145 const char *val = NULL; 146 char *eq = NULL; 147 148 /* Compatibility syntax: */ 149 if (featurestr[0] == '+') { 150 plus_features = g_list_append(plus_features, 151 g_strdup(featurestr + 1)); 152 continue; 153 } else if (featurestr[0] == '-') { 154 minus_features = g_list_append(minus_features, 155 g_strdup(featurestr + 1)); 156 continue; 157 } 158 159 eq = strchr(featurestr, '='); 160 name = featurestr; 161 if (eq) { 162 *eq++ = 0; 163 val = eq; 164 165 /* 166 * Temporarily, only +feat/-feat will be supported 167 * for boolean properties until we remove the 168 * minus-overrides-plus semantics and just follow 169 * the order options appear on the command-line. 170 * 171 * TODO: warn if user is relying on minus-override-plus semantics 172 * TODO: remove minus-override-plus semantics after 173 * warning for a few releases 174 */ 175 if (!strcasecmp(val, "on") || 176 !strcasecmp(val, "off") || 177 !strcasecmp(val, "true") || 178 !strcasecmp(val, "false")) { 179 error_setg(errp, "Boolean properties in format %s=%s" 180 " are not supported", name, val); 181 return; 182 } 183 } else { 184 error_setg(errp, "Unsupported property format: %s", name); 185 return; 186 } 187 cpu_add_feat_as_prop(typename, name, val); 188 } 189 190 for (l = plus_features; l; l = l->next) { 191 const char *name = l->data; 192 cpu_add_feat_as_prop(typename, name, "on"); 193 } 194 g_list_free_full(plus_features, g_free); 195 196 for (l = minus_features; l; l = l->next) { 197 const char *name = l->data; 198 cpu_add_feat_as_prop(typename, name, "off"); 199 } 200 g_list_free_full(minus_features, g_free); 201 } 202 203 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 204 { 205 #if !defined(TARGET_SPARC64) 206 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 207 #endif 208 } 209 210 static const sparc_def_t sparc_defs[] = { 211 #ifdef TARGET_SPARC64 212 { 213 .name = "Fujitsu-Sparc64", 214 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 215 .fpu_version = 0x00000000, 216 .mmu_version = mmu_us_12, 217 .nwindows = 4, 218 .maxtl = 4, 219 .features = CPU_DEFAULT_FEATURES, 220 }, 221 { 222 .name = "Fujitsu-Sparc64-III", 223 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 224 .fpu_version = 0x00000000, 225 .mmu_version = mmu_us_12, 226 .nwindows = 5, 227 .maxtl = 4, 228 .features = CPU_DEFAULT_FEATURES, 229 }, 230 { 231 .name = "Fujitsu-Sparc64-IV", 232 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 233 .fpu_version = 0x00000000, 234 .mmu_version = mmu_us_12, 235 .nwindows = 8, 236 .maxtl = 5, 237 .features = CPU_DEFAULT_FEATURES, 238 }, 239 { 240 .name = "Fujitsu-Sparc64-V", 241 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 242 .fpu_version = 0x00000000, 243 .mmu_version = mmu_us_12, 244 .nwindows = 8, 245 .maxtl = 5, 246 .features = CPU_DEFAULT_FEATURES, 247 }, 248 { 249 .name = "TI-UltraSparc-I", 250 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 251 .fpu_version = 0x00000000, 252 .mmu_version = mmu_us_12, 253 .nwindows = 8, 254 .maxtl = 5, 255 .features = CPU_DEFAULT_FEATURES, 256 }, 257 { 258 .name = "TI-UltraSparc-II", 259 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 260 .fpu_version = 0x00000000, 261 .mmu_version = mmu_us_12, 262 .nwindows = 8, 263 .maxtl = 5, 264 .features = CPU_DEFAULT_FEATURES, 265 }, 266 { 267 .name = "TI-UltraSparc-IIi", 268 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 269 .fpu_version = 0x00000000, 270 .mmu_version = mmu_us_12, 271 .nwindows = 8, 272 .maxtl = 5, 273 .features = CPU_DEFAULT_FEATURES, 274 }, 275 { 276 .name = "TI-UltraSparc-IIe", 277 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 278 .fpu_version = 0x00000000, 279 .mmu_version = mmu_us_12, 280 .nwindows = 8, 281 .maxtl = 5, 282 .features = CPU_DEFAULT_FEATURES, 283 }, 284 { 285 .name = "Sun-UltraSparc-III", 286 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 287 .fpu_version = 0x00000000, 288 .mmu_version = mmu_us_12, 289 .nwindows = 8, 290 .maxtl = 5, 291 .features = CPU_DEFAULT_FEATURES, 292 }, 293 { 294 .name = "Sun-UltraSparc-III-Cu", 295 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 296 .fpu_version = 0x00000000, 297 .mmu_version = mmu_us_3, 298 .nwindows = 8, 299 .maxtl = 5, 300 .features = CPU_DEFAULT_FEATURES, 301 }, 302 { 303 .name = "Sun-UltraSparc-IIIi", 304 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 305 .fpu_version = 0x00000000, 306 .mmu_version = mmu_us_12, 307 .nwindows = 8, 308 .maxtl = 5, 309 .features = CPU_DEFAULT_FEATURES, 310 }, 311 { 312 .name = "Sun-UltraSparc-IV", 313 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 314 .fpu_version = 0x00000000, 315 .mmu_version = mmu_us_4, 316 .nwindows = 8, 317 .maxtl = 5, 318 .features = CPU_DEFAULT_FEATURES, 319 }, 320 { 321 .name = "Sun-UltraSparc-IV-plus", 322 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 323 .fpu_version = 0x00000000, 324 .mmu_version = mmu_us_12, 325 .nwindows = 8, 326 .maxtl = 5, 327 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 328 }, 329 { 330 .name = "Sun-UltraSparc-IIIi-plus", 331 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 332 .fpu_version = 0x00000000, 333 .mmu_version = mmu_us_3, 334 .nwindows = 8, 335 .maxtl = 5, 336 .features = CPU_DEFAULT_FEATURES, 337 }, 338 { 339 .name = "Sun-UltraSparc-T1", 340 /* defined in sparc_ifu_fdp.v and ctu.h */ 341 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 342 .fpu_version = 0x00000000, 343 .mmu_version = mmu_sun4v, 344 .nwindows = 8, 345 .maxtl = 6, 346 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 347 | CPU_FEATURE_GL, 348 }, 349 { 350 .name = "Sun-UltraSparc-T2", 351 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 352 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 353 .fpu_version = 0x00000000, 354 .mmu_version = mmu_sun4v, 355 .nwindows = 8, 356 .maxtl = 6, 357 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 358 | CPU_FEATURE_GL, 359 }, 360 { 361 .name = "NEC-UltraSparc-I", 362 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 363 .fpu_version = 0x00000000, 364 .mmu_version = mmu_us_12, 365 .nwindows = 8, 366 .maxtl = 5, 367 .features = CPU_DEFAULT_FEATURES, 368 }, 369 #else 370 { 371 .name = "Fujitsu-MB86904", 372 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 373 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 374 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 375 .mmu_bm = 0x00004000, 376 .mmu_ctpr_mask = 0x00ffffc0, 377 .mmu_cxr_mask = 0x000000ff, 378 .mmu_sfsr_mask = 0x00016fff, 379 .mmu_trcr_mask = 0x00ffffff, 380 .nwindows = 8, 381 .features = CPU_DEFAULT_FEATURES, 382 }, 383 { 384 .name = "Fujitsu-MB86907", 385 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 386 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 387 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 388 .mmu_bm = 0x00004000, 389 .mmu_ctpr_mask = 0xffffffc0, 390 .mmu_cxr_mask = 0x000000ff, 391 .mmu_sfsr_mask = 0x00016fff, 392 .mmu_trcr_mask = 0xffffffff, 393 .nwindows = 8, 394 .features = CPU_DEFAULT_FEATURES, 395 }, 396 { 397 .name = "TI-MicroSparc-I", 398 .iu_version = 0x41000000, 399 .fpu_version = 4 << FSR_VER_SHIFT, 400 .mmu_version = 0x41000000, 401 .mmu_bm = 0x00004000, 402 .mmu_ctpr_mask = 0x007ffff0, 403 .mmu_cxr_mask = 0x0000003f, 404 .mmu_sfsr_mask = 0x00016fff, 405 .mmu_trcr_mask = 0x0000003f, 406 .nwindows = 7, 407 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV, 408 }, 409 { 410 .name = "TI-MicroSparc-II", 411 .iu_version = 0x42000000, 412 .fpu_version = 4 << FSR_VER_SHIFT, 413 .mmu_version = 0x02000000, 414 .mmu_bm = 0x00004000, 415 .mmu_ctpr_mask = 0x00ffffc0, 416 .mmu_cxr_mask = 0x000000ff, 417 .mmu_sfsr_mask = 0x00016fff, 418 .mmu_trcr_mask = 0x00ffffff, 419 .nwindows = 8, 420 .features = CPU_DEFAULT_FEATURES, 421 }, 422 { 423 .name = "TI-MicroSparc-IIep", 424 .iu_version = 0x42000000, 425 .fpu_version = 4 << FSR_VER_SHIFT, 426 .mmu_version = 0x04000000, 427 .mmu_bm = 0x00004000, 428 .mmu_ctpr_mask = 0x00ffffc0, 429 .mmu_cxr_mask = 0x000000ff, 430 .mmu_sfsr_mask = 0x00016bff, 431 .mmu_trcr_mask = 0x00ffffff, 432 .nwindows = 8, 433 .features = CPU_DEFAULT_FEATURES, 434 }, 435 { 436 .name = "TI-SuperSparc-40", /* STP1020NPGA */ 437 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 438 .fpu_version = 0 << FSR_VER_SHIFT, 439 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 440 .mmu_bm = 0x00002000, 441 .mmu_ctpr_mask = 0xffffffc0, 442 .mmu_cxr_mask = 0x0000ffff, 443 .mmu_sfsr_mask = 0xffffffff, 444 .mmu_trcr_mask = 0xffffffff, 445 .nwindows = 8, 446 .features = CPU_DEFAULT_FEATURES, 447 }, 448 { 449 .name = "TI-SuperSparc-50", /* STP1020PGA */ 450 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 451 .fpu_version = 0 << FSR_VER_SHIFT, 452 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 453 .mmu_bm = 0x00002000, 454 .mmu_ctpr_mask = 0xffffffc0, 455 .mmu_cxr_mask = 0x0000ffff, 456 .mmu_sfsr_mask = 0xffffffff, 457 .mmu_trcr_mask = 0xffffffff, 458 .nwindows = 8, 459 .features = CPU_DEFAULT_FEATURES, 460 }, 461 { 462 .name = "TI-SuperSparc-51", 463 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 464 .fpu_version = 0 << FSR_VER_SHIFT, 465 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 466 .mmu_bm = 0x00002000, 467 .mmu_ctpr_mask = 0xffffffc0, 468 .mmu_cxr_mask = 0x0000ffff, 469 .mmu_sfsr_mask = 0xffffffff, 470 .mmu_trcr_mask = 0xffffffff, 471 .mxcc_version = 0x00000104, 472 .nwindows = 8, 473 .features = CPU_DEFAULT_FEATURES, 474 }, 475 { 476 .name = "TI-SuperSparc-60", /* STP1020APGA */ 477 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 478 .fpu_version = 0 << FSR_VER_SHIFT, 479 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 480 .mmu_bm = 0x00002000, 481 .mmu_ctpr_mask = 0xffffffc0, 482 .mmu_cxr_mask = 0x0000ffff, 483 .mmu_sfsr_mask = 0xffffffff, 484 .mmu_trcr_mask = 0xffffffff, 485 .nwindows = 8, 486 .features = CPU_DEFAULT_FEATURES, 487 }, 488 { 489 .name = "TI-SuperSparc-61", 490 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 491 .fpu_version = 0 << FSR_VER_SHIFT, 492 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 493 .mmu_bm = 0x00002000, 494 .mmu_ctpr_mask = 0xffffffc0, 495 .mmu_cxr_mask = 0x0000ffff, 496 .mmu_sfsr_mask = 0xffffffff, 497 .mmu_trcr_mask = 0xffffffff, 498 .mxcc_version = 0x00000104, 499 .nwindows = 8, 500 .features = CPU_DEFAULT_FEATURES, 501 }, 502 { 503 .name = "TI-SuperSparc-II", 504 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 505 .fpu_version = 0 << FSR_VER_SHIFT, 506 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 507 .mmu_bm = 0x00002000, 508 .mmu_ctpr_mask = 0xffffffc0, 509 .mmu_cxr_mask = 0x0000ffff, 510 .mmu_sfsr_mask = 0xffffffff, 511 .mmu_trcr_mask = 0xffffffff, 512 .mxcc_version = 0x00000104, 513 .nwindows = 8, 514 .features = CPU_DEFAULT_FEATURES, 515 }, 516 { 517 .name = "LEON2", 518 .iu_version = 0xf2000000, 519 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 520 .mmu_version = 0xf2000000, 521 .mmu_bm = 0x00004000, 522 .mmu_ctpr_mask = 0x007ffff0, 523 .mmu_cxr_mask = 0x0000003f, 524 .mmu_sfsr_mask = 0xffffffff, 525 .mmu_trcr_mask = 0xffffffff, 526 .nwindows = 8, 527 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 528 }, 529 { 530 .name = "LEON3", 531 .iu_version = 0xf3000000, 532 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 533 .mmu_version = 0xf3000000, 534 .mmu_bm = 0x00000000, 535 .mmu_ctpr_mask = 0xfffffffc, 536 .mmu_cxr_mask = 0x000000ff, 537 .mmu_sfsr_mask = 0xffffffff, 538 .mmu_trcr_mask = 0xffffffff, 539 .nwindows = 8, 540 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 541 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 542 CPU_FEATURE_CASA, 543 }, 544 #endif 545 }; 546 547 /* This must match sparc_cpu_properties[]. */ 548 static const char * const feature_name[] = { 549 [CPU_FEATURE_BIT_FLOAT128] = "float128", 550 #ifdef TARGET_SPARC64 551 [CPU_FEATURE_BIT_CMT] = "cmt", 552 [CPU_FEATURE_BIT_GL] = "gl", 553 [CPU_FEATURE_BIT_HYPV] = "hypv", 554 [CPU_FEATURE_BIT_VIS1] = "vis1", 555 [CPU_FEATURE_BIT_VIS2] = "vis2", 556 [CPU_FEATURE_BIT_FMAF] = "fmaf", 557 [CPU_FEATURE_BIT_VIS3] = "vis3", 558 [CPU_FEATURE_BIT_IMA] = "ima", 559 [CPU_FEATURE_BIT_VIS4] = "vis4", 560 #else 561 [CPU_FEATURE_BIT_MUL] = "mul", 562 [CPU_FEATURE_BIT_DIV] = "div", 563 [CPU_FEATURE_BIT_FSMULD] = "fsmuld", 564 #endif 565 }; 566 567 static void print_features(uint32_t features, const char *prefix) 568 { 569 unsigned int i; 570 571 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 572 if (feature_name[i] && (features & (1 << i))) { 573 if (prefix) { 574 qemu_printf("%s", prefix); 575 } 576 qemu_printf("%s ", feature_name[i]); 577 } 578 } 579 } 580 581 void sparc_cpu_list(void) 582 { 583 unsigned int i; 584 585 qemu_printf("Available CPU types:\n"); 586 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 587 qemu_printf(" %-20s (IU " TARGET_FMT_lx 588 " FPU %08x MMU %08x NWINS %d) ", 589 sparc_defs[i].name, 590 sparc_defs[i].iu_version, 591 sparc_defs[i].fpu_version, 592 sparc_defs[i].mmu_version, 593 sparc_defs[i].nwindows); 594 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); 595 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); 596 qemu_printf("\n"); 597 } 598 qemu_printf("Default CPU feature flags (use '-' to remove): "); 599 print_features(CPU_DEFAULT_FEATURES, NULL); 600 qemu_printf("\n"); 601 qemu_printf("Available CPU feature flags (use '+' to add): "); 602 print_features(~CPU_DEFAULT_FEATURES, NULL); 603 qemu_printf("\n"); 604 qemu_printf("Numerical features (use '=' to set): iu_version " 605 "fpu_version mmu_version nwindows\n"); 606 } 607 608 static void cpu_print_cc(FILE *f, uint32_t cc) 609 { 610 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 611 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 612 cc & PSR_CARRY ? 'C' : '-'); 613 } 614 615 #ifdef TARGET_SPARC64 616 #define REGS_PER_LINE 4 617 #else 618 #define REGS_PER_LINE 8 619 #endif 620 621 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 622 { 623 CPUSPARCState *env = cpu_env(cs); 624 int i, x; 625 626 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 627 env->npc); 628 629 for (i = 0; i < 8; i++) { 630 if (i % REGS_PER_LINE == 0) { 631 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 632 } 633 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 634 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 635 qemu_fprintf(f, "\n"); 636 } 637 } 638 for (x = 0; x < 3; x++) { 639 for (i = 0; i < 8; i++) { 640 if (i % REGS_PER_LINE == 0) { 641 qemu_fprintf(f, "%%%c%d-%d: ", 642 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 643 i, i + REGS_PER_LINE - 1); 644 } 645 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 646 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 647 qemu_fprintf(f, "\n"); 648 } 649 } 650 } 651 652 if (flags & CPU_DUMP_FPU) { 653 for (i = 0; i < TARGET_DPREGS; i++) { 654 if ((i & 3) == 0) { 655 qemu_fprintf(f, "%%f%02d: ", i * 2); 656 } 657 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 658 if ((i & 3) == 3) { 659 qemu_fprintf(f, "\n"); 660 } 661 } 662 } 663 664 #ifdef TARGET_SPARC64 665 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 666 (unsigned)cpu_get_ccr(env)); 667 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 668 qemu_fprintf(f, " xcc: "); 669 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 670 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 671 env->psrpil, env->gl); 672 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 673 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 674 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 675 "cleanwin: %d cwp: %d\n", 676 env->cansave, env->canrestore, env->otherwin, env->wstate, 677 env->cleanwin, env->nwindows - 1 - env->cwp); 678 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", 679 cpu_get_fsr(env), env->y, env->fprs); 680 681 #else 682 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 683 cpu_print_cc(f, cpu_get_psr(env)); 684 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 685 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 686 env->wim); 687 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 688 cpu_get_fsr(env), env->y); 689 #endif 690 qemu_fprintf(f, "\n"); 691 } 692 693 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 694 { 695 SPARCCPU *cpu = SPARC_CPU(cs); 696 697 cpu->env.pc = value; 698 cpu->env.npc = value + 4; 699 } 700 701 static vaddr sparc_cpu_get_pc(CPUState *cs) 702 { 703 SPARCCPU *cpu = SPARC_CPU(cs); 704 705 return cpu->env.pc; 706 } 707 708 static void sparc_cpu_synchronize_from_tb(CPUState *cs, 709 const TranslationBlock *tb) 710 { 711 SPARCCPU *cpu = SPARC_CPU(cs); 712 713 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 714 cpu->env.pc = tb->pc; 715 cpu->env.npc = tb->cs_base; 716 } 717 718 void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 719 uint64_t *cs_base, uint32_t *pflags) 720 { 721 uint32_t flags; 722 *pc = env->pc; 723 *cs_base = env->npc; 724 flags = cpu_mmu_index(env_cpu(env), false); 725 #ifndef CONFIG_USER_ONLY 726 if (cpu_supervisor_mode(env)) { 727 flags |= TB_FLAG_SUPER; 728 } 729 #endif 730 #ifdef TARGET_SPARC64 731 #ifndef CONFIG_USER_ONLY 732 if (cpu_hypervisor_mode(env)) { 733 flags |= TB_FLAG_HYPER; 734 } 735 #endif 736 if (env->pstate & PS_AM) { 737 flags |= TB_FLAG_AM_ENABLED; 738 } 739 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 740 flags |= TB_FLAG_FPU_ENABLED; 741 } 742 flags |= env->asi << TB_FLAG_ASI_SHIFT; 743 #else 744 if (env->psref) { 745 flags |= TB_FLAG_FPU_ENABLED; 746 } 747 #ifndef CONFIG_USER_ONLY 748 if (env->fsr_qne) { 749 flags |= TB_FLAG_FSR_QNE; 750 } 751 #endif /* !CONFIG_USER_ONLY */ 752 #endif /* TARGET_SPARC64 */ 753 *pflags = flags; 754 } 755 756 static void sparc_restore_state_to_opc(CPUState *cs, 757 const TranslationBlock *tb, 758 const uint64_t *data) 759 { 760 CPUSPARCState *env = cpu_env(cs); 761 target_ulong pc = data[0]; 762 target_ulong npc = data[1]; 763 764 env->pc = pc; 765 if (npc == DYNAMIC_PC) { 766 /* dynamic NPC: already stored */ 767 } else if (npc & JUMP_PC) { 768 /* jump PC: use 'cond' and the jump targets of the translation */ 769 if (env->cond) { 770 env->npc = npc & ~3; 771 } else { 772 env->npc = pc + 4; 773 } 774 } else { 775 env->npc = npc; 776 } 777 } 778 779 static bool sparc_cpu_has_work(CPUState *cs) 780 { 781 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 782 cpu_interrupts_enabled(cpu_env(cs)); 783 } 784 785 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) 786 { 787 CPUSPARCState *env = cpu_env(cs); 788 789 #ifndef TARGET_SPARC64 790 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 791 return MMU_PHYS_IDX; 792 } else { 793 return env->psrs; 794 } 795 #else 796 /* IMMU or DMMU disabled. */ 797 if (ifetch 798 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 799 : (env->lsu & DMMU_E) == 0) { 800 return MMU_PHYS_IDX; 801 } else if (cpu_hypervisor_mode(env)) { 802 return MMU_PHYS_IDX; 803 } else if (env->tl > 0) { 804 return MMU_NUCLEUS_IDX; 805 } else if (cpu_supervisor_mode(env)) { 806 return MMU_KERNEL_IDX; 807 } else { 808 return MMU_USER_IDX; 809 } 810 #endif 811 } 812 813 static char *sparc_cpu_type_name(const char *cpu_model) 814 { 815 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); 816 char *s = name; 817 818 /* SPARC cpu model names happen to have whitespaces, 819 * as type names shouldn't have spaces replace them with '-' 820 */ 821 while ((s = strchr(s, ' '))) { 822 *s = '-'; 823 } 824 825 return name; 826 } 827 828 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 829 { 830 ObjectClass *oc; 831 char *typename; 832 833 typename = sparc_cpu_type_name(cpu_model); 834 835 /* Fix up legacy names with '+' in it */ 836 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { 837 g_free(typename); 838 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus")); 839 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) { 840 g_free(typename); 841 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus")); 842 } 843 844 oc = object_class_by_name(typename); 845 g_free(typename); 846 return oc; 847 } 848 849 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 850 { 851 CPUState *cs = CPU(dev); 852 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 853 Error *local_err = NULL; 854 CPUSPARCState *env = cpu_env(cs); 855 856 #if defined(CONFIG_USER_ONLY) 857 /* We are emulating the kernel, which will trap and emulate float128. */ 858 env->def.features |= CPU_FEATURE_FLOAT128; 859 #endif 860 861 env->version = env->def.iu_version; 862 env->nwindows = env->def.nwindows; 863 #if !defined(TARGET_SPARC64) 864 env->mmuregs[0] |= env->def.mmu_version; 865 cpu_sparc_set_id(env, 0); 866 env->mxccregs[7] |= env->def.mxcc_version; 867 #else 868 env->mmu_version = env->def.mmu_version; 869 env->maxtl = env->def.maxtl; 870 env->version |= env->def.maxtl << 8; 871 env->version |= env->def.nwindows - 1; 872 #endif 873 874 /* 875 * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize 876 * rather than reset, because fp_status is after 'end_reset_fields' in 877 * the CPU state struct so it won't get zeroed on reset. 878 */ 879 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); 880 /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ 881 set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); 882 /* For inf * 0 + NaN, return the input NaN */ 883 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 884 /* Default NaN value: sign bit clear, all frac bits set */ 885 set_float_default_nan_pattern(0b01111111, &env->fp_status); 886 887 cpu_exec_realizefn(cs, &local_err); 888 if (local_err != NULL) { 889 error_propagate(errp, local_err); 890 return; 891 } 892 893 qemu_init_vcpu(cs); 894 895 scc->parent_realize(dev, errp); 896 } 897 898 static void sparc_cpu_initfn(Object *obj) 899 { 900 SPARCCPU *cpu = SPARC_CPU(obj); 901 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 902 CPUSPARCState *env = &cpu->env; 903 904 if (scc->cpu_def) { 905 env->def = *scc->cpu_def; 906 } 907 } 908 909 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, 910 void *opaque, Error **errp) 911 { 912 SPARCCPU *cpu = SPARC_CPU(obj); 913 int64_t value = cpu->env.def.nwindows; 914 915 visit_type_int(v, name, &value, errp); 916 } 917 918 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, 919 void *opaque, Error **errp) 920 { 921 const int64_t min = MIN_NWINDOWS; 922 const int64_t max = MAX_NWINDOWS; 923 SPARCCPU *cpu = SPARC_CPU(obj); 924 int64_t value; 925 926 if (!visit_type_int(v, name, &value, errp)) { 927 return; 928 } 929 930 if (value < min || value > max) { 931 error_setg(errp, "Property %s.%s doesn't take value %" PRId64 932 " (minimum: %" PRId64 ", maximum: %" PRId64 ")", 933 object_get_typename(obj), name ? name : "null", 934 value, min, max); 935 return; 936 } 937 cpu->env.def.nwindows = value; 938 } 939 940 static const PropertyInfo qdev_prop_nwindows = { 941 .name = "int", 942 .get = sparc_get_nwindows, 943 .set = sparc_set_nwindows, 944 }; 945 946 /* This must match feature_name[]. */ 947 static const Property sparc_cpu_properties[] = { 948 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 949 CPU_FEATURE_BIT_FLOAT128, false), 950 #ifdef TARGET_SPARC64 951 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 952 CPU_FEATURE_BIT_CMT, false), 953 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 954 CPU_FEATURE_BIT_GL, false), 955 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 956 CPU_FEATURE_BIT_HYPV, false), 957 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 958 CPU_FEATURE_BIT_VIS1, false), 959 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 960 CPU_FEATURE_BIT_VIS2, false), 961 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, 962 CPU_FEATURE_BIT_FMAF, false), 963 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, 964 CPU_FEATURE_BIT_VIS3, false), 965 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, 966 CPU_FEATURE_BIT_IMA, false), 967 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, 968 CPU_FEATURE_BIT_VIS4, false), 969 #else 970 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 971 CPU_FEATURE_BIT_MUL, false), 972 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 973 CPU_FEATURE_BIT_DIV, false), 974 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 975 CPU_FEATURE_BIT_FSMULD, false), 976 #endif 977 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, 978 qdev_prop_uint64, target_ulong), 979 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), 980 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), 981 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, 982 qdev_prop_nwindows, uint32_t), 983 }; 984 985 #ifndef CONFIG_USER_ONLY 986 #include "hw/core/sysemu-cpu-ops.h" 987 988 static const struct SysemuCPUOps sparc_sysemu_ops = { 989 .get_phys_page_debug = sparc_cpu_get_phys_page_debug, 990 .legacy_vmsd = &vmstate_sparc_cpu, 991 }; 992 #endif 993 994 #ifdef CONFIG_TCG 995 #include "hw/core/tcg-cpu-ops.h" 996 997 static const TCGCPUOps sparc_tcg_ops = { 998 .initialize = sparc_tcg_init, 999 .translate_code = sparc_translate_code, 1000 .synchronize_from_tb = sparc_cpu_synchronize_from_tb, 1001 .restore_state_to_opc = sparc_restore_state_to_opc, 1002 1003 #ifndef CONFIG_USER_ONLY 1004 .tlb_fill = sparc_cpu_tlb_fill, 1005 .cpu_exec_interrupt = sparc_cpu_exec_interrupt, 1006 .cpu_exec_halt = sparc_cpu_has_work, 1007 .do_interrupt = sparc_cpu_do_interrupt, 1008 .do_transaction_failed = sparc_cpu_do_transaction_failed, 1009 .do_unaligned_access = sparc_cpu_do_unaligned_access, 1010 #endif /* !CONFIG_USER_ONLY */ 1011 }; 1012 #endif /* CONFIG_TCG */ 1013 1014 static void sparc_cpu_class_init(ObjectClass *oc, void *data) 1015 { 1016 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1017 CPUClass *cc = CPU_CLASS(oc); 1018 DeviceClass *dc = DEVICE_CLASS(oc); 1019 ResettableClass *rc = RESETTABLE_CLASS(oc); 1020 1021 device_class_set_parent_realize(dc, sparc_cpu_realizefn, 1022 &scc->parent_realize); 1023 device_class_set_props(dc, sparc_cpu_properties); 1024 1025 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, 1026 &scc->parent_phases); 1027 1028 cc->class_by_name = sparc_cpu_class_by_name; 1029 cc->parse_features = sparc_cpu_parse_features; 1030 cc->has_work = sparc_cpu_has_work; 1031 cc->mmu_index = sparc_cpu_mmu_index; 1032 cc->dump_state = sparc_cpu_dump_state; 1033 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 1034 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 1035 #endif 1036 cc->set_pc = sparc_cpu_set_pc; 1037 cc->get_pc = sparc_cpu_get_pc; 1038 cc->gdb_read_register = sparc_cpu_gdb_read_register; 1039 cc->gdb_write_register = sparc_cpu_gdb_write_register; 1040 #ifndef CONFIG_USER_ONLY 1041 cc->sysemu_ops = &sparc_sysemu_ops; 1042 #endif 1043 cc->disas_set_info = cpu_sparc_disas_set_info; 1044 1045 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1046 cc->gdb_num_core_regs = 86; 1047 #else 1048 cc->gdb_num_core_regs = 72; 1049 #endif 1050 cc->tcg_ops = &sparc_tcg_ops; 1051 } 1052 1053 static const TypeInfo sparc_cpu_type_info = { 1054 .name = TYPE_SPARC_CPU, 1055 .parent = TYPE_CPU, 1056 .instance_size = sizeof(SPARCCPU), 1057 .instance_align = __alignof(SPARCCPU), 1058 .instance_init = sparc_cpu_initfn, 1059 .abstract = true, 1060 .class_size = sizeof(SPARCCPUClass), 1061 .class_init = sparc_cpu_class_init, 1062 }; 1063 1064 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) 1065 { 1066 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1067 scc->cpu_def = data; 1068 } 1069 1070 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 1071 { 1072 char *typename = sparc_cpu_type_name(def->name); 1073 TypeInfo ti = { 1074 .name = typename, 1075 .parent = TYPE_SPARC_CPU, 1076 .class_init = sparc_cpu_cpudef_class_init, 1077 .class_data = (void *)def, 1078 }; 1079 1080 type_register_static(&ti); 1081 g_free(typename); 1082 } 1083 1084 static void sparc_cpu_register_types(void) 1085 { 1086 int i; 1087 1088 type_register_static(&sparc_cpu_type_info); 1089 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 1090 sparc_register_cpudef_type(&sparc_defs[i]); 1091 } 1092 } 1093 1094 type_init(sparc_cpu_register_types) 1095