1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/module.h" 24 #include "qemu/qemu-print.h" 25 #include "accel/tcg/cpu-mmu-index.h" 26 #include "exec/exec-all.h" 27 #include "exec/translation-block.h" 28 #include "hw/qdev-properties.h" 29 #include "qapi/visitor.h" 30 #include "tcg/tcg.h" 31 #include "fpu/softfloat.h" 32 #include "target/sparc/translate.h" 33 34 //#define DEBUG_FEATURES 35 36 static void sparc_cpu_reset_hold(Object *obj, ResetType type) 37 { 38 CPUState *cs = CPU(obj); 39 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 40 CPUSPARCState *env = cpu_env(cs); 41 42 if (scc->parent_phases.hold) { 43 scc->parent_phases.hold(obj, type); 44 } 45 46 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 47 env->cwp = 0; 48 #ifndef TARGET_SPARC64 49 env->wim = 1; 50 #endif 51 env->regwptr = env->regbase + (env->cwp * 16); 52 #if defined(CONFIG_USER_ONLY) 53 #ifdef TARGET_SPARC64 54 env->cleanwin = env->nwindows - 2; 55 env->cansave = env->nwindows - 2; 56 env->pstate = PS_RMO | PS_PEF | PS_IE; 57 env->asi = 0x82; /* Primary no-fault */ 58 #endif 59 #else 60 #if !defined(TARGET_SPARC64) 61 env->psret = 0; 62 env->psrs = 1; 63 env->psrps = 1; 64 #endif 65 #ifdef TARGET_SPARC64 66 env->pstate = PS_PRIV | PS_RED | PS_PEF; 67 if (!cpu_has_hypervisor(env)) { 68 env->pstate |= PS_AG; 69 } 70 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 71 env->tl = env->maxtl; 72 env->gl = 2; 73 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 74 env->lsu = 0; 75 #else 76 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 77 env->mmuregs[0] |= env->def.mmu_bm; 78 #endif 79 env->pc = 0; 80 env->npc = env->pc + 4; 81 #endif 82 env->cache_control = 0; 83 cpu_put_fsr(env, 0); 84 } 85 86 #ifndef CONFIG_USER_ONLY 87 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 88 { 89 if (interrupt_request & CPU_INTERRUPT_HARD) { 90 CPUSPARCState *env = cpu_env(cs); 91 92 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 93 int pil = env->interrupt_index & 0xf; 94 int type = env->interrupt_index & 0xf0; 95 96 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 97 cs->exception_index = env->interrupt_index; 98 sparc_cpu_do_interrupt(cs); 99 return true; 100 } 101 } 102 } 103 return false; 104 } 105 #endif /* !CONFIG_USER_ONLY */ 106 107 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 108 { 109 info->print_insn = print_insn_sparc; 110 info->endian = BFD_ENDIAN_BIG; 111 #ifdef TARGET_SPARC64 112 info->mach = bfd_mach_sparc_v9b; 113 #endif 114 } 115 116 static void 117 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) 118 { 119 GlobalProperty *prop = g_new0(typeof(*prop), 1); 120 prop->driver = typename; 121 prop->property = g_strdup(name); 122 prop->value = g_strdup(val); 123 qdev_prop_register_global(prop); 124 } 125 126 /* Parse "+feature,-feature,feature=foo" CPU feature string */ 127 static void sparc_cpu_parse_features(const char *typename, char *features, 128 Error **errp) 129 { 130 GList *l, *plus_features = NULL, *minus_features = NULL; 131 char *featurestr; /* Single 'key=value" string being parsed */ 132 static bool cpu_globals_initialized; 133 134 if (cpu_globals_initialized) { 135 return; 136 } 137 cpu_globals_initialized = true; 138 139 if (!features) { 140 return; 141 } 142 143 for (featurestr = strtok(features, ","); 144 featurestr; 145 featurestr = strtok(NULL, ",")) { 146 const char *name; 147 const char *val = NULL; 148 char *eq = NULL; 149 150 /* Compatibility syntax: */ 151 if (featurestr[0] == '+') { 152 plus_features = g_list_append(plus_features, 153 g_strdup(featurestr + 1)); 154 continue; 155 } else if (featurestr[0] == '-') { 156 minus_features = g_list_append(minus_features, 157 g_strdup(featurestr + 1)); 158 continue; 159 } 160 161 eq = strchr(featurestr, '='); 162 name = featurestr; 163 if (eq) { 164 *eq++ = 0; 165 val = eq; 166 167 /* 168 * Temporarily, only +feat/-feat will be supported 169 * for boolean properties until we remove the 170 * minus-overrides-plus semantics and just follow 171 * the order options appear on the command-line. 172 * 173 * TODO: warn if user is relying on minus-override-plus semantics 174 * TODO: remove minus-override-plus semantics after 175 * warning for a few releases 176 */ 177 if (!strcasecmp(val, "on") || 178 !strcasecmp(val, "off") || 179 !strcasecmp(val, "true") || 180 !strcasecmp(val, "false")) { 181 error_setg(errp, "Boolean properties in format %s=%s" 182 " are not supported", name, val); 183 return; 184 } 185 } else { 186 error_setg(errp, "Unsupported property format: %s", name); 187 return; 188 } 189 cpu_add_feat_as_prop(typename, name, val); 190 } 191 192 for (l = plus_features; l; l = l->next) { 193 const char *name = l->data; 194 cpu_add_feat_as_prop(typename, name, "on"); 195 } 196 g_list_free_full(plus_features, g_free); 197 198 for (l = minus_features; l; l = l->next) { 199 const char *name = l->data; 200 cpu_add_feat_as_prop(typename, name, "off"); 201 } 202 g_list_free_full(minus_features, g_free); 203 } 204 205 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 206 { 207 #if !defined(TARGET_SPARC64) 208 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 209 #endif 210 } 211 212 static const sparc_def_t sparc_defs[] = { 213 #ifdef TARGET_SPARC64 214 { 215 .name = "Fujitsu-Sparc64", 216 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 217 .fpu_version = 0x00000000, 218 .mmu_version = mmu_us_12, 219 .nwindows = 4, 220 .maxtl = 4, 221 .features = CPU_DEFAULT_FEATURES, 222 }, 223 { 224 .name = "Fujitsu-Sparc64-III", 225 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 226 .fpu_version = 0x00000000, 227 .mmu_version = mmu_us_12, 228 .nwindows = 5, 229 .maxtl = 4, 230 .features = CPU_DEFAULT_FEATURES, 231 }, 232 { 233 .name = "Fujitsu-Sparc64-IV", 234 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 235 .fpu_version = 0x00000000, 236 .mmu_version = mmu_us_12, 237 .nwindows = 8, 238 .maxtl = 5, 239 .features = CPU_DEFAULT_FEATURES, 240 }, 241 { 242 .name = "Fujitsu-Sparc64-V", 243 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 244 .fpu_version = 0x00000000, 245 .mmu_version = mmu_us_12, 246 .nwindows = 8, 247 .maxtl = 5, 248 .features = CPU_DEFAULT_FEATURES, 249 }, 250 { 251 .name = "TI-UltraSparc-I", 252 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 253 .fpu_version = 0x00000000, 254 .mmu_version = mmu_us_12, 255 .nwindows = 8, 256 .maxtl = 5, 257 .features = CPU_DEFAULT_FEATURES, 258 }, 259 { 260 .name = "TI-UltraSparc-II", 261 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 262 .fpu_version = 0x00000000, 263 .mmu_version = mmu_us_12, 264 .nwindows = 8, 265 .maxtl = 5, 266 .features = CPU_DEFAULT_FEATURES, 267 }, 268 { 269 .name = "TI-UltraSparc-IIi", 270 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 271 .fpu_version = 0x00000000, 272 .mmu_version = mmu_us_12, 273 .nwindows = 8, 274 .maxtl = 5, 275 .features = CPU_DEFAULT_FEATURES, 276 }, 277 { 278 .name = "TI-UltraSparc-IIe", 279 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 280 .fpu_version = 0x00000000, 281 .mmu_version = mmu_us_12, 282 .nwindows = 8, 283 .maxtl = 5, 284 .features = CPU_DEFAULT_FEATURES, 285 }, 286 { 287 .name = "Sun-UltraSparc-III", 288 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 289 .fpu_version = 0x00000000, 290 .mmu_version = mmu_us_12, 291 .nwindows = 8, 292 .maxtl = 5, 293 .features = CPU_DEFAULT_FEATURES, 294 }, 295 { 296 .name = "Sun-UltraSparc-III-Cu", 297 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 298 .fpu_version = 0x00000000, 299 .mmu_version = mmu_us_3, 300 .nwindows = 8, 301 .maxtl = 5, 302 .features = CPU_DEFAULT_FEATURES, 303 }, 304 { 305 .name = "Sun-UltraSparc-IIIi", 306 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 307 .fpu_version = 0x00000000, 308 .mmu_version = mmu_us_12, 309 .nwindows = 8, 310 .maxtl = 5, 311 .features = CPU_DEFAULT_FEATURES, 312 }, 313 { 314 .name = "Sun-UltraSparc-IV", 315 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 316 .fpu_version = 0x00000000, 317 .mmu_version = mmu_us_4, 318 .nwindows = 8, 319 .maxtl = 5, 320 .features = CPU_DEFAULT_FEATURES, 321 }, 322 { 323 .name = "Sun-UltraSparc-IV-plus", 324 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 325 .fpu_version = 0x00000000, 326 .mmu_version = mmu_us_12, 327 .nwindows = 8, 328 .maxtl = 5, 329 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 330 }, 331 { 332 .name = "Sun-UltraSparc-IIIi-plus", 333 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 334 .fpu_version = 0x00000000, 335 .mmu_version = mmu_us_3, 336 .nwindows = 8, 337 .maxtl = 5, 338 .features = CPU_DEFAULT_FEATURES, 339 }, 340 { 341 .name = "Sun-UltraSparc-T1", 342 /* defined in sparc_ifu_fdp.v and ctu.h */ 343 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 344 .fpu_version = 0x00000000, 345 .mmu_version = mmu_sun4v, 346 .nwindows = 8, 347 .maxtl = 6, 348 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 349 | CPU_FEATURE_GL, 350 }, 351 { 352 .name = "Sun-UltraSparc-T2", 353 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 354 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 355 .fpu_version = 0x00000000, 356 .mmu_version = mmu_sun4v, 357 .nwindows = 8, 358 .maxtl = 6, 359 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 360 | CPU_FEATURE_GL, 361 }, 362 { 363 .name = "NEC-UltraSparc-I", 364 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 365 .fpu_version = 0x00000000, 366 .mmu_version = mmu_us_12, 367 .nwindows = 8, 368 .maxtl = 5, 369 .features = CPU_DEFAULT_FEATURES, 370 }, 371 #else 372 { 373 .name = "Fujitsu-MB86904", 374 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 375 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 376 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 377 .mmu_bm = 0x00004000, 378 .mmu_ctpr_mask = 0x00ffffc0, 379 .mmu_cxr_mask = 0x000000ff, 380 .mmu_sfsr_mask = 0x00016fff, 381 .mmu_trcr_mask = 0x00ffffff, 382 .nwindows = 8, 383 .features = CPU_DEFAULT_FEATURES, 384 }, 385 { 386 .name = "Fujitsu-MB86907", 387 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 388 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 389 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 390 .mmu_bm = 0x00004000, 391 .mmu_ctpr_mask = 0xffffffc0, 392 .mmu_cxr_mask = 0x000000ff, 393 .mmu_sfsr_mask = 0x00016fff, 394 .mmu_trcr_mask = 0xffffffff, 395 .nwindows = 8, 396 .features = CPU_DEFAULT_FEATURES, 397 }, 398 { 399 .name = "TI-MicroSparc-I", 400 .iu_version = 0x41000000, 401 .fpu_version = 4 << FSR_VER_SHIFT, 402 .mmu_version = 0x41000000, 403 .mmu_bm = 0x00004000, 404 .mmu_ctpr_mask = 0x007ffff0, 405 .mmu_cxr_mask = 0x0000003f, 406 .mmu_sfsr_mask = 0x00016fff, 407 .mmu_trcr_mask = 0x0000003f, 408 .nwindows = 7, 409 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV, 410 }, 411 { 412 .name = "TI-MicroSparc-II", 413 .iu_version = 0x42000000, 414 .fpu_version = 4 << FSR_VER_SHIFT, 415 .mmu_version = 0x02000000, 416 .mmu_bm = 0x00004000, 417 .mmu_ctpr_mask = 0x00ffffc0, 418 .mmu_cxr_mask = 0x000000ff, 419 .mmu_sfsr_mask = 0x00016fff, 420 .mmu_trcr_mask = 0x00ffffff, 421 .nwindows = 8, 422 .features = CPU_DEFAULT_FEATURES, 423 }, 424 { 425 .name = "TI-MicroSparc-IIep", 426 .iu_version = 0x42000000, 427 .fpu_version = 4 << FSR_VER_SHIFT, 428 .mmu_version = 0x04000000, 429 .mmu_bm = 0x00004000, 430 .mmu_ctpr_mask = 0x00ffffc0, 431 .mmu_cxr_mask = 0x000000ff, 432 .mmu_sfsr_mask = 0x00016bff, 433 .mmu_trcr_mask = 0x00ffffff, 434 .nwindows = 8, 435 .features = CPU_DEFAULT_FEATURES, 436 }, 437 { 438 .name = "TI-SuperSparc-40", /* STP1020NPGA */ 439 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 440 .fpu_version = 0 << FSR_VER_SHIFT, 441 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 442 .mmu_bm = 0x00002000, 443 .mmu_ctpr_mask = 0xffffffc0, 444 .mmu_cxr_mask = 0x0000ffff, 445 .mmu_sfsr_mask = 0xffffffff, 446 .mmu_trcr_mask = 0xffffffff, 447 .nwindows = 8, 448 .features = CPU_DEFAULT_FEATURES, 449 }, 450 { 451 .name = "TI-SuperSparc-50", /* STP1020PGA */ 452 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 453 .fpu_version = 0 << FSR_VER_SHIFT, 454 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 455 .mmu_bm = 0x00002000, 456 .mmu_ctpr_mask = 0xffffffc0, 457 .mmu_cxr_mask = 0x0000ffff, 458 .mmu_sfsr_mask = 0xffffffff, 459 .mmu_trcr_mask = 0xffffffff, 460 .nwindows = 8, 461 .features = CPU_DEFAULT_FEATURES, 462 }, 463 { 464 .name = "TI-SuperSparc-51", 465 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 466 .fpu_version = 0 << FSR_VER_SHIFT, 467 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 468 .mmu_bm = 0x00002000, 469 .mmu_ctpr_mask = 0xffffffc0, 470 .mmu_cxr_mask = 0x0000ffff, 471 .mmu_sfsr_mask = 0xffffffff, 472 .mmu_trcr_mask = 0xffffffff, 473 .mxcc_version = 0x00000104, 474 .nwindows = 8, 475 .features = CPU_DEFAULT_FEATURES, 476 }, 477 { 478 .name = "TI-SuperSparc-60", /* STP1020APGA */ 479 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 480 .fpu_version = 0 << FSR_VER_SHIFT, 481 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 482 .mmu_bm = 0x00002000, 483 .mmu_ctpr_mask = 0xffffffc0, 484 .mmu_cxr_mask = 0x0000ffff, 485 .mmu_sfsr_mask = 0xffffffff, 486 .mmu_trcr_mask = 0xffffffff, 487 .nwindows = 8, 488 .features = CPU_DEFAULT_FEATURES, 489 }, 490 { 491 .name = "TI-SuperSparc-61", 492 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 493 .fpu_version = 0 << FSR_VER_SHIFT, 494 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 495 .mmu_bm = 0x00002000, 496 .mmu_ctpr_mask = 0xffffffc0, 497 .mmu_cxr_mask = 0x0000ffff, 498 .mmu_sfsr_mask = 0xffffffff, 499 .mmu_trcr_mask = 0xffffffff, 500 .mxcc_version = 0x00000104, 501 .nwindows = 8, 502 .features = CPU_DEFAULT_FEATURES, 503 }, 504 { 505 .name = "TI-SuperSparc-II", 506 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 507 .fpu_version = 0 << FSR_VER_SHIFT, 508 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 509 .mmu_bm = 0x00002000, 510 .mmu_ctpr_mask = 0xffffffc0, 511 .mmu_cxr_mask = 0x0000ffff, 512 .mmu_sfsr_mask = 0xffffffff, 513 .mmu_trcr_mask = 0xffffffff, 514 .mxcc_version = 0x00000104, 515 .nwindows = 8, 516 .features = CPU_DEFAULT_FEATURES, 517 }, 518 { 519 .name = "LEON2", 520 .iu_version = 0xf2000000, 521 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 522 .mmu_version = 0xf2000000, 523 .mmu_bm = 0x00004000, 524 .mmu_ctpr_mask = 0x007ffff0, 525 .mmu_cxr_mask = 0x0000003f, 526 .mmu_sfsr_mask = 0xffffffff, 527 .mmu_trcr_mask = 0xffffffff, 528 .nwindows = 8, 529 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 530 }, 531 { 532 .name = "LEON3", 533 .iu_version = 0xf3000000, 534 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ 535 .mmu_version = 0xf3000000, 536 .mmu_bm = 0x00000000, 537 .mmu_ctpr_mask = 0xfffffffc, 538 .mmu_cxr_mask = 0x000000ff, 539 .mmu_sfsr_mask = 0xffffffff, 540 .mmu_trcr_mask = 0xffffffff, 541 .nwindows = 8, 542 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 543 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 544 CPU_FEATURE_CASA, 545 }, 546 #endif 547 }; 548 549 /* This must match sparc_cpu_properties[]. */ 550 static const char * const feature_name[] = { 551 [CPU_FEATURE_BIT_FLOAT128] = "float128", 552 #ifdef TARGET_SPARC64 553 [CPU_FEATURE_BIT_CMT] = "cmt", 554 [CPU_FEATURE_BIT_GL] = "gl", 555 [CPU_FEATURE_BIT_HYPV] = "hypv", 556 [CPU_FEATURE_BIT_VIS1] = "vis1", 557 [CPU_FEATURE_BIT_VIS2] = "vis2", 558 [CPU_FEATURE_BIT_FMAF] = "fmaf", 559 [CPU_FEATURE_BIT_VIS3] = "vis3", 560 [CPU_FEATURE_BIT_IMA] = "ima", 561 [CPU_FEATURE_BIT_VIS4] = "vis4", 562 #else 563 [CPU_FEATURE_BIT_MUL] = "mul", 564 [CPU_FEATURE_BIT_DIV] = "div", 565 [CPU_FEATURE_BIT_FSMULD] = "fsmuld", 566 #endif 567 }; 568 569 static void print_features(uint32_t features, const char *prefix) 570 { 571 unsigned int i; 572 573 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 574 if (feature_name[i] && (features & (1 << i))) { 575 if (prefix) { 576 qemu_printf("%s", prefix); 577 } 578 qemu_printf("%s ", feature_name[i]); 579 } 580 } 581 } 582 583 static void sparc_cpu_list(void) 584 { 585 unsigned int i; 586 587 qemu_printf("Available CPU types:\n"); 588 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 589 qemu_printf(" %-20s (IU " TARGET_FMT_lx 590 " FPU %08x MMU %08x NWINS %d) ", 591 sparc_defs[i].name, 592 sparc_defs[i].iu_version, 593 sparc_defs[i].fpu_version, 594 sparc_defs[i].mmu_version, 595 sparc_defs[i].nwindows); 596 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); 597 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); 598 qemu_printf("\n"); 599 } 600 qemu_printf("Default CPU feature flags (use '-' to remove): "); 601 print_features(CPU_DEFAULT_FEATURES, NULL); 602 qemu_printf("\n"); 603 qemu_printf("Available CPU feature flags (use '+' to add): "); 604 print_features(~CPU_DEFAULT_FEATURES, NULL); 605 qemu_printf("\n"); 606 qemu_printf("Numerical features (use '=' to set): iu_version " 607 "fpu_version mmu_version nwindows\n"); 608 } 609 610 static void cpu_print_cc(FILE *f, uint32_t cc) 611 { 612 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 613 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 614 cc & PSR_CARRY ? 'C' : '-'); 615 } 616 617 #ifdef TARGET_SPARC64 618 #define REGS_PER_LINE 4 619 #else 620 #define REGS_PER_LINE 8 621 #endif 622 623 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 624 { 625 CPUSPARCState *env = cpu_env(cs); 626 int i, x; 627 628 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 629 env->npc); 630 631 for (i = 0; i < 8; i++) { 632 if (i % REGS_PER_LINE == 0) { 633 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 634 } 635 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 636 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 637 qemu_fprintf(f, "\n"); 638 } 639 } 640 for (x = 0; x < 3; x++) { 641 for (i = 0; i < 8; i++) { 642 if (i % REGS_PER_LINE == 0) { 643 qemu_fprintf(f, "%%%c%d-%d: ", 644 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 645 i, i + REGS_PER_LINE - 1); 646 } 647 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 648 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 649 qemu_fprintf(f, "\n"); 650 } 651 } 652 } 653 654 if (flags & CPU_DUMP_FPU) { 655 for (i = 0; i < TARGET_DPREGS; i++) { 656 if ((i & 3) == 0) { 657 qemu_fprintf(f, "%%f%02d: ", i * 2); 658 } 659 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 660 if ((i & 3) == 3) { 661 qemu_fprintf(f, "\n"); 662 } 663 } 664 } 665 666 #ifdef TARGET_SPARC64 667 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 668 (unsigned)cpu_get_ccr(env)); 669 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 670 qemu_fprintf(f, " xcc: "); 671 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 672 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 673 env->psrpil, env->gl); 674 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 675 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 676 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 677 "cleanwin: %d cwp: %d\n", 678 env->cansave, env->canrestore, env->otherwin, env->wstate, 679 env->cleanwin, env->nwindows - 1 - env->cwp); 680 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", 681 cpu_get_fsr(env), env->y, env->fprs); 682 683 #else 684 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 685 cpu_print_cc(f, cpu_get_psr(env)); 686 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 687 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 688 env->wim); 689 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 690 cpu_get_fsr(env), env->y); 691 #endif 692 qemu_fprintf(f, "\n"); 693 } 694 695 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 696 { 697 SPARCCPU *cpu = SPARC_CPU(cs); 698 699 cpu->env.pc = value; 700 cpu->env.npc = value + 4; 701 } 702 703 static vaddr sparc_cpu_get_pc(CPUState *cs) 704 { 705 SPARCCPU *cpu = SPARC_CPU(cs); 706 707 return cpu->env.pc; 708 } 709 710 static void sparc_cpu_synchronize_from_tb(CPUState *cs, 711 const TranslationBlock *tb) 712 { 713 SPARCCPU *cpu = SPARC_CPU(cs); 714 715 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 716 cpu->env.pc = tb->pc; 717 cpu->env.npc = tb->cs_base; 718 } 719 720 void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 721 uint64_t *cs_base, uint32_t *pflags) 722 { 723 uint32_t flags; 724 *pc = env->pc; 725 *cs_base = env->npc; 726 flags = cpu_mmu_index(env_cpu(env), false); 727 #ifndef CONFIG_USER_ONLY 728 if (cpu_supervisor_mode(env)) { 729 flags |= TB_FLAG_SUPER; 730 } 731 #endif 732 #ifdef TARGET_SPARC64 733 #ifndef CONFIG_USER_ONLY 734 if (cpu_hypervisor_mode(env)) { 735 flags |= TB_FLAG_HYPER; 736 } 737 #endif 738 if (env->pstate & PS_AM) { 739 flags |= TB_FLAG_AM_ENABLED; 740 } 741 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 742 flags |= TB_FLAG_FPU_ENABLED; 743 } 744 flags |= env->asi << TB_FLAG_ASI_SHIFT; 745 #else 746 if (env->psref) { 747 flags |= TB_FLAG_FPU_ENABLED; 748 } 749 #ifndef CONFIG_USER_ONLY 750 if (env->fsr_qne) { 751 flags |= TB_FLAG_FSR_QNE; 752 } 753 #endif /* !CONFIG_USER_ONLY */ 754 #endif /* TARGET_SPARC64 */ 755 *pflags = flags; 756 } 757 758 static void sparc_restore_state_to_opc(CPUState *cs, 759 const TranslationBlock *tb, 760 const uint64_t *data) 761 { 762 CPUSPARCState *env = cpu_env(cs); 763 target_ulong pc = data[0]; 764 target_ulong npc = data[1]; 765 766 env->pc = pc; 767 if (npc == DYNAMIC_PC) { 768 /* dynamic NPC: already stored */ 769 } else if (npc & JUMP_PC) { 770 /* jump PC: use 'cond' and the jump targets of the translation */ 771 if (env->cond) { 772 env->npc = npc & ~3; 773 } else { 774 env->npc = pc + 4; 775 } 776 } else { 777 env->npc = npc; 778 } 779 } 780 781 #ifndef CONFIG_USER_ONLY 782 static bool sparc_cpu_has_work(CPUState *cs) 783 { 784 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 785 cpu_interrupts_enabled(cpu_env(cs)); 786 } 787 #endif /* !CONFIG_USER_ONLY */ 788 789 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) 790 { 791 CPUSPARCState *env = cpu_env(cs); 792 793 #ifndef TARGET_SPARC64 794 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 795 return MMU_PHYS_IDX; 796 } else { 797 return env->psrs; 798 } 799 #else 800 /* IMMU or DMMU disabled. */ 801 if (ifetch 802 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 803 : (env->lsu & DMMU_E) == 0) { 804 return MMU_PHYS_IDX; 805 } else if (cpu_hypervisor_mode(env)) { 806 return MMU_PHYS_IDX; 807 } else if (env->tl > 0) { 808 return MMU_NUCLEUS_IDX; 809 } else if (cpu_supervisor_mode(env)) { 810 return MMU_KERNEL_IDX; 811 } else { 812 return MMU_USER_IDX; 813 } 814 #endif 815 } 816 817 static char *sparc_cpu_type_name(const char *cpu_model) 818 { 819 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); 820 char *s = name; 821 822 /* SPARC cpu model names happen to have whitespaces, 823 * as type names shouldn't have spaces replace them with '-' 824 */ 825 while ((s = strchr(s, ' '))) { 826 *s = '-'; 827 } 828 829 return name; 830 } 831 832 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 833 { 834 ObjectClass *oc; 835 char *typename; 836 837 typename = sparc_cpu_type_name(cpu_model); 838 839 /* Fix up legacy names with '+' in it */ 840 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { 841 g_free(typename); 842 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus")); 843 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) { 844 g_free(typename); 845 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus")); 846 } 847 848 oc = object_class_by_name(typename); 849 g_free(typename); 850 return oc; 851 } 852 853 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 854 { 855 CPUState *cs = CPU(dev); 856 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 857 Error *local_err = NULL; 858 CPUSPARCState *env = cpu_env(cs); 859 860 #if defined(CONFIG_USER_ONLY) 861 /* We are emulating the kernel, which will trap and emulate float128. */ 862 env->def.features |= CPU_FEATURE_FLOAT128; 863 #endif 864 865 env->version = env->def.iu_version; 866 env->nwindows = env->def.nwindows; 867 #if !defined(TARGET_SPARC64) 868 env->mmuregs[0] |= env->def.mmu_version; 869 cpu_sparc_set_id(env, 0); 870 env->mxccregs[7] |= env->def.mxcc_version; 871 #else 872 env->mmu_version = env->def.mmu_version; 873 env->maxtl = env->def.maxtl; 874 env->version |= env->def.maxtl << 8; 875 env->version |= env->def.nwindows - 1; 876 #endif 877 878 /* 879 * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize 880 * rather than reset, because fp_status is after 'end_reset_fields' in 881 * the CPU state struct so it won't get zeroed on reset. 882 */ 883 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); 884 /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ 885 set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); 886 /* For inf * 0 + NaN, return the input NaN */ 887 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 888 /* Default NaN value: sign bit clear, all frac bits set */ 889 set_float_default_nan_pattern(0b01111111, &env->fp_status); 890 891 cpu_exec_realizefn(cs, &local_err); 892 if (local_err != NULL) { 893 error_propagate(errp, local_err); 894 return; 895 } 896 897 qemu_init_vcpu(cs); 898 899 scc->parent_realize(dev, errp); 900 } 901 902 static void sparc_cpu_initfn(Object *obj) 903 { 904 SPARCCPU *cpu = SPARC_CPU(obj); 905 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 906 CPUSPARCState *env = &cpu->env; 907 908 if (scc->cpu_def) { 909 env->def = *scc->cpu_def; 910 } 911 } 912 913 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, 914 void *opaque, Error **errp) 915 { 916 SPARCCPU *cpu = SPARC_CPU(obj); 917 int64_t value = cpu->env.def.nwindows; 918 919 visit_type_int(v, name, &value, errp); 920 } 921 922 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, 923 void *opaque, Error **errp) 924 { 925 const int64_t min = MIN_NWINDOWS; 926 const int64_t max = MAX_NWINDOWS; 927 SPARCCPU *cpu = SPARC_CPU(obj); 928 int64_t value; 929 930 if (!visit_type_int(v, name, &value, errp)) { 931 return; 932 } 933 934 if (value < min || value > max) { 935 error_setg(errp, "Property %s.%s doesn't take value %" PRId64 936 " (minimum: %" PRId64 ", maximum: %" PRId64 ")", 937 object_get_typename(obj), name ? name : "null", 938 value, min, max); 939 return; 940 } 941 cpu->env.def.nwindows = value; 942 } 943 944 static const PropertyInfo qdev_prop_nwindows = { 945 .type = "int", 946 .description = "Number of register windows", 947 .get = sparc_get_nwindows, 948 .set = sparc_set_nwindows, 949 }; 950 951 /* This must match feature_name[]. */ 952 static const Property sparc_cpu_properties[] = { 953 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 954 CPU_FEATURE_BIT_FLOAT128, false), 955 #ifdef TARGET_SPARC64 956 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 957 CPU_FEATURE_BIT_CMT, false), 958 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 959 CPU_FEATURE_BIT_GL, false), 960 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 961 CPU_FEATURE_BIT_HYPV, false), 962 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 963 CPU_FEATURE_BIT_VIS1, false), 964 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 965 CPU_FEATURE_BIT_VIS2, false), 966 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, 967 CPU_FEATURE_BIT_FMAF, false), 968 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, 969 CPU_FEATURE_BIT_VIS3, false), 970 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, 971 CPU_FEATURE_BIT_IMA, false), 972 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, 973 CPU_FEATURE_BIT_VIS4, false), 974 #else 975 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 976 CPU_FEATURE_BIT_MUL, false), 977 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 978 CPU_FEATURE_BIT_DIV, false), 979 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 980 CPU_FEATURE_BIT_FSMULD, false), 981 #endif 982 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, 983 qdev_prop_uint64, target_ulong), 984 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), 985 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), 986 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, 987 qdev_prop_nwindows, uint32_t), 988 }; 989 990 #ifndef CONFIG_USER_ONLY 991 #include "hw/core/sysemu-cpu-ops.h" 992 993 static const struct SysemuCPUOps sparc_sysemu_ops = { 994 .has_work = sparc_cpu_has_work, 995 .get_phys_page_debug = sparc_cpu_get_phys_page_debug, 996 .legacy_vmsd = &vmstate_sparc_cpu, 997 }; 998 #endif 999 1000 #ifdef CONFIG_TCG 1001 #include "accel/tcg/cpu-ops.h" 1002 1003 static const TCGCPUOps sparc_tcg_ops = { 1004 /* 1005 * From Oracle SPARC Architecture 2015: 1006 * 1007 * Compatibility notes: The PSO memory model described in SPARC V8 and 1008 * SPARC V9 compatibility architecture specifications was never 1009 * implemented in a SPARC V9 implementation and is not included in the 1010 * Oracle SPARC Architecture specification. 1011 * 1012 * The RMO memory model described in the SPARC V9 specification was 1013 * implemented in some non-Sun SPARC V9 implementations, but is not 1014 * directly supported in Oracle SPARC Architecture 2015 implementations. 1015 * 1016 * Therefore always use TSO in QEMU. 1017 * 1018 * D.5 Specification of Partial Store Order (PSO) 1019 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 1020 * 1021 * D.6 Specification of Total Store Order (TSO) 1022 * ... PSO with the additional requirement that all [stores] are followed 1023 * by an implied MEMBAR #StoreStore. 1024 */ 1025 .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST, 1026 .mttcg_supported = true, 1027 1028 .initialize = sparc_tcg_init, 1029 .translate_code = sparc_translate_code, 1030 .synchronize_from_tb = sparc_cpu_synchronize_from_tb, 1031 .restore_state_to_opc = sparc_restore_state_to_opc, 1032 .mmu_index = sparc_cpu_mmu_index, 1033 1034 #ifndef CONFIG_USER_ONLY 1035 .tlb_fill = sparc_cpu_tlb_fill, 1036 .cpu_exec_interrupt = sparc_cpu_exec_interrupt, 1037 .cpu_exec_halt = sparc_cpu_has_work, 1038 .do_interrupt = sparc_cpu_do_interrupt, 1039 .do_transaction_failed = sparc_cpu_do_transaction_failed, 1040 .do_unaligned_access = sparc_cpu_do_unaligned_access, 1041 #endif /* !CONFIG_USER_ONLY */ 1042 }; 1043 #endif /* CONFIG_TCG */ 1044 1045 static void sparc_cpu_class_init(ObjectClass *oc, const void *data) 1046 { 1047 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1048 CPUClass *cc = CPU_CLASS(oc); 1049 DeviceClass *dc = DEVICE_CLASS(oc); 1050 ResettableClass *rc = RESETTABLE_CLASS(oc); 1051 1052 device_class_set_parent_realize(dc, sparc_cpu_realizefn, 1053 &scc->parent_realize); 1054 device_class_set_props(dc, sparc_cpu_properties); 1055 1056 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, 1057 &scc->parent_phases); 1058 1059 cc->class_by_name = sparc_cpu_class_by_name; 1060 cc->list_cpus = sparc_cpu_list, 1061 cc->parse_features = sparc_cpu_parse_features; 1062 cc->dump_state = sparc_cpu_dump_state; 1063 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 1064 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 1065 #endif 1066 cc->set_pc = sparc_cpu_set_pc; 1067 cc->get_pc = sparc_cpu_get_pc; 1068 cc->gdb_read_register = sparc_cpu_gdb_read_register; 1069 cc->gdb_write_register = sparc_cpu_gdb_write_register; 1070 #ifndef CONFIG_USER_ONLY 1071 cc->sysemu_ops = &sparc_sysemu_ops; 1072 #endif 1073 cc->disas_set_info = cpu_sparc_disas_set_info; 1074 1075 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1076 cc->gdb_num_core_regs = 86; 1077 #else 1078 cc->gdb_num_core_regs = 72; 1079 #endif 1080 cc->tcg_ops = &sparc_tcg_ops; 1081 } 1082 1083 static const TypeInfo sparc_cpu_type_info = { 1084 .name = TYPE_SPARC_CPU, 1085 .parent = TYPE_CPU, 1086 .instance_size = sizeof(SPARCCPU), 1087 .instance_align = __alignof(SPARCCPU), 1088 .instance_init = sparc_cpu_initfn, 1089 .abstract = true, 1090 .class_size = sizeof(SPARCCPUClass), 1091 .class_init = sparc_cpu_class_init, 1092 }; 1093 1094 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 1095 { 1096 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 1097 scc->cpu_def = data; 1098 } 1099 1100 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 1101 { 1102 char *typename = sparc_cpu_type_name(def->name); 1103 TypeInfo ti = { 1104 .name = typename, 1105 .parent = TYPE_SPARC_CPU, 1106 .class_init = sparc_cpu_cpudef_class_init, 1107 .class_data = def, 1108 }; 1109 1110 type_register_static(&ti); 1111 g_free(typename); 1112 } 1113 1114 static void sparc_cpu_register_types(void) 1115 { 1116 int i; 1117 1118 type_register_static(&sparc_cpu_type_info); 1119 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 1120 sparc_register_cpudef_type(&sparc_defs[i]); 1121 } 1122 } 1123 1124 type_init(sparc_cpu_register_types) 1125