1 /* 2 * Sparc cpu parameters for qemu. 3 * 4 * SPDX-License-Identifier: LGPL-2.0-or-later 5 */ 6 7 #ifndef SPARC_CPU_PARAM_H 8 #define SPARC_CPU_PARAM_H 9 10 #ifdef TARGET_SPARC64 11 # define TARGET_PAGE_BITS 13 /* 8k */ 12 # define TARGET_PHYS_ADDR_SPACE_BITS 41 13 # ifdef TARGET_ABI32 14 # define TARGET_VIRT_ADDR_SPACE_BITS 32 15 # else 16 # define TARGET_VIRT_ADDR_SPACE_BITS 44 17 # endif 18 #else 19 # define TARGET_PAGE_BITS 12 /* 4k */ 20 # define TARGET_PHYS_ADDR_SPACE_BITS 36 21 # define TARGET_VIRT_ADDR_SPACE_BITS 32 22 #endif 23 24 /* 25 * From Oracle SPARC Architecture 2015: 26 * 27 * Compatibility notes: The PSO memory model described in SPARC V8 and 28 * SPARC V9 compatibility architecture specifications was never implemented 29 * in a SPARC V9 implementation and is not included in the Oracle SPARC 30 * Architecture specification. 31 * 32 * The RMO memory model described in the SPARC V9 specification was 33 * implemented in some non-Sun SPARC V9 implementations, but is not 34 * directly supported in Oracle SPARC Architecture 2015 implementations. 35 * 36 * Therefore always use TSO in QEMU. 37 * 38 * D.5 Specification of Partial Store Order (PSO) 39 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 40 * 41 * D.6 Specification of Total Store Order (TSO) 42 * ... PSO with the additional requirement that all [stores] are followed 43 * by an implied MEMBAR #StoreStore. 44 */ 45 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 46 47 #endif 48