174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * Sparc cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 574433bf0SRichard Henderson */ 674433bf0SRichard Henderson 774433bf0SRichard Henderson #ifndef SPARC_CPU_PARAM_H 84f31b54bSMarkus Armbruster #define SPARC_CPU_PARAM_H 974433bf0SRichard Henderson 1074433bf0SRichard Henderson #ifdef TARGET_SPARC64 1174433bf0SRichard Henderson # define TARGET_LONG_BITS 64 1274433bf0SRichard Henderson # define TARGET_PAGE_BITS 13 /* 8k */ 1374433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 41 1474433bf0SRichard Henderson # ifdef TARGET_ABI32 1574433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 1674433bf0SRichard Henderson # else 1774433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 44 1874433bf0SRichard Henderson # endif 1974433bf0SRichard Henderson #else 2074433bf0SRichard Henderson # define TARGET_LONG_BITS 32 2174433bf0SRichard Henderson # define TARGET_PAGE_BITS 12 /* 4k */ 2274433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 36 2374433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 2474433bf0SRichard Henderson #endif 2574433bf0SRichard Henderson 26*e92dd332SPhilippe Mathieu-Daudé /* 27*e92dd332SPhilippe Mathieu-Daudé * From Oracle SPARC Architecture 2015: 28*e92dd332SPhilippe Mathieu-Daudé * 29*e92dd332SPhilippe Mathieu-Daudé * Compatibility notes: The PSO memory model described in SPARC V8 and 30*e92dd332SPhilippe Mathieu-Daudé * SPARC V9 compatibility architecture specifications was never implemented 31*e92dd332SPhilippe Mathieu-Daudé * in a SPARC V9 implementation and is not included in the Oracle SPARC 32*e92dd332SPhilippe Mathieu-Daudé * Architecture specification. 33*e92dd332SPhilippe Mathieu-Daudé * 34*e92dd332SPhilippe Mathieu-Daudé * The RMO memory model described in the SPARC V9 specification was 35*e92dd332SPhilippe Mathieu-Daudé * implemented in some non-Sun SPARC V9 implementations, but is not 36*e92dd332SPhilippe Mathieu-Daudé * directly supported in Oracle SPARC Architecture 2015 implementations. 37*e92dd332SPhilippe Mathieu-Daudé * 38*e92dd332SPhilippe Mathieu-Daudé * Therefore always use TSO in QEMU. 39*e92dd332SPhilippe Mathieu-Daudé * 40*e92dd332SPhilippe Mathieu-Daudé * D.5 Specification of Partial Store Order (PSO) 41*e92dd332SPhilippe Mathieu-Daudé * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 42*e92dd332SPhilippe Mathieu-Daudé * 43*e92dd332SPhilippe Mathieu-Daudé * D.6 Specification of Total Store Order (TSO) 44*e92dd332SPhilippe Mathieu-Daudé * ... PSO with the additional requirement that all [stores] are followed 45*e92dd332SPhilippe Mathieu-Daudé * by an implied MEMBAR #StoreStore. 46*e92dd332SPhilippe Mathieu-Daudé */ 47*e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 48*e92dd332SPhilippe Mathieu-Daudé 4974433bf0SRichard Henderson #endif 50