174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * Sparc cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 574433bf0SRichard Henderson */ 674433bf0SRichard Henderson 774433bf0SRichard Henderson #ifndef SPARC_CPU_PARAM_H 8*4f31b54bSMarkus Armbruster #define SPARC_CPU_PARAM_H 974433bf0SRichard Henderson 1074433bf0SRichard Henderson #ifdef TARGET_SPARC64 1174433bf0SRichard Henderson # define TARGET_LONG_BITS 64 1274433bf0SRichard Henderson # define TARGET_PAGE_BITS 13 /* 8k */ 1374433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 41 1474433bf0SRichard Henderson # ifdef TARGET_ABI32 1574433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 1674433bf0SRichard Henderson # else 1774433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 44 1874433bf0SRichard Henderson # endif 1974433bf0SRichard Henderson # define NB_MMU_MODES 6 2074433bf0SRichard Henderson #else 2174433bf0SRichard Henderson # define TARGET_LONG_BITS 32 2274433bf0SRichard Henderson # define TARGET_PAGE_BITS 12 /* 4k */ 2374433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 36 2474433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 2574433bf0SRichard Henderson # define NB_MMU_MODES 3 2674433bf0SRichard Henderson #endif 2774433bf0SRichard Henderson 2874433bf0SRichard Henderson #endif 29