1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "exec/translation-block.h" 29 #include "fpu/softfloat-helpers.h" 30 #include "tcg/tcg.h" 31 32 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 SuperHCPU *cpu = SUPERH_CPU(cs); 35 36 cpu->env.pc = value; 37 } 38 39 static vaddr superh_cpu_get_pc(CPUState *cs) 40 { 41 SuperHCPU *cpu = SUPERH_CPU(cs); 42 43 return cpu->env.pc; 44 } 45 46 static void superh_cpu_synchronize_from_tb(CPUState *cs, 47 const TranslationBlock *tb) 48 { 49 SuperHCPU *cpu = SUPERH_CPU(cs); 50 51 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 52 cpu->env.pc = tb->pc; 53 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 54 } 55 56 static void superh_restore_state_to_opc(CPUState *cs, 57 const TranslationBlock *tb, 58 const uint64_t *data) 59 { 60 SuperHCPU *cpu = SUPERH_CPU(cs); 61 62 cpu->env.pc = data[0]; 63 cpu->env.flags = data[1]; 64 /* 65 * Theoretically delayed_pc should also be restored. In practice the 66 * branch instruction is re-executed after exception, so the delayed 67 * branch target will be recomputed. 68 */ 69 } 70 71 #ifndef CONFIG_USER_ONLY 72 static bool superh_io_recompile_replay_branch(CPUState *cs, 73 const TranslationBlock *tb) 74 { 75 CPUSH4State *env = cpu_env(cs); 76 77 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 78 && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) { 79 env->pc -= 2; 80 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 81 return true; 82 } 83 return false; 84 } 85 #endif 86 87 static bool superh_cpu_has_work(CPUState *cs) 88 { 89 return cs->interrupt_request & CPU_INTERRUPT_HARD; 90 } 91 92 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) 93 { 94 CPUSH4State *env = cpu_env(cs); 95 96 /* 97 * The instruction in a RTE delay slot is fetched in privileged mode, 98 * but executed in user mode. 99 */ 100 if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { 101 return 0; 102 } else { 103 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; 104 } 105 } 106 107 static void superh_cpu_reset_hold(Object *obj, ResetType type) 108 { 109 CPUState *cs = CPU(obj); 110 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj); 111 CPUSH4State *env = cpu_env(cs); 112 113 if (scc->parent_phases.hold) { 114 scc->parent_phases.hold(obj, type); 115 } 116 117 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 118 119 env->pc = 0xA0000000; 120 #if defined(CONFIG_USER_ONLY) 121 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 122 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 123 #else 124 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 125 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 126 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 127 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 128 set_flush_to_zero(1, &env->fp_status); 129 #endif 130 set_default_nan_mode(1, &env->fp_status); 131 /* sign bit clear, set all frac bits other than msb */ 132 set_float_default_nan_pattern(0b00111111, &env->fp_status); 133 } 134 135 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 136 { 137 info->mach = bfd_mach_sh4; 138 info->print_insn = print_insn_sh; 139 } 140 141 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 142 { 143 ObjectClass *oc; 144 char *s, *typename = NULL; 145 146 s = g_ascii_strdown(cpu_model, -1); 147 if (strcmp(s, "any") == 0) { 148 oc = object_class_by_name(TYPE_SH7750R_CPU); 149 goto out; 150 } 151 152 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 153 oc = object_class_by_name(typename); 154 155 out: 156 g_free(s); 157 g_free(typename); 158 return oc; 159 } 160 161 static void sh7750r_cpu_initfn(Object *obj) 162 { 163 CPUSH4State *env = cpu_env(CPU(obj)); 164 165 env->id = SH_CPU_SH7750R; 166 env->features = SH_FEATURE_BCR3_AND_BCR4; 167 } 168 169 static void sh7750r_class_init(ObjectClass *oc, void *data) 170 { 171 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 172 173 scc->pvr = 0x00050000; 174 scc->prr = 0x00000100; 175 scc->cvr = 0x00110000; 176 } 177 178 static void sh7751r_cpu_initfn(Object *obj) 179 { 180 CPUSH4State *env = cpu_env(CPU(obj)); 181 182 env->id = SH_CPU_SH7751R; 183 env->features = SH_FEATURE_BCR3_AND_BCR4; 184 } 185 186 static void sh7751r_class_init(ObjectClass *oc, void *data) 187 { 188 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 189 190 scc->pvr = 0x04050005; 191 scc->prr = 0x00000113; 192 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 193 } 194 195 static void sh7785_cpu_initfn(Object *obj) 196 { 197 CPUSH4State *env = cpu_env(CPU(obj)); 198 199 env->id = SH_CPU_SH7785; 200 env->features = SH_FEATURE_SH4A; 201 } 202 203 static void sh7785_class_init(ObjectClass *oc, void *data) 204 { 205 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 206 207 scc->pvr = 0x10300700; 208 scc->prr = 0x00000200; 209 scc->cvr = 0x71440211; 210 } 211 212 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 213 { 214 CPUState *cs = CPU(dev); 215 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 216 Error *local_err = NULL; 217 218 cpu_exec_realizefn(cs, &local_err); 219 if (local_err != NULL) { 220 error_propagate(errp, local_err); 221 return; 222 } 223 224 cpu_reset(cs); 225 qemu_init_vcpu(cs); 226 227 scc->parent_realize(dev, errp); 228 } 229 230 static void superh_cpu_initfn(Object *obj) 231 { 232 CPUSH4State *env = cpu_env(CPU(obj)); 233 234 env->movcal_backup_tail = &(env->movcal_backup); 235 } 236 237 #ifndef CONFIG_USER_ONLY 238 static const VMStateDescription vmstate_sh_cpu = { 239 .name = "cpu", 240 .unmigratable = 1, 241 }; 242 243 #include "hw/core/sysemu-cpu-ops.h" 244 245 static const struct SysemuCPUOps sh4_sysemu_ops = { 246 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 247 }; 248 #endif 249 250 #include "hw/core/tcg-cpu-ops.h" 251 252 static const TCGCPUOps superh_tcg_ops = { 253 .initialize = sh4_translate_init, 254 .translate_code = sh4_translate_code, 255 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 256 .restore_state_to_opc = superh_restore_state_to_opc, 257 258 #ifndef CONFIG_USER_ONLY 259 .tlb_fill = superh_cpu_tlb_fill, 260 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 261 .cpu_exec_halt = superh_cpu_has_work, 262 .do_interrupt = superh_cpu_do_interrupt, 263 .do_unaligned_access = superh_cpu_do_unaligned_access, 264 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 265 #endif /* !CONFIG_USER_ONLY */ 266 }; 267 268 static void superh_cpu_class_init(ObjectClass *oc, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(oc); 271 CPUClass *cc = CPU_CLASS(oc); 272 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 273 ResettableClass *rc = RESETTABLE_CLASS(oc); 274 275 device_class_set_parent_realize(dc, superh_cpu_realizefn, 276 &scc->parent_realize); 277 278 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, 279 &scc->parent_phases); 280 281 cc->class_by_name = superh_cpu_class_by_name; 282 cc->has_work = superh_cpu_has_work; 283 cc->mmu_index = sh4_cpu_mmu_index; 284 cc->dump_state = superh_cpu_dump_state; 285 cc->set_pc = superh_cpu_set_pc; 286 cc->get_pc = superh_cpu_get_pc; 287 cc->gdb_read_register = superh_cpu_gdb_read_register; 288 cc->gdb_write_register = superh_cpu_gdb_write_register; 289 #ifndef CONFIG_USER_ONLY 290 cc->sysemu_ops = &sh4_sysemu_ops; 291 dc->vmsd = &vmstate_sh_cpu; 292 #endif 293 cc->disas_set_info = superh_cpu_disas_set_info; 294 295 cc->gdb_num_core_regs = 59; 296 cc->tcg_ops = &superh_tcg_ops; 297 } 298 299 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 300 { \ 301 .name = type_name, \ 302 .parent = TYPE_SUPERH_CPU, \ 303 .class_init = cinit, \ 304 .instance_init = initfn, \ 305 } 306 static const TypeInfo superh_cpu_type_infos[] = { 307 { 308 .name = TYPE_SUPERH_CPU, 309 .parent = TYPE_CPU, 310 .instance_size = sizeof(SuperHCPU), 311 .instance_align = __alignof(SuperHCPU), 312 .instance_init = superh_cpu_initfn, 313 .abstract = true, 314 .class_size = sizeof(SuperHCPUClass), 315 .class_init = superh_cpu_class_init, 316 }, 317 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 318 sh7750r_cpu_initfn), 319 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 320 sh7751r_cpu_initfn), 321 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 322 sh7785_cpu_initfn), 323 324 }; 325 326 DEFINE_TYPES(superh_cpu_type_infos) 327