1 /* 2 * S390x MMU related functions 3 * 4 * Copyright (c) 2011 Alexander Graf 5 * Copyright (c) 2015 Thomas Huth, IBM Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/error-report.h" 20 #include "system/address-spaces.h" 21 #include "cpu.h" 22 #include "s390x-internal.h" 23 #include "kvm/kvm_s390x.h" 24 #include "system/kvm.h" 25 #include "system/tcg.h" 26 #include "exec/exec-all.h" 27 #include "exec/page-protection.h" 28 #include "exec/target_page.h" 29 #include "hw/hw.h" 30 #include "hw/s390x/storage-keys.h" 31 #include "hw/boards.h" 32 33 /* Fetch/store bits in the translation exception code: */ 34 #define FS_READ 0x800 35 #define FS_WRITE 0x400 36 37 static void trigger_access_exception(CPUS390XState *env, uint32_t type, 38 uint64_t tec) 39 { 40 S390CPU *cpu = env_archcpu(env); 41 42 if (kvm_enabled()) { 43 kvm_s390_access_exception(cpu, type, tec); 44 } else { 45 CPUState *cs = env_cpu(env); 46 if (type != PGM_ADDRESSING) { 47 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); 48 } 49 trigger_pgm_exception(env, type); 50 } 51 } 52 53 /* check whether the address would be proteted by Low-Address Protection */ 54 static bool is_low_address(uint64_t addr) 55 { 56 return addr <= 511 || (addr >= 4096 && addr <= 4607); 57 } 58 59 /* check whether Low-Address Protection is enabled for mmu_translate() */ 60 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc) 61 { 62 if (!(env->cregs[0] & CR0_LOWPROT)) { 63 return false; 64 } 65 if (!(env->psw.mask & PSW_MASK_DAT)) { 66 return true; 67 } 68 69 /* Check the private-space control bit */ 70 switch (asc) { 71 case PSW_ASC_PRIMARY: 72 return !(env->cregs[1] & ASCE_PRIVATE_SPACE); 73 case PSW_ASC_SECONDARY: 74 return !(env->cregs[7] & ASCE_PRIVATE_SPACE); 75 case PSW_ASC_HOME: 76 return !(env->cregs[13] & ASCE_PRIVATE_SPACE); 77 default: 78 /* We don't support access register mode */ 79 error_report("unsupported addressing mode"); 80 exit(1); 81 } 82 } 83 84 /** 85 * Translate real address to absolute (= physical) 86 * address by taking care of the prefix mapping. 87 */ 88 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr) 89 { 90 if (raddr < 0x2000) { 91 return raddr + env->psa; /* Map the lowcore. */ 92 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) { 93 return raddr - env->psa; /* Map the 0 page. */ 94 } 95 return raddr; 96 } 97 98 bool mmu_absolute_addr_valid(target_ulong addr, bool is_write) 99 { 100 return address_space_access_valid(&address_space_memory, 101 addr & TARGET_PAGE_MASK, 102 TARGET_PAGE_SIZE, is_write, 103 MEMTXATTRS_UNSPECIFIED); 104 } 105 106 static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, 107 uint64_t *entry) 108 { 109 CPUState *cs = env_cpu(env); 110 111 /* 112 * According to the PoP, these table addresses are "unpredictably real 113 * or absolute". Also, "it is unpredictable whether the address wraps 114 * or an addressing exception is recognized". 115 * 116 * We treat them as absolute addresses and don't wrap them. 117 */ 118 if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, 119 entry, sizeof(*entry)) != 120 MEMTX_OK)) { 121 return false; 122 } 123 *entry = be64_to_cpu(*entry); 124 return true; 125 } 126 127 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, 128 uint64_t asc, uint64_t asce, target_ulong *raddr, 129 int *flags) 130 { 131 const bool edat1 = (env->cregs[0] & CR0_EDAT) && 132 s390_has_feat(S390_FEAT_EDAT); 133 const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2); 134 const bool iep = (env->cregs[0] & CR0_IEP) && 135 s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT); 136 const int asce_tl = asce & ASCE_TABLE_LENGTH; 137 const int asce_p = asce & ASCE_PRIVATE_SPACE; 138 hwaddr gaddr = asce & ASCE_ORIGIN; 139 uint64_t entry; 140 141 if (asce & ASCE_REAL_SPACE) { 142 /* direct mapping */ 143 *raddr = vaddr; 144 return 0; 145 } 146 147 switch (asce & ASCE_TYPE_MASK) { 148 case ASCE_TYPE_REGION1: 149 if (VADDR_REGION1_TL(vaddr) > asce_tl) { 150 return PGM_REG_FIRST_TRANS; 151 } 152 gaddr += VADDR_REGION1_TX(vaddr) * 8; 153 break; 154 case ASCE_TYPE_REGION2: 155 if (VADDR_REGION1_TX(vaddr)) { 156 return PGM_ASCE_TYPE; 157 } 158 if (VADDR_REGION2_TL(vaddr) > asce_tl) { 159 return PGM_REG_SEC_TRANS; 160 } 161 gaddr += VADDR_REGION2_TX(vaddr) * 8; 162 break; 163 case ASCE_TYPE_REGION3: 164 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) { 165 return PGM_ASCE_TYPE; 166 } 167 if (VADDR_REGION3_TL(vaddr) > asce_tl) { 168 return PGM_REG_THIRD_TRANS; 169 } 170 gaddr += VADDR_REGION3_TX(vaddr) * 8; 171 break; 172 case ASCE_TYPE_SEGMENT: 173 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) || 174 VADDR_REGION3_TX(vaddr)) { 175 return PGM_ASCE_TYPE; 176 } 177 if (VADDR_SEGMENT_TL(vaddr) > asce_tl) { 178 return PGM_SEGMENT_TRANS; 179 } 180 gaddr += VADDR_SEGMENT_TX(vaddr) * 8; 181 break; 182 } 183 184 switch (asce & ASCE_TYPE_MASK) { 185 case ASCE_TYPE_REGION1: 186 if (!read_table_entry(env, gaddr, &entry)) { 187 return PGM_ADDRESSING; 188 } 189 if (entry & REGION_ENTRY_I) { 190 return PGM_REG_FIRST_TRANS; 191 } 192 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) { 193 return PGM_TRANS_SPEC; 194 } 195 if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 196 VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 197 return PGM_REG_SEC_TRANS; 198 } 199 if (edat1 && (entry & REGION_ENTRY_P)) { 200 *flags &= ~PAGE_WRITE; 201 } 202 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8; 203 /* fall through */ 204 case ASCE_TYPE_REGION2: 205 if (!read_table_entry(env, gaddr, &entry)) { 206 return PGM_ADDRESSING; 207 } 208 if (entry & REGION_ENTRY_I) { 209 return PGM_REG_SEC_TRANS; 210 } 211 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) { 212 return PGM_TRANS_SPEC; 213 } 214 if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 215 VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 216 return PGM_REG_THIRD_TRANS; 217 } 218 if (edat1 && (entry & REGION_ENTRY_P)) { 219 *flags &= ~PAGE_WRITE; 220 } 221 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8; 222 /* fall through */ 223 case ASCE_TYPE_REGION3: 224 if (!read_table_entry(env, gaddr, &entry)) { 225 return PGM_ADDRESSING; 226 } 227 if (entry & REGION_ENTRY_I) { 228 return PGM_REG_THIRD_TRANS; 229 } 230 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) { 231 return PGM_TRANS_SPEC; 232 } 233 if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) { 234 return PGM_TRANS_SPEC; 235 } 236 if (edat1 && (entry & REGION_ENTRY_P)) { 237 *flags &= ~PAGE_WRITE; 238 } 239 if (edat2 && (entry & REGION3_ENTRY_FC)) { 240 if (iep && (entry & REGION3_ENTRY_IEP)) { 241 *flags &= ~PAGE_EXEC; 242 } 243 *raddr = (entry & REGION3_ENTRY_RFAA) | 244 (vaddr & ~REGION3_ENTRY_RFAA); 245 return 0; 246 } 247 if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 248 VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 249 return PGM_SEGMENT_TRANS; 250 } 251 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8; 252 /* fall through */ 253 case ASCE_TYPE_SEGMENT: 254 if (!read_table_entry(env, gaddr, &entry)) { 255 return PGM_ADDRESSING; 256 } 257 if (entry & SEGMENT_ENTRY_I) { 258 return PGM_SEGMENT_TRANS; 259 } 260 if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) { 261 return PGM_TRANS_SPEC; 262 } 263 if ((entry & SEGMENT_ENTRY_CS) && asce_p) { 264 return PGM_TRANS_SPEC; 265 } 266 if (entry & SEGMENT_ENTRY_P) { 267 *flags &= ~PAGE_WRITE; 268 } 269 if (edat1 && (entry & SEGMENT_ENTRY_FC)) { 270 if (iep && (entry & SEGMENT_ENTRY_IEP)) { 271 *flags &= ~PAGE_EXEC; 272 } 273 *raddr = (entry & SEGMENT_ENTRY_SFAA) | 274 (vaddr & ~SEGMENT_ENTRY_SFAA); 275 return 0; 276 } 277 gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8; 278 break; 279 } 280 281 if (!read_table_entry(env, gaddr, &entry)) { 282 return PGM_ADDRESSING; 283 } 284 if (entry & PAGE_ENTRY_I) { 285 return PGM_PAGE_TRANS; 286 } 287 if (entry & PAGE_ENTRY_0) { 288 return PGM_TRANS_SPEC; 289 } 290 if (entry & PAGE_ENTRY_P) { 291 *flags &= ~PAGE_WRITE; 292 } 293 if (iep && (entry & PAGE_ENTRY_IEP)) { 294 *flags &= ~PAGE_EXEC; 295 } 296 297 *raddr = entry & TARGET_PAGE_MASK; 298 return 0; 299 } 300 301 static void mmu_handle_skey(target_ulong addr, int rw, int *flags) 302 { 303 static S390SKeysClass *skeyclass; 304 static S390SKeysState *ss; 305 uint8_t key, old_key; 306 307 /* 308 * We expect to be called with an absolute address that has already been 309 * validated, such that we can reliably use it to lookup the storage key. 310 */ 311 if (unlikely(!ss)) { 312 ss = s390_get_skeys_device(); 313 skeyclass = S390_SKEYS_GET_CLASS(ss); 314 } 315 316 /* 317 * Don't enable storage keys if they are still disabled, i.e., no actual 318 * storage key instruction was issued yet. 319 */ 320 if (!skeyclass->skeys_are_enabled(ss)) { 321 return; 322 } 323 324 /* 325 * Whenever we create a new TLB entry, we set the storage key reference 326 * bit. In case we allow write accesses, we set the storage key change 327 * bit. Whenever the guest changes the storage key, we have to flush the 328 * TLBs of all CPUs (the whole TLB or all affected entries), so that the 329 * next reference/change will result in an MMU fault and make us properly 330 * update the storage key here. 331 * 332 * Note 1: "record of references ... is not necessarily accurate", 333 * "change bit may be set in case no storing has occurred". 334 * -> We can set reference/change bits even on exceptions. 335 * Note 2: certain accesses seem to ignore storage keys. For example, 336 * DAT translation does not set reference bits for table accesses. 337 * 338 * TODO: key-controlled protection. Only CPU accesses make use of the 339 * PSW key. CSS accesses are different - we have to pass in the key. 340 * 341 * TODO: we have races between getting and setting the key. 342 */ 343 if (s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key)) { 344 return; 345 } 346 old_key = key; 347 348 switch (rw) { 349 case MMU_DATA_LOAD: 350 case MMU_INST_FETCH: 351 /* 352 * The TLB entry has to remain write-protected on read-faults if 353 * the storage key does not indicate a change already. Otherwise 354 * we might miss setting the change bit on write accesses. 355 */ 356 if (!(key & SK_C)) { 357 *flags &= ~PAGE_WRITE; 358 } 359 break; 360 case MMU_DATA_STORE: 361 key |= SK_C; 362 break; 363 default: 364 g_assert_not_reached(); 365 } 366 367 /* Any store/fetch sets the reference bit */ 368 key |= SK_R; 369 370 if (key != old_key) { 371 s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key); 372 } 373 } 374 375 /** 376 * Translate a virtual (logical) address into a physical (absolute) address. 377 * @param vaddr the virtual address 378 * @param rw 0 = read, 1 = write, 2 = code fetch, < 0 = load real address 379 * @param asc address space control (one of the PSW_ASC_* modes) 380 * @param raddr the translated address is stored to this pointer 381 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 382 * @param tec the translation exception code if stored to this pointer if 383 * there is an exception to raise 384 * @return 0 = success, != 0, the exception to raise 385 */ 386 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, 387 target_ulong *raddr, int *flags, uint64_t *tec) 388 { 389 uint64_t asce; 390 int r; 391 392 *tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) | 393 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ); 394 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 395 396 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) { 397 /* 398 * If any part of this page is currently protected, make sure the 399 * TLB entry will not be reused. 400 * 401 * As the protected range is always the first 512 bytes of the 402 * two first pages, we are able to catch all writes to these areas 403 * just by looking at the start address (triggering the tlb miss). 404 */ 405 *flags |= PAGE_WRITE_INV; 406 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { 407 /* LAP sets bit 56 */ 408 *tec |= 0x80; 409 return PGM_PROTECTION; 410 } 411 } 412 413 vaddr &= TARGET_PAGE_MASK; 414 415 if (rw != MMU_S390_LRA && !(env->psw.mask & PSW_MASK_DAT)) { 416 *raddr = vaddr; 417 goto nodat; 418 } 419 420 switch (asc) { 421 case PSW_ASC_PRIMARY: 422 asce = env->cregs[1]; 423 break; 424 case PSW_ASC_HOME: 425 asce = env->cregs[13]; 426 break; 427 case PSW_ASC_SECONDARY: 428 asce = env->cregs[7]; 429 break; 430 case PSW_ASC_ACCREG: 431 default: 432 hw_error("guest switched to unknown asc mode\n"); 433 break; 434 } 435 436 /* perform the DAT translation */ 437 r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags); 438 if (unlikely(r)) { 439 return r; 440 } 441 442 /* check for DAT protection */ 443 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) { 444 /* DAT sets bit 61 only */ 445 *tec |= 0x4; 446 return PGM_PROTECTION; 447 } 448 449 /* check for Instruction-Execution-Protection */ 450 if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) { 451 /* IEP sets bit 56 and 61 */ 452 *tec |= 0x84; 453 return PGM_PROTECTION; 454 } 455 456 nodat: 457 if (rw >= 0) { 458 /* Convert real address -> absolute address */ 459 *raddr = mmu_real2abs(env, *raddr); 460 461 if (!mmu_absolute_addr_valid(*raddr, rw == MMU_DATA_STORE)) { 462 *tec = 0; /* unused */ 463 return PGM_ADDRESSING; 464 } 465 466 mmu_handle_skey(*raddr, rw, flags); 467 } 468 return 0; 469 } 470 471 /** 472 * translate_pages: Translate a set of consecutive logical page addresses 473 * to absolute addresses. This function is used for TCG and old KVM without 474 * the MEMOP interface. 475 */ 476 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, 477 target_ulong *pages, bool is_write, uint64_t *tec) 478 { 479 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC; 480 CPUS390XState *env = &cpu->env; 481 int ret, i, pflags; 482 483 for (i = 0; i < nr_pages; i++) { 484 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, tec); 485 if (ret) { 486 return ret; 487 } 488 addr += TARGET_PAGE_SIZE; 489 } 490 491 return 0; 492 } 493 494 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 495 int len, bool is_write) 496 { 497 int ret; 498 499 if (kvm_enabled()) { 500 ret = kvm_s390_mem_op_pv(cpu, offset, hostbuf, len, is_write); 501 } else { 502 /* Protected Virtualization is a KVM/Hardware only feature */ 503 g_assert_not_reached(); 504 } 505 return ret; 506 } 507 508 /** 509 * s390_cpu_virt_mem_rw: 510 * @laddr: the logical start address 511 * @ar: the access register number 512 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying 513 * @len: length that should be transferred 514 * @is_write: true = write, false = read 515 * Returns: 0 on success, non-zero if an exception occurred 516 * 517 * Copy from/to guest memory using logical addresses. Note that we inject a 518 * program interrupt in case there is an error while accessing the memory. 519 * 520 * This function will always return (also for TCG), make sure to call 521 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop. 522 */ 523 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 524 int len, bool is_write) 525 { 526 int currlen, nr_pages, i; 527 target_ulong *pages; 528 uint64_t tec; 529 int ret; 530 531 if (kvm_enabled()) { 532 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write); 533 if (ret >= 0) { 534 return ret; 535 } 536 } 537 538 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS) 539 + 1; 540 pages = g_malloc(nr_pages * sizeof(*pages)); 541 542 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write, &tec); 543 if (ret) { 544 trigger_access_exception(&cpu->env, ret, tec); 545 } else if (hostbuf != NULL) { 546 /* Copy data by stepping through the area page by page */ 547 for (i = 0; i < nr_pages; i++) { 548 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE)); 549 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK), 550 hostbuf, currlen, is_write); 551 laddr += currlen; 552 hostbuf += currlen; 553 len -= currlen; 554 } 555 } 556 557 g_free(pages); 558 return ret; 559 } 560 561 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra) 562 { 563 /* KVM will handle the interrupt automatically, TCG has to exit the TB */ 564 #ifdef CONFIG_TCG 565 if (tcg_enabled()) { 566 cpu_loop_exit_restore(CPU(cpu), ra); 567 } 568 #endif 569 } 570 571 /** 572 * Translate a real address into a physical (absolute) address. 573 * @param raddr the real address 574 * @param rw 0 = read, 1 = write, 2 = code fetch 575 * @param addr the translated address is stored to this pointer 576 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 577 * @return 0 = success, != 0, the exception to raise 578 */ 579 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, 580 target_ulong *addr, int *flags, uint64_t *tec) 581 { 582 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT; 583 584 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 585 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) { 586 /* see comment in mmu_translate() how this works */ 587 *flags |= PAGE_WRITE_INV; 588 if (is_low_address(raddr) && rw == MMU_DATA_STORE) { 589 /* LAP sets bit 56 */ 590 *tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80; 591 return PGM_PROTECTION; 592 } 593 } 594 595 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK); 596 597 if (!mmu_absolute_addr_valid(*addr, rw == MMU_DATA_STORE)) { 598 /* unused */ 599 *tec = 0; 600 return PGM_ADDRESSING; 601 } 602 603 mmu_handle_skey(*addr, rw, flags); 604 return 0; 605 } 606