1e5918d7dSYoshinori Sato /* 2e5918d7dSYoshinori Sato * RX translation 3e5918d7dSYoshinori Sato * 4e5918d7dSYoshinori Sato * Copyright (c) 2019 Yoshinori Sato 5e5918d7dSYoshinori Sato * 6e5918d7dSYoshinori Sato * This program is free software; you can redistribute it and/or modify it 7e5918d7dSYoshinori Sato * under the terms and conditions of the GNU General Public License, 8e5918d7dSYoshinori Sato * version 2 or later, as published by the Free Software Foundation. 9e5918d7dSYoshinori Sato * 10e5918d7dSYoshinori Sato * This program is distributed in the hope it will be useful, but WITHOUT 11e5918d7dSYoshinori Sato * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12e5918d7dSYoshinori Sato * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13e5918d7dSYoshinori Sato * more details. 14e5918d7dSYoshinori Sato * 15e5918d7dSYoshinori Sato * You should have received a copy of the GNU General Public License along with 16e5918d7dSYoshinori Sato * this program. If not, see <http://www.gnu.org/licenses/>. 17e5918d7dSYoshinori Sato */ 18e5918d7dSYoshinori Sato 19e5918d7dSYoshinori Sato #include "qemu/osdep.h" 20e5918d7dSYoshinori Sato #include "qemu/bswap.h" 21e5918d7dSYoshinori Sato #include "qemu/qemu-print.h" 22e5918d7dSYoshinori Sato #include "cpu.h" 23e5918d7dSYoshinori Sato #include "exec/exec-all.h" 24e5918d7dSYoshinori Sato #include "tcg/tcg-op.h" 25e5918d7dSYoshinori Sato #include "exec/helper-proto.h" 26e5918d7dSYoshinori Sato #include "exec/helper-gen.h" 27e5918d7dSYoshinori Sato #include "exec/translator.h" 28e5918d7dSYoshinori Sato #include "exec/log.h" 29e5918d7dSYoshinori Sato 30d53106c9SRichard Henderson #define HELPER_H "helper.h" 31d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 32d53106c9SRichard Henderson #undef HELPER_H 33d53106c9SRichard Henderson 34d53106c9SRichard Henderson 35e5918d7dSYoshinori Sato typedef struct DisasContext { 36e5918d7dSYoshinori Sato DisasContextBase base; 37e5918d7dSYoshinori Sato CPURXState *env; 38e5918d7dSYoshinori Sato uint32_t pc; 394341631eSRichard Henderson uint32_t tb_flags; 40e5918d7dSYoshinori Sato } DisasContext; 41e5918d7dSYoshinori Sato 42e5918d7dSYoshinori Sato typedef struct DisasCompare { 43e5918d7dSYoshinori Sato TCGv value; 44e5918d7dSYoshinori Sato TCGv temp; 45e5918d7dSYoshinori Sato TCGCond cond; 46e5918d7dSYoshinori Sato } DisasCompare; 47e5918d7dSYoshinori Sato 4827a4a30eSYoshinori Sato const char *rx_crname(uint8_t cr) 4927a4a30eSYoshinori Sato { 5027a4a30eSYoshinori Sato static const char *cr_names[] = { 51e5918d7dSYoshinori Sato "psw", "pc", "usp", "fpsw", "", "", "", "", 5227a4a30eSYoshinori Sato "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 53e5918d7dSYoshinori Sato }; 5427a4a30eSYoshinori Sato if (cr >= ARRAY_SIZE(cr_names)) { 5527a4a30eSYoshinori Sato return "illegal"; 5627a4a30eSYoshinori Sato } 5727a4a30eSYoshinori Sato return cr_names[cr]; 5827a4a30eSYoshinori Sato } 59e5918d7dSYoshinori Sato 60e5918d7dSYoshinori Sato /* Target-specific values for dc->base.is_jmp. */ 61e5918d7dSYoshinori Sato #define DISAS_JUMP DISAS_TARGET_0 62e5918d7dSYoshinori Sato #define DISAS_UPDATE DISAS_TARGET_1 63e5918d7dSYoshinori Sato #define DISAS_EXIT DISAS_TARGET_2 64e5918d7dSYoshinori Sato 65e5918d7dSYoshinori Sato /* global register indexes */ 66e5918d7dSYoshinori Sato static TCGv cpu_regs[16]; 67e5918d7dSYoshinori Sato static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 68e5918d7dSYoshinori Sato static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 69e5918d7dSYoshinori Sato static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 70e5918d7dSYoshinori Sato static TCGv cpu_fintv, cpu_intb, cpu_pc; 71e5918d7dSYoshinori Sato static TCGv_i64 cpu_acc; 72e5918d7dSYoshinori Sato 73e5918d7dSYoshinori Sato #define cpu_sp cpu_regs[0] 74e5918d7dSYoshinori Sato 75e5918d7dSYoshinori Sato /* decoder helper */ 76e5918d7dSYoshinori Sato static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 77e5918d7dSYoshinori Sato int i, int n) 78e5918d7dSYoshinori Sato { 79e5918d7dSYoshinori Sato while (++i <= n) { 80104cf552SRichard Henderson uint8_t b = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next++); 81e5918d7dSYoshinori Sato insn |= b << (32 - i * 8); 82e5918d7dSYoshinori Sato } 83e5918d7dSYoshinori Sato return insn; 84e5918d7dSYoshinori Sato } 85e5918d7dSYoshinori Sato 86e5918d7dSYoshinori Sato static uint32_t li(DisasContext *ctx, int sz) 87e5918d7dSYoshinori Sato { 88*83340193SRichard Henderson target_ulong addr; 89*83340193SRichard Henderson uint32_t tmp; 90e5918d7dSYoshinori Sato CPURXState *env = ctx->env; 91e5918d7dSYoshinori Sato addr = ctx->base.pc_next; 92e5918d7dSYoshinori Sato 93e5918d7dSYoshinori Sato switch (sz) { 94e5918d7dSYoshinori Sato case 1: 95e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 96104cf552SRichard Henderson return (int8_t)translator_ldub(env, &ctx->base, addr); 97e5918d7dSYoshinori Sato case 2: 98e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 99104cf552SRichard Henderson return (int16_t)translator_lduw(env, &ctx->base, addr); 100e5918d7dSYoshinori Sato case 3: 101e5918d7dSYoshinori Sato ctx->base.pc_next += 3; 102104cf552SRichard Henderson tmp = (int8_t)translator_ldub(env, &ctx->base, addr + 2); 103104cf552SRichard Henderson tmp <<= 16; 104104cf552SRichard Henderson tmp |= translator_lduw(env, &ctx->base, addr); 105e5918d7dSYoshinori Sato return tmp; 106e5918d7dSYoshinori Sato case 0: 107e5918d7dSYoshinori Sato ctx->base.pc_next += 4; 108104cf552SRichard Henderson return translator_ldl(env, &ctx->base, addr); 109104cf552SRichard Henderson default: 110104cf552SRichard Henderson g_assert_not_reached(); 111e5918d7dSYoshinori Sato } 112e5918d7dSYoshinori Sato return 0; 113e5918d7dSYoshinori Sato } 114e5918d7dSYoshinori Sato 115e5918d7dSYoshinori Sato static int bdsp_s(DisasContext *ctx, int d) 116e5918d7dSYoshinori Sato { 117e5918d7dSYoshinori Sato /* 118e5918d7dSYoshinori Sato * 0 -> 8 119e5918d7dSYoshinori Sato * 1 -> 9 120e5918d7dSYoshinori Sato * 2 -> 10 121e5918d7dSYoshinori Sato * 3 -> 3 122e5918d7dSYoshinori Sato * : 123e5918d7dSYoshinori Sato * 7 -> 7 124e5918d7dSYoshinori Sato */ 125e5918d7dSYoshinori Sato if (d < 3) { 126e5918d7dSYoshinori Sato d += 8; 127e5918d7dSYoshinori Sato } 128e5918d7dSYoshinori Sato return d; 129e5918d7dSYoshinori Sato } 130e5918d7dSYoshinori Sato 131e5918d7dSYoshinori Sato /* Include the auto-generated decoder. */ 132abff1abfSPaolo Bonzini #include "decode-insns.c.inc" 133e5918d7dSYoshinori Sato 134e5918d7dSYoshinori Sato void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 135e5918d7dSYoshinori Sato { 136f2a4459dSPhilippe Mathieu-Daudé CPURXState *env = cpu_env(cs); 137e5918d7dSYoshinori Sato int i; 138e5918d7dSYoshinori Sato uint32_t psw; 139e5918d7dSYoshinori Sato 140e5918d7dSYoshinori Sato psw = rx_cpu_pack_psw(env); 141e5918d7dSYoshinori Sato qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 142e5918d7dSYoshinori Sato env->pc, psw); 143e5918d7dSYoshinori Sato for (i = 0; i < 16; i += 4) { 144e5918d7dSYoshinori Sato qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 145e5918d7dSYoshinori Sato i, env->regs[i], i + 1, env->regs[i + 1], 146e5918d7dSYoshinori Sato i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 147e5918d7dSYoshinori Sato } 148e5918d7dSYoshinori Sato } 149e5918d7dSYoshinori Sato 150e5918d7dSYoshinori Sato static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 151e5918d7dSYoshinori Sato { 152f3f713ccSRichard Henderson if (translator_use_goto_tb(&dc->base, dest)) { 153e5918d7dSYoshinori Sato tcg_gen_goto_tb(n); 154e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 155e5918d7dSYoshinori Sato tcg_gen_exit_tb(dc->base.tb, n); 156e5918d7dSYoshinori Sato } else { 157e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 158e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 159e5918d7dSYoshinori Sato } 160e5918d7dSYoshinori Sato dc->base.is_jmp = DISAS_NORETURN; 161e5918d7dSYoshinori Sato } 162e5918d7dSYoshinori Sato 163e5918d7dSYoshinori Sato /* generic load wrapper */ 164e5918d7dSYoshinori Sato static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 165e5918d7dSYoshinori Sato { 166e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 167e5918d7dSYoshinori Sato } 168e5918d7dSYoshinori Sato 169e5918d7dSYoshinori Sato /* unsigned load wrapper */ 170e5918d7dSYoshinori Sato static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 171e5918d7dSYoshinori Sato { 172e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 173e5918d7dSYoshinori Sato } 174e5918d7dSYoshinori Sato 175e5918d7dSYoshinori Sato /* generic store wrapper */ 176e5918d7dSYoshinori Sato static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 177e5918d7dSYoshinori Sato { 178e5918d7dSYoshinori Sato tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 179e5918d7dSYoshinori Sato } 180e5918d7dSYoshinori Sato 181e5918d7dSYoshinori Sato /* [ri, rb] */ 182e5918d7dSYoshinori Sato static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 183e5918d7dSYoshinori Sato int size, int ri, int rb) 184e5918d7dSYoshinori Sato { 185e5918d7dSYoshinori Sato tcg_gen_shli_i32(mem, cpu_regs[ri], size); 186e5918d7dSYoshinori Sato tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 187e5918d7dSYoshinori Sato } 188e5918d7dSYoshinori Sato 189e5918d7dSYoshinori Sato /* dsp[reg] */ 190e5918d7dSYoshinori Sato static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 191e5918d7dSYoshinori Sato int ld, int size, int reg) 192e5918d7dSYoshinori Sato { 193e5918d7dSYoshinori Sato uint32_t dsp; 194e5918d7dSYoshinori Sato 195e5918d7dSYoshinori Sato switch (ld) { 196e5918d7dSYoshinori Sato case 0: 197e5918d7dSYoshinori Sato return cpu_regs[reg]; 198e5918d7dSYoshinori Sato case 1: 199104cf552SRichard Henderson dsp = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next) << size; 200e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 201e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 202e5918d7dSYoshinori Sato return mem; 203e5918d7dSYoshinori Sato case 2: 204104cf552SRichard Henderson dsp = translator_lduw(ctx->env, &ctx->base, ctx->base.pc_next) << size; 205e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 206e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 207e5918d7dSYoshinori Sato return mem; 208104cf552SRichard Henderson default: 209104cf552SRichard Henderson g_assert_not_reached(); 210e5918d7dSYoshinori Sato } 211e5918d7dSYoshinori Sato } 212e5918d7dSYoshinori Sato 213e5918d7dSYoshinori Sato static inline MemOp mi_to_mop(unsigned mi) 214e5918d7dSYoshinori Sato { 215e5918d7dSYoshinori Sato static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 216e5918d7dSYoshinori Sato tcg_debug_assert(mi < 5); 217e5918d7dSYoshinori Sato return mop[mi]; 218e5918d7dSYoshinori Sato } 219e5918d7dSYoshinori Sato 220e5918d7dSYoshinori Sato /* load source operand */ 221e5918d7dSYoshinori Sato static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 222e5918d7dSYoshinori Sato int ld, int mi, int rs) 223e5918d7dSYoshinori Sato { 224e5918d7dSYoshinori Sato TCGv addr; 225e5918d7dSYoshinori Sato MemOp mop; 226e5918d7dSYoshinori Sato if (ld < 3) { 227e5918d7dSYoshinori Sato mop = mi_to_mop(mi); 228e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 229e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 230e5918d7dSYoshinori Sato return mem; 231e5918d7dSYoshinori Sato } else { 232e5918d7dSYoshinori Sato return cpu_regs[rs]; 233e5918d7dSYoshinori Sato } 234e5918d7dSYoshinori Sato } 235e5918d7dSYoshinori Sato 236e5918d7dSYoshinori Sato /* Processor mode check */ 237e5918d7dSYoshinori Sato static int is_privileged(DisasContext *ctx, int is_exception) 238e5918d7dSYoshinori Sato { 2394341631eSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { 240e5918d7dSYoshinori Sato if (is_exception) { 241ad75a51eSRichard Henderson gen_helper_raise_privilege_violation(tcg_env); 242e5918d7dSYoshinori Sato } 243e5918d7dSYoshinori Sato return 0; 244e5918d7dSYoshinori Sato } else { 245e5918d7dSYoshinori Sato return 1; 246e5918d7dSYoshinori Sato } 247e5918d7dSYoshinori Sato } 248e5918d7dSYoshinori Sato 249e5918d7dSYoshinori Sato /* generate QEMU condition */ 250e5918d7dSYoshinori Sato static void psw_cond(DisasCompare *dc, uint32_t cond) 251e5918d7dSYoshinori Sato { 252e5918d7dSYoshinori Sato tcg_debug_assert(cond < 16); 253e5918d7dSYoshinori Sato switch (cond) { 254e5918d7dSYoshinori Sato case 0: /* z */ 255e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 256e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 257e5918d7dSYoshinori Sato break; 258e5918d7dSYoshinori Sato case 1: /* nz */ 259e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 260e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 261e5918d7dSYoshinori Sato break; 262e5918d7dSYoshinori Sato case 2: /* c */ 263e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 264e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 265e5918d7dSYoshinori Sato break; 266e5918d7dSYoshinori Sato case 3: /* nc */ 267e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 268e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 269e5918d7dSYoshinori Sato break; 270e5918d7dSYoshinori Sato case 4: /* gtu (C& ~Z) == 1 */ 271e5918d7dSYoshinori Sato case 5: /* leu (C& ~Z) == 0 */ 272e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 273e5918d7dSYoshinori Sato tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 274e5918d7dSYoshinori Sato dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 275e5918d7dSYoshinori Sato dc->value = dc->temp; 276e5918d7dSYoshinori Sato break; 277e5918d7dSYoshinori Sato case 6: /* pz (S == 0) */ 278e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 279e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 280e5918d7dSYoshinori Sato break; 281e5918d7dSYoshinori Sato case 7: /* n (S == 1) */ 282e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 283e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 284e5918d7dSYoshinori Sato break; 285e5918d7dSYoshinori Sato case 8: /* ge (S^O)==0 */ 286e5918d7dSYoshinori Sato case 9: /* lt (S^O)==1 */ 287e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 288e5918d7dSYoshinori Sato dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 289e5918d7dSYoshinori Sato dc->value = dc->temp; 290e5918d7dSYoshinori Sato break; 291e5918d7dSYoshinori Sato case 10: /* gt ((S^O)|Z)==0 */ 292e5918d7dSYoshinori Sato case 11: /* le ((S^O)|Z)==1 */ 293e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 294e5918d7dSYoshinori Sato tcg_gen_sari_i32(dc->temp, dc->temp, 31); 295e5918d7dSYoshinori Sato tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 296e5918d7dSYoshinori Sato dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 297e5918d7dSYoshinori Sato dc->value = dc->temp; 298e5918d7dSYoshinori Sato break; 299e5918d7dSYoshinori Sato case 12: /* o */ 300e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 301e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 302e5918d7dSYoshinori Sato break; 303e5918d7dSYoshinori Sato case 13: /* no */ 304e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 305e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 306e5918d7dSYoshinori Sato break; 307e5918d7dSYoshinori Sato case 14: /* always true */ 308e5918d7dSYoshinori Sato dc->cond = TCG_COND_ALWAYS; 309e5918d7dSYoshinori Sato dc->value = dc->temp; 310e5918d7dSYoshinori Sato break; 311e5918d7dSYoshinori Sato case 15: /* always false */ 312e5918d7dSYoshinori Sato dc->cond = TCG_COND_NEVER; 313e5918d7dSYoshinori Sato dc->value = dc->temp; 314e5918d7dSYoshinori Sato break; 315e5918d7dSYoshinori Sato } 316e5918d7dSYoshinori Sato } 317e5918d7dSYoshinori Sato 3183626a3feSRichard Henderson static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) 319e5918d7dSYoshinori Sato { 320e5918d7dSYoshinori Sato switch (cr) { 321e5918d7dSYoshinori Sato case 0: /* PSW */ 322ad75a51eSRichard Henderson gen_helper_pack_psw(ret, tcg_env); 323e5918d7dSYoshinori Sato break; 324e5918d7dSYoshinori Sato case 1: /* PC */ 325e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, pc); 326e5918d7dSYoshinori Sato break; 327e5918d7dSYoshinori Sato case 2: /* USP */ 3283626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3293626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_sp); 3303626a3feSRichard Henderson } else { 3313626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_usp); 3323626a3feSRichard Henderson } 333e5918d7dSYoshinori Sato break; 334e5918d7dSYoshinori Sato case 3: /* FPSW */ 335e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fpsw); 336e5918d7dSYoshinori Sato break; 337e5918d7dSYoshinori Sato case 8: /* BPSW */ 338e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpsw); 339e5918d7dSYoshinori Sato break; 340e5918d7dSYoshinori Sato case 9: /* BPC */ 341e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpc); 342e5918d7dSYoshinori Sato break; 343e5918d7dSYoshinori Sato case 10: /* ISP */ 3443626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3453626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_isp); 3463626a3feSRichard Henderson } else { 3473626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_sp); 3483626a3feSRichard Henderson } 349e5918d7dSYoshinori Sato break; 350e5918d7dSYoshinori Sato case 11: /* FINTV */ 351e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fintv); 352e5918d7dSYoshinori Sato break; 353e5918d7dSYoshinori Sato case 12: /* INTB */ 354e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_intb); 355e5918d7dSYoshinori Sato break; 356e5918d7dSYoshinori Sato default: 357e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 358e5918d7dSYoshinori Sato /* Unimplement registers return 0 */ 359e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, 0); 360e5918d7dSYoshinori Sato break; 361e5918d7dSYoshinori Sato } 362e5918d7dSYoshinori Sato } 363e5918d7dSYoshinori Sato 364e5918d7dSYoshinori Sato static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 365e5918d7dSYoshinori Sato { 366e5918d7dSYoshinori Sato if (cr >= 8 && !is_privileged(ctx, 0)) { 367e5918d7dSYoshinori Sato /* Some control registers can only be written in privileged mode. */ 368e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 36927a4a30eSYoshinori Sato "disallow control register write %s", rx_crname(cr)); 370e5918d7dSYoshinori Sato return; 371e5918d7dSYoshinori Sato } 372e5918d7dSYoshinori Sato switch (cr) { 373e5918d7dSYoshinori Sato case 0: /* PSW */ 374ad75a51eSRichard Henderson gen_helper_set_psw(tcg_env, val); 375d3562fe2SRichard Henderson if (is_privileged(ctx, 0)) { 376d3562fe2SRichard Henderson /* PSW.{I,U} may be updated here. exit TB. */ 377d3562fe2SRichard Henderson ctx->base.is_jmp = DISAS_UPDATE; 378d3562fe2SRichard Henderson } 379e5918d7dSYoshinori Sato break; 380e5918d7dSYoshinori Sato /* case 1: to PC not supported */ 381e5918d7dSYoshinori Sato case 2: /* USP */ 3823626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3833626a3feSRichard Henderson tcg_gen_mov_i32(cpu_sp, val); 3843626a3feSRichard Henderson } else { 385e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_usp, val); 3863626a3feSRichard Henderson } 387e5918d7dSYoshinori Sato break; 388e5918d7dSYoshinori Sato case 3: /* FPSW */ 389ad75a51eSRichard Henderson gen_helper_set_fpsw(tcg_env, val); 390e5918d7dSYoshinori Sato break; 391e5918d7dSYoshinori Sato case 8: /* BPSW */ 392e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpsw, val); 393e5918d7dSYoshinori Sato break; 394e5918d7dSYoshinori Sato case 9: /* BPC */ 395e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpc, val); 396e5918d7dSYoshinori Sato break; 397e5918d7dSYoshinori Sato case 10: /* ISP */ 3983626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 399e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_isp, val); 4003626a3feSRichard Henderson } else { 4013626a3feSRichard Henderson tcg_gen_mov_i32(cpu_sp, val); 4023626a3feSRichard Henderson } 403e5918d7dSYoshinori Sato break; 404e5918d7dSYoshinori Sato case 11: /* FINTV */ 405e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_fintv, val); 406e5918d7dSYoshinori Sato break; 407e5918d7dSYoshinori Sato case 12: /* INTB */ 408e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_intb, val); 409e5918d7dSYoshinori Sato break; 410e5918d7dSYoshinori Sato default: 411e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 412e5918d7dSYoshinori Sato "Unimplement control register %d", cr); 413e5918d7dSYoshinori Sato break; 414e5918d7dSYoshinori Sato } 415e5918d7dSYoshinori Sato } 416e5918d7dSYoshinori Sato 417e5918d7dSYoshinori Sato static void push(TCGv val) 418e5918d7dSYoshinori Sato { 419e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 420e5918d7dSYoshinori Sato rx_gen_st(MO_32, val, cpu_sp); 421e5918d7dSYoshinori Sato } 422e5918d7dSYoshinori Sato 423e5918d7dSYoshinori Sato static void pop(TCGv ret) 424e5918d7dSYoshinori Sato { 425e5918d7dSYoshinori Sato rx_gen_ld(MO_32, ret, cpu_sp); 426e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 427e5918d7dSYoshinori Sato } 428e5918d7dSYoshinori Sato 429e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp5[rd] */ 430e5918d7dSYoshinori Sato static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 431e5918d7dSYoshinori Sato { 432e5918d7dSYoshinori Sato TCGv mem; 433e5918d7dSYoshinori Sato mem = tcg_temp_new(); 434e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 435e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 436e5918d7dSYoshinori Sato return true; 437e5918d7dSYoshinori Sato } 438e5918d7dSYoshinori Sato 439e5918d7dSYoshinori Sato /* mov.<bwl> dsp5[rs],rd */ 440e5918d7dSYoshinori Sato static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 441e5918d7dSYoshinori Sato { 442e5918d7dSYoshinori Sato TCGv mem; 443e5918d7dSYoshinori Sato mem = tcg_temp_new(); 444e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 445e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 446e5918d7dSYoshinori Sato return true; 447e5918d7dSYoshinori Sato } 448e5918d7dSYoshinori Sato 449e5918d7dSYoshinori Sato /* mov.l #uimm4,rd */ 450e5918d7dSYoshinori Sato /* mov.l #uimm8,rd */ 451e5918d7dSYoshinori Sato /* mov.l #imm,rd */ 452e5918d7dSYoshinori Sato static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 453e5918d7dSYoshinori Sato { 454e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 455e5918d7dSYoshinori Sato return true; 456e5918d7dSYoshinori Sato } 457e5918d7dSYoshinori Sato 458e5918d7dSYoshinori Sato /* mov.<bwl> #uimm8,dsp[rd] */ 459e5918d7dSYoshinori Sato /* mov.<bwl> #imm, dsp[rd] */ 460e5918d7dSYoshinori Sato static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 461e5918d7dSYoshinori Sato { 462e5918d7dSYoshinori Sato TCGv imm, mem; 463daefc085SRichard Henderson imm = tcg_constant_i32(a->imm); 464e5918d7dSYoshinori Sato mem = tcg_temp_new(); 465e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 466e5918d7dSYoshinori Sato rx_gen_st(a->sz, imm, mem); 467e5918d7dSYoshinori Sato return true; 468e5918d7dSYoshinori Sato } 469e5918d7dSYoshinori Sato 470e5918d7dSYoshinori Sato /* mov.<bwl> [ri,rb],rd */ 471e5918d7dSYoshinori Sato static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 472e5918d7dSYoshinori Sato { 473e5918d7dSYoshinori Sato TCGv mem; 474e5918d7dSYoshinori Sato mem = tcg_temp_new(); 475e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 476e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 477e5918d7dSYoshinori Sato return true; 478e5918d7dSYoshinori Sato } 479e5918d7dSYoshinori Sato 480e5918d7dSYoshinori Sato /* mov.<bwl> rd,[ri,rb] */ 481e5918d7dSYoshinori Sato static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 482e5918d7dSYoshinori Sato { 483e5918d7dSYoshinori Sato TCGv mem; 484e5918d7dSYoshinori Sato mem = tcg_temp_new(); 485e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 486e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 487e5918d7dSYoshinori Sato return true; 488e5918d7dSYoshinori Sato } 489e5918d7dSYoshinori Sato 490e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 491e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 492e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 493e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 494e5918d7dSYoshinori Sato static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 495e5918d7dSYoshinori Sato { 496e5918d7dSYoshinori Sato TCGv tmp, mem, addr; 4970d67249cSRichard Henderson 498e5918d7dSYoshinori Sato if (a->lds == 3 && a->ldd == 3) { 499e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 5000d67249cSRichard Henderson tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); 501e5918d7dSYoshinori Sato return true; 502e5918d7dSYoshinori Sato } 503e5918d7dSYoshinori Sato 504e5918d7dSYoshinori Sato mem = tcg_temp_new(); 505e5918d7dSYoshinori Sato if (a->lds == 3) { 506e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 507e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 508e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rd], addr); 509e5918d7dSYoshinori Sato } else if (a->ldd == 3) { 510e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 511e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 512e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 513e5918d7dSYoshinori Sato } else { 514e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 515e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 516e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 517e5918d7dSYoshinori Sato rx_gen_ld(a->sz, tmp, addr); 518e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 519e5918d7dSYoshinori Sato rx_gen_st(a->sz, tmp, addr); 520e5918d7dSYoshinori Sato } 521e5918d7dSYoshinori Sato return true; 522e5918d7dSYoshinori Sato } 523e5918d7dSYoshinori Sato 524e5918d7dSYoshinori Sato /* mov.<bwl> rs,[rd+] */ 525e5918d7dSYoshinori Sato /* mov.<bwl> rs,[-rd] */ 526e5918d7dSYoshinori Sato static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 527e5918d7dSYoshinori Sato { 528e5918d7dSYoshinori Sato TCGv val; 529e5918d7dSYoshinori Sato val = tcg_temp_new(); 530e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 531e5918d7dSYoshinori Sato if (a->ad == 1) { 532e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 533e5918d7dSYoshinori Sato } 534e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_regs[a->rd]); 535e5918d7dSYoshinori Sato if (a->ad == 0) { 536e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 537e5918d7dSYoshinori Sato } 538e5918d7dSYoshinori Sato return true; 539e5918d7dSYoshinori Sato } 540e5918d7dSYoshinori Sato 541e5918d7dSYoshinori Sato /* mov.<bwl> [rd+],rs */ 542e5918d7dSYoshinori Sato /* mov.<bwl> [-rd],rs */ 543e5918d7dSYoshinori Sato static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 544e5918d7dSYoshinori Sato { 545e5918d7dSYoshinori Sato TCGv val; 546e5918d7dSYoshinori Sato val = tcg_temp_new(); 547e5918d7dSYoshinori Sato if (a->ad == 1) { 548e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 549e5918d7dSYoshinori Sato } 550e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 551e5918d7dSYoshinori Sato if (a->ad == 0) { 552e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 553e5918d7dSYoshinori Sato } 554e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 555e5918d7dSYoshinori Sato return true; 556e5918d7dSYoshinori Sato } 557e5918d7dSYoshinori Sato 558e5918d7dSYoshinori Sato /* movu.<bw> dsp5[rs],rd */ 559e5918d7dSYoshinori Sato /* movu.<bw> dsp[rs],rd */ 560e5918d7dSYoshinori Sato static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 561e5918d7dSYoshinori Sato { 562e5918d7dSYoshinori Sato TCGv mem; 563e5918d7dSYoshinori Sato mem = tcg_temp_new(); 564e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 565e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 566e5918d7dSYoshinori Sato return true; 567e5918d7dSYoshinori Sato } 568e5918d7dSYoshinori Sato 569e5918d7dSYoshinori Sato /* movu.<bw> rs,rd */ 570e5918d7dSYoshinori Sato static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 571e5918d7dSYoshinori Sato { 5720d67249cSRichard Henderson tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz); 573e5918d7dSYoshinori Sato return true; 574e5918d7dSYoshinori Sato } 575e5918d7dSYoshinori Sato 576e5918d7dSYoshinori Sato /* movu.<bw> [ri,rb],rd */ 577e5918d7dSYoshinori Sato static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 578e5918d7dSYoshinori Sato { 579e5918d7dSYoshinori Sato TCGv mem; 580e5918d7dSYoshinori Sato mem = tcg_temp_new(); 581e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 582e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 583e5918d7dSYoshinori Sato return true; 584e5918d7dSYoshinori Sato } 585e5918d7dSYoshinori Sato 586e5918d7dSYoshinori Sato /* movu.<bw> [rd+],rs */ 587e5918d7dSYoshinori Sato /* mov.<bw> [-rd],rs */ 588e5918d7dSYoshinori Sato static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 589e5918d7dSYoshinori Sato { 590e5918d7dSYoshinori Sato TCGv val; 591e5918d7dSYoshinori Sato val = tcg_temp_new(); 592e5918d7dSYoshinori Sato if (a->ad == 1) { 593e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 594e5918d7dSYoshinori Sato } 595e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 596e5918d7dSYoshinori Sato if (a->ad == 0) { 597e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 598e5918d7dSYoshinori Sato } 599e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 600e5918d7dSYoshinori Sato return true; 601e5918d7dSYoshinori Sato } 602e5918d7dSYoshinori Sato 603e5918d7dSYoshinori Sato 604e5918d7dSYoshinori Sato /* pop rd */ 605e5918d7dSYoshinori Sato static bool trans_POP(DisasContext *ctx, arg_POP *a) 606e5918d7dSYoshinori Sato { 607e5918d7dSYoshinori Sato /* mov.l [r0+], rd */ 608e5918d7dSYoshinori Sato arg_MOV_rp mov_a; 609e5918d7dSYoshinori Sato mov_a.rd = 0; 610e5918d7dSYoshinori Sato mov_a.rs = a->rd; 611e5918d7dSYoshinori Sato mov_a.ad = 0; 612e5918d7dSYoshinori Sato mov_a.sz = MO_32; 613e5918d7dSYoshinori Sato trans_MOV_pr(ctx, &mov_a); 614e5918d7dSYoshinori Sato return true; 615e5918d7dSYoshinori Sato } 616e5918d7dSYoshinori Sato 617e5918d7dSYoshinori Sato /* popc cr */ 618e5918d7dSYoshinori Sato static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 619e5918d7dSYoshinori Sato { 620e5918d7dSYoshinori Sato TCGv val; 621e5918d7dSYoshinori Sato val = tcg_temp_new(); 622e5918d7dSYoshinori Sato pop(val); 623e5918d7dSYoshinori Sato move_to_cr(ctx, val, a->cr); 624e5918d7dSYoshinori Sato return true; 625e5918d7dSYoshinori Sato } 626e5918d7dSYoshinori Sato 627e5918d7dSYoshinori Sato /* popm rd-rd2 */ 628e5918d7dSYoshinori Sato static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 629e5918d7dSYoshinori Sato { 630e5918d7dSYoshinori Sato int r; 631e5918d7dSYoshinori Sato if (a->rd == 0 || a->rd >= a->rd2) { 632e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 633e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rd, a->rd2); 634e5918d7dSYoshinori Sato } 635e5918d7dSYoshinori Sato r = a->rd; 636e5918d7dSYoshinori Sato while (r <= a->rd2 && r < 16) { 637e5918d7dSYoshinori Sato pop(cpu_regs[r++]); 638e5918d7dSYoshinori Sato } 639e5918d7dSYoshinori Sato return true; 640e5918d7dSYoshinori Sato } 641e5918d7dSYoshinori Sato 642e5918d7dSYoshinori Sato 643e5918d7dSYoshinori Sato /* push.<bwl> rs */ 644e5918d7dSYoshinori Sato static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 645e5918d7dSYoshinori Sato { 646e5918d7dSYoshinori Sato TCGv val; 647e5918d7dSYoshinori Sato val = tcg_temp_new(); 648e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 649e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 650e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 651e5918d7dSYoshinori Sato return true; 652e5918d7dSYoshinori Sato } 653e5918d7dSYoshinori Sato 654e5918d7dSYoshinori Sato /* push.<bwl> dsp[rs] */ 655e5918d7dSYoshinori Sato static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 656e5918d7dSYoshinori Sato { 657e5918d7dSYoshinori Sato TCGv mem, val, addr; 658e5918d7dSYoshinori Sato mem = tcg_temp_new(); 659e5918d7dSYoshinori Sato val = tcg_temp_new(); 660e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 661e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, addr); 662e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 663e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 664e5918d7dSYoshinori Sato return true; 665e5918d7dSYoshinori Sato } 666e5918d7dSYoshinori Sato 667e5918d7dSYoshinori Sato /* pushc rx */ 668e5918d7dSYoshinori Sato static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 669e5918d7dSYoshinori Sato { 670e5918d7dSYoshinori Sato TCGv val; 671e5918d7dSYoshinori Sato val = tcg_temp_new(); 6723626a3feSRichard Henderson move_from_cr(ctx, val, a->cr, ctx->pc); 673e5918d7dSYoshinori Sato push(val); 674e5918d7dSYoshinori Sato return true; 675e5918d7dSYoshinori Sato } 676e5918d7dSYoshinori Sato 677e5918d7dSYoshinori Sato /* pushm rs-rs2 */ 678e5918d7dSYoshinori Sato static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 679e5918d7dSYoshinori Sato { 680e5918d7dSYoshinori Sato int r; 681e5918d7dSYoshinori Sato 682e5918d7dSYoshinori Sato if (a->rs == 0 || a->rs >= a->rs2) { 683e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 684e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rs, a->rs2); 685e5918d7dSYoshinori Sato } 686e5918d7dSYoshinori Sato r = a->rs2; 687e5918d7dSYoshinori Sato while (r >= a->rs && r >= 0) { 688e5918d7dSYoshinori Sato push(cpu_regs[r--]); 689e5918d7dSYoshinori Sato } 690e5918d7dSYoshinori Sato return true; 691e5918d7dSYoshinori Sato } 692e5918d7dSYoshinori Sato 693e5918d7dSYoshinori Sato /* xchg rs,rd */ 694e5918d7dSYoshinori Sato static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 695e5918d7dSYoshinori Sato { 696e5918d7dSYoshinori Sato TCGv tmp; 697e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 698e5918d7dSYoshinori Sato tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 699e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 700e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 701e5918d7dSYoshinori Sato return true; 702e5918d7dSYoshinori Sato } 703e5918d7dSYoshinori Sato 704e5918d7dSYoshinori Sato /* xchg dsp[rs].<mi>,rd */ 705e5918d7dSYoshinori Sato static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 706e5918d7dSYoshinori Sato { 707e5918d7dSYoshinori Sato TCGv mem, addr; 708e5918d7dSYoshinori Sato mem = tcg_temp_new(); 709e5918d7dSYoshinori Sato switch (a->mi) { 710e5918d7dSYoshinori Sato case 0: /* dsp[rs].b */ 711e5918d7dSYoshinori Sato case 1: /* dsp[rs].w */ 712e5918d7dSYoshinori Sato case 2: /* dsp[rs].l */ 713e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 714e5918d7dSYoshinori Sato break; 715e5918d7dSYoshinori Sato case 3: /* dsp[rs].uw */ 716e5918d7dSYoshinori Sato case 4: /* dsp[rs].ub */ 717e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 718e5918d7dSYoshinori Sato break; 719e5918d7dSYoshinori Sato default: 720e5918d7dSYoshinori Sato g_assert_not_reached(); 721e5918d7dSYoshinori Sato } 722e5918d7dSYoshinori Sato tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 723e5918d7dSYoshinori Sato 0, mi_to_mop(a->mi)); 724e5918d7dSYoshinori Sato return true; 725e5918d7dSYoshinori Sato } 726e5918d7dSYoshinori Sato 727e5918d7dSYoshinori Sato static inline void stcond(TCGCond cond, int rd, int imm) 728e5918d7dSYoshinori Sato { 729e5918d7dSYoshinori Sato TCGv z; 730e5918d7dSYoshinori Sato TCGv _imm; 731daefc085SRichard Henderson z = tcg_constant_i32(0); 732daefc085SRichard Henderson _imm = tcg_constant_i32(imm); 733e5918d7dSYoshinori Sato tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 734e5918d7dSYoshinori Sato _imm, cpu_regs[rd]); 735e5918d7dSYoshinori Sato } 736e5918d7dSYoshinori Sato 737e5918d7dSYoshinori Sato /* stz #imm,rd */ 738e5918d7dSYoshinori Sato static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 739e5918d7dSYoshinori Sato { 740e5918d7dSYoshinori Sato stcond(TCG_COND_EQ, a->rd, a->imm); 741e5918d7dSYoshinori Sato return true; 742e5918d7dSYoshinori Sato } 743e5918d7dSYoshinori Sato 744e5918d7dSYoshinori Sato /* stnz #imm,rd */ 745e5918d7dSYoshinori Sato static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 746e5918d7dSYoshinori Sato { 747e5918d7dSYoshinori Sato stcond(TCG_COND_NE, a->rd, a->imm); 748e5918d7dSYoshinori Sato return true; 749e5918d7dSYoshinori Sato } 750e5918d7dSYoshinori Sato 751e5918d7dSYoshinori Sato /* sccnd.<bwl> rd */ 752e5918d7dSYoshinori Sato /* sccnd.<bwl> dsp:[rd] */ 753e5918d7dSYoshinori Sato static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 754e5918d7dSYoshinori Sato { 755e5918d7dSYoshinori Sato DisasCompare dc; 756e5918d7dSYoshinori Sato TCGv val, mem, addr; 757e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 758e5918d7dSYoshinori Sato psw_cond(&dc, a->cd); 759e5918d7dSYoshinori Sato if (a->ld < 3) { 760e5918d7dSYoshinori Sato val = tcg_temp_new(); 761e5918d7dSYoshinori Sato mem = tcg_temp_new(); 762e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 763e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 764e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, addr); 765e5918d7dSYoshinori Sato } else { 766e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 767e5918d7dSYoshinori Sato } 768e5918d7dSYoshinori Sato return true; 769e5918d7dSYoshinori Sato } 770e5918d7dSYoshinori Sato 771e5918d7dSYoshinori Sato /* rtsd #imm */ 772e5918d7dSYoshinori Sato static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 773e5918d7dSYoshinori Sato { 774e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 775e5918d7dSYoshinori Sato pop(cpu_pc); 776e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 777e5918d7dSYoshinori Sato return true; 778e5918d7dSYoshinori Sato } 779e5918d7dSYoshinori Sato 780e5918d7dSYoshinori Sato /* rtsd #imm, rd-rd2 */ 781e5918d7dSYoshinori Sato static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 782e5918d7dSYoshinori Sato { 783e5918d7dSYoshinori Sato int dst; 784e5918d7dSYoshinori Sato int adj; 785e5918d7dSYoshinori Sato 786e5918d7dSYoshinori Sato if (a->rd2 >= a->rd) { 787e5918d7dSYoshinori Sato adj = a->imm - (a->rd2 - a->rd + 1); 788e5918d7dSYoshinori Sato } else { 789e5918d7dSYoshinori Sato adj = a->imm - (15 - a->rd + 1); 790e5918d7dSYoshinori Sato } 791e5918d7dSYoshinori Sato 792e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 793e5918d7dSYoshinori Sato dst = a->rd; 794e5918d7dSYoshinori Sato while (dst <= a->rd2 && dst < 16) { 795e5918d7dSYoshinori Sato pop(cpu_regs[dst++]); 796e5918d7dSYoshinori Sato } 797e5918d7dSYoshinori Sato pop(cpu_pc); 798e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 799e5918d7dSYoshinori Sato return true; 800e5918d7dSYoshinori Sato } 801e5918d7dSYoshinori Sato 802e5918d7dSYoshinori Sato typedef void (*op2fn)(TCGv ret, TCGv arg1); 803e5918d7dSYoshinori Sato typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 804e5918d7dSYoshinori Sato 805e5918d7dSYoshinori Sato static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 806e5918d7dSYoshinori Sato { 807e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src]); 808e5918d7dSYoshinori Sato } 809e5918d7dSYoshinori Sato 810e5918d7dSYoshinori Sato static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 811e5918d7dSYoshinori Sato { 812e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 813e5918d7dSYoshinori Sato } 814e5918d7dSYoshinori Sato 815e5918d7dSYoshinori Sato static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 816e5918d7dSYoshinori Sato { 817daefc085SRichard Henderson TCGv imm = tcg_constant_i32(src2); 818e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], imm); 819e5918d7dSYoshinori Sato } 820e5918d7dSYoshinori Sato 821e5918d7dSYoshinori Sato static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 822e5918d7dSYoshinori Sato int dst, int src, int ld, int mi) 823e5918d7dSYoshinori Sato { 824e5918d7dSYoshinori Sato TCGv val, mem; 825e5918d7dSYoshinori Sato mem = tcg_temp_new(); 826e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, ld, mi, src); 827e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[dst], val); 828e5918d7dSYoshinori Sato } 829e5918d7dSYoshinori Sato 830e5918d7dSYoshinori Sato static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 831e5918d7dSYoshinori Sato { 832e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 833e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 834e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 835e5918d7dSYoshinori Sato } 836e5918d7dSYoshinori Sato 837e5918d7dSYoshinori Sato /* and #uimm:4, rd */ 838e5918d7dSYoshinori Sato /* and #imm, rd */ 839e5918d7dSYoshinori Sato static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 840e5918d7dSYoshinori Sato { 841e5918d7dSYoshinori Sato rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 842e5918d7dSYoshinori Sato return true; 843e5918d7dSYoshinori Sato } 844e5918d7dSYoshinori Sato 845e5918d7dSYoshinori Sato /* and dsp[rs], rd */ 846e5918d7dSYoshinori Sato /* and rs,rd */ 847e5918d7dSYoshinori Sato static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 848e5918d7dSYoshinori Sato { 849e5918d7dSYoshinori Sato rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 850e5918d7dSYoshinori Sato return true; 851e5918d7dSYoshinori Sato } 852e5918d7dSYoshinori Sato 853e5918d7dSYoshinori Sato /* and rs,rs2,rd */ 854e5918d7dSYoshinori Sato static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 855e5918d7dSYoshinori Sato { 856e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 857e5918d7dSYoshinori Sato return true; 858e5918d7dSYoshinori Sato } 859e5918d7dSYoshinori Sato 860e5918d7dSYoshinori Sato static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 861e5918d7dSYoshinori Sato { 862e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 863e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 864e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 865e5918d7dSYoshinori Sato } 866e5918d7dSYoshinori Sato 867e5918d7dSYoshinori Sato /* or #uimm:4, rd */ 868e5918d7dSYoshinori Sato /* or #imm, rd */ 869e5918d7dSYoshinori Sato static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 870e5918d7dSYoshinori Sato { 871e5918d7dSYoshinori Sato rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 872e5918d7dSYoshinori Sato return true; 873e5918d7dSYoshinori Sato } 874e5918d7dSYoshinori Sato 875e5918d7dSYoshinori Sato /* or dsp[rs], rd */ 876e5918d7dSYoshinori Sato /* or rs,rd */ 877e5918d7dSYoshinori Sato static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 878e5918d7dSYoshinori Sato { 879e5918d7dSYoshinori Sato rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 880e5918d7dSYoshinori Sato return true; 881e5918d7dSYoshinori Sato } 882e5918d7dSYoshinori Sato 883e5918d7dSYoshinori Sato /* or rs,rs2,rd */ 884e5918d7dSYoshinori Sato static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 885e5918d7dSYoshinori Sato { 886e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 887e5918d7dSYoshinori Sato return true; 888e5918d7dSYoshinori Sato } 889e5918d7dSYoshinori Sato 890e5918d7dSYoshinori Sato static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 891e5918d7dSYoshinori Sato { 892e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 893e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 894e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 895e5918d7dSYoshinori Sato } 896e5918d7dSYoshinori Sato 897e5918d7dSYoshinori Sato /* xor #imm, rd */ 898e5918d7dSYoshinori Sato static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 899e5918d7dSYoshinori Sato { 900e5918d7dSYoshinori Sato rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 901e5918d7dSYoshinori Sato return true; 902e5918d7dSYoshinori Sato } 903e5918d7dSYoshinori Sato 904e5918d7dSYoshinori Sato /* xor dsp[rs], rd */ 905e5918d7dSYoshinori Sato /* xor rs,rd */ 906e5918d7dSYoshinori Sato static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 907e5918d7dSYoshinori Sato { 908e5918d7dSYoshinori Sato rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 909e5918d7dSYoshinori Sato return true; 910e5918d7dSYoshinori Sato } 911e5918d7dSYoshinori Sato 912e5918d7dSYoshinori Sato static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 913e5918d7dSYoshinori Sato { 914e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 915e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 916e5918d7dSYoshinori Sato } 917e5918d7dSYoshinori Sato 918e5918d7dSYoshinori Sato /* tst #imm, rd */ 919e5918d7dSYoshinori Sato static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 920e5918d7dSYoshinori Sato { 921e5918d7dSYoshinori Sato rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 922e5918d7dSYoshinori Sato return true; 923e5918d7dSYoshinori Sato } 924e5918d7dSYoshinori Sato 925e5918d7dSYoshinori Sato /* tst dsp[rs], rd */ 926e5918d7dSYoshinori Sato /* tst rs, rd */ 927e5918d7dSYoshinori Sato static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 928e5918d7dSYoshinori Sato { 929e5918d7dSYoshinori Sato rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 930e5918d7dSYoshinori Sato return true; 931e5918d7dSYoshinori Sato } 932e5918d7dSYoshinori Sato 933e5918d7dSYoshinori Sato static void rx_not(TCGv ret, TCGv arg1) 934e5918d7dSYoshinori Sato { 935e5918d7dSYoshinori Sato tcg_gen_not_i32(ret, arg1); 936e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 937e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 938e5918d7dSYoshinori Sato } 939e5918d7dSYoshinori Sato 940e5918d7dSYoshinori Sato /* not rd */ 941e5918d7dSYoshinori Sato /* not rs, rd */ 942e5918d7dSYoshinori Sato static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 943e5918d7dSYoshinori Sato { 944e5918d7dSYoshinori Sato rx_gen_op_rr(rx_not, a->rd, a->rs); 945e5918d7dSYoshinori Sato return true; 946e5918d7dSYoshinori Sato } 947e5918d7dSYoshinori Sato 948e5918d7dSYoshinori Sato static void rx_neg(TCGv ret, TCGv arg1) 949e5918d7dSYoshinori Sato { 950e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 951e5918d7dSYoshinori Sato tcg_gen_neg_i32(ret, arg1); 952e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 953e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 954e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 955e5918d7dSYoshinori Sato } 956e5918d7dSYoshinori Sato 957e5918d7dSYoshinori Sato 958e5918d7dSYoshinori Sato /* neg rd */ 959e5918d7dSYoshinori Sato /* neg rs, rd */ 960e5918d7dSYoshinori Sato static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 961e5918d7dSYoshinori Sato { 962e5918d7dSYoshinori Sato rx_gen_op_rr(rx_neg, a->rd, a->rs); 963e5918d7dSYoshinori Sato return true; 964e5918d7dSYoshinori Sato } 965e5918d7dSYoshinori Sato 966e5918d7dSYoshinori Sato /* ret = arg1 + arg2 + psw_c */ 967e5918d7dSYoshinori Sato static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 968e5918d7dSYoshinori Sato { 969bb09b540SRichard Henderson TCGv z = tcg_constant_i32(0); 970e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 971e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 972e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 973bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 974bb09b540SRichard Henderson tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 975bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 976e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 977e5918d7dSYoshinori Sato } 978e5918d7dSYoshinori Sato 979e5918d7dSYoshinori Sato /* adc #imm, rd */ 980e5918d7dSYoshinori Sato static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 981e5918d7dSYoshinori Sato { 982e5918d7dSYoshinori Sato rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 983e5918d7dSYoshinori Sato return true; 984e5918d7dSYoshinori Sato } 985e5918d7dSYoshinori Sato 986e5918d7dSYoshinori Sato /* adc rs, rd */ 987e5918d7dSYoshinori Sato static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 988e5918d7dSYoshinori Sato { 989e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 990e5918d7dSYoshinori Sato return true; 991e5918d7dSYoshinori Sato } 992e5918d7dSYoshinori Sato 993e5918d7dSYoshinori Sato /* adc dsp[rs], rd */ 994e5918d7dSYoshinori Sato static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 995e5918d7dSYoshinori Sato { 996e5918d7dSYoshinori Sato /* mi only 2 */ 997e5918d7dSYoshinori Sato if (a->mi != 2) { 998e5918d7dSYoshinori Sato return false; 999e5918d7dSYoshinori Sato } 1000e5918d7dSYoshinori Sato rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 1001e5918d7dSYoshinori Sato return true; 1002e5918d7dSYoshinori Sato } 1003e5918d7dSYoshinori Sato 1004e5918d7dSYoshinori Sato /* ret = arg1 + arg2 */ 1005e5918d7dSYoshinori Sato static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1006e5918d7dSYoshinori Sato { 1007bb09b540SRichard Henderson TCGv z = tcg_constant_i32(0); 1008e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1009e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1010bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1011bb09b540SRichard Henderson tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1012bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1013e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1014e5918d7dSYoshinori Sato } 1015e5918d7dSYoshinori Sato 1016e5918d7dSYoshinori Sato /* add #uimm4, rd */ 1017e5918d7dSYoshinori Sato /* add #imm, rs, rd */ 1018e5918d7dSYoshinori Sato static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1019e5918d7dSYoshinori Sato { 1020e5918d7dSYoshinori Sato rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1021e5918d7dSYoshinori Sato return true; 1022e5918d7dSYoshinori Sato } 1023e5918d7dSYoshinori Sato 1024e5918d7dSYoshinori Sato /* add rs, rd */ 1025e5918d7dSYoshinori Sato /* add dsp[rs], rd */ 1026e5918d7dSYoshinori Sato static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1027e5918d7dSYoshinori Sato { 1028e5918d7dSYoshinori Sato rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1029e5918d7dSYoshinori Sato return true; 1030e5918d7dSYoshinori Sato } 1031e5918d7dSYoshinori Sato 1032e5918d7dSYoshinori Sato /* add rs, rs2, rd */ 1033e5918d7dSYoshinori Sato static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1034e5918d7dSYoshinori Sato { 1035e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1036e5918d7dSYoshinori Sato return true; 1037e5918d7dSYoshinori Sato } 1038e5918d7dSYoshinori Sato 1039e5918d7dSYoshinori Sato /* ret = arg1 - arg2 */ 1040e5918d7dSYoshinori Sato static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1041e5918d7dSYoshinori Sato { 1042e5918d7dSYoshinori Sato tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1043e5918d7dSYoshinori Sato tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1044e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1045bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1046bb09b540SRichard Henderson tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1047bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 104897841438SLichang Zhao /* CMP not required return */ 1049e5918d7dSYoshinori Sato if (ret) { 1050e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1051e5918d7dSYoshinori Sato } 1052e5918d7dSYoshinori Sato } 1053bb09b540SRichard Henderson 1054e5918d7dSYoshinori Sato static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1055e5918d7dSYoshinori Sato { 1056e5918d7dSYoshinori Sato rx_sub(NULL, arg1, arg2); 1057e5918d7dSYoshinori Sato } 1058bb09b540SRichard Henderson 1059e5918d7dSYoshinori Sato /* ret = arg1 - arg2 - !psw_c */ 1060e5918d7dSYoshinori Sato /* -> ret = arg1 + ~arg2 + psw_c */ 1061e5918d7dSYoshinori Sato static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1062e5918d7dSYoshinori Sato { 1063e5918d7dSYoshinori Sato TCGv temp; 1064e5918d7dSYoshinori Sato temp = tcg_temp_new(); 1065e5918d7dSYoshinori Sato tcg_gen_not_i32(temp, arg2); 1066e5918d7dSYoshinori Sato rx_adc(ret, arg1, temp); 1067e5918d7dSYoshinori Sato } 1068e5918d7dSYoshinori Sato 1069e5918d7dSYoshinori Sato /* cmp #imm4, rs2 */ 1070e5918d7dSYoshinori Sato /* cmp #imm8, rs2 */ 1071e5918d7dSYoshinori Sato /* cmp #imm, rs2 */ 1072e5918d7dSYoshinori Sato static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1073e5918d7dSYoshinori Sato { 1074e5918d7dSYoshinori Sato rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1075e5918d7dSYoshinori Sato return true; 1076e5918d7dSYoshinori Sato } 1077e5918d7dSYoshinori Sato 1078e5918d7dSYoshinori Sato /* cmp rs, rs2 */ 1079e5918d7dSYoshinori Sato /* cmp dsp[rs], rs2 */ 1080e5918d7dSYoshinori Sato static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1081e5918d7dSYoshinori Sato { 1082e5918d7dSYoshinori Sato rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1083e5918d7dSYoshinori Sato return true; 1084e5918d7dSYoshinori Sato } 1085e5918d7dSYoshinori Sato 1086e5918d7dSYoshinori Sato /* sub #imm4, rd */ 1087e5918d7dSYoshinori Sato static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1088e5918d7dSYoshinori Sato { 1089e5918d7dSYoshinori Sato rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1090e5918d7dSYoshinori Sato return true; 1091e5918d7dSYoshinori Sato } 1092e5918d7dSYoshinori Sato 1093e5918d7dSYoshinori Sato /* sub rs, rd */ 1094e5918d7dSYoshinori Sato /* sub dsp[rs], rd */ 1095e5918d7dSYoshinori Sato static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1096e5918d7dSYoshinori Sato { 1097e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1098e5918d7dSYoshinori Sato return true; 1099e5918d7dSYoshinori Sato } 1100e5918d7dSYoshinori Sato 1101e5918d7dSYoshinori Sato /* sub rs2, rs, rd */ 1102e5918d7dSYoshinori Sato static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1103e5918d7dSYoshinori Sato { 1104e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1105e5918d7dSYoshinori Sato return true; 1106e5918d7dSYoshinori Sato } 1107e5918d7dSYoshinori Sato 1108e5918d7dSYoshinori Sato /* sbb rs, rd */ 1109e5918d7dSYoshinori Sato static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1110e5918d7dSYoshinori Sato { 1111e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1112e5918d7dSYoshinori Sato return true; 1113e5918d7dSYoshinori Sato } 1114e5918d7dSYoshinori Sato 1115e5918d7dSYoshinori Sato /* sbb dsp[rs], rd */ 1116e5918d7dSYoshinori Sato static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1117e5918d7dSYoshinori Sato { 1118e5918d7dSYoshinori Sato /* mi only 2 */ 1119e5918d7dSYoshinori Sato if (a->mi != 2) { 1120e5918d7dSYoshinori Sato return false; 1121e5918d7dSYoshinori Sato } 1122e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1123e5918d7dSYoshinori Sato return true; 1124e5918d7dSYoshinori Sato } 1125e5918d7dSYoshinori Sato 1126e5918d7dSYoshinori Sato /* abs rd */ 1127e5918d7dSYoshinori Sato /* abs rs, rd */ 1128e5918d7dSYoshinori Sato static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1129e5918d7dSYoshinori Sato { 11304b01ff25SRichard Henderson rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); 1131e5918d7dSYoshinori Sato return true; 1132e5918d7dSYoshinori Sato } 1133e5918d7dSYoshinori Sato 1134e5918d7dSYoshinori Sato /* max #imm, rd */ 1135e5918d7dSYoshinori Sato static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1136e5918d7dSYoshinori Sato { 1137e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1138e5918d7dSYoshinori Sato return true; 1139e5918d7dSYoshinori Sato } 1140e5918d7dSYoshinori Sato 1141e5918d7dSYoshinori Sato /* max rs, rd */ 1142e5918d7dSYoshinori Sato /* max dsp[rs], rd */ 1143e5918d7dSYoshinori Sato static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1144e5918d7dSYoshinori Sato { 1145e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1146e5918d7dSYoshinori Sato return true; 1147e5918d7dSYoshinori Sato } 1148e5918d7dSYoshinori Sato 1149e5918d7dSYoshinori Sato /* min #imm, rd */ 1150e5918d7dSYoshinori Sato static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1151e5918d7dSYoshinori Sato { 1152e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1153e5918d7dSYoshinori Sato return true; 1154e5918d7dSYoshinori Sato } 1155e5918d7dSYoshinori Sato 1156e5918d7dSYoshinori Sato /* min rs, rd */ 1157e5918d7dSYoshinori Sato /* min dsp[rs], rd */ 1158e5918d7dSYoshinori Sato static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1159e5918d7dSYoshinori Sato { 1160e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1161e5918d7dSYoshinori Sato return true; 1162e5918d7dSYoshinori Sato } 1163e5918d7dSYoshinori Sato 1164e5918d7dSYoshinori Sato /* mul #uimm4, rd */ 1165e5918d7dSYoshinori Sato /* mul #imm, rd */ 1166e5918d7dSYoshinori Sato static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1167e5918d7dSYoshinori Sato { 1168e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1169e5918d7dSYoshinori Sato return true; 1170e5918d7dSYoshinori Sato } 1171e5918d7dSYoshinori Sato 1172e5918d7dSYoshinori Sato /* mul rs, rd */ 1173e5918d7dSYoshinori Sato /* mul dsp[rs], rd */ 1174e5918d7dSYoshinori Sato static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1175e5918d7dSYoshinori Sato { 1176e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1177e5918d7dSYoshinori Sato return true; 1178e5918d7dSYoshinori Sato } 1179e5918d7dSYoshinori Sato 1180e5918d7dSYoshinori Sato /* mul rs, rs2, rd */ 1181e5918d7dSYoshinori Sato static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1182e5918d7dSYoshinori Sato { 1183e5918d7dSYoshinori Sato rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1184e5918d7dSYoshinori Sato return true; 1185e5918d7dSYoshinori Sato } 1186e5918d7dSYoshinori Sato 1187e5918d7dSYoshinori Sato /* emul #imm, rd */ 1188e5918d7dSYoshinori Sato static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1189e5918d7dSYoshinori Sato { 1190daefc085SRichard Henderson TCGv imm = tcg_constant_i32(a->imm); 1191e5918d7dSYoshinori Sato if (a->rd > 14) { 1192e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1193e5918d7dSYoshinori Sato } 1194e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1195e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1196e5918d7dSYoshinori Sato return true; 1197e5918d7dSYoshinori Sato } 1198e5918d7dSYoshinori Sato 1199e5918d7dSYoshinori Sato /* emul rs, rd */ 1200e5918d7dSYoshinori Sato /* emul dsp[rs], rd */ 1201e5918d7dSYoshinori Sato static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1202e5918d7dSYoshinori Sato { 1203e5918d7dSYoshinori Sato TCGv val, mem; 1204e5918d7dSYoshinori Sato if (a->rd > 14) { 1205e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1206e5918d7dSYoshinori Sato } 1207e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1208e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1209e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1210e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1211e5918d7dSYoshinori Sato return true; 1212e5918d7dSYoshinori Sato } 1213e5918d7dSYoshinori Sato 1214e5918d7dSYoshinori Sato /* emulu #imm, rd */ 1215e5918d7dSYoshinori Sato static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1216e5918d7dSYoshinori Sato { 1217daefc085SRichard Henderson TCGv imm = tcg_constant_i32(a->imm); 1218e5918d7dSYoshinori Sato if (a->rd > 14) { 1219e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1220e5918d7dSYoshinori Sato } 1221e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1222e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1223e5918d7dSYoshinori Sato return true; 1224e5918d7dSYoshinori Sato } 1225e5918d7dSYoshinori Sato 1226e5918d7dSYoshinori Sato /* emulu rs, rd */ 1227e5918d7dSYoshinori Sato /* emulu dsp[rs], rd */ 1228e5918d7dSYoshinori Sato static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1229e5918d7dSYoshinori Sato { 1230e5918d7dSYoshinori Sato TCGv val, mem; 1231e5918d7dSYoshinori Sato if (a->rd > 14) { 1232e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1233e5918d7dSYoshinori Sato } 1234e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1235e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1236e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1237e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1238e5918d7dSYoshinori Sato return true; 1239e5918d7dSYoshinori Sato } 1240e5918d7dSYoshinori Sato 1241e5918d7dSYoshinori Sato static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1242e5918d7dSYoshinori Sato { 1243ad75a51eSRichard Henderson gen_helper_div(ret, tcg_env, arg1, arg2); 1244e5918d7dSYoshinori Sato } 1245e5918d7dSYoshinori Sato 1246e5918d7dSYoshinori Sato static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1247e5918d7dSYoshinori Sato { 1248ad75a51eSRichard Henderson gen_helper_divu(ret, tcg_env, arg1, arg2); 1249e5918d7dSYoshinori Sato } 1250e5918d7dSYoshinori Sato 1251e5918d7dSYoshinori Sato /* div #imm, rd */ 1252e5918d7dSYoshinori Sato static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1253e5918d7dSYoshinori Sato { 1254e5918d7dSYoshinori Sato rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1255e5918d7dSYoshinori Sato return true; 1256e5918d7dSYoshinori Sato } 1257e5918d7dSYoshinori Sato 1258e5918d7dSYoshinori Sato /* div rs, rd */ 1259e5918d7dSYoshinori Sato /* div dsp[rs], rd */ 1260e5918d7dSYoshinori Sato static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1261e5918d7dSYoshinori Sato { 1262e5918d7dSYoshinori Sato rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1263e5918d7dSYoshinori Sato return true; 1264e5918d7dSYoshinori Sato } 1265e5918d7dSYoshinori Sato 1266e5918d7dSYoshinori Sato /* divu #imm, rd */ 1267e5918d7dSYoshinori Sato static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1268e5918d7dSYoshinori Sato { 1269e5918d7dSYoshinori Sato rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1270e5918d7dSYoshinori Sato return true; 1271e5918d7dSYoshinori Sato } 1272e5918d7dSYoshinori Sato 1273e5918d7dSYoshinori Sato /* divu rs, rd */ 1274e5918d7dSYoshinori Sato /* divu dsp[rs], rd */ 1275e5918d7dSYoshinori Sato static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1276e5918d7dSYoshinori Sato { 1277e5918d7dSYoshinori Sato rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1278e5918d7dSYoshinori Sato return true; 1279e5918d7dSYoshinori Sato } 1280e5918d7dSYoshinori Sato 1281e5918d7dSYoshinori Sato 1282e5918d7dSYoshinori Sato /* shll #imm:5, rd */ 1283e5918d7dSYoshinori Sato /* shll #imm:5, rs2, rd */ 1284e5918d7dSYoshinori Sato static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1285e5918d7dSYoshinori Sato { 1286e5918d7dSYoshinori Sato TCGv tmp; 1287e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1288e5918d7dSYoshinori Sato if (a->imm) { 1289e5918d7dSYoshinori Sato tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1290e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1291e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1292e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1293e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1294e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1295e5918d7dSYoshinori Sato } else { 1296e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1297e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1298e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1299e5918d7dSYoshinori Sato } 1300e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1301e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1302e5918d7dSYoshinori Sato return true; 1303e5918d7dSYoshinori Sato } 1304e5918d7dSYoshinori Sato 1305e5918d7dSYoshinori Sato /* shll rs, rd */ 1306e5918d7dSYoshinori Sato static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1307e5918d7dSYoshinori Sato { 1308e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1309e5918d7dSYoshinori Sato TCGv count, tmp; 1310e5918d7dSYoshinori Sato 1311e5918d7dSYoshinori Sato noshift = gen_new_label(); 1312e5918d7dSYoshinori Sato done = gen_new_label(); 1313e5918d7dSYoshinori Sato /* if (cpu_regs[a->rs]) { */ 1314e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 131509374ee2SRichard Henderson count = tcg_temp_new(); 1316e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1317e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 131809374ee2SRichard Henderson tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); 1319e5918d7dSYoshinori Sato tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1320e5918d7dSYoshinori Sato tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1321e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1322e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1323e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1324e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1325e5918d7dSYoshinori Sato tcg_gen_br(done); 1326e5918d7dSYoshinori Sato /* } else { */ 1327e5918d7dSYoshinori Sato gen_set_label(noshift); 1328e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1329e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1330e5918d7dSYoshinori Sato /* } */ 1331e5918d7dSYoshinori Sato gen_set_label(done); 1332e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1333e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1334e5918d7dSYoshinori Sato return true; 1335e5918d7dSYoshinori Sato } 1336e5918d7dSYoshinori Sato 1337e5918d7dSYoshinori Sato static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1338e5918d7dSYoshinori Sato unsigned int alith) 1339e5918d7dSYoshinori Sato { 1340e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1341e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1342e5918d7dSYoshinori Sato }; 1343e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1344e5918d7dSYoshinori Sato if (imm) { 1345e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1346e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1347e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1348e5918d7dSYoshinori Sato } else { 1349e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1350e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1351e5918d7dSYoshinori Sato } 1352e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1353e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1354e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1355e5918d7dSYoshinori Sato } 1356e5918d7dSYoshinori Sato 1357e5918d7dSYoshinori Sato static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1358e5918d7dSYoshinori Sato { 1359e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1360e5918d7dSYoshinori Sato TCGv count; 1361e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1362e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1363e5918d7dSYoshinori Sato }; 1364e5918d7dSYoshinori Sato static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1365e5918d7dSYoshinori Sato tcg_gen_shr_i32, tcg_gen_sar_i32, 1366e5918d7dSYoshinori Sato }; 1367e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1368e5918d7dSYoshinori Sato noshift = gen_new_label(); 1369e5918d7dSYoshinori Sato done = gen_new_label(); 1370e5918d7dSYoshinori Sato count = tcg_temp_new(); 1371e5918d7dSYoshinori Sato /* if (cpu_regs[rs]) { */ 1372e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1373e5918d7dSYoshinori Sato tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1374e5918d7dSYoshinori Sato tcg_gen_subi_i32(count, count, 1); 1375e5918d7dSYoshinori Sato gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1376e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1377e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1378e5918d7dSYoshinori Sato tcg_gen_br(done); 1379e5918d7dSYoshinori Sato /* } else { */ 1380e5918d7dSYoshinori Sato gen_set_label(noshift); 1381e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1382e5918d7dSYoshinori Sato /* } */ 1383e5918d7dSYoshinori Sato gen_set_label(done); 1384e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1385e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1386e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1387e5918d7dSYoshinori Sato } 1388e5918d7dSYoshinori Sato 1389e5918d7dSYoshinori Sato /* shar #imm:5, rd */ 1390e5918d7dSYoshinori Sato /* shar #imm:5, rs2, rd */ 1391e5918d7dSYoshinori Sato static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1392e5918d7dSYoshinori Sato { 1393e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 1); 1394e5918d7dSYoshinori Sato return true; 1395e5918d7dSYoshinori Sato } 1396e5918d7dSYoshinori Sato 1397e5918d7dSYoshinori Sato /* shar rs, rd */ 1398e5918d7dSYoshinori Sato static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1399e5918d7dSYoshinori Sato { 1400e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 1); 1401e5918d7dSYoshinori Sato return true; 1402e5918d7dSYoshinori Sato } 1403e5918d7dSYoshinori Sato 1404e5918d7dSYoshinori Sato /* shlr #imm:5, rd */ 1405e5918d7dSYoshinori Sato /* shlr #imm:5, rs2, rd */ 1406e5918d7dSYoshinori Sato static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1407e5918d7dSYoshinori Sato { 1408e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 0); 1409e5918d7dSYoshinori Sato return true; 1410e5918d7dSYoshinori Sato } 1411e5918d7dSYoshinori Sato 1412e5918d7dSYoshinori Sato /* shlr rs, rd */ 1413e5918d7dSYoshinori Sato static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1414e5918d7dSYoshinori Sato { 1415e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 0); 1416e5918d7dSYoshinori Sato return true; 1417e5918d7dSYoshinori Sato } 1418e5918d7dSYoshinori Sato 1419e5918d7dSYoshinori Sato /* rolc rd */ 1420e5918d7dSYoshinori Sato static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1421e5918d7dSYoshinori Sato { 1422e5918d7dSYoshinori Sato TCGv tmp; 1423e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1424e5918d7dSYoshinori Sato tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1425e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1426e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1427e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1428e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1429e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1430e5918d7dSYoshinori Sato return true; 1431e5918d7dSYoshinori Sato } 1432e5918d7dSYoshinori Sato 1433e5918d7dSYoshinori Sato /* rorc rd */ 1434e5918d7dSYoshinori Sato static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1435e5918d7dSYoshinori Sato { 1436e5918d7dSYoshinori Sato TCGv tmp; 1437e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1438e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1439e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1440e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1441e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1442e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1443e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1444e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1445e5918d7dSYoshinori Sato return true; 1446e5918d7dSYoshinori Sato } 1447e5918d7dSYoshinori Sato 1448e5918d7dSYoshinori Sato enum {ROTR = 0, ROTL = 1}; 1449e5918d7dSYoshinori Sato enum {ROT_IMM = 0, ROT_REG = 1}; 1450e5918d7dSYoshinori Sato static inline void rx_rot(int ir, int dir, int rd, int src) 1451e5918d7dSYoshinori Sato { 1452e5918d7dSYoshinori Sato switch (dir) { 1453e5918d7dSYoshinori Sato case ROTL: 1454e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1455e5918d7dSYoshinori Sato tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1456e5918d7dSYoshinori Sato } else { 1457e5918d7dSYoshinori Sato tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1458e5918d7dSYoshinori Sato } 1459e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1460e5918d7dSYoshinori Sato break; 1461e5918d7dSYoshinori Sato case ROTR: 1462e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1463e5918d7dSYoshinori Sato tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1464e5918d7dSYoshinori Sato } else { 1465e5918d7dSYoshinori Sato tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1466e5918d7dSYoshinori Sato } 1467e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1468e5918d7dSYoshinori Sato break; 1469e5918d7dSYoshinori Sato } 1470e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1471e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1472e5918d7dSYoshinori Sato } 1473e5918d7dSYoshinori Sato 1474e5918d7dSYoshinori Sato /* rotl #imm, rd */ 1475e5918d7dSYoshinori Sato static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1476e5918d7dSYoshinori Sato { 1477e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1478e5918d7dSYoshinori Sato return true; 1479e5918d7dSYoshinori Sato } 1480e5918d7dSYoshinori Sato 1481e5918d7dSYoshinori Sato /* rotl rs, rd */ 1482e5918d7dSYoshinori Sato static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1483e5918d7dSYoshinori Sato { 1484e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1485e5918d7dSYoshinori Sato return true; 1486e5918d7dSYoshinori Sato } 1487e5918d7dSYoshinori Sato 1488e5918d7dSYoshinori Sato /* rotr #imm, rd */ 1489e5918d7dSYoshinori Sato static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1490e5918d7dSYoshinori Sato { 1491e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1492e5918d7dSYoshinori Sato return true; 1493e5918d7dSYoshinori Sato } 1494e5918d7dSYoshinori Sato 1495e5918d7dSYoshinori Sato /* rotr rs, rd */ 1496e5918d7dSYoshinori Sato static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1497e5918d7dSYoshinori Sato { 1498e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1499e5918d7dSYoshinori Sato return true; 1500e5918d7dSYoshinori Sato } 1501e5918d7dSYoshinori Sato 1502e5918d7dSYoshinori Sato /* revl rs, rd */ 1503e5918d7dSYoshinori Sato static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1504e5918d7dSYoshinori Sato { 1505e5918d7dSYoshinori Sato tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1506e5918d7dSYoshinori Sato return true; 1507e5918d7dSYoshinori Sato } 1508e5918d7dSYoshinori Sato 1509e5918d7dSYoshinori Sato /* revw rs, rd */ 1510e5918d7dSYoshinori Sato static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1511e5918d7dSYoshinori Sato { 1512e5918d7dSYoshinori Sato TCGv tmp; 1513e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1514e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1515e5918d7dSYoshinori Sato tcg_gen_shli_i32(tmp, tmp, 8); 1516e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1517e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1518e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1519e5918d7dSYoshinori Sato return true; 1520e5918d7dSYoshinori Sato } 1521e5918d7dSYoshinori Sato 1522e5918d7dSYoshinori Sato /* conditional branch helper */ 1523e5918d7dSYoshinori Sato static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1524e5918d7dSYoshinori Sato { 1525e5918d7dSYoshinori Sato DisasCompare dc; 1526e5918d7dSYoshinori Sato TCGLabel *t, *done; 1527e5918d7dSYoshinori Sato 1528e5918d7dSYoshinori Sato switch (cd) { 1529e5918d7dSYoshinori Sato case 0 ... 13: 1530e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 1531e5918d7dSYoshinori Sato psw_cond(&dc, cd); 1532e5918d7dSYoshinori Sato t = gen_new_label(); 1533e5918d7dSYoshinori Sato done = gen_new_label(); 1534e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1535e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->base.pc_next); 1536e5918d7dSYoshinori Sato tcg_gen_br(done); 1537e5918d7dSYoshinori Sato gen_set_label(t); 1538e5918d7dSYoshinori Sato gen_goto_tb(ctx, 1, ctx->pc + dst); 1539e5918d7dSYoshinori Sato gen_set_label(done); 1540e5918d7dSYoshinori Sato break; 1541e5918d7dSYoshinori Sato case 14: 1542e5918d7dSYoshinori Sato /* always true case */ 1543e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->pc + dst); 1544e5918d7dSYoshinori Sato break; 1545e5918d7dSYoshinori Sato case 15: 1546e5918d7dSYoshinori Sato /* always false case */ 1547e5918d7dSYoshinori Sato /* Nothing do */ 1548e5918d7dSYoshinori Sato break; 1549e5918d7dSYoshinori Sato } 1550e5918d7dSYoshinori Sato } 1551e5918d7dSYoshinori Sato 1552e5918d7dSYoshinori Sato /* beq dsp:3 / bne dsp:3 */ 1553e5918d7dSYoshinori Sato /* beq dsp:8 / bne dsp:8 */ 1554e5918d7dSYoshinori Sato /* bc dsp:8 / bnc dsp:8 */ 1555e5918d7dSYoshinori Sato /* bgtu dsp:8 / bleu dsp:8 */ 1556e5918d7dSYoshinori Sato /* bpz dsp:8 / bn dsp:8 */ 1557e5918d7dSYoshinori Sato /* bge dsp:8 / blt dsp:8 */ 1558e5918d7dSYoshinori Sato /* bgt dsp:8 / ble dsp:8 */ 1559e5918d7dSYoshinori Sato /* bo dsp:8 / bno dsp:8 */ 1560e5918d7dSYoshinori Sato /* beq dsp:16 / bne dsp:16 */ 1561e5918d7dSYoshinori Sato static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1562e5918d7dSYoshinori Sato { 1563e5918d7dSYoshinori Sato rx_bcnd_main(ctx, a->cd, a->dsp); 1564e5918d7dSYoshinori Sato return true; 1565e5918d7dSYoshinori Sato } 1566e5918d7dSYoshinori Sato 1567e5918d7dSYoshinori Sato /* bra dsp:3 */ 1568e5918d7dSYoshinori Sato /* bra dsp:8 */ 1569e5918d7dSYoshinori Sato /* bra dsp:16 */ 1570e5918d7dSYoshinori Sato /* bra dsp:24 */ 1571e5918d7dSYoshinori Sato static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1572e5918d7dSYoshinori Sato { 1573e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1574e5918d7dSYoshinori Sato return true; 1575e5918d7dSYoshinori Sato } 1576e5918d7dSYoshinori Sato 1577e5918d7dSYoshinori Sato /* bra rs */ 1578e5918d7dSYoshinori Sato static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1579e5918d7dSYoshinori Sato { 1580e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1581e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1582e5918d7dSYoshinori Sato return true; 1583e5918d7dSYoshinori Sato } 1584e5918d7dSYoshinori Sato 1585e5918d7dSYoshinori Sato static inline void rx_save_pc(DisasContext *ctx) 1586e5918d7dSYoshinori Sato { 1587daefc085SRichard Henderson TCGv pc = tcg_constant_i32(ctx->base.pc_next); 1588e5918d7dSYoshinori Sato push(pc); 1589e5918d7dSYoshinori Sato } 1590e5918d7dSYoshinori Sato 1591e5918d7dSYoshinori Sato /* jmp rs */ 1592e5918d7dSYoshinori Sato static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1593e5918d7dSYoshinori Sato { 1594e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1595e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1596e5918d7dSYoshinori Sato return true; 1597e5918d7dSYoshinori Sato } 1598e5918d7dSYoshinori Sato 1599e5918d7dSYoshinori Sato /* jsr rs */ 1600e5918d7dSYoshinori Sato static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1601e5918d7dSYoshinori Sato { 1602e5918d7dSYoshinori Sato rx_save_pc(ctx); 1603e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1604e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1605e5918d7dSYoshinori Sato return true; 1606e5918d7dSYoshinori Sato } 1607e5918d7dSYoshinori Sato 1608e5918d7dSYoshinori Sato /* bsr dsp:16 */ 1609e5918d7dSYoshinori Sato /* bsr dsp:24 */ 1610e5918d7dSYoshinori Sato static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1611e5918d7dSYoshinori Sato { 1612e5918d7dSYoshinori Sato rx_save_pc(ctx); 1613e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1614e5918d7dSYoshinori Sato return true; 1615e5918d7dSYoshinori Sato } 1616e5918d7dSYoshinori Sato 1617e5918d7dSYoshinori Sato /* bsr rs */ 1618e5918d7dSYoshinori Sato static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1619e5918d7dSYoshinori Sato { 1620e5918d7dSYoshinori Sato rx_save_pc(ctx); 1621e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1622e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1623e5918d7dSYoshinori Sato return true; 1624e5918d7dSYoshinori Sato } 1625e5918d7dSYoshinori Sato 1626e5918d7dSYoshinori Sato /* rts */ 1627e5918d7dSYoshinori Sato static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1628e5918d7dSYoshinori Sato { 1629e5918d7dSYoshinori Sato pop(cpu_pc); 1630e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1631e5918d7dSYoshinori Sato return true; 1632e5918d7dSYoshinori Sato } 1633e5918d7dSYoshinori Sato 1634e5918d7dSYoshinori Sato /* nop */ 1635e5918d7dSYoshinori Sato static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1636e5918d7dSYoshinori Sato { 1637e5918d7dSYoshinori Sato return true; 1638e5918d7dSYoshinori Sato } 1639e5918d7dSYoshinori Sato 1640e5918d7dSYoshinori Sato /* scmpu */ 1641e5918d7dSYoshinori Sato static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1642e5918d7dSYoshinori Sato { 1643ad75a51eSRichard Henderson gen_helper_scmpu(tcg_env); 1644e5918d7dSYoshinori Sato return true; 1645e5918d7dSYoshinori Sato } 1646e5918d7dSYoshinori Sato 1647e5918d7dSYoshinori Sato /* smovu */ 1648e5918d7dSYoshinori Sato static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1649e5918d7dSYoshinori Sato { 1650ad75a51eSRichard Henderson gen_helper_smovu(tcg_env); 1651e5918d7dSYoshinori Sato return true; 1652e5918d7dSYoshinori Sato } 1653e5918d7dSYoshinori Sato 1654e5918d7dSYoshinori Sato /* smovf */ 1655e5918d7dSYoshinori Sato static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1656e5918d7dSYoshinori Sato { 1657ad75a51eSRichard Henderson gen_helper_smovf(tcg_env); 1658e5918d7dSYoshinori Sato return true; 1659e5918d7dSYoshinori Sato } 1660e5918d7dSYoshinori Sato 1661e5918d7dSYoshinori Sato /* smovb */ 1662e5918d7dSYoshinori Sato static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1663e5918d7dSYoshinori Sato { 1664ad75a51eSRichard Henderson gen_helper_smovb(tcg_env); 1665e5918d7dSYoshinori Sato return true; 1666e5918d7dSYoshinori Sato } 1667e5918d7dSYoshinori Sato 1668e5918d7dSYoshinori Sato #define STRING(op) \ 1669e5918d7dSYoshinori Sato do { \ 1670daefc085SRichard Henderson TCGv size = tcg_constant_i32(a->sz); \ 1671ad75a51eSRichard Henderson gen_helper_##op(tcg_env, size); \ 1672e5918d7dSYoshinori Sato } while (0) 1673e5918d7dSYoshinori Sato 1674e5918d7dSYoshinori Sato /* suntile.<bwl> */ 1675e5918d7dSYoshinori Sato static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1676e5918d7dSYoshinori Sato { 1677e5918d7dSYoshinori Sato STRING(suntil); 1678e5918d7dSYoshinori Sato return true; 1679e5918d7dSYoshinori Sato } 1680e5918d7dSYoshinori Sato 1681e5918d7dSYoshinori Sato /* swhile.<bwl> */ 1682e5918d7dSYoshinori Sato static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1683e5918d7dSYoshinori Sato { 1684e5918d7dSYoshinori Sato STRING(swhile); 1685e5918d7dSYoshinori Sato return true; 1686e5918d7dSYoshinori Sato } 1687e5918d7dSYoshinori Sato /* sstr.<bwl> */ 1688e5918d7dSYoshinori Sato static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1689e5918d7dSYoshinori Sato { 1690e5918d7dSYoshinori Sato STRING(sstr); 1691e5918d7dSYoshinori Sato return true; 1692e5918d7dSYoshinori Sato } 1693e5918d7dSYoshinori Sato 1694e5918d7dSYoshinori Sato /* rmpa.<bwl> */ 1695e5918d7dSYoshinori Sato static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1696e5918d7dSYoshinori Sato { 1697e5918d7dSYoshinori Sato STRING(rmpa); 1698e5918d7dSYoshinori Sato return true; 1699e5918d7dSYoshinori Sato } 1700e5918d7dSYoshinori Sato 1701e5918d7dSYoshinori Sato static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1702e5918d7dSYoshinori Sato { 1703e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1704e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1705e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1706e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1707e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp0, tmp0, 16); 1708e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1709e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp1, tmp1, 16); 1710e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1711e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1712e5918d7dSYoshinori Sato } 1713e5918d7dSYoshinori Sato 1714e5918d7dSYoshinori Sato static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1715e5918d7dSYoshinori Sato { 1716e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1717e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1718e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1719e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1720e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp0, tmp0); 1721e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1722e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp1, tmp1); 1723e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1724e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1725e5918d7dSYoshinori Sato } 1726e5918d7dSYoshinori Sato 1727e5918d7dSYoshinori Sato /* mulhi rs,rs2 */ 1728e5918d7dSYoshinori Sato static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1729e5918d7dSYoshinori Sato { 1730e5918d7dSYoshinori Sato rx_mul64hi(cpu_acc, a->rs, a->rs2); 1731e5918d7dSYoshinori Sato return true; 1732e5918d7dSYoshinori Sato } 1733e5918d7dSYoshinori Sato 1734e5918d7dSYoshinori Sato /* mullo rs,rs2 */ 1735e5918d7dSYoshinori Sato static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1736e5918d7dSYoshinori Sato { 1737e5918d7dSYoshinori Sato rx_mul64lo(cpu_acc, a->rs, a->rs2); 1738e5918d7dSYoshinori Sato return true; 1739e5918d7dSYoshinori Sato } 1740e5918d7dSYoshinori Sato 1741e5918d7dSYoshinori Sato /* machi rs,rs2 */ 1742e5918d7dSYoshinori Sato static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1743e5918d7dSYoshinori Sato { 1744e5918d7dSYoshinori Sato TCGv_i64 tmp; 1745e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1746e5918d7dSYoshinori Sato rx_mul64hi(tmp, a->rs, a->rs2); 1747e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1748e5918d7dSYoshinori Sato return true; 1749e5918d7dSYoshinori Sato } 1750e5918d7dSYoshinori Sato 1751e5918d7dSYoshinori Sato /* maclo rs,rs2 */ 1752e5918d7dSYoshinori Sato static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1753e5918d7dSYoshinori Sato { 1754e5918d7dSYoshinori Sato TCGv_i64 tmp; 1755e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1756e5918d7dSYoshinori Sato rx_mul64lo(tmp, a->rs, a->rs2); 1757e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1758e5918d7dSYoshinori Sato return true; 1759e5918d7dSYoshinori Sato } 1760e5918d7dSYoshinori Sato 1761e5918d7dSYoshinori Sato /* mvfachi rd */ 1762e5918d7dSYoshinori Sato static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1763e5918d7dSYoshinori Sato { 1764e5918d7dSYoshinori Sato tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1765e5918d7dSYoshinori Sato return true; 1766e5918d7dSYoshinori Sato } 1767e5918d7dSYoshinori Sato 1768e5918d7dSYoshinori Sato /* mvfacmi rd */ 1769e5918d7dSYoshinori Sato static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1770e5918d7dSYoshinori Sato { 1771e5918d7dSYoshinori Sato TCGv_i64 rd64; 1772e5918d7dSYoshinori Sato rd64 = tcg_temp_new_i64(); 1773e5918d7dSYoshinori Sato tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1774e5918d7dSYoshinori Sato tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1775e5918d7dSYoshinori Sato return true; 1776e5918d7dSYoshinori Sato } 1777e5918d7dSYoshinori Sato 1778e5918d7dSYoshinori Sato /* mvtachi rs */ 1779e5918d7dSYoshinori Sato static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1780e5918d7dSYoshinori Sato { 1781e5918d7dSYoshinori Sato TCGv_i64 rs64; 1782e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1783e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1784e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1785e5918d7dSYoshinori Sato return true; 1786e5918d7dSYoshinori Sato } 1787e5918d7dSYoshinori Sato 1788e5918d7dSYoshinori Sato /* mvtaclo rs */ 1789e5918d7dSYoshinori Sato static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1790e5918d7dSYoshinori Sato { 1791e5918d7dSYoshinori Sato TCGv_i64 rs64; 1792e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1793e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1794e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1795e5918d7dSYoshinori Sato return true; 1796e5918d7dSYoshinori Sato } 1797e5918d7dSYoshinori Sato 1798e5918d7dSYoshinori Sato /* racw #imm */ 1799e5918d7dSYoshinori Sato static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1800e5918d7dSYoshinori Sato { 1801daefc085SRichard Henderson TCGv imm = tcg_constant_i32(a->imm + 1); 1802ad75a51eSRichard Henderson gen_helper_racw(tcg_env, imm); 1803e5918d7dSYoshinori Sato return true; 1804e5918d7dSYoshinori Sato } 1805e5918d7dSYoshinori Sato 1806e5918d7dSYoshinori Sato /* sat rd */ 1807e5918d7dSYoshinori Sato static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1808e5918d7dSYoshinori Sato { 1809e5918d7dSYoshinori Sato TCGv tmp, z; 1810e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1811daefc085SRichard Henderson z = tcg_constant_i32(0); 1812e5918d7dSYoshinori Sato /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1813e5918d7dSYoshinori Sato tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1814e5918d7dSYoshinori Sato /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1815e5918d7dSYoshinori Sato tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1816e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1817e5918d7dSYoshinori Sato cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1818e5918d7dSYoshinori Sato return true; 1819e5918d7dSYoshinori Sato } 1820e5918d7dSYoshinori Sato 1821e5918d7dSYoshinori Sato /* satr */ 1822e5918d7dSYoshinori Sato static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1823e5918d7dSYoshinori Sato { 1824ad75a51eSRichard Henderson gen_helper_satr(tcg_env); 1825e5918d7dSYoshinori Sato return true; 1826e5918d7dSYoshinori Sato } 1827e5918d7dSYoshinori Sato 1828e5918d7dSYoshinori Sato #define cat3(a, b, c) a##b##c 1829e5918d7dSYoshinori Sato #define FOP(name, op) \ 1830e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1831e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 1832e5918d7dSYoshinori Sato { \ 1833daefc085SRichard Henderson TCGv imm = tcg_constant_i32(li(ctx, 0)); \ 1834ad75a51eSRichard Henderson gen_helper_##op(cpu_regs[a->rd], tcg_env, \ 1835e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); \ 1836e5918d7dSYoshinori Sato return true; \ 1837e5918d7dSYoshinori Sato } \ 1838e5918d7dSYoshinori Sato static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1839e5918d7dSYoshinori Sato cat3(arg_, name, _mr) * a) \ 1840e5918d7dSYoshinori Sato { \ 1841e5918d7dSYoshinori Sato TCGv val, mem; \ 1842e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1843e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1844ad75a51eSRichard Henderson gen_helper_##op(cpu_regs[a->rd], tcg_env, \ 1845e5918d7dSYoshinori Sato cpu_regs[a->rd], val); \ 1846e5918d7dSYoshinori Sato return true; \ 1847e5918d7dSYoshinori Sato } 1848e5918d7dSYoshinori Sato 1849e5918d7dSYoshinori Sato #define FCONVOP(name, op) \ 1850e5918d7dSYoshinori Sato static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1851e5918d7dSYoshinori Sato { \ 1852e5918d7dSYoshinori Sato TCGv val, mem; \ 1853e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1854e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1855ad75a51eSRichard Henderson gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \ 1856e5918d7dSYoshinori Sato return true; \ 1857e5918d7dSYoshinori Sato } 1858e5918d7dSYoshinori Sato 1859e5918d7dSYoshinori Sato FOP(FADD, fadd) 1860e5918d7dSYoshinori Sato FOP(FSUB, fsub) 1861e5918d7dSYoshinori Sato FOP(FMUL, fmul) 1862e5918d7dSYoshinori Sato FOP(FDIV, fdiv) 1863e5918d7dSYoshinori Sato 1864e5918d7dSYoshinori Sato /* fcmp #imm, rd */ 1865e5918d7dSYoshinori Sato static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1866e5918d7dSYoshinori Sato { 1867daefc085SRichard Henderson TCGv imm = tcg_constant_i32(li(ctx, 0)); 1868ad75a51eSRichard Henderson gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); 1869e5918d7dSYoshinori Sato return true; 1870e5918d7dSYoshinori Sato } 1871e5918d7dSYoshinori Sato 1872e5918d7dSYoshinori Sato /* fcmp dsp[rs], rd */ 1873e5918d7dSYoshinori Sato /* fcmp rs, rd */ 1874e5918d7dSYoshinori Sato static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1875e5918d7dSYoshinori Sato { 1876e5918d7dSYoshinori Sato TCGv val, mem; 1877e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1878e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1879ad75a51eSRichard Henderson gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); 1880e5918d7dSYoshinori Sato return true; 1881e5918d7dSYoshinori Sato } 1882e5918d7dSYoshinori Sato 1883e5918d7dSYoshinori Sato FCONVOP(FTOI, ftoi) 1884e5918d7dSYoshinori Sato FCONVOP(ROUND, round) 1885e5918d7dSYoshinori Sato 1886e5918d7dSYoshinori Sato /* itof rs, rd */ 1887e5918d7dSYoshinori Sato /* itof dsp[rs], rd */ 1888e5918d7dSYoshinori Sato static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1889e5918d7dSYoshinori Sato { 1890e5918d7dSYoshinori Sato TCGv val, mem; 1891e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1892e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1893ad75a51eSRichard Henderson gen_helper_itof(cpu_regs[a->rd], tcg_env, val); 1894e5918d7dSYoshinori Sato return true; 1895e5918d7dSYoshinori Sato } 1896e5918d7dSYoshinori Sato 1897e5918d7dSYoshinori Sato static void rx_bsetm(TCGv mem, TCGv mask) 1898e5918d7dSYoshinori Sato { 1899e5918d7dSYoshinori Sato TCGv val; 1900e5918d7dSYoshinori Sato val = tcg_temp_new(); 1901e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1902e5918d7dSYoshinori Sato tcg_gen_or_i32(val, val, mask); 1903e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1904e5918d7dSYoshinori Sato } 1905e5918d7dSYoshinori Sato 1906e5918d7dSYoshinori Sato static void rx_bclrm(TCGv mem, TCGv mask) 1907e5918d7dSYoshinori Sato { 1908e5918d7dSYoshinori Sato TCGv val; 1909e5918d7dSYoshinori Sato val = tcg_temp_new(); 1910e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1911e5918d7dSYoshinori Sato tcg_gen_andc_i32(val, val, mask); 1912e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1913e5918d7dSYoshinori Sato } 1914e5918d7dSYoshinori Sato 1915e5918d7dSYoshinori Sato static void rx_btstm(TCGv mem, TCGv mask) 1916e5918d7dSYoshinori Sato { 1917e5918d7dSYoshinori Sato TCGv val; 1918e5918d7dSYoshinori Sato val = tcg_temp_new(); 1919e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1920e5918d7dSYoshinori Sato tcg_gen_and_i32(val, val, mask); 1921e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 1922e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1923e5918d7dSYoshinori Sato } 1924e5918d7dSYoshinori Sato 1925e5918d7dSYoshinori Sato static void rx_bnotm(TCGv mem, TCGv mask) 1926e5918d7dSYoshinori Sato { 1927e5918d7dSYoshinori Sato TCGv val; 1928e5918d7dSYoshinori Sato val = tcg_temp_new(); 1929e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1930e5918d7dSYoshinori Sato tcg_gen_xor_i32(val, val, mask); 1931e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1932e5918d7dSYoshinori Sato } 1933e5918d7dSYoshinori Sato 1934e5918d7dSYoshinori Sato static void rx_bsetr(TCGv reg, TCGv mask) 1935e5918d7dSYoshinori Sato { 1936e5918d7dSYoshinori Sato tcg_gen_or_i32(reg, reg, mask); 1937e5918d7dSYoshinori Sato } 1938e5918d7dSYoshinori Sato 1939e5918d7dSYoshinori Sato static void rx_bclrr(TCGv reg, TCGv mask) 1940e5918d7dSYoshinori Sato { 1941e5918d7dSYoshinori Sato tcg_gen_andc_i32(reg, reg, mask); 1942e5918d7dSYoshinori Sato } 1943e5918d7dSYoshinori Sato 1944e5918d7dSYoshinori Sato static inline void rx_btstr(TCGv reg, TCGv mask) 1945e5918d7dSYoshinori Sato { 1946e5918d7dSYoshinori Sato TCGv t0; 1947e5918d7dSYoshinori Sato t0 = tcg_temp_new(); 1948e5918d7dSYoshinori Sato tcg_gen_and_i32(t0, reg, mask); 1949e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 1950e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1951e5918d7dSYoshinori Sato } 1952e5918d7dSYoshinori Sato 1953e5918d7dSYoshinori Sato static inline void rx_bnotr(TCGv reg, TCGv mask) 1954e5918d7dSYoshinori Sato { 1955e5918d7dSYoshinori Sato tcg_gen_xor_i32(reg, reg, mask); 1956e5918d7dSYoshinori Sato } 1957e5918d7dSYoshinori Sato 1958e5918d7dSYoshinori Sato #define BITOP(name, op) \ 1959e5918d7dSYoshinori Sato static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 1960e5918d7dSYoshinori Sato cat3(arg_, name, _im) * a) \ 1961e5918d7dSYoshinori Sato { \ 1962e5918d7dSYoshinori Sato TCGv mask, mem, addr; \ 1963e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1964daefc085SRichard Henderson mask = tcg_constant_i32(1 << a->imm); \ 1965e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1966e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 1967e5918d7dSYoshinori Sato return true; \ 1968e5918d7dSYoshinori Sato } \ 1969e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1970e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 1971e5918d7dSYoshinori Sato { \ 1972e5918d7dSYoshinori Sato TCGv mask; \ 1973daefc085SRichard Henderson mask = tcg_constant_i32(1 << a->imm); \ 1974e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1975e5918d7dSYoshinori Sato return true; \ 1976e5918d7dSYoshinori Sato } \ 1977e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 1978e5918d7dSYoshinori Sato cat3(arg_, name, _rr) * a) \ 1979e5918d7dSYoshinori Sato { \ 1980e5918d7dSYoshinori Sato TCGv mask, b; \ 198109374ee2SRichard Henderson mask = tcg_temp_new(); \ 1982e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 1983e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 198409374ee2SRichard Henderson tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1985e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1986e5918d7dSYoshinori Sato return true; \ 1987e5918d7dSYoshinori Sato } \ 1988e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 1989e5918d7dSYoshinori Sato cat3(arg_, name, _rm) * a) \ 1990e5918d7dSYoshinori Sato { \ 1991e5918d7dSYoshinori Sato TCGv mask, mem, addr, b; \ 199209374ee2SRichard Henderson mask = tcg_temp_new(); \ 1993e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 1994e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 199509374ee2SRichard Henderson tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1996e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1997e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1998e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 1999e5918d7dSYoshinori Sato return true; \ 2000e5918d7dSYoshinori Sato } 2001e5918d7dSYoshinori Sato 2002e5918d7dSYoshinori Sato BITOP(BSET, bset) 2003e5918d7dSYoshinori Sato BITOP(BCLR, bclr) 2004e5918d7dSYoshinori Sato BITOP(BTST, btst) 2005e5918d7dSYoshinori Sato BITOP(BNOT, bnot) 2006e5918d7dSYoshinori Sato 2007e5918d7dSYoshinori Sato static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2008e5918d7dSYoshinori Sato { 2009e5918d7dSYoshinori Sato TCGv bit; 2010e5918d7dSYoshinori Sato DisasCompare dc; 2011e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 2012e5918d7dSYoshinori Sato bit = tcg_temp_new(); 2013e5918d7dSYoshinori Sato psw_cond(&dc, cond); 2014e5918d7dSYoshinori Sato tcg_gen_andi_i32(val, val, ~(1 << pos)); 2015e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2016e5918d7dSYoshinori Sato tcg_gen_deposit_i32(val, val, bit, pos, 1); 2017e5918d7dSYoshinori Sato } 2018e5918d7dSYoshinori Sato 2019e5918d7dSYoshinori Sato /* bmcnd #imm, dsp[rd] */ 2020e5918d7dSYoshinori Sato static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2021e5918d7dSYoshinori Sato { 2022e5918d7dSYoshinori Sato TCGv val, mem, addr; 2023e5918d7dSYoshinori Sato val = tcg_temp_new(); 2024e5918d7dSYoshinori Sato mem = tcg_temp_new(); 2025e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2026e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, addr); 2027e5918d7dSYoshinori Sato bmcnd_op(val, a->cd, a->imm); 2028e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, addr); 2029e5918d7dSYoshinori Sato return true; 2030e5918d7dSYoshinori Sato } 2031e5918d7dSYoshinori Sato 2032e5918d7dSYoshinori Sato /* bmcond #imm, rd */ 2033e5918d7dSYoshinori Sato static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2034e5918d7dSYoshinori Sato { 2035e5918d7dSYoshinori Sato bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2036e5918d7dSYoshinori Sato return true; 2037e5918d7dSYoshinori Sato } 2038e5918d7dSYoshinori Sato 2039e5918d7dSYoshinori Sato enum { 2040e5918d7dSYoshinori Sato PSW_C = 0, 2041e5918d7dSYoshinori Sato PSW_Z = 1, 2042e5918d7dSYoshinori Sato PSW_S = 2, 2043e5918d7dSYoshinori Sato PSW_O = 3, 2044e5918d7dSYoshinori Sato PSW_I = 8, 2045e5918d7dSYoshinori Sato PSW_U = 9, 2046e5918d7dSYoshinori Sato }; 2047e5918d7dSYoshinori Sato 2048e5918d7dSYoshinori Sato static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2049e5918d7dSYoshinori Sato { 2050e5918d7dSYoshinori Sato if (cb < 8) { 2051e5918d7dSYoshinori Sato switch (cb) { 2052e5918d7dSYoshinori Sato case PSW_C: 2053e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, val); 2054e5918d7dSYoshinori Sato break; 2055e5918d7dSYoshinori Sato case PSW_Z: 2056e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_z, val == 0); 2057e5918d7dSYoshinori Sato break; 2058e5918d7dSYoshinori Sato case PSW_S: 2059e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2060e5918d7dSYoshinori Sato break; 2061e5918d7dSYoshinori Sato case PSW_O: 2062e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, val << 31); 2063e5918d7dSYoshinori Sato break; 2064e5918d7dSYoshinori Sato default: 20658b81968cSMichael Tokarev qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); 2066e5918d7dSYoshinori Sato break; 2067e5918d7dSYoshinori Sato } 2068e5918d7dSYoshinori Sato } else if (is_privileged(ctx, 0)) { 2069e5918d7dSYoshinori Sato switch (cb) { 2070e5918d7dSYoshinori Sato case PSW_I: 2071e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_i, val); 2072e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2073e5918d7dSYoshinori Sato break; 2074e5918d7dSYoshinori Sato case PSW_U: 20753c69336aSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { 20763c69336aSRichard Henderson ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); 2077e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_u, val); 20783c69336aSRichard Henderson tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); 20793c69336aSRichard Henderson tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); 20803c69336aSRichard Henderson } 2081e5918d7dSYoshinori Sato break; 2082e5918d7dSYoshinori Sato default: 20838b81968cSMichael Tokarev qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); 2084e5918d7dSYoshinori Sato break; 2085e5918d7dSYoshinori Sato } 2086e5918d7dSYoshinori Sato } 2087e5918d7dSYoshinori Sato } 2088e5918d7dSYoshinori Sato 2089e5918d7dSYoshinori Sato /* clrpsw psw */ 2090e5918d7dSYoshinori Sato static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2091e5918d7dSYoshinori Sato { 2092e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 0); 2093e5918d7dSYoshinori Sato return true; 2094e5918d7dSYoshinori Sato } 2095e5918d7dSYoshinori Sato 2096e5918d7dSYoshinori Sato /* setpsw psw */ 2097e5918d7dSYoshinori Sato static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2098e5918d7dSYoshinori Sato { 2099e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 1); 2100e5918d7dSYoshinori Sato return true; 2101e5918d7dSYoshinori Sato } 2102e5918d7dSYoshinori Sato 2103e5918d7dSYoshinori Sato /* mvtipl #imm */ 2104e5918d7dSYoshinori Sato static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2105e5918d7dSYoshinori Sato { 2106e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2107e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2108e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2109e5918d7dSYoshinori Sato } 2110e5918d7dSYoshinori Sato return true; 2111e5918d7dSYoshinori Sato } 2112e5918d7dSYoshinori Sato 2113e5918d7dSYoshinori Sato /* mvtc #imm, rd */ 2114e5918d7dSYoshinori Sato static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2115e5918d7dSYoshinori Sato { 2116e5918d7dSYoshinori Sato TCGv imm; 2117e5918d7dSYoshinori Sato 2118daefc085SRichard Henderson imm = tcg_constant_i32(a->imm); 2119e5918d7dSYoshinori Sato move_to_cr(ctx, imm, a->cr); 2120e5918d7dSYoshinori Sato return true; 2121e5918d7dSYoshinori Sato } 2122e5918d7dSYoshinori Sato 2123e5918d7dSYoshinori Sato /* mvtc rs, rd */ 2124e5918d7dSYoshinori Sato static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2125e5918d7dSYoshinori Sato { 2126e5918d7dSYoshinori Sato move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2127e5918d7dSYoshinori Sato return true; 2128e5918d7dSYoshinori Sato } 2129e5918d7dSYoshinori Sato 2130e5918d7dSYoshinori Sato /* mvfc rs, rd */ 2131e5918d7dSYoshinori Sato static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2132e5918d7dSYoshinori Sato { 21333626a3feSRichard Henderson move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); 2134e5918d7dSYoshinori Sato return true; 2135e5918d7dSYoshinori Sato } 2136e5918d7dSYoshinori Sato 2137e5918d7dSYoshinori Sato /* rtfi */ 2138e5918d7dSYoshinori Sato static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2139e5918d7dSYoshinori Sato { 2140e5918d7dSYoshinori Sato TCGv psw; 2141e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2142e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2143e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2144e5918d7dSYoshinori Sato tcg_gen_mov_i32(psw, cpu_bpsw); 2145ad75a51eSRichard Henderson gen_helper_set_psw_rte(tcg_env, psw); 2146e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2147e5918d7dSYoshinori Sato } 2148e5918d7dSYoshinori Sato return true; 2149e5918d7dSYoshinori Sato } 2150e5918d7dSYoshinori Sato 2151e5918d7dSYoshinori Sato /* rte */ 2152e5918d7dSYoshinori Sato static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2153e5918d7dSYoshinori Sato { 2154e5918d7dSYoshinori Sato TCGv psw; 2155e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2156e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2157e5918d7dSYoshinori Sato pop(cpu_pc); 2158e5918d7dSYoshinori Sato pop(psw); 2159ad75a51eSRichard Henderson gen_helper_set_psw_rte(tcg_env, psw); 2160e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2161e5918d7dSYoshinori Sato } 2162e5918d7dSYoshinori Sato return true; 2163e5918d7dSYoshinori Sato } 2164e5918d7dSYoshinori Sato 2165e5918d7dSYoshinori Sato /* brk */ 2166e5918d7dSYoshinori Sato static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2167e5918d7dSYoshinori Sato { 2168e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2169ad75a51eSRichard Henderson gen_helper_rxbrk(tcg_env); 2170e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2171e5918d7dSYoshinori Sato return true; 2172e5918d7dSYoshinori Sato } 2173e5918d7dSYoshinori Sato 2174e5918d7dSYoshinori Sato /* int #imm */ 2175e5918d7dSYoshinori Sato static bool trans_INT(DisasContext *ctx, arg_INT *a) 2176e5918d7dSYoshinori Sato { 2177e5918d7dSYoshinori Sato TCGv vec; 2178e5918d7dSYoshinori Sato 2179e5918d7dSYoshinori Sato tcg_debug_assert(a->imm < 0x100); 2180daefc085SRichard Henderson vec = tcg_constant_i32(a->imm); 2181e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2182ad75a51eSRichard Henderson gen_helper_rxint(tcg_env, vec); 2183e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2184e5918d7dSYoshinori Sato return true; 2185e5918d7dSYoshinori Sato } 2186e5918d7dSYoshinori Sato 2187e5918d7dSYoshinori Sato /* wait */ 2188e5918d7dSYoshinori Sato static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2189e5918d7dSYoshinori Sato { 2190e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2191724eaeceSTomoaki Kawada tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2192ad75a51eSRichard Henderson gen_helper_wait(tcg_env); 2193e5918d7dSYoshinori Sato } 2194e5918d7dSYoshinori Sato return true; 2195e5918d7dSYoshinori Sato } 2196e5918d7dSYoshinori Sato 2197e5918d7dSYoshinori Sato static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2198e5918d7dSYoshinori Sato { 2199e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 220094956d7bSPhilippe Mathieu-Daudé ctx->env = cpu_env(cs); 22014341631eSRichard Henderson ctx->tb_flags = ctx->base.tb->flags; 2202e5918d7dSYoshinori Sato } 2203e5918d7dSYoshinori Sato 2204e5918d7dSYoshinori Sato static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2205e5918d7dSYoshinori Sato { 2206e5918d7dSYoshinori Sato } 2207e5918d7dSYoshinori Sato 2208e5918d7dSYoshinori Sato static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2209e5918d7dSYoshinori Sato { 2210e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2211e5918d7dSYoshinori Sato 2212e5918d7dSYoshinori Sato tcg_gen_insn_start(ctx->base.pc_next); 2213e5918d7dSYoshinori Sato } 2214e5918d7dSYoshinori Sato 2215e5918d7dSYoshinori Sato static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2216e5918d7dSYoshinori Sato { 2217e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2218e5918d7dSYoshinori Sato uint32_t insn; 2219e5918d7dSYoshinori Sato 2220e5918d7dSYoshinori Sato ctx->pc = ctx->base.pc_next; 2221e5918d7dSYoshinori Sato insn = decode_load(ctx); 2222e5918d7dSYoshinori Sato if (!decode(ctx, insn)) { 2223ad75a51eSRichard Henderson gen_helper_raise_illegal_instruction(tcg_env); 2224e5918d7dSYoshinori Sato } 2225e5918d7dSYoshinori Sato } 2226e5918d7dSYoshinori Sato 2227e5918d7dSYoshinori Sato static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2228e5918d7dSYoshinori Sato { 2229e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2230e5918d7dSYoshinori Sato 2231e5918d7dSYoshinori Sato switch (ctx->base.is_jmp) { 2232e5918d7dSYoshinori Sato case DISAS_NEXT: 2233e5918d7dSYoshinori Sato case DISAS_TOO_MANY: 2234e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, dcbase->pc_next); 2235e5918d7dSYoshinori Sato break; 2236e5918d7dSYoshinori Sato case DISAS_JUMP: 2237e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 2238e5918d7dSYoshinori Sato break; 2239e5918d7dSYoshinori Sato case DISAS_UPDATE: 2240e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 224140bd0502SPhilippe Mathieu-Daudé /* fall through */ 2242e5918d7dSYoshinori Sato case DISAS_EXIT: 2243e5918d7dSYoshinori Sato tcg_gen_exit_tb(NULL, 0); 2244e5918d7dSYoshinori Sato break; 2245e5918d7dSYoshinori Sato case DISAS_NORETURN: 2246e5918d7dSYoshinori Sato break; 2247e5918d7dSYoshinori Sato default: 2248e5918d7dSYoshinori Sato g_assert_not_reached(); 2249e5918d7dSYoshinori Sato } 2250e5918d7dSYoshinori Sato } 2251e5918d7dSYoshinori Sato 2252e5918d7dSYoshinori Sato static const TranslatorOps rx_tr_ops = { 2253e5918d7dSYoshinori Sato .init_disas_context = rx_tr_init_disas_context, 2254e5918d7dSYoshinori Sato .tb_start = rx_tr_tb_start, 2255e5918d7dSYoshinori Sato .insn_start = rx_tr_insn_start, 2256e5918d7dSYoshinori Sato .translate_insn = rx_tr_translate_insn, 2257e5918d7dSYoshinori Sato .tb_stop = rx_tr_tb_stop, 2258e5918d7dSYoshinori Sato }; 2259e5918d7dSYoshinori Sato 2260597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 226132f0c394SAnton Johansson vaddr pc, void *host_pc) 2262e5918d7dSYoshinori Sato { 2263e5918d7dSYoshinori Sato DisasContext dc; 2264e5918d7dSYoshinori Sato 2265306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); 2266e5918d7dSYoshinori Sato } 2267e5918d7dSYoshinori Sato 2268e5918d7dSYoshinori Sato #define ALLOC_REGISTER(sym, name) \ 2269ad75a51eSRichard Henderson cpu_##sym = tcg_global_mem_new_i32(tcg_env, \ 2270e5918d7dSYoshinori Sato offsetof(CPURXState, sym), name) 2271e5918d7dSYoshinori Sato 2272e5918d7dSYoshinori Sato void rx_translate_init(void) 2273e5918d7dSYoshinori Sato { 2274e5918d7dSYoshinori Sato static const char * const regnames[NUM_REGS] = { 2275e5918d7dSYoshinori Sato "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2276e5918d7dSYoshinori Sato "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2277e5918d7dSYoshinori Sato }; 2278e5918d7dSYoshinori Sato int i; 2279e5918d7dSYoshinori Sato 2280e5918d7dSYoshinori Sato for (i = 0; i < NUM_REGS; i++) { 2281ad75a51eSRichard Henderson cpu_regs[i] = tcg_global_mem_new_i32(tcg_env, 2282e5918d7dSYoshinori Sato offsetof(CPURXState, regs[i]), 2283e5918d7dSYoshinori Sato regnames[i]); 2284e5918d7dSYoshinori Sato } 2285e5918d7dSYoshinori Sato ALLOC_REGISTER(pc, "PC"); 2286e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_o, "PSW(O)"); 2287e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_s, "PSW(S)"); 2288e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_z, "PSW(Z)"); 2289e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_c, "PSW(C)"); 2290e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_u, "PSW(U)"); 2291e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_i, "PSW(I)"); 2292e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2293e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2294e5918d7dSYoshinori Sato ALLOC_REGISTER(usp, "USP"); 2295e5918d7dSYoshinori Sato ALLOC_REGISTER(fpsw, "FPSW"); 2296e5918d7dSYoshinori Sato ALLOC_REGISTER(bpsw, "BPSW"); 2297e5918d7dSYoshinori Sato ALLOC_REGISTER(bpc, "BPC"); 2298e5918d7dSYoshinori Sato ALLOC_REGISTER(isp, "ISP"); 2299e5918d7dSYoshinori Sato ALLOC_REGISTER(fintv, "FINTV"); 2300e5918d7dSYoshinori Sato ALLOC_REGISTER(intb, "INTB"); 2301ad75a51eSRichard Henderson cpu_acc = tcg_global_mem_new_i64(tcg_env, 2302e5918d7dSYoshinori Sato offsetof(CPURXState, acc), "ACC"); 2303e5918d7dSYoshinori Sato } 2304