1 /* 2 * RX emulation 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "cpu.h" 22 #include "exec/log.h" 23 #include "exec/cpu_ldst.h" 24 #include "hw/irq.h" 25 26 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) 27 { 28 if (env->psw_pm == 0) { 29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); 30 if (rte) { 31 /* PSW.PM can write RTE and RTFI */ 32 env->psw_pm = FIELD_EX32(psw, PSW, PM); 33 } 34 env->psw_u = FIELD_EX32(psw, PSW, U); 35 env->psw_i = FIELD_EX32(psw, PSW, I); 36 } 37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; 38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; 39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); 40 env->psw_c = FIELD_EX32(psw, PSW, C); 41 } 42 43 #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) 44 void rx_cpu_do_interrupt(CPUState *cs) 45 { 46 CPURXState *env = cpu_env(cs); 47 int do_irq = cs->interrupt_request & INT_FLAGS; 48 uint32_t save_psw; 49 50 env->in_sleep = 0; 51 52 if (env->psw_u) { 53 env->usp = env->regs[0]; 54 } else { 55 env->isp = env->regs[0]; 56 } 57 save_psw = rx_cpu_pack_psw(env); 58 env->psw_pm = env->psw_i = env->psw_u = 0; 59 60 if (do_irq) { 61 if (do_irq & CPU_INTERRUPT_FIR) { 62 env->bpc = env->pc; 63 env->bpsw = save_psw; 64 env->pc = env->fintv; 65 env->psw_ipl = 15; 66 cs->interrupt_request &= ~CPU_INTERRUPT_FIR; 67 qemu_set_irq(env->ack, env->ack_irq); 68 qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); 69 } else if (do_irq & CPU_INTERRUPT_HARD) { 70 env->isp -= 4; 71 cpu_stl_data(env, env->isp, save_psw); 72 env->isp -= 4; 73 cpu_stl_data(env, env->isp, env->pc); 74 env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4); 75 env->psw_ipl = env->ack_ipl; 76 cs->interrupt_request &= ~CPU_INTERRUPT_HARD; 77 qemu_set_irq(env->ack, env->ack_irq); 78 qemu_log_mask(CPU_LOG_INT, 79 "interrupt 0x%02x raised\n", env->ack_irq); 80 } 81 } else { 82 uint32_t vec = cs->exception_index; 83 const char *expname = "unknown exception"; 84 85 env->isp -= 4; 86 cpu_stl_data(env, env->isp, save_psw); 87 env->isp -= 4; 88 cpu_stl_data(env, env->isp, env->pc); 89 90 if (vec < 0x100) { 91 env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4); 92 } else { 93 env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); 94 } 95 switch (vec) { 96 case 20: 97 expname = "privilege violation"; 98 break; 99 case 21: 100 expname = "access exception"; 101 break; 102 case 23: 103 expname = "illegal instruction"; 104 break; 105 case 25: 106 expname = "fpu exception"; 107 break; 108 case 30: 109 expname = "non-maskable interrupt"; 110 break; 111 case 0x100 ... 0x1ff: 112 expname = "unconditional trap"; 113 } 114 qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", 115 (vec & 0xff), expname); 116 } 117 env->regs[0] = env->isp; 118 } 119 120 bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 121 { 122 CPURXState *env = cpu_env(cs); 123 int accept = 0; 124 /* hardware interrupt (Normal) */ 125 if ((interrupt_request & CPU_INTERRUPT_HARD) && 126 env->psw_i && (env->psw_ipl < env->req_ipl)) { 127 env->ack_irq = env->req_irq; 128 env->ack_ipl = env->req_ipl; 129 accept = 1; 130 } 131 /* hardware interrupt (FIR) */ 132 if ((interrupt_request & CPU_INTERRUPT_FIR) && 133 env->psw_i && (env->psw_ipl < 15)) { 134 accept = 1; 135 } 136 if (accept) { 137 rx_cpu_do_interrupt(cs); 138 return true; 139 } 140 return false; 141 } 142 143 hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 144 { 145 return addr; 146 } 147