1 /* 2 * RX emulation definition 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RX_CPU_H 20 #define RX_CPU_H 21 22 #include "qemu/bitops.h" 23 #include "hw/registerfields.h" 24 #include "cpu-qom.h" 25 26 #include "exec/cpu-common.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/cpu-interrupt.h" 29 #include "qemu/cpu-float.h" 30 31 #ifdef CONFIG_USER_ONLY 32 #error "RX does not support user mode emulation" 33 #endif 34 35 /* PSW define */ 36 REG32(PSW, 0) 37 FIELD(PSW, C, 0, 1) 38 FIELD(PSW, Z, 1, 1) 39 FIELD(PSW, S, 2, 1) 40 FIELD(PSW, O, 3, 1) 41 FIELD(PSW, I, 16, 1) 42 FIELD(PSW, U, 17, 1) 43 FIELD(PSW, PM, 20, 1) 44 FIELD(PSW, IPL, 24, 4) 45 46 /* FPSW define */ 47 REG32(FPSW, 0) 48 FIELD(FPSW, RM, 0, 2) 49 FIELD(FPSW, CV, 2, 1) 50 FIELD(FPSW, CO, 3, 1) 51 FIELD(FPSW, CZ, 4, 1) 52 FIELD(FPSW, CU, 5, 1) 53 FIELD(FPSW, CX, 6, 1) 54 FIELD(FPSW, CE, 7, 1) 55 FIELD(FPSW, CAUSE, 2, 6) 56 FIELD(FPSW, DN, 8, 1) 57 FIELD(FPSW, EV, 10, 1) 58 FIELD(FPSW, EO, 11, 1) 59 FIELD(FPSW, EZ, 12, 1) 60 FIELD(FPSW, EU, 13, 1) 61 FIELD(FPSW, EX, 14, 1) 62 FIELD(FPSW, ENABLE, 10, 5) 63 FIELD(FPSW, FV, 26, 1) 64 FIELD(FPSW, FO, 27, 1) 65 FIELD(FPSW, FZ, 28, 1) 66 FIELD(FPSW, FU, 29, 1) 67 FIELD(FPSW, FX, 30, 1) 68 FIELD(FPSW, FLAGS, 26, 4) 69 FIELD(FPSW, FS, 31, 1) 70 71 enum { 72 NUM_REGS = 16, 73 }; 74 75 typedef struct CPUArchState { 76 /* CPU registers */ 77 uint32_t regs[NUM_REGS]; /* general registers */ 78 uint32_t psw_o; /* O bit of status register */ 79 uint32_t psw_s; /* S bit of status register */ 80 uint32_t psw_z; /* Z bit of status register */ 81 uint32_t psw_c; /* C bit of status register */ 82 uint32_t psw_u; 83 uint32_t psw_i; 84 uint32_t psw_pm; 85 uint32_t psw_ipl; 86 uint32_t bpsw; /* backup status */ 87 uint32_t bpc; /* backup pc */ 88 uint32_t isp; /* global base register */ 89 uint32_t usp; /* vector base register */ 90 uint32_t pc; /* program counter */ 91 uint32_t intb; /* interrupt vector */ 92 uint32_t fintv; 93 uint32_t fpsw; 94 uint64_t acc; 95 96 /* Fields up to this point are cleared by a CPU reset */ 97 struct {} end_reset_fields; 98 99 /* Internal use */ 100 uint32_t in_sleep; 101 uint32_t req_irq; /* Requested interrupt no (hard) */ 102 uint32_t req_ipl; /* Requested interrupt level */ 103 uint32_t ack_irq; /* execute irq */ 104 uint32_t ack_ipl; /* execute ipl */ 105 float_status fp_status; 106 qemu_irq ack; /* Interrupt acknowledge */ 107 } CPURXState; 108 109 /* 110 * RXCPU: 111 * @env: #CPURXState 112 * 113 * A RX CPU 114 */ 115 struct ArchCPU { 116 CPUState parent_obj; 117 118 CPURXState env; 119 }; 120 121 /* 122 * RXCPUClass: 123 * @parent_realize: The parent class' realize handler. 124 * @parent_phases: The parent class' reset phase handlers. 125 * 126 * A RX CPU model. 127 */ 128 struct RXCPUClass { 129 CPUClass parent_class; 130 131 DeviceRealize parent_realize; 132 ResettablePhases parent_phases; 133 }; 134 135 #define CPU_RESOLVING_TYPE TYPE_RX_CPU 136 137 const char *rx_crname(uint8_t cr); 138 void rx_cpu_do_interrupt(CPUState *cpu); 139 bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); 140 hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 141 void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 142 int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 143 int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 144 145 void rx_translate_init(void); 146 void rx_translate_code(CPUState *cs, TranslationBlock *tb, 147 int *max_insns, vaddr pc, void *host_pc); 148 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); 149 150 #define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 151 #define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 152 153 #define RX_CPU_IRQ 0 154 #define RX_CPU_FIR 1 155 156 static inline uint32_t rx_cpu_pack_psw(CPURXState *env) 157 { 158 uint32_t psw = 0; 159 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); 160 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); 161 psw = FIELD_DP32(psw, PSW, U, env->psw_u); 162 psw = FIELD_DP32(psw, PSW, I, env->psw_i); 163 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); 164 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); 165 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); 166 psw = FIELD_DP32(psw, PSW, C, env->psw_c); 167 return psw; 168 } 169 170 #endif /* RX_CPU_H */ 171