1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exec/helper-gen.h" 26 27 #include "exec/translator.h" 28 #include "exec/translation-block.h" 29 #include "exec/log.h" 30 #include "semihosting/semihost.h" 31 32 #include "internals.h" 33 34 #define HELPER_H "helper.h" 35 #include "exec/helper-info.c.inc" 36 #undef HELPER_H 37 38 #include "tcg/tcg-cpu.h" 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 target_ulong cur_insn_len; 60 target_ulong pc_save; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 RISCVMXL address_xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 RISCVExtStatus mstatus_fs; 68 RISCVExtStatus mstatus_vs; 69 uint32_t mem_idx; 70 uint32_t priv; 71 /* 72 * Remember the rounding mode encoded in the previous fp instruction, 73 * which we have already installed into env->fp_status. Or -1 for 74 * no previous fp instruction. Note that we exit the TB when writing 75 * to any system register, which includes CSR_FRM, so we do not have 76 * to reset this known value. 77 */ 78 int frm; 79 RISCVMXL ol; 80 bool virt_inst_excp; 81 bool virt_enabled; 82 const RISCVCPUConfig *cfg_ptr; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 bool vstart_eq_zero; 103 bool vl_eq_vlmax; 104 CPUState *cs; 105 TCGv zero; 106 /* actual address width */ 107 uint8_t addr_xl; 108 bool addr_signed; 109 /* Ztso */ 110 bool ztso; 111 /* Use icount trigger for native debug */ 112 bool itrigger; 113 /* FRM is known to contain a valid value. */ 114 bool frm_valid; 115 bool insn_start_updated; 116 const GPtrArray *decoders; 117 /* zicfilp extension. fcfi_enabled, lp expected or not */ 118 bool fcfi_enabled; 119 bool fcfi_lp_expected; 120 /* zicfiss extension, if shadow stack was enabled during TB gen */ 121 bool bcfi_enabled; 122 } DisasContext; 123 124 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 125 { 126 return ctx->misa_ext & ext; 127 } 128 129 #ifdef TARGET_RISCV32 130 #define get_xl(ctx) MXL_RV32 131 #elif defined(CONFIG_USER_ONLY) 132 #define get_xl(ctx) MXL_RV64 133 #else 134 #define get_xl(ctx) ((ctx)->xl) 135 #endif 136 137 #ifdef TARGET_RISCV32 138 #define get_address_xl(ctx) MXL_RV32 139 #elif defined(CONFIG_USER_ONLY) 140 #define get_address_xl(ctx) MXL_RV64 141 #else 142 #define get_address_xl(ctx) ((ctx)->address_xl) 143 #endif 144 145 #define mxl_memop(ctx) ((get_xl(ctx) + 1) | MO_TE) 146 147 /* The word size for this machine mode. */ 148 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 149 { 150 return 16 << get_xl(ctx); 151 } 152 153 /* The operation length, as opposed to the xlen. */ 154 #ifdef TARGET_RISCV32 155 #define get_ol(ctx) MXL_RV32 156 #else 157 #define get_ol(ctx) ((ctx)->ol) 158 #endif 159 160 static inline int get_olen(DisasContext *ctx) 161 { 162 return 16 << get_ol(ctx); 163 } 164 165 /* The maximum register length */ 166 #ifdef TARGET_RISCV32 167 #define get_xl_max(ctx) MXL_RV32 168 #else 169 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 170 #endif 171 172 /* 173 * RISC-V requires NaN-boxing of narrower width floating point values. 174 * This applies when a 32-bit value is assigned to a 64-bit FP register. 175 * For consistency and simplicity, we nanbox results even when the RVD 176 * extension is not present. 177 */ 178 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 179 { 180 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 181 } 182 183 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 184 { 185 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 186 } 187 188 /* 189 * A narrow n-bit operation, where n < FLEN, checks that input operands 190 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 191 * If so, the least-significant bits of the input are used, otherwise the 192 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 193 * 194 * Here, the result is always nan-boxed, even the canonical nan. 195 */ 196 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 197 { 198 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 199 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 200 201 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 202 } 203 204 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 205 { 206 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 207 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 208 209 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 210 } 211 212 static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2) 213 { 214 assert(!ctx->insn_start_updated); 215 ctx->insn_start_updated = true; 216 tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); 217 tcg_set_insn_start_param(ctx->base.insn_start, 2, excp_uw2); 218 } 219 220 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 221 target_long diff) 222 { 223 target_ulong dest = ctx->base.pc_next + diff; 224 225 assert(ctx->pc_save != -1); 226 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 227 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 228 if (get_xl(ctx) == MXL_RV32) { 229 tcg_gen_ext32s_tl(target, target); 230 } 231 } else { 232 if (get_xl(ctx) == MXL_RV32) { 233 dest = (int32_t)dest; 234 } 235 tcg_gen_movi_tl(target, dest); 236 } 237 } 238 239 static void gen_update_pc(DisasContext *ctx, target_long diff) 240 { 241 gen_pc_plus_diff(cpu_pc, ctx, diff); 242 ctx->pc_save = ctx->base.pc_next + diff; 243 } 244 245 static void generate_exception(DisasContext *ctx, RISCVException excp) 246 { 247 gen_update_pc(ctx, 0); 248 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 249 ctx->base.is_jmp = DISAS_NORETURN; 250 } 251 252 static void gen_exception_illegal(DisasContext *ctx) 253 { 254 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 255 offsetof(CPURISCVState, bins)); 256 if (ctx->virt_inst_excp) { 257 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 258 } else { 259 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 260 } 261 } 262 263 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 264 { 265 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 266 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 267 } 268 269 static void lookup_and_goto_ptr(DisasContext *ctx) 270 { 271 #ifndef CONFIG_USER_ONLY 272 if (ctx->itrigger) { 273 gen_helper_itrigger_match(tcg_env); 274 } 275 #endif 276 tcg_gen_lookup_and_goto_ptr(); 277 } 278 279 static void exit_tb(DisasContext *ctx) 280 { 281 #ifndef CONFIG_USER_ONLY 282 if (ctx->itrigger) { 283 gen_helper_itrigger_match(tcg_env); 284 } 285 #endif 286 tcg_gen_exit_tb(NULL, 0); 287 } 288 289 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 290 { 291 target_ulong dest = ctx->base.pc_next + diff; 292 293 /* 294 * Under itrigger, instruction executes one by one like singlestep, 295 * direct block chain benefits will be small. 296 */ 297 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 298 /* 299 * For pcrel, the pc must always be up-to-date on entry to 300 * the linked TB, so that it can use simple additions for all 301 * further adjustments. For !pcrel, the linked TB is compiled 302 * to know its full virtual address, so we can delay the 303 * update to pc to the unlinked path. A long chain of links 304 * can thus avoid many updates to the PC. 305 */ 306 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 307 gen_update_pc(ctx, diff); 308 tcg_gen_goto_tb(n); 309 } else { 310 tcg_gen_goto_tb(n); 311 gen_update_pc(ctx, diff); 312 } 313 tcg_gen_exit_tb(ctx->base.tb, n); 314 } else { 315 gen_update_pc(ctx, diff); 316 lookup_and_goto_ptr(ctx); 317 } 318 } 319 320 /* 321 * Wrappers for getting reg values. 322 * 323 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 324 * constant zero as a source, and an uninitialized sink as destination. 325 * 326 * Further, we may provide an extension for word operations. 327 */ 328 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 329 { 330 TCGv t; 331 332 if (reg_num == 0) { 333 return ctx->zero; 334 } 335 336 switch (get_ol(ctx)) { 337 case MXL_RV32: 338 switch (ext) { 339 case EXT_NONE: 340 break; 341 case EXT_SIGN: 342 t = tcg_temp_new(); 343 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 344 return t; 345 case EXT_ZERO: 346 t = tcg_temp_new(); 347 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 348 return t; 349 default: 350 g_assert_not_reached(); 351 } 352 break; 353 case MXL_RV64: 354 case MXL_RV128: 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 return cpu_gpr[reg_num]; 360 } 361 362 static TCGv get_gprh(DisasContext *ctx, int reg_num) 363 { 364 assert(get_xl(ctx) == MXL_RV128); 365 if (reg_num == 0) { 366 return ctx->zero; 367 } 368 return cpu_gprh[reg_num]; 369 } 370 371 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 372 { 373 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 374 return tcg_temp_new(); 375 } 376 return cpu_gpr[reg_num]; 377 } 378 379 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 380 { 381 if (reg_num == 0) { 382 return tcg_temp_new(); 383 } 384 return cpu_gprh[reg_num]; 385 } 386 387 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 388 { 389 if (reg_num != 0) { 390 switch (get_ol(ctx)) { 391 case MXL_RV32: 392 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 393 break; 394 case MXL_RV64: 395 case MXL_RV128: 396 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 397 break; 398 default: 399 g_assert_not_reached(); 400 } 401 402 if (get_xl_max(ctx) == MXL_RV128) { 403 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 404 } 405 } 406 } 407 408 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 409 { 410 if (reg_num != 0) { 411 switch (get_ol(ctx)) { 412 case MXL_RV32: 413 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 414 break; 415 case MXL_RV64: 416 case MXL_RV128: 417 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 418 break; 419 default: 420 g_assert_not_reached(); 421 } 422 423 if (get_xl_max(ctx) == MXL_RV128) { 424 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 425 } 426 } 427 } 428 429 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 430 { 431 assert(get_ol(ctx) == MXL_RV128); 432 if (reg_num != 0) { 433 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 434 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 435 } 436 } 437 438 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 439 { 440 if (!ctx->cfg_ptr->ext_zfinx) { 441 return cpu_fpr[reg_num]; 442 } 443 444 if (reg_num == 0) { 445 return tcg_constant_i64(0); 446 } 447 switch (get_xl(ctx)) { 448 case MXL_RV32: 449 #ifdef TARGET_RISCV32 450 { 451 TCGv_i64 t = tcg_temp_new_i64(); 452 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 453 return t; 454 } 455 #else 456 /* fall through */ 457 case MXL_RV64: 458 return cpu_gpr[reg_num]; 459 #endif 460 default: 461 g_assert_not_reached(); 462 } 463 } 464 465 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 466 { 467 if (!ctx->cfg_ptr->ext_zfinx) { 468 return cpu_fpr[reg_num]; 469 } 470 471 if (reg_num == 0) { 472 return tcg_constant_i64(0); 473 } 474 switch (get_xl(ctx)) { 475 case MXL_RV32: 476 { 477 TCGv_i64 t = tcg_temp_new_i64(); 478 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 479 return t; 480 } 481 #ifdef TARGET_RISCV64 482 case MXL_RV64: 483 return cpu_gpr[reg_num]; 484 #endif 485 default: 486 g_assert_not_reached(); 487 } 488 } 489 490 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 491 { 492 if (!ctx->cfg_ptr->ext_zfinx) { 493 return cpu_fpr[reg_num]; 494 } 495 496 if (reg_num == 0) { 497 return tcg_temp_new_i64(); 498 } 499 500 switch (get_xl(ctx)) { 501 case MXL_RV32: 502 return tcg_temp_new_i64(); 503 #ifdef TARGET_RISCV64 504 case MXL_RV64: 505 return cpu_gpr[reg_num]; 506 #endif 507 default: 508 g_assert_not_reached(); 509 } 510 } 511 512 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 513 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 514 { 515 if (!ctx->cfg_ptr->ext_zfinx) { 516 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 517 return; 518 } 519 if (reg_num != 0) { 520 switch (get_xl(ctx)) { 521 case MXL_RV32: 522 #ifdef TARGET_RISCV32 523 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 524 break; 525 #else 526 /* fall through */ 527 case MXL_RV64: 528 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 529 break; 530 #endif 531 default: 532 g_assert_not_reached(); 533 } 534 } 535 } 536 537 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 538 { 539 if (!ctx->cfg_ptr->ext_zfinx) { 540 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 541 return; 542 } 543 544 if (reg_num != 0) { 545 switch (get_xl(ctx)) { 546 case MXL_RV32: 547 #ifdef TARGET_RISCV32 548 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 549 break; 550 #else 551 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 552 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 553 break; 554 case MXL_RV64: 555 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 556 break; 557 #endif 558 default: 559 g_assert_not_reached(); 560 } 561 } 562 } 563 564 #ifndef CONFIG_USER_ONLY 565 /* 566 * Direct calls 567 * - jal x1; 568 * - jal x5; 569 * - c.jal. 570 * - cm.jalt. 571 * 572 * Direct jumps 573 * - jal x0; 574 * - c.j; 575 * - cm.jt. 576 * 577 * Other direct jumps 578 * - jal rd where rd != x1 and rd != x5 and rd != x0; 579 */ 580 static void gen_ctr_jal(DisasContext *ctx, int rd, target_ulong imm) 581 { 582 TCGv dest = tcg_temp_new(); 583 TCGv src = tcg_temp_new(); 584 TCGv type; 585 586 /* 587 * If rd is x1 or x5 link registers, treat this as direct call otherwise 588 * its a direct jump. 589 */ 590 if (rd == 1 || rd == 5) { 591 type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL); 592 } else if (rd == 0) { 593 type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP); 594 } else { 595 type = tcg_constant_tl(CTRDATA_TYPE_OTHER_DIRECT_JUMP); 596 } 597 598 gen_pc_plus_diff(dest, ctx, imm); 599 gen_pc_plus_diff(src, ctx, 0); 600 gen_helper_ctr_add_entry(tcg_env, src, dest, type); 601 } 602 #endif 603 604 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 605 { 606 TCGv succ_pc = dest_gpr(ctx, rd); 607 608 /* check misaligned: */ 609 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 610 if ((imm & 0x3) != 0) { 611 TCGv target_pc = tcg_temp_new(); 612 gen_pc_plus_diff(target_pc, ctx, imm); 613 gen_exception_inst_addr_mis(ctx, target_pc); 614 return; 615 } 616 } 617 618 #ifndef CONFIG_USER_ONLY 619 if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { 620 gen_ctr_jal(ctx, rd, imm); 621 } 622 #endif 623 624 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 625 gen_set_gpr(ctx, rd, succ_pc); 626 627 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 628 ctx->base.is_jmp = DISAS_NORETURN; 629 } 630 631 /* Compute a canonical address from a register plus offset. */ 632 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 633 { 634 TCGv addr = tcg_temp_new(); 635 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 636 637 tcg_gen_addi_tl(addr, src1, imm); 638 if (ctx->addr_signed) { 639 tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); 640 } else { 641 tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); 642 } 643 644 return addr; 645 } 646 647 /* Compute a canonical address from a register plus reg offset. */ 648 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 649 { 650 TCGv addr = tcg_temp_new(); 651 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 652 653 tcg_gen_add_tl(addr, src1, offs); 654 if (ctx->addr_signed) { 655 tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); 656 } else { 657 tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); 658 } 659 660 return addr; 661 } 662 663 #ifndef CONFIG_USER_ONLY 664 /* 665 * We will have already diagnosed disabled state, 666 * and need to turn initial/clean into dirty. 667 */ 668 static void mark_fs_dirty(DisasContext *ctx) 669 { 670 TCGv tmp; 671 672 if (!has_ext(ctx, RVF)) { 673 return; 674 } 675 676 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 677 /* Remember the state change for the rest of the TB. */ 678 ctx->mstatus_fs = EXT_STATUS_DIRTY; 679 680 tmp = tcg_temp_new(); 681 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 682 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 683 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 684 685 if (ctx->virt_enabled) { 686 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 687 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 688 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 689 } 690 } 691 } 692 #else 693 static inline void mark_fs_dirty(DisasContext *ctx) { } 694 #endif 695 696 #ifndef CONFIG_USER_ONLY 697 /* 698 * We will have already diagnosed disabled state, 699 * and need to turn initial/clean into dirty. 700 */ 701 static void mark_vs_dirty(DisasContext *ctx) 702 { 703 TCGv tmp; 704 705 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 706 /* Remember the state change for the rest of the TB. */ 707 ctx->mstatus_vs = EXT_STATUS_DIRTY; 708 709 tmp = tcg_temp_new(); 710 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 711 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 712 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 713 714 if (ctx->virt_enabled) { 715 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 716 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 717 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 718 } 719 } 720 } 721 #else 722 static inline void mark_vs_dirty(DisasContext *ctx) { } 723 #endif 724 725 static void finalize_rvv_inst(DisasContext *ctx) 726 { 727 mark_vs_dirty(ctx); 728 ctx->vstart_eq_zero = true; 729 } 730 731 static void gen_set_rm(DisasContext *ctx, int rm) 732 { 733 if (ctx->frm == rm) { 734 return; 735 } 736 ctx->frm = rm; 737 738 if (rm == RISCV_FRM_DYN) { 739 /* The helper will return only if frm valid. */ 740 ctx->frm_valid = true; 741 } 742 743 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 744 decode_save_opc(ctx, 0); 745 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 746 } 747 748 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 749 { 750 if (ctx->frm == rm && ctx->frm_valid) { 751 return; 752 } 753 ctx->frm = rm; 754 ctx->frm_valid = true; 755 756 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 757 decode_save_opc(ctx, 0); 758 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 759 } 760 761 static int ex_plus_1(DisasContext *ctx, int nf) 762 { 763 return nf + 1; 764 } 765 766 #define EX_SH(amount) \ 767 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 768 { \ 769 return imm << amount; \ 770 } 771 EX_SH(1) 772 EX_SH(2) 773 EX_SH(3) 774 EX_SH(4) 775 EX_SH(12) 776 777 #define REQUIRE_EXT(ctx, ext) do { \ 778 if (!has_ext(ctx, ext)) { \ 779 return false; \ 780 } \ 781 } while (0) 782 783 #define REQUIRE_32BIT(ctx) do { \ 784 if (get_xl(ctx) != MXL_RV32) { \ 785 return false; \ 786 } \ 787 } while (0) 788 789 #define REQUIRE_64BIT(ctx) do { \ 790 if (get_xl(ctx) != MXL_RV64) { \ 791 return false; \ 792 } \ 793 } while (0) 794 795 #define REQUIRE_128BIT(ctx) do { \ 796 if (get_xl(ctx) != MXL_RV128) { \ 797 return false; \ 798 } \ 799 } while (0) 800 801 #define REQUIRE_64_OR_128BIT(ctx) do { \ 802 if (get_xl(ctx) == MXL_RV32) { \ 803 return false; \ 804 } \ 805 } while (0) 806 807 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 808 if (!ctx->cfg_ptr->ext_##A && \ 809 !ctx->cfg_ptr->ext_##B) { \ 810 return false; \ 811 } \ 812 } while (0) 813 814 static int ex_rvc_register(DisasContext *ctx, int reg) 815 { 816 return 8 + reg; 817 } 818 819 static int ex_sreg_register(DisasContext *ctx, int reg) 820 { 821 return reg < 2 ? reg + 8 : reg + 16; 822 } 823 824 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 825 { 826 /* For RV128 a shamt of 0 means a shift by 64. */ 827 if (get_ol(ctx) == MXL_RV128) { 828 imm = imm ? imm : 64; 829 } 830 return imm; 831 } 832 833 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 834 { 835 /* 836 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 837 * shifts, the shamt is sign-extended. 838 */ 839 if (get_ol(ctx) == MXL_RV128) { 840 imm = imm | (imm & 32) << 1; 841 imm = imm ? imm : 64; 842 } 843 return imm; 844 } 845 846 /* Include the auto-generated decoder for 32 bit insn */ 847 #include "decode-insn32.c.inc" 848 849 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 850 void (*func)(TCGv, TCGv, target_long)) 851 { 852 TCGv dest = dest_gpr(ctx, a->rd); 853 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 854 855 func(dest, src1, a->imm); 856 857 if (get_xl(ctx) == MXL_RV128) { 858 TCGv src1h = get_gprh(ctx, a->rs1); 859 TCGv desth = dest_gprh(ctx, a->rd); 860 861 func(desth, src1h, -(a->imm < 0)); 862 gen_set_gpr128(ctx, a->rd, dest, desth); 863 } else { 864 gen_set_gpr(ctx, a->rd, dest); 865 } 866 867 return true; 868 } 869 870 static bool gen_logic(DisasContext *ctx, arg_r *a, 871 void (*func)(TCGv, TCGv, TCGv)) 872 { 873 TCGv dest = dest_gpr(ctx, a->rd); 874 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 875 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 876 877 func(dest, src1, src2); 878 879 if (get_xl(ctx) == MXL_RV128) { 880 TCGv src1h = get_gprh(ctx, a->rs1); 881 TCGv src2h = get_gprh(ctx, a->rs2); 882 TCGv desth = dest_gprh(ctx, a->rd); 883 884 func(desth, src1h, src2h); 885 gen_set_gpr128(ctx, a->rd, dest, desth); 886 } else { 887 gen_set_gpr(ctx, a->rd, dest); 888 } 889 890 return true; 891 } 892 893 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 894 void (*func)(TCGv, TCGv, target_long), 895 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 896 { 897 TCGv dest = dest_gpr(ctx, a->rd); 898 TCGv src1 = get_gpr(ctx, a->rs1, ext); 899 900 if (get_ol(ctx) < MXL_RV128) { 901 func(dest, src1, a->imm); 902 gen_set_gpr(ctx, a->rd, dest); 903 } else { 904 if (f128 == NULL) { 905 return false; 906 } 907 908 TCGv src1h = get_gprh(ctx, a->rs1); 909 TCGv desth = dest_gprh(ctx, a->rd); 910 911 f128(dest, desth, src1, src1h, a->imm); 912 gen_set_gpr128(ctx, a->rd, dest, desth); 913 } 914 return true; 915 } 916 917 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 918 void (*func)(TCGv, TCGv, TCGv), 919 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 920 { 921 TCGv dest = dest_gpr(ctx, a->rd); 922 TCGv src1 = get_gpr(ctx, a->rs1, ext); 923 TCGv src2 = tcg_constant_tl(a->imm); 924 925 if (get_ol(ctx) < MXL_RV128) { 926 func(dest, src1, src2); 927 gen_set_gpr(ctx, a->rd, dest); 928 } else { 929 if (f128 == NULL) { 930 return false; 931 } 932 933 TCGv src1h = get_gprh(ctx, a->rs1); 934 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 935 TCGv desth = dest_gprh(ctx, a->rd); 936 937 f128(dest, desth, src1, src1h, src2, src2h); 938 gen_set_gpr128(ctx, a->rd, dest, desth); 939 } 940 return true; 941 } 942 943 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 944 void (*func)(TCGv, TCGv, TCGv), 945 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 946 { 947 TCGv dest = dest_gpr(ctx, a->rd); 948 TCGv src1 = get_gpr(ctx, a->rs1, ext); 949 TCGv src2 = get_gpr(ctx, a->rs2, ext); 950 951 if (get_ol(ctx) < MXL_RV128) { 952 func(dest, src1, src2); 953 gen_set_gpr(ctx, a->rd, dest); 954 } else { 955 if (f128 == NULL) { 956 return false; 957 } 958 959 TCGv src1h = get_gprh(ctx, a->rs1); 960 TCGv src2h = get_gprh(ctx, a->rs2); 961 TCGv desth = dest_gprh(ctx, a->rd); 962 963 f128(dest, desth, src1, src1h, src2, src2h); 964 gen_set_gpr128(ctx, a->rd, dest, desth); 965 } 966 return true; 967 } 968 969 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 970 void (*f_tl)(TCGv, TCGv, TCGv), 971 void (*f_32)(TCGv, TCGv, TCGv), 972 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 973 { 974 int olen = get_olen(ctx); 975 976 if (olen != TARGET_LONG_BITS) { 977 if (olen == 32) { 978 f_tl = f_32; 979 } else if (olen != 128) { 980 g_assert_not_reached(); 981 } 982 } 983 return gen_arith(ctx, a, ext, f_tl, f_128); 984 } 985 986 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 987 void (*func)(TCGv, TCGv, target_long), 988 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 989 { 990 TCGv dest, src1; 991 int max_len = get_olen(ctx); 992 993 if (a->shamt >= max_len) { 994 return false; 995 } 996 997 dest = dest_gpr(ctx, a->rd); 998 src1 = get_gpr(ctx, a->rs1, ext); 999 1000 if (max_len < 128) { 1001 func(dest, src1, a->shamt); 1002 gen_set_gpr(ctx, a->rd, dest); 1003 } else { 1004 TCGv src1h = get_gprh(ctx, a->rs1); 1005 TCGv desth = dest_gprh(ctx, a->rd); 1006 1007 if (f128 == NULL) { 1008 return false; 1009 } 1010 f128(dest, desth, src1, src1h, a->shamt); 1011 gen_set_gpr128(ctx, a->rd, dest, desth); 1012 } 1013 return true; 1014 } 1015 1016 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 1017 DisasExtend ext, 1018 void (*f_tl)(TCGv, TCGv, target_long), 1019 void (*f_32)(TCGv, TCGv, target_long), 1020 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 1021 target_long)) 1022 { 1023 int olen = get_olen(ctx); 1024 if (olen != TARGET_LONG_BITS) { 1025 if (olen == 32) { 1026 f_tl = f_32; 1027 } else if (olen != 128) { 1028 g_assert_not_reached(); 1029 } 1030 } 1031 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 1032 } 1033 1034 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 1035 void (*func)(TCGv, TCGv, TCGv)) 1036 { 1037 TCGv dest, src1, src2; 1038 int max_len = get_olen(ctx); 1039 1040 if (a->shamt >= max_len) { 1041 return false; 1042 } 1043 1044 dest = dest_gpr(ctx, a->rd); 1045 src1 = get_gpr(ctx, a->rs1, ext); 1046 src2 = tcg_constant_tl(a->shamt); 1047 1048 func(dest, src1, src2); 1049 1050 gen_set_gpr(ctx, a->rd, dest); 1051 return true; 1052 } 1053 1054 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1055 void (*func)(TCGv, TCGv, TCGv), 1056 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1057 { 1058 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1059 TCGv ext2 = tcg_temp_new(); 1060 int max_len = get_olen(ctx); 1061 1062 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1063 1064 TCGv dest = dest_gpr(ctx, a->rd); 1065 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1066 1067 if (max_len < 128) { 1068 func(dest, src1, ext2); 1069 gen_set_gpr(ctx, a->rd, dest); 1070 } else { 1071 TCGv src1h = get_gprh(ctx, a->rs1); 1072 TCGv desth = dest_gprh(ctx, a->rd); 1073 1074 if (f128 == NULL) { 1075 return false; 1076 } 1077 f128(dest, desth, src1, src1h, ext2); 1078 gen_set_gpr128(ctx, a->rd, dest, desth); 1079 } 1080 return true; 1081 } 1082 1083 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1084 void (*f_tl)(TCGv, TCGv, TCGv), 1085 void (*f_32)(TCGv, TCGv, TCGv), 1086 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1087 { 1088 int olen = get_olen(ctx); 1089 if (olen != TARGET_LONG_BITS) { 1090 if (olen == 32) { 1091 f_tl = f_32; 1092 } else if (olen != 128) { 1093 g_assert_not_reached(); 1094 } 1095 } 1096 return gen_shift(ctx, a, ext, f_tl, f_128); 1097 } 1098 1099 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1100 void (*func)(TCGv, TCGv)) 1101 { 1102 TCGv dest = dest_gpr(ctx, a->rd); 1103 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1104 1105 func(dest, src1); 1106 1107 gen_set_gpr(ctx, a->rd, dest); 1108 return true; 1109 } 1110 1111 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1112 void (*f_tl)(TCGv, TCGv), 1113 void (*f_32)(TCGv, TCGv)) 1114 { 1115 int olen = get_olen(ctx); 1116 1117 if (olen != TARGET_LONG_BITS) { 1118 if (olen == 32) { 1119 f_tl = f_32; 1120 } else { 1121 g_assert_not_reached(); 1122 } 1123 } 1124 return gen_unary(ctx, a, ext, f_tl); 1125 } 1126 1127 static bool gen_amo(DisasContext *ctx, arg_atomic *a, 1128 void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), 1129 MemOp mop) 1130 { 1131 TCGv dest = dest_gpr(ctx, a->rd); 1132 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1133 MemOp size = mop & MO_SIZE; 1134 1135 if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) { 1136 mop |= MO_ATOM_WITHIN16; 1137 } else { 1138 mop |= MO_ALIGN; 1139 } 1140 1141 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1142 src1 = get_address(ctx, a->rs1, 0); 1143 func(dest, src1, src2, ctx->mem_idx, mop); 1144 1145 gen_set_gpr(ctx, a->rd, dest); 1146 return true; 1147 } 1148 1149 static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) 1150 { 1151 TCGv dest = get_gpr(ctx, a->rd, EXT_NONE); 1152 TCGv src1 = get_address(ctx, a->rs1, 0); 1153 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1154 1155 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1156 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); 1157 1158 gen_set_gpr(ctx, a->rd, dest); 1159 return true; 1160 } 1161 1162 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1163 { 1164 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1165 CPUState *cpu = ctx->cs; 1166 CPURISCVState *env = cpu_env(cpu); 1167 1168 return translator_ldl(env, &ctx->base, pc); 1169 } 1170 1171 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) 1172 1173 /* Include insn module translation function */ 1174 #include "insn_trans/trans_rvi.c.inc" 1175 #include "insn_trans/trans_rvm.c.inc" 1176 #include "insn_trans/trans_rva.c.inc" 1177 #include "insn_trans/trans_rvf.c.inc" 1178 #include "insn_trans/trans_rvd.c.inc" 1179 #include "insn_trans/trans_rvh.c.inc" 1180 #include "insn_trans/trans_rvv.c.inc" 1181 #include "insn_trans/trans_rvb.c.inc" 1182 #include "insn_trans/trans_rvzicond.c.inc" 1183 #include "insn_trans/trans_rvzacas.c.inc" 1184 #include "insn_trans/trans_rvzabha.c.inc" 1185 #include "insn_trans/trans_rvzawrs.c.inc" 1186 #include "insn_trans/trans_rvzicbo.c.inc" 1187 #include "insn_trans/trans_rvzimop.c.inc" 1188 #include "insn_trans/trans_rvzfa.c.inc" 1189 #include "insn_trans/trans_rvzfh.c.inc" 1190 #include "insn_trans/trans_rvk.c.inc" 1191 #include "insn_trans/trans_rvvk.c.inc" 1192 #include "insn_trans/trans_privileged.c.inc" 1193 #include "insn_trans/trans_svinval.c.inc" 1194 #include "insn_trans/trans_rvbf16.c.inc" 1195 #include "decode-xthead.c.inc" 1196 #include "insn_trans/trans_xthead.c.inc" 1197 #include "insn_trans/trans_xventanacondops.c.inc" 1198 1199 /* Include the auto-generated decoder for 16 bit insn */ 1200 #include "decode-insn16.c.inc" 1201 #include "insn_trans/trans_rvzce.c.inc" 1202 #include "insn_trans/trans_rvzcmop.c.inc" 1203 #include "insn_trans/trans_rvzicfiss.c.inc" 1204 1205 /* Include decoders for factored-out extensions */ 1206 #include "decode-XVentanaCondOps.c.inc" 1207 1208 /* The specification allows for longer insns, but not supported by qemu. */ 1209 #define MAX_INSN_LEN 4 1210 1211 static inline int insn_len(uint16_t first_word) 1212 { 1213 return (first_word & 3) == 3 ? 4 : 2; 1214 } 1215 1216 const RISCVDecoder decoder_table[] = { 1217 { always_true_p, decode_insn32 }, 1218 { has_xthead_p, decode_xthead}, 1219 { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, 1220 }; 1221 1222 const size_t decoder_table_size = ARRAY_SIZE(decoder_table); 1223 1224 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1225 { 1226 ctx->virt_inst_excp = false; 1227 ctx->cur_insn_len = insn_len(opcode); 1228 /* Check for compressed insn */ 1229 if (ctx->cur_insn_len == 2) { 1230 ctx->opcode = opcode; 1231 /* 1232 * The Zca extension is added as way to refer to instructions in the C 1233 * extension that do not include the floating-point loads and stores 1234 */ 1235 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1236 decode_insn16(ctx, opcode)) { 1237 return; 1238 } 1239 } else { 1240 uint32_t opcode32 = opcode; 1241 opcode32 = deposit32(opcode32, 16, 16, 1242 translator_lduw(env, &ctx->base, 1243 ctx->base.pc_next + 2)); 1244 ctx->opcode = opcode32; 1245 1246 for (guint i = 0; i < ctx->decoders->len; ++i) { 1247 riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i); 1248 if (func(ctx, opcode32)) { 1249 return; 1250 } 1251 } 1252 } 1253 1254 gen_exception_illegal(ctx); 1255 } 1256 1257 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1258 { 1259 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1260 CPURISCVState *env = cpu_env(cs); 1261 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1262 RISCVCPU *cpu = RISCV_CPU(cs); 1263 uint32_t tb_flags = ctx->base.tb->flags; 1264 1265 ctx->pc_save = ctx->base.pc_first; 1266 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1267 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1268 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1269 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1270 ctx->priv_ver = env->priv_ver; 1271 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1272 ctx->misa_ext = env->misa_ext; 1273 ctx->frm = -1; /* unknown rounding mode */ 1274 ctx->cfg_ptr = &(cpu->cfg); 1275 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1276 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1277 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1278 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1279 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1280 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1281 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1282 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1283 ctx->misa_mxl_max = mcc->misa_mxl_max; 1284 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1285 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1286 ctx->cs = cs; 1287 if (get_xl(ctx) == MXL_RV32) { 1288 ctx->addr_xl = 32; 1289 ctx->addr_signed = false; 1290 } else { 1291 int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); 1292 ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm); 1293 ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); 1294 } 1295 ctx->ztso = cpu->cfg.ext_ztso; 1296 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1297 ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); 1298 ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); 1299 ctx->fcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); 1300 ctx->zero = tcg_constant_tl(0); 1301 ctx->virt_inst_excp = false; 1302 ctx->decoders = cpu->decoders; 1303 } 1304 1305 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1306 { 1307 } 1308 1309 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1310 { 1311 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1312 target_ulong pc_next = ctx->base.pc_next; 1313 1314 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1315 pc_next &= ~TARGET_PAGE_MASK; 1316 } 1317 1318 tcg_gen_insn_start(pc_next, 0, 0); 1319 ctx->insn_start_updated = false; 1320 } 1321 1322 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1323 { 1324 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1325 CPURISCVState *env = cpu_env(cpu); 1326 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1327 1328 ctx->ol = ctx->xl; 1329 decode_opc(env, ctx, opcode16); 1330 ctx->base.pc_next += ctx->cur_insn_len; 1331 1332 /* 1333 * If 'fcfi_lp_expected' is still true after processing the instruction, 1334 * then we did not see an 'lpad' instruction, and must raise an exception. 1335 * Insert code to raise the exception at the start of the insn; any other 1336 * code the insn may have emitted will be deleted as dead code following 1337 * the noreturn exception 1338 */ 1339 if (ctx->fcfi_lp_expected) { 1340 /* Emit after insn_start, i.e. before the op following insn_start. */ 1341 tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link); 1342 tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), 1343 tcg_env, offsetof(CPURISCVState, sw_check_code)); 1344 gen_helper_raise_exception(tcg_env, 1345 tcg_constant_i32(RISCV_EXCP_SW_CHECK)); 1346 tcg_ctx->emit_before_op = NULL; 1347 ctx->base.is_jmp = DISAS_NORETURN; 1348 } 1349 1350 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1351 if (ctx->base.is_jmp == DISAS_NEXT) { 1352 if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->base.pc_next)) { 1353 ctx->base.is_jmp = DISAS_TOO_MANY; 1354 } else { 1355 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1356 1357 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1358 uint16_t next_insn = 1359 translator_lduw(env, &ctx->base, ctx->base.pc_next); 1360 int len = insn_len(next_insn); 1361 1362 if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1363 ctx->base.is_jmp = DISAS_TOO_MANY; 1364 } 1365 } 1366 } 1367 } 1368 } 1369 1370 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1371 { 1372 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1373 1374 switch (ctx->base.is_jmp) { 1375 case DISAS_TOO_MANY: 1376 gen_goto_tb(ctx, 0, 0); 1377 break; 1378 case DISAS_NORETURN: 1379 break; 1380 default: 1381 g_assert_not_reached(); 1382 } 1383 } 1384 1385 static const TranslatorOps riscv_tr_ops = { 1386 .init_disas_context = riscv_tr_init_disas_context, 1387 .tb_start = riscv_tr_tb_start, 1388 .insn_start = riscv_tr_insn_start, 1389 .translate_insn = riscv_tr_translate_insn, 1390 .tb_stop = riscv_tr_tb_stop, 1391 }; 1392 1393 void riscv_translate_code(CPUState *cs, TranslationBlock *tb, 1394 int *max_insns, vaddr pc, void *host_pc) 1395 { 1396 DisasContext ctx; 1397 1398 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1399 } 1400 1401 void riscv_translate_init(void) 1402 { 1403 int i; 1404 1405 /* 1406 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1407 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1408 * unless you specifically block reads/writes to reg 0. 1409 */ 1410 cpu_gpr[0] = NULL; 1411 cpu_gprh[0] = NULL; 1412 1413 for (i = 1; i < 32; i++) { 1414 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1415 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1416 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1417 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1418 } 1419 1420 for (i = 0; i < 32; i++) { 1421 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1422 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1423 } 1424 1425 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1426 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1427 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1428 "vstart"); 1429 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1430 "load_res"); 1431 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1432 "load_val"); 1433 } 1434