1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exec/helper-gen.h" 26 27 #include "exec/translator.h" 28 #include "exec/translation-block.h" 29 #include "exec/log.h" 30 #include "semihosting/semihost.h" 31 32 #include "internals.h" 33 34 #define HELPER_H "helper.h" 35 #include "exec/helper-info.c.inc" 36 #undef HELPER_H 37 38 #include "tcg/tcg-cpu.h" 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 target_ulong cur_insn_len; 63 target_ulong pc_save; 64 target_ulong priv_ver; 65 RISCVMXL misa_mxl_max; 66 RISCVMXL xl; 67 RISCVMXL address_xl; 68 uint32_t misa_ext; 69 uint32_t opcode; 70 RISCVExtStatus mstatus_fs; 71 RISCVExtStatus mstatus_vs; 72 uint32_t mem_idx; 73 uint32_t priv; 74 /* 75 * Remember the rounding mode encoded in the previous fp instruction, 76 * which we have already installed into env->fp_status. Or -1 for 77 * no previous fp instruction. Note that we exit the TB when writing 78 * to any system register, which includes CSR_FRM, so we do not have 79 * to reset this known value. 80 */ 81 int frm; 82 RISCVMXL ol; 83 bool virt_inst_excp; 84 bool virt_enabled; 85 const RISCVCPUConfig *cfg_ptr; 86 /* vector extension */ 87 bool vill; 88 /* 89 * Encode LMUL to lmul as follows: 90 * LMUL vlmul lmul 91 * 1 000 0 92 * 2 001 1 93 * 4 010 2 94 * 8 011 3 95 * - 100 - 96 * 1/8 101 -3 97 * 1/4 110 -2 98 * 1/2 111 -1 99 */ 100 int8_t lmul; 101 uint8_t sew; 102 uint8_t vta; 103 uint8_t vma; 104 bool cfg_vta_all_1s; 105 bool vstart_eq_zero; 106 bool vl_eq_vlmax; 107 CPUState *cs; 108 TCGv zero; 109 /* PointerMasking extension */ 110 bool pm_mask_enabled; 111 bool pm_base_enabled; 112 /* Ztso */ 113 bool ztso; 114 /* Use icount trigger for native debug */ 115 bool itrigger; 116 /* FRM is known to contain a valid value. */ 117 bool frm_valid; 118 bool insn_start_updated; 119 const GPtrArray *decoders; 120 /* zicfilp extension. fcfi_enabled, lp expected or not */ 121 bool fcfi_enabled; 122 bool fcfi_lp_expected; 123 /* zicfiss extension, if shadow stack was enabled during TB gen */ 124 bool bcfi_enabled; 125 } DisasContext; 126 127 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 128 { 129 return ctx->misa_ext & ext; 130 } 131 132 #ifdef TARGET_RISCV32 133 #define get_xl(ctx) MXL_RV32 134 #elif defined(CONFIG_USER_ONLY) 135 #define get_xl(ctx) MXL_RV64 136 #else 137 #define get_xl(ctx) ((ctx)->xl) 138 #endif 139 140 #ifdef TARGET_RISCV32 141 #define get_address_xl(ctx) MXL_RV32 142 #elif defined(CONFIG_USER_ONLY) 143 #define get_address_xl(ctx) MXL_RV64 144 #else 145 #define get_address_xl(ctx) ((ctx)->address_xl) 146 #endif 147 148 #define mxl_memop(ctx) ((get_xl(ctx) + 1) | MO_TE) 149 150 /* The word size for this machine mode. */ 151 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 152 { 153 return 16 << get_xl(ctx); 154 } 155 156 /* The operation length, as opposed to the xlen. */ 157 #ifdef TARGET_RISCV32 158 #define get_ol(ctx) MXL_RV32 159 #else 160 #define get_ol(ctx) ((ctx)->ol) 161 #endif 162 163 static inline int get_olen(DisasContext *ctx) 164 { 165 return 16 << get_ol(ctx); 166 } 167 168 /* The maximum register length */ 169 #ifdef TARGET_RISCV32 170 #define get_xl_max(ctx) MXL_RV32 171 #else 172 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 173 #endif 174 175 /* 176 * RISC-V requires NaN-boxing of narrower width floating point values. 177 * This applies when a 32-bit value is assigned to a 64-bit FP register. 178 * For consistency and simplicity, we nanbox results even when the RVD 179 * extension is not present. 180 */ 181 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 182 { 183 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 184 } 185 186 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 187 { 188 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 189 } 190 191 /* 192 * A narrow n-bit operation, where n < FLEN, checks that input operands 193 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 194 * If so, the least-significant bits of the input are used, otherwise the 195 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 196 * 197 * Here, the result is always nan-boxed, even the canonical nan. 198 */ 199 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 200 { 201 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 202 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 203 204 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 205 } 206 207 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 208 { 209 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 210 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 211 212 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 213 } 214 215 static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2) 216 { 217 assert(!ctx->insn_start_updated); 218 ctx->insn_start_updated = true; 219 tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); 220 tcg_set_insn_start_param(ctx->base.insn_start, 2, excp_uw2); 221 } 222 223 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 224 target_long diff) 225 { 226 target_ulong dest = ctx->base.pc_next + diff; 227 228 assert(ctx->pc_save != -1); 229 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 230 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 231 if (get_xl(ctx) == MXL_RV32) { 232 tcg_gen_ext32s_tl(target, target); 233 } 234 } else { 235 if (get_xl(ctx) == MXL_RV32) { 236 dest = (int32_t)dest; 237 } 238 tcg_gen_movi_tl(target, dest); 239 } 240 } 241 242 static void gen_update_pc(DisasContext *ctx, target_long diff) 243 { 244 gen_pc_plus_diff(cpu_pc, ctx, diff); 245 ctx->pc_save = ctx->base.pc_next + diff; 246 } 247 248 static void generate_exception(DisasContext *ctx, int excp) 249 { 250 gen_update_pc(ctx, 0); 251 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 252 ctx->base.is_jmp = DISAS_NORETURN; 253 } 254 255 static void gen_exception_illegal(DisasContext *ctx) 256 { 257 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 258 offsetof(CPURISCVState, bins)); 259 if (ctx->virt_inst_excp) { 260 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 261 } else { 262 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 263 } 264 } 265 266 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 267 { 268 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 269 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 270 } 271 272 static void lookup_and_goto_ptr(DisasContext *ctx) 273 { 274 #ifndef CONFIG_USER_ONLY 275 if (ctx->itrigger) { 276 gen_helper_itrigger_match(tcg_env); 277 } 278 #endif 279 tcg_gen_lookup_and_goto_ptr(); 280 } 281 282 static void exit_tb(DisasContext *ctx) 283 { 284 #ifndef CONFIG_USER_ONLY 285 if (ctx->itrigger) { 286 gen_helper_itrigger_match(tcg_env); 287 } 288 #endif 289 tcg_gen_exit_tb(NULL, 0); 290 } 291 292 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 293 { 294 target_ulong dest = ctx->base.pc_next + diff; 295 296 /* 297 * Under itrigger, instruction executes one by one like singlestep, 298 * direct block chain benefits will be small. 299 */ 300 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 301 /* 302 * For pcrel, the pc must always be up-to-date on entry to 303 * the linked TB, so that it can use simple additions for all 304 * further adjustments. For !pcrel, the linked TB is compiled 305 * to know its full virtual address, so we can delay the 306 * update to pc to the unlinked path. A long chain of links 307 * can thus avoid many updates to the PC. 308 */ 309 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 310 gen_update_pc(ctx, diff); 311 tcg_gen_goto_tb(n); 312 } else { 313 tcg_gen_goto_tb(n); 314 gen_update_pc(ctx, diff); 315 } 316 tcg_gen_exit_tb(ctx->base.tb, n); 317 } else { 318 gen_update_pc(ctx, diff); 319 lookup_and_goto_ptr(ctx); 320 } 321 } 322 323 /* 324 * Wrappers for getting reg values. 325 * 326 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 327 * constant zero as a source, and an uninitialized sink as destination. 328 * 329 * Further, we may provide an extension for word operations. 330 */ 331 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 332 { 333 TCGv t; 334 335 if (reg_num == 0) { 336 return ctx->zero; 337 } 338 339 switch (get_ol(ctx)) { 340 case MXL_RV32: 341 switch (ext) { 342 case EXT_NONE: 343 break; 344 case EXT_SIGN: 345 t = tcg_temp_new(); 346 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 347 return t; 348 case EXT_ZERO: 349 t = tcg_temp_new(); 350 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 351 return t; 352 default: 353 g_assert_not_reached(); 354 } 355 break; 356 case MXL_RV64: 357 case MXL_RV128: 358 break; 359 default: 360 g_assert_not_reached(); 361 } 362 return cpu_gpr[reg_num]; 363 } 364 365 static TCGv get_gprh(DisasContext *ctx, int reg_num) 366 { 367 assert(get_xl(ctx) == MXL_RV128); 368 if (reg_num == 0) { 369 return ctx->zero; 370 } 371 return cpu_gprh[reg_num]; 372 } 373 374 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 375 { 376 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 377 return tcg_temp_new(); 378 } 379 return cpu_gpr[reg_num]; 380 } 381 382 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 383 { 384 if (reg_num == 0) { 385 return tcg_temp_new(); 386 } 387 return cpu_gprh[reg_num]; 388 } 389 390 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 391 { 392 if (reg_num != 0) { 393 switch (get_ol(ctx)) { 394 case MXL_RV32: 395 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 396 break; 397 case MXL_RV64: 398 case MXL_RV128: 399 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 400 break; 401 default: 402 g_assert_not_reached(); 403 } 404 405 if (get_xl_max(ctx) == MXL_RV128) { 406 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 407 } 408 } 409 } 410 411 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 412 { 413 if (reg_num != 0) { 414 switch (get_ol(ctx)) { 415 case MXL_RV32: 416 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 417 break; 418 case MXL_RV64: 419 case MXL_RV128: 420 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 421 break; 422 default: 423 g_assert_not_reached(); 424 } 425 426 if (get_xl_max(ctx) == MXL_RV128) { 427 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 428 } 429 } 430 } 431 432 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 433 { 434 assert(get_ol(ctx) == MXL_RV128); 435 if (reg_num != 0) { 436 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 437 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 438 } 439 } 440 441 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 442 { 443 if (!ctx->cfg_ptr->ext_zfinx) { 444 return cpu_fpr[reg_num]; 445 } 446 447 if (reg_num == 0) { 448 return tcg_constant_i64(0); 449 } 450 switch (get_xl(ctx)) { 451 case MXL_RV32: 452 #ifdef TARGET_RISCV32 453 { 454 TCGv_i64 t = tcg_temp_new_i64(); 455 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 456 return t; 457 } 458 #else 459 /* fall through */ 460 case MXL_RV64: 461 return cpu_gpr[reg_num]; 462 #endif 463 default: 464 g_assert_not_reached(); 465 } 466 } 467 468 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 469 { 470 if (!ctx->cfg_ptr->ext_zfinx) { 471 return cpu_fpr[reg_num]; 472 } 473 474 if (reg_num == 0) { 475 return tcg_constant_i64(0); 476 } 477 switch (get_xl(ctx)) { 478 case MXL_RV32: 479 { 480 TCGv_i64 t = tcg_temp_new_i64(); 481 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 482 return t; 483 } 484 #ifdef TARGET_RISCV64 485 case MXL_RV64: 486 return cpu_gpr[reg_num]; 487 #endif 488 default: 489 g_assert_not_reached(); 490 } 491 } 492 493 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 494 { 495 if (!ctx->cfg_ptr->ext_zfinx) { 496 return cpu_fpr[reg_num]; 497 } 498 499 if (reg_num == 0) { 500 return tcg_temp_new_i64(); 501 } 502 503 switch (get_xl(ctx)) { 504 case MXL_RV32: 505 return tcg_temp_new_i64(); 506 #ifdef TARGET_RISCV64 507 case MXL_RV64: 508 return cpu_gpr[reg_num]; 509 #endif 510 default: 511 g_assert_not_reached(); 512 } 513 } 514 515 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 516 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 517 { 518 if (!ctx->cfg_ptr->ext_zfinx) { 519 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 520 return; 521 } 522 if (reg_num != 0) { 523 switch (get_xl(ctx)) { 524 case MXL_RV32: 525 #ifdef TARGET_RISCV32 526 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 527 break; 528 #else 529 /* fall through */ 530 case MXL_RV64: 531 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 532 break; 533 #endif 534 default: 535 g_assert_not_reached(); 536 } 537 } 538 } 539 540 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 541 { 542 if (!ctx->cfg_ptr->ext_zfinx) { 543 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 544 return; 545 } 546 547 if (reg_num != 0) { 548 switch (get_xl(ctx)) { 549 case MXL_RV32: 550 #ifdef TARGET_RISCV32 551 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 552 break; 553 #else 554 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 555 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 556 break; 557 case MXL_RV64: 558 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 559 break; 560 #endif 561 default: 562 g_assert_not_reached(); 563 } 564 } 565 } 566 567 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 568 { 569 TCGv succ_pc = dest_gpr(ctx, rd); 570 571 /* check misaligned: */ 572 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 573 if ((imm & 0x3) != 0) { 574 TCGv target_pc = tcg_temp_new(); 575 gen_pc_plus_diff(target_pc, ctx, imm); 576 gen_exception_inst_addr_mis(ctx, target_pc); 577 return; 578 } 579 } 580 581 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 582 gen_set_gpr(ctx, rd, succ_pc); 583 584 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 585 ctx->base.is_jmp = DISAS_NORETURN; 586 } 587 588 /* Compute a canonical address from a register plus offset. */ 589 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 590 { 591 TCGv addr = tcg_temp_new(); 592 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 593 594 tcg_gen_addi_tl(addr, src1, imm); 595 if (ctx->pm_mask_enabled) { 596 tcg_gen_andc_tl(addr, addr, pm_mask); 597 } else if (get_address_xl(ctx) == MXL_RV32) { 598 tcg_gen_ext32u_tl(addr, addr); 599 } 600 if (ctx->pm_base_enabled) { 601 tcg_gen_or_tl(addr, addr, pm_base); 602 } 603 604 return addr; 605 } 606 607 /* Compute a canonical address from a register plus reg offset. */ 608 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 609 { 610 TCGv addr = tcg_temp_new(); 611 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 612 613 tcg_gen_add_tl(addr, src1, offs); 614 if (ctx->pm_mask_enabled) { 615 tcg_gen_andc_tl(addr, addr, pm_mask); 616 } else if (get_xl(ctx) == MXL_RV32) { 617 tcg_gen_ext32u_tl(addr, addr); 618 } 619 if (ctx->pm_base_enabled) { 620 tcg_gen_or_tl(addr, addr, pm_base); 621 } 622 return addr; 623 } 624 625 #ifndef CONFIG_USER_ONLY 626 /* 627 * We will have already diagnosed disabled state, 628 * and need to turn initial/clean into dirty. 629 */ 630 static void mark_fs_dirty(DisasContext *ctx) 631 { 632 TCGv tmp; 633 634 if (!has_ext(ctx, RVF)) { 635 return; 636 } 637 638 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 639 /* Remember the state change for the rest of the TB. */ 640 ctx->mstatus_fs = EXT_STATUS_DIRTY; 641 642 tmp = tcg_temp_new(); 643 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 644 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 645 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 646 647 if (ctx->virt_enabled) { 648 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 649 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 650 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 651 } 652 } 653 } 654 #else 655 static inline void mark_fs_dirty(DisasContext *ctx) { } 656 #endif 657 658 #ifndef CONFIG_USER_ONLY 659 /* 660 * We will have already diagnosed disabled state, 661 * and need to turn initial/clean into dirty. 662 */ 663 static void mark_vs_dirty(DisasContext *ctx) 664 { 665 TCGv tmp; 666 667 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 668 /* Remember the state change for the rest of the TB. */ 669 ctx->mstatus_vs = EXT_STATUS_DIRTY; 670 671 tmp = tcg_temp_new(); 672 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 673 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 674 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 675 676 if (ctx->virt_enabled) { 677 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 678 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 679 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 680 } 681 } 682 } 683 #else 684 static inline void mark_vs_dirty(DisasContext *ctx) { } 685 #endif 686 687 static void finalize_rvv_inst(DisasContext *ctx) 688 { 689 mark_vs_dirty(ctx); 690 ctx->vstart_eq_zero = true; 691 } 692 693 static void gen_set_rm(DisasContext *ctx, int rm) 694 { 695 if (ctx->frm == rm) { 696 return; 697 } 698 ctx->frm = rm; 699 700 if (rm == RISCV_FRM_DYN) { 701 /* The helper will return only if frm valid. */ 702 ctx->frm_valid = true; 703 } 704 705 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 706 decode_save_opc(ctx, 0); 707 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 708 } 709 710 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 711 { 712 if (ctx->frm == rm && ctx->frm_valid) { 713 return; 714 } 715 ctx->frm = rm; 716 ctx->frm_valid = true; 717 718 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 719 decode_save_opc(ctx, 0); 720 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 721 } 722 723 static int ex_plus_1(DisasContext *ctx, int nf) 724 { 725 return nf + 1; 726 } 727 728 #define EX_SH(amount) \ 729 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 730 { \ 731 return imm << amount; \ 732 } 733 EX_SH(1) 734 EX_SH(2) 735 EX_SH(3) 736 EX_SH(4) 737 EX_SH(12) 738 739 #define REQUIRE_EXT(ctx, ext) do { \ 740 if (!has_ext(ctx, ext)) { \ 741 return false; \ 742 } \ 743 } while (0) 744 745 #define REQUIRE_32BIT(ctx) do { \ 746 if (get_xl(ctx) != MXL_RV32) { \ 747 return false; \ 748 } \ 749 } while (0) 750 751 #define REQUIRE_64BIT(ctx) do { \ 752 if (get_xl(ctx) != MXL_RV64) { \ 753 return false; \ 754 } \ 755 } while (0) 756 757 #define REQUIRE_128BIT(ctx) do { \ 758 if (get_xl(ctx) != MXL_RV128) { \ 759 return false; \ 760 } \ 761 } while (0) 762 763 #define REQUIRE_64_OR_128BIT(ctx) do { \ 764 if (get_xl(ctx) == MXL_RV32) { \ 765 return false; \ 766 } \ 767 } while (0) 768 769 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 770 if (!ctx->cfg_ptr->ext_##A && \ 771 !ctx->cfg_ptr->ext_##B) { \ 772 return false; \ 773 } \ 774 } while (0) 775 776 static int ex_rvc_register(DisasContext *ctx, int reg) 777 { 778 return 8 + reg; 779 } 780 781 static int ex_sreg_register(DisasContext *ctx, int reg) 782 { 783 return reg < 2 ? reg + 8 : reg + 16; 784 } 785 786 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 787 { 788 /* For RV128 a shamt of 0 means a shift by 64. */ 789 if (get_ol(ctx) == MXL_RV128) { 790 imm = imm ? imm : 64; 791 } 792 return imm; 793 } 794 795 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 796 { 797 /* 798 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 799 * shifts, the shamt is sign-extended. 800 */ 801 if (get_ol(ctx) == MXL_RV128) { 802 imm = imm | (imm & 32) << 1; 803 imm = imm ? imm : 64; 804 } 805 return imm; 806 } 807 808 /* Include the auto-generated decoder for 32 bit insn */ 809 #include "decode-insn32.c.inc" 810 811 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 812 void (*func)(TCGv, TCGv, target_long)) 813 { 814 TCGv dest = dest_gpr(ctx, a->rd); 815 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 816 817 func(dest, src1, a->imm); 818 819 if (get_xl(ctx) == MXL_RV128) { 820 TCGv src1h = get_gprh(ctx, a->rs1); 821 TCGv desth = dest_gprh(ctx, a->rd); 822 823 func(desth, src1h, -(a->imm < 0)); 824 gen_set_gpr128(ctx, a->rd, dest, desth); 825 } else { 826 gen_set_gpr(ctx, a->rd, dest); 827 } 828 829 return true; 830 } 831 832 static bool gen_logic(DisasContext *ctx, arg_r *a, 833 void (*func)(TCGv, TCGv, TCGv)) 834 { 835 TCGv dest = dest_gpr(ctx, a->rd); 836 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 837 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 838 839 func(dest, src1, src2); 840 841 if (get_xl(ctx) == MXL_RV128) { 842 TCGv src1h = get_gprh(ctx, a->rs1); 843 TCGv src2h = get_gprh(ctx, a->rs2); 844 TCGv desth = dest_gprh(ctx, a->rd); 845 846 func(desth, src1h, src2h); 847 gen_set_gpr128(ctx, a->rd, dest, desth); 848 } else { 849 gen_set_gpr(ctx, a->rd, dest); 850 } 851 852 return true; 853 } 854 855 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 856 void (*func)(TCGv, TCGv, target_long), 857 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 858 { 859 TCGv dest = dest_gpr(ctx, a->rd); 860 TCGv src1 = get_gpr(ctx, a->rs1, ext); 861 862 if (get_ol(ctx) < MXL_RV128) { 863 func(dest, src1, a->imm); 864 gen_set_gpr(ctx, a->rd, dest); 865 } else { 866 if (f128 == NULL) { 867 return false; 868 } 869 870 TCGv src1h = get_gprh(ctx, a->rs1); 871 TCGv desth = dest_gprh(ctx, a->rd); 872 873 f128(dest, desth, src1, src1h, a->imm); 874 gen_set_gpr128(ctx, a->rd, dest, desth); 875 } 876 return true; 877 } 878 879 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 880 void (*func)(TCGv, TCGv, TCGv), 881 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 882 { 883 TCGv dest = dest_gpr(ctx, a->rd); 884 TCGv src1 = get_gpr(ctx, a->rs1, ext); 885 TCGv src2 = tcg_constant_tl(a->imm); 886 887 if (get_ol(ctx) < MXL_RV128) { 888 func(dest, src1, src2); 889 gen_set_gpr(ctx, a->rd, dest); 890 } else { 891 if (f128 == NULL) { 892 return false; 893 } 894 895 TCGv src1h = get_gprh(ctx, a->rs1); 896 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 897 TCGv desth = dest_gprh(ctx, a->rd); 898 899 f128(dest, desth, src1, src1h, src2, src2h); 900 gen_set_gpr128(ctx, a->rd, dest, desth); 901 } 902 return true; 903 } 904 905 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 906 void (*func)(TCGv, TCGv, TCGv), 907 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 908 { 909 TCGv dest = dest_gpr(ctx, a->rd); 910 TCGv src1 = get_gpr(ctx, a->rs1, ext); 911 TCGv src2 = get_gpr(ctx, a->rs2, ext); 912 913 if (get_ol(ctx) < MXL_RV128) { 914 func(dest, src1, src2); 915 gen_set_gpr(ctx, a->rd, dest); 916 } else { 917 if (f128 == NULL) { 918 return false; 919 } 920 921 TCGv src1h = get_gprh(ctx, a->rs1); 922 TCGv src2h = get_gprh(ctx, a->rs2); 923 TCGv desth = dest_gprh(ctx, a->rd); 924 925 f128(dest, desth, src1, src1h, src2, src2h); 926 gen_set_gpr128(ctx, a->rd, dest, desth); 927 } 928 return true; 929 } 930 931 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 932 void (*f_tl)(TCGv, TCGv, TCGv), 933 void (*f_32)(TCGv, TCGv, TCGv), 934 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 935 { 936 int olen = get_olen(ctx); 937 938 if (olen != TARGET_LONG_BITS) { 939 if (olen == 32) { 940 f_tl = f_32; 941 } else if (olen != 128) { 942 g_assert_not_reached(); 943 } 944 } 945 return gen_arith(ctx, a, ext, f_tl, f_128); 946 } 947 948 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 949 void (*func)(TCGv, TCGv, target_long), 950 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 951 { 952 TCGv dest, src1; 953 int max_len = get_olen(ctx); 954 955 if (a->shamt >= max_len) { 956 return false; 957 } 958 959 dest = dest_gpr(ctx, a->rd); 960 src1 = get_gpr(ctx, a->rs1, ext); 961 962 if (max_len < 128) { 963 func(dest, src1, a->shamt); 964 gen_set_gpr(ctx, a->rd, dest); 965 } else { 966 TCGv src1h = get_gprh(ctx, a->rs1); 967 TCGv desth = dest_gprh(ctx, a->rd); 968 969 if (f128 == NULL) { 970 return false; 971 } 972 f128(dest, desth, src1, src1h, a->shamt); 973 gen_set_gpr128(ctx, a->rd, dest, desth); 974 } 975 return true; 976 } 977 978 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 979 DisasExtend ext, 980 void (*f_tl)(TCGv, TCGv, target_long), 981 void (*f_32)(TCGv, TCGv, target_long), 982 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 983 target_long)) 984 { 985 int olen = get_olen(ctx); 986 if (olen != TARGET_LONG_BITS) { 987 if (olen == 32) { 988 f_tl = f_32; 989 } else if (olen != 128) { 990 g_assert_not_reached(); 991 } 992 } 993 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 994 } 995 996 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 997 void (*func)(TCGv, TCGv, TCGv)) 998 { 999 TCGv dest, src1, src2; 1000 int max_len = get_olen(ctx); 1001 1002 if (a->shamt >= max_len) { 1003 return false; 1004 } 1005 1006 dest = dest_gpr(ctx, a->rd); 1007 src1 = get_gpr(ctx, a->rs1, ext); 1008 src2 = tcg_constant_tl(a->shamt); 1009 1010 func(dest, src1, src2); 1011 1012 gen_set_gpr(ctx, a->rd, dest); 1013 return true; 1014 } 1015 1016 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1017 void (*func)(TCGv, TCGv, TCGv), 1018 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1019 { 1020 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1021 TCGv ext2 = tcg_temp_new(); 1022 int max_len = get_olen(ctx); 1023 1024 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1025 1026 TCGv dest = dest_gpr(ctx, a->rd); 1027 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1028 1029 if (max_len < 128) { 1030 func(dest, src1, ext2); 1031 gen_set_gpr(ctx, a->rd, dest); 1032 } else { 1033 TCGv src1h = get_gprh(ctx, a->rs1); 1034 TCGv desth = dest_gprh(ctx, a->rd); 1035 1036 if (f128 == NULL) { 1037 return false; 1038 } 1039 f128(dest, desth, src1, src1h, ext2); 1040 gen_set_gpr128(ctx, a->rd, dest, desth); 1041 } 1042 return true; 1043 } 1044 1045 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1046 void (*f_tl)(TCGv, TCGv, TCGv), 1047 void (*f_32)(TCGv, TCGv, TCGv), 1048 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1049 { 1050 int olen = get_olen(ctx); 1051 if (olen != TARGET_LONG_BITS) { 1052 if (olen == 32) { 1053 f_tl = f_32; 1054 } else if (olen != 128) { 1055 g_assert_not_reached(); 1056 } 1057 } 1058 return gen_shift(ctx, a, ext, f_tl, f_128); 1059 } 1060 1061 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1062 void (*func)(TCGv, TCGv)) 1063 { 1064 TCGv dest = dest_gpr(ctx, a->rd); 1065 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1066 1067 func(dest, src1); 1068 1069 gen_set_gpr(ctx, a->rd, dest); 1070 return true; 1071 } 1072 1073 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1074 void (*f_tl)(TCGv, TCGv), 1075 void (*f_32)(TCGv, TCGv)) 1076 { 1077 int olen = get_olen(ctx); 1078 1079 if (olen != TARGET_LONG_BITS) { 1080 if (olen == 32) { 1081 f_tl = f_32; 1082 } else { 1083 g_assert_not_reached(); 1084 } 1085 } 1086 return gen_unary(ctx, a, ext, f_tl); 1087 } 1088 1089 static bool gen_amo(DisasContext *ctx, arg_atomic *a, 1090 void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), 1091 MemOp mop) 1092 { 1093 TCGv dest = dest_gpr(ctx, a->rd); 1094 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1095 MemOp size = mop & MO_SIZE; 1096 1097 if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) { 1098 mop |= MO_ATOM_WITHIN16; 1099 } else { 1100 mop |= MO_ALIGN; 1101 } 1102 1103 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1104 src1 = get_address(ctx, a->rs1, 0); 1105 func(dest, src1, src2, ctx->mem_idx, mop); 1106 1107 gen_set_gpr(ctx, a->rd, dest); 1108 return true; 1109 } 1110 1111 static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) 1112 { 1113 TCGv dest = get_gpr(ctx, a->rd, EXT_NONE); 1114 TCGv src1 = get_address(ctx, a->rs1, 0); 1115 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1116 1117 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1118 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); 1119 1120 gen_set_gpr(ctx, a->rd, dest); 1121 return true; 1122 } 1123 1124 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1125 { 1126 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1127 CPUState *cpu = ctx->cs; 1128 CPURISCVState *env = cpu_env(cpu); 1129 1130 return translator_ldl(env, &ctx->base, pc); 1131 } 1132 1133 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) 1134 1135 /* Include insn module translation function */ 1136 #include "insn_trans/trans_rvi.c.inc" 1137 #include "insn_trans/trans_rvm.c.inc" 1138 #include "insn_trans/trans_rva.c.inc" 1139 #include "insn_trans/trans_rvf.c.inc" 1140 #include "insn_trans/trans_rvd.c.inc" 1141 #include "insn_trans/trans_rvh.c.inc" 1142 #include "insn_trans/trans_rvv.c.inc" 1143 #include "insn_trans/trans_rvb.c.inc" 1144 #include "insn_trans/trans_rvzicond.c.inc" 1145 #include "insn_trans/trans_rvzacas.c.inc" 1146 #include "insn_trans/trans_rvzabha.c.inc" 1147 #include "insn_trans/trans_rvzawrs.c.inc" 1148 #include "insn_trans/trans_rvzicbo.c.inc" 1149 #include "insn_trans/trans_rvzimop.c.inc" 1150 #include "insn_trans/trans_rvzfa.c.inc" 1151 #include "insn_trans/trans_rvzfh.c.inc" 1152 #include "insn_trans/trans_rvk.c.inc" 1153 #include "insn_trans/trans_rvvk.c.inc" 1154 #include "insn_trans/trans_privileged.c.inc" 1155 #include "insn_trans/trans_svinval.c.inc" 1156 #include "insn_trans/trans_rvbf16.c.inc" 1157 #include "decode-xthead.c.inc" 1158 #include "insn_trans/trans_xthead.c.inc" 1159 #include "insn_trans/trans_xventanacondops.c.inc" 1160 1161 /* Include the auto-generated decoder for 16 bit insn */ 1162 #include "decode-insn16.c.inc" 1163 #include "insn_trans/trans_rvzce.c.inc" 1164 #include "insn_trans/trans_rvzcmop.c.inc" 1165 #include "insn_trans/trans_rvzicfiss.c.inc" 1166 1167 /* Include decoders for factored-out extensions */ 1168 #include "decode-XVentanaCondOps.c.inc" 1169 1170 /* The specification allows for longer insns, but not supported by qemu. */ 1171 #define MAX_INSN_LEN 4 1172 1173 static inline int insn_len(uint16_t first_word) 1174 { 1175 return (first_word & 3) == 3 ? 4 : 2; 1176 } 1177 1178 const RISCVDecoder decoder_table[] = { 1179 { always_true_p, decode_insn32 }, 1180 { has_xthead_p, decode_xthead}, 1181 { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, 1182 }; 1183 1184 const size_t decoder_table_size = ARRAY_SIZE(decoder_table); 1185 1186 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1187 { 1188 ctx->virt_inst_excp = false; 1189 ctx->cur_insn_len = insn_len(opcode); 1190 /* Check for compressed insn */ 1191 if (ctx->cur_insn_len == 2) { 1192 ctx->opcode = opcode; 1193 /* 1194 * The Zca extension is added as way to refer to instructions in the C 1195 * extension that do not include the floating-point loads and stores 1196 */ 1197 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1198 decode_insn16(ctx, opcode)) { 1199 return; 1200 } 1201 } else { 1202 uint32_t opcode32 = opcode; 1203 opcode32 = deposit32(opcode32, 16, 16, 1204 translator_lduw(env, &ctx->base, 1205 ctx->base.pc_next + 2)); 1206 ctx->opcode = opcode32; 1207 1208 for (guint i = 0; i < ctx->decoders->len; ++i) { 1209 riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i); 1210 if (func(ctx, opcode32)) { 1211 return; 1212 } 1213 } 1214 } 1215 1216 gen_exception_illegal(ctx); 1217 } 1218 1219 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1220 { 1221 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1222 CPURISCVState *env = cpu_env(cs); 1223 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1224 RISCVCPU *cpu = RISCV_CPU(cs); 1225 uint32_t tb_flags = ctx->base.tb->flags; 1226 1227 ctx->pc_save = ctx->base.pc_first; 1228 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1229 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1230 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1231 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1232 ctx->priv_ver = env->priv_ver; 1233 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1234 ctx->misa_ext = env->misa_ext; 1235 ctx->frm = -1; /* unknown rounding mode */ 1236 ctx->cfg_ptr = &(cpu->cfg); 1237 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1238 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1239 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1240 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1241 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1242 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1243 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1244 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1245 ctx->misa_mxl_max = mcc->misa_mxl_max; 1246 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1247 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1248 ctx->cs = cs; 1249 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1250 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1251 ctx->ztso = cpu->cfg.ext_ztso; 1252 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1253 ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); 1254 ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); 1255 ctx->fcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); 1256 ctx->zero = tcg_constant_tl(0); 1257 ctx->virt_inst_excp = false; 1258 ctx->decoders = cpu->decoders; 1259 } 1260 1261 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1262 { 1263 } 1264 1265 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1266 { 1267 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1268 target_ulong pc_next = ctx->base.pc_next; 1269 1270 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1271 pc_next &= ~TARGET_PAGE_MASK; 1272 } 1273 1274 tcg_gen_insn_start(pc_next, 0, 0); 1275 ctx->insn_start_updated = false; 1276 } 1277 1278 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1279 { 1280 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1281 CPURISCVState *env = cpu_env(cpu); 1282 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1283 1284 ctx->ol = ctx->xl; 1285 decode_opc(env, ctx, opcode16); 1286 ctx->base.pc_next += ctx->cur_insn_len; 1287 1288 /* 1289 * If 'fcfi_lp_expected' is still true after processing the instruction, 1290 * then we did not see an 'lpad' instruction, and must raise an exception. 1291 * Insert code to raise the exception at the start of the insn; any other 1292 * code the insn may have emitted will be deleted as dead code following 1293 * the noreturn exception 1294 */ 1295 if (ctx->fcfi_lp_expected) { 1296 /* Emit after insn_start, i.e. before the op following insn_start. */ 1297 tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link); 1298 tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), 1299 tcg_env, offsetof(CPURISCVState, sw_check_code)); 1300 gen_helper_raise_exception(tcg_env, 1301 tcg_constant_i32(RISCV_EXCP_SW_CHECK)); 1302 tcg_ctx->emit_before_op = NULL; 1303 ctx->base.is_jmp = DISAS_NORETURN; 1304 } 1305 1306 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1307 if (ctx->base.is_jmp == DISAS_NEXT) { 1308 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1309 ctx->base.is_jmp = DISAS_TOO_MANY; 1310 } else { 1311 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1312 1313 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1314 uint16_t next_insn = 1315 translator_lduw(env, &ctx->base, ctx->base.pc_next); 1316 int len = insn_len(next_insn); 1317 1318 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1319 ctx->base.is_jmp = DISAS_TOO_MANY; 1320 } 1321 } 1322 } 1323 } 1324 } 1325 1326 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1327 { 1328 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1329 1330 switch (ctx->base.is_jmp) { 1331 case DISAS_TOO_MANY: 1332 gen_goto_tb(ctx, 0, 0); 1333 break; 1334 case DISAS_NORETURN: 1335 break; 1336 default: 1337 g_assert_not_reached(); 1338 } 1339 } 1340 1341 static const TranslatorOps riscv_tr_ops = { 1342 .init_disas_context = riscv_tr_init_disas_context, 1343 .tb_start = riscv_tr_tb_start, 1344 .insn_start = riscv_tr_insn_start, 1345 .translate_insn = riscv_tr_translate_insn, 1346 .tb_stop = riscv_tr_tb_stop, 1347 }; 1348 1349 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1350 vaddr pc, void *host_pc) 1351 { 1352 DisasContext ctx; 1353 1354 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1355 } 1356 1357 void riscv_translate_init(void) 1358 { 1359 int i; 1360 1361 /* 1362 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1363 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1364 * unless you specifically block reads/writes to reg 0. 1365 */ 1366 cpu_gpr[0] = NULL; 1367 cpu_gprh[0] = NULL; 1368 1369 for (i = 1; i < 32; i++) { 1370 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1371 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1372 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1373 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1374 } 1375 1376 for (i = 0; i < 32; i++) { 1377 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1378 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1379 } 1380 1381 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1382 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1383 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1384 "vstart"); 1385 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1386 "load_res"); 1387 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1388 "load_val"); 1389 /* Assign PM CSRs to tcg globals */ 1390 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1391 "pmmask"); 1392 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1393 "pmbase"); 1394 } 1395