1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/translation-block.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "exec/target_page.h" 25 #include "internals.h" 26 #include "pmu.h" 27 #include "time_helper.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/accel.h" 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "accel/accel-cpu-target.h" 34 #include "accel/tcg/cpu-ops.h" 35 #include "tcg/tcg.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "hw/boards.h" 38 #include "system/tcg.h" 39 #include "exec/icount.h" 40 #endif 41 42 /* Hash that stores user set extensions */ 43 static GHashTable *multi_ext_user_opts; 44 static GHashTable *misa_ext_user_opts; 45 46 static GHashTable *multi_ext_implied_rules; 47 static GHashTable *misa_ext_implied_rules; 48 49 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 50 { 51 return g_hash_table_contains(multi_ext_user_opts, 52 GUINT_TO_POINTER(ext_offset)); 53 } 54 55 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 56 { 57 return g_hash_table_contains(misa_ext_user_opts, 58 GUINT_TO_POINTER(misa_bit)); 59 } 60 61 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 62 { 63 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 64 (gpointer)value); 65 } 66 67 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 68 { 69 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 70 (gpointer)value); 71 } 72 73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 74 bool enabled) 75 { 76 CPURISCVState *env = &cpu->env; 77 78 if (enabled) { 79 env->misa_ext |= bit; 80 env->misa_ext_mask |= bit; 81 } else { 82 env->misa_ext &= ~bit; 83 env->misa_ext_mask &= ~bit; 84 } 85 } 86 87 static const char *cpu_priv_ver_to_str(int priv_ver) 88 { 89 const char *priv_spec_str = priv_spec_to_str(priv_ver); 90 91 g_assert(priv_spec_str); 92 93 return priv_spec_str; 94 } 95 96 static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) 97 { 98 return riscv_env_mmu_index(cpu_env(cs), ifetch); 99 } 100 101 static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) 102 { 103 CPURISCVState *env = cpu_env(cs); 104 RISCVCPU *cpu = env_archcpu(env); 105 RISCVExtStatus fs, vs; 106 uint32_t flags = 0; 107 bool pm_signext = riscv_cpu_virt_mem_enabled(env); 108 109 if (cpu->cfg.ext_zve32x) { 110 /* 111 * If env->vl equals to VLMAX, we can use generic vector operation 112 * expanders (GVEC) to accerlate the vector operations. 113 * However, as LMUL could be a fractional number. The maximum 114 * vector size can be operated might be less than 8 bytes, 115 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 116 * only when maxsz >= 8 bytes. 117 */ 118 119 /* lmul encoded as in DisasContext::lmul */ 120 int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); 121 uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); 122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); 123 uint32_t maxsz = vlmax << vsew; 124 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 125 (maxsz >= 8); 126 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 127 flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); 128 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 129 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 130 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 131 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 132 FIELD_EX64(env->vtype, VTYPE, VTA)); 133 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 134 FIELD_EX64(env->vtype, VTYPE, VMA)); 135 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 136 } else { 137 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 138 } 139 140 if (cpu_get_fcfien(env)) { 141 /* 142 * For Forward CFI, only the expectation of a lpad at 143 * the start of the block is tracked via env->elp. env->elp 144 * is turned on during jalr translation. 145 */ 146 flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); 147 flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); 148 } 149 150 if (cpu_get_bcfien(env)) { 151 flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); 152 } 153 154 #ifdef CONFIG_USER_ONLY 155 fs = EXT_STATUS_DIRTY; 156 vs = EXT_STATUS_DIRTY; 157 #else 158 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); 159 160 flags |= riscv_env_mmu_index(env, 0); 161 fs = get_field(env->mstatus, MSTATUS_FS); 162 vs = get_field(env->mstatus, MSTATUS_VS); 163 164 if (env->virt_enabled) { 165 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 166 /* 167 * Merge DISABLED and !DIRTY states using MIN. 168 * We will set both fields when dirtying. 169 */ 170 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 171 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 172 } 173 174 /* With Zfinx, floating point is enabled/disabled by Smstateen. */ 175 if (!riscv_has_ext(env, RVF)) { 176 fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) 177 ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; 178 } 179 180 if (cpu->cfg.debug && !icount_enabled()) { 181 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 182 } 183 #endif 184 185 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 186 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 187 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 188 flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); 189 flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); 190 flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); 191 192 return (TCGTBCPUState){ 193 .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, 194 .flags = flags 195 }; 196 } 197 198 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 199 const TranslationBlock *tb) 200 { 201 if (!(tb_cflags(tb) & CF_PCREL)) { 202 RISCVCPU *cpu = RISCV_CPU(cs); 203 CPURISCVState *env = &cpu->env; 204 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 205 206 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 207 208 if (xl == MXL_RV32) { 209 env->pc = (int32_t) tb->pc; 210 } else { 211 env->pc = tb->pc; 212 } 213 } 214 } 215 216 static void riscv_restore_state_to_opc(CPUState *cs, 217 const TranslationBlock *tb, 218 const uint64_t *data) 219 { 220 RISCVCPU *cpu = RISCV_CPU(cs); 221 CPURISCVState *env = &cpu->env; 222 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 223 target_ulong pc; 224 225 if (tb_cflags(tb) & CF_PCREL) { 226 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 227 } else { 228 pc = data[0]; 229 } 230 231 if (xl == MXL_RV32) { 232 env->pc = (int32_t)pc; 233 } else { 234 env->pc = pc; 235 } 236 env->bins = data[1]; 237 env->excp_uw2 = data[2]; 238 } 239 240 const TCGCPUOps riscv_tcg_ops = { 241 .mttcg_supported = true, 242 .guest_default_memory_order = 0, 243 244 .initialize = riscv_translate_init, 245 .translate_code = riscv_translate_code, 246 .get_tb_cpu_state = riscv_get_tb_cpu_state, 247 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 248 .restore_state_to_opc = riscv_restore_state_to_opc, 249 .mmu_index = riscv_cpu_mmu_index, 250 251 #ifndef CONFIG_USER_ONLY 252 .tlb_fill = riscv_cpu_tlb_fill, 253 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 254 .cpu_exec_halt = riscv_cpu_has_work, 255 .cpu_exec_reset = cpu_reset, 256 .do_interrupt = riscv_cpu_do_interrupt, 257 .do_transaction_failed = riscv_cpu_do_transaction_failed, 258 .do_unaligned_access = riscv_cpu_do_unaligned_access, 259 .debug_excp_handler = riscv_cpu_debug_excp_handler, 260 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 261 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 262 #endif /* !CONFIG_USER_ONLY */ 263 }; 264 265 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 266 { 267 const RISCVIsaExtData *edata; 268 269 for (edata = isa_edata_arr; edata && edata->name; edata++) { 270 if (edata->ext_enable_offset != ext_offset) { 271 continue; 272 } 273 274 return edata->min_version; 275 } 276 277 g_assert_not_reached(); 278 } 279 280 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 281 { 282 const RISCVCPUMultiExtConfig *feat; 283 const RISCVIsaExtData *edata; 284 285 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 286 if (edata->ext_enable_offset == ext_offset) { 287 return edata->name; 288 } 289 } 290 291 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 292 if (feat->offset == ext_offset) { 293 return feat->name; 294 } 295 } 296 297 g_assert_not_reached(); 298 } 299 300 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 301 { 302 const RISCVCPUMultiExtConfig *feat; 303 304 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 305 if (feat->offset == ext_offset) { 306 return true; 307 } 308 } 309 310 return false; 311 } 312 313 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 314 { 315 /* 316 * All other named features are already enabled 317 * in riscv_tcg_cpu_instance_init(). 318 */ 319 switch (feat_offset) { 320 case CPU_CFG_OFFSET(ext_zic64b): 321 cpu->cfg.cbom_blocksize = 64; 322 cpu->cfg.cbop_blocksize = 64; 323 cpu->cfg.cboz_blocksize = 64; 324 break; 325 case CPU_CFG_OFFSET(ext_sha): 326 if (!cpu_misa_ext_is_user_set(RVH)) { 327 riscv_cpu_write_misa_bit(cpu, RVH, true); 328 } 329 /* fallthrough */ 330 case CPU_CFG_OFFSET(ext_ssstateen): 331 cpu->cfg.ext_smstateen = true; 332 break; 333 } 334 } 335 336 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 337 uint32_t ext_offset) 338 { 339 int ext_priv_ver; 340 341 if (env->priv_ver == PRIV_VERSION_LATEST) { 342 return; 343 } 344 345 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 346 347 if (env->priv_ver < ext_priv_ver) { 348 /* 349 * Note: the 'priv_spec' command line option, if present, 350 * will take precedence over this priv_ver bump. 351 */ 352 env->priv_ver = ext_priv_ver; 353 } 354 } 355 356 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 357 bool value) 358 { 359 CPURISCVState *env = &cpu->env; 360 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 361 int min_version; 362 363 if (prev_val == value) { 364 return; 365 } 366 367 if (cpu_cfg_ext_is_user_set(ext_offset)) { 368 return; 369 } 370 371 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 372 /* Do not enable it if priv_ver is older than min_version */ 373 min_version = cpu_cfg_ext_get_min_version(ext_offset); 374 if (env->priv_ver < min_version) { 375 return; 376 } 377 } 378 379 isa_ext_update_enabled(cpu, ext_offset, value); 380 } 381 382 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 383 { 384 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 385 error_setg(errp, "H extension requires priv spec 1.12.0"); 386 return; 387 } 388 } 389 390 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 391 Error **errp) 392 { 393 uint32_t vlen = cfg->vlenb << 3; 394 395 if (vlen > RV_VLEN_MAX || vlen < 128) { 396 error_setg(errp, 397 "Vector extension implementation only supports VLEN " 398 "in the range [128, %d]", RV_VLEN_MAX); 399 return; 400 } 401 402 if (cfg->elen > 64 || cfg->elen < 8) { 403 error_setg(errp, 404 "Vector extension implementation only supports ELEN " 405 "in the range [8, 64]"); 406 return; 407 } 408 } 409 410 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 411 { 412 CPURISCVState *env = &cpu->env; 413 const RISCVIsaExtData *edata; 414 415 /* Force disable extensions if priv spec version does not match */ 416 for (edata = isa_edata_arr; edata && edata->name; edata++) { 417 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 418 (env->priv_ver < edata->min_version)) { 419 /* 420 * These two extensions are always enabled as they were supported 421 * by QEMU before they were added as extensions in the ISA. 422 */ 423 if (!strcmp(edata->name, "zicntr") || 424 !strcmp(edata->name, "zihpm")) { 425 continue; 426 } 427 428 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 429 430 /* 431 * Do not show user warnings for named features that users 432 * can't enable/disable in the command line. See commit 433 * 68c9e54bea for more info. 434 */ 435 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 436 continue; 437 } 438 #ifndef CONFIG_USER_ONLY 439 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 440 " because privilege spec version does not match", 441 edata->name, env->mhartid); 442 #else 443 warn_report("disabling %s extension because " 444 "privilege spec version does not match", 445 edata->name); 446 #endif 447 } 448 } 449 } 450 451 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 452 { 453 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 454 cpu->cfg.has_priv_1_11 = true; 455 } 456 457 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 458 cpu->cfg.has_priv_1_12 = true; 459 } 460 461 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 462 cpu->cfg.has_priv_1_13 = true; 463 } 464 465 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 466 cpu->cfg.cbop_blocksize == 64 && 467 cpu->cfg.cboz_blocksize == 64; 468 469 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 470 471 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 472 cpu->cfg.ext_ssstateen; 473 474 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; 475 } 476 477 static void riscv_cpu_validate_g(RISCVCPU *cpu) 478 { 479 const char *warn_msg = "RVG mandates disabled extension %s"; 480 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 481 bool send_warn = cpu_misa_ext_is_user_set(RVG); 482 483 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 484 uint32_t bit = g_misa_bits[i]; 485 486 if (riscv_has_ext(&cpu->env, bit)) { 487 continue; 488 } 489 490 if (!cpu_misa_ext_is_user_set(bit)) { 491 riscv_cpu_write_misa_bit(cpu, bit, true); 492 continue; 493 } 494 495 if (send_warn) { 496 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 497 } 498 } 499 500 if (!cpu->cfg.ext_zicsr) { 501 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 502 cpu->cfg.ext_zicsr = true; 503 } else if (send_warn) { 504 warn_report(warn_msg, "zicsr"); 505 } 506 } 507 508 if (!cpu->cfg.ext_zifencei) { 509 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 510 cpu->cfg.ext_zifencei = true; 511 } else if (send_warn) { 512 warn_report(warn_msg, "zifencei"); 513 } 514 } 515 } 516 517 static void riscv_cpu_validate_b(RISCVCPU *cpu) 518 { 519 const char *warn_msg = "RVB mandates disabled extension %s"; 520 521 if (!cpu->cfg.ext_zba) { 522 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 523 cpu->cfg.ext_zba = true; 524 } else { 525 warn_report(warn_msg, "zba"); 526 } 527 } 528 529 if (!cpu->cfg.ext_zbb) { 530 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 531 cpu->cfg.ext_zbb = true; 532 } else { 533 warn_report(warn_msg, "zbb"); 534 } 535 } 536 537 if (!cpu->cfg.ext_zbs) { 538 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 539 cpu->cfg.ext_zbs = true; 540 } else { 541 warn_report(warn_msg, "zbs"); 542 } 543 } 544 } 545 546 /* 547 * Check consistency between chosen extensions while setting 548 * cpu->cfg accordingly. 549 */ 550 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 551 { 552 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 553 CPURISCVState *env = &cpu->env; 554 Error *local_err = NULL; 555 556 if (riscv_has_ext(env, RVG)) { 557 riscv_cpu_validate_g(cpu); 558 } 559 560 if (riscv_has_ext(env, RVB)) { 561 riscv_cpu_validate_b(cpu); 562 } 563 564 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 565 error_setg(errp, 566 "I and E extensions are incompatible"); 567 return; 568 } 569 570 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 571 error_setg(errp, 572 "Either I or E extension must be set"); 573 return; 574 } 575 576 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 577 error_setg(errp, 578 "Setting S extension without U extension is illegal"); 579 return; 580 } 581 582 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 583 error_setg(errp, 584 "H depends on an I base integer ISA with 32 x registers"); 585 return; 586 } 587 588 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 589 error_setg(errp, "H extension implicitly requires S-mode"); 590 return; 591 } 592 593 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 594 error_setg(errp, "F extension requires Zicsr"); 595 return; 596 } 597 598 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 599 error_setg(errp, "Zacas extension requires A extension"); 600 return; 601 } 602 603 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 604 error_setg(errp, "Zawrs extension requires A extension"); 605 return; 606 } 607 608 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 609 error_setg(errp, "Zfa extension requires F extension"); 610 return; 611 } 612 613 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 614 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 615 return; 616 } 617 618 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 619 error_setg(errp, "Zfbfmin extension depends on F extension"); 620 return; 621 } 622 623 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 624 error_setg(errp, "D extension requires F extension"); 625 return; 626 } 627 628 if (riscv_has_ext(env, RVV)) { 629 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 630 if (local_err != NULL) { 631 error_propagate(errp, local_err); 632 return; 633 } 634 } 635 636 /* The Zve64d extension depends on the Zve64f extension */ 637 if (cpu->cfg.ext_zve64d) { 638 if (!riscv_has_ext(env, RVD)) { 639 error_setg(errp, "Zve64d/V extensions require D extension"); 640 return; 641 } 642 } 643 644 /* The Zve32f extension depends on the Zve32x extension */ 645 if (cpu->cfg.ext_zve32f) { 646 if (!riscv_has_ext(env, RVF)) { 647 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 648 return; 649 } 650 } 651 652 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 653 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 654 return; 655 } 656 657 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 658 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 659 return; 660 } 661 662 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 663 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 664 return; 665 } 666 667 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 668 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 669 return; 670 } 671 672 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 673 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 674 return; 675 } 676 677 if (cpu->cfg.ext_zfinx) { 678 if (!cpu->cfg.ext_zicsr) { 679 error_setg(errp, "Zfinx extension requires Zicsr"); 680 return; 681 } 682 if (riscv_has_ext(env, RVF)) { 683 error_setg(errp, 684 "Zfinx cannot be supported together with F extension"); 685 return; 686 } 687 } 688 689 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 690 error_setg(errp, "Zcmop extensions require Zca"); 691 return; 692 } 693 694 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 695 error_setg(errp, "Zcf extension is only relevant to RV32"); 696 return; 697 } 698 699 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 700 error_setg(errp, "Zcf extension requires F extension"); 701 return; 702 } 703 704 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 705 error_setg(errp, "Zcd extension requires D extension"); 706 return; 707 } 708 709 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 710 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 711 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 712 "extension"); 713 return; 714 } 715 716 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 717 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 718 "Zcd extension"); 719 return; 720 } 721 722 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 723 error_setg(errp, "Zcmt extension requires Zicsr extension"); 724 return; 725 } 726 727 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 728 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 729 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 730 error_setg(errp, 731 "Vector crypto extensions require V or Zve* extensions"); 732 return; 733 } 734 735 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 736 error_setg( 737 errp, 738 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 739 return; 740 } 741 742 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 743 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 744 error_setg(errp, "zicntr requires zicsr"); 745 return; 746 } 747 cpu->cfg.ext_zicntr = false; 748 } 749 750 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 751 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 752 error_setg(errp, "zihpm requires zicsr"); 753 return; 754 } 755 cpu->cfg.ext_zihpm = false; 756 } 757 758 if (cpu->cfg.ext_zicfiss) { 759 if (!cpu->cfg.ext_zicsr) { 760 error_setg(errp, "zicfiss extension requires zicsr extension"); 761 return; 762 } 763 if (!riscv_has_ext(env, RVA)) { 764 error_setg(errp, "zicfiss extension requires A extension"); 765 return; 766 } 767 if (!riscv_has_ext(env, RVS)) { 768 error_setg(errp, "zicfiss extension requires S"); 769 return; 770 } 771 if (!cpu->cfg.ext_zimop) { 772 error_setg(errp, "zicfiss extension requires zimop extension"); 773 return; 774 } 775 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 776 error_setg(errp, "zicfiss with zca requires zcmop extension"); 777 return; 778 } 779 } 780 781 if (!cpu->cfg.ext_zihpm) { 782 cpu->cfg.pmu_mask = 0; 783 cpu->pmu_avail_ctrs = 0; 784 } 785 786 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 787 error_setg(errp, "zicfilp extension requires zicsr extension"); 788 return; 789 } 790 791 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 792 error_setg(errp, "svukte is not supported for RV32"); 793 return; 794 } 795 796 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && 797 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { 798 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || 799 cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { 800 error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"); 801 return; 802 } 803 cpu->cfg.ext_smctr = false; 804 cpu->cfg.ext_ssctr = false; 805 } 806 807 /* 808 * Disable isa extensions based on priv spec after we 809 * validated and set everything we need. 810 */ 811 riscv_cpu_disable_priv_spec_isa_exts(cpu); 812 } 813 814 #ifndef CONFIG_USER_ONLY 815 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 816 RISCVCPUProfile *profile, 817 bool send_warn) 818 { 819 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 820 821 if (profile->satp_mode > satp_max) { 822 if (send_warn) { 823 bool is_32bit = riscv_cpu_is_32bit(cpu); 824 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 825 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 826 827 warn_report("Profile %s requires satp mode %s, " 828 "but satp mode %s was set", profile->name, 829 req_satp, cur_satp); 830 } 831 832 return false; 833 } 834 835 return true; 836 } 837 #endif 838 839 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, 840 RISCVCPUProfile *profile, 841 RISCVCPUProfile *parent) 842 { 843 const char *parent_name; 844 bool parent_enabled; 845 846 if (!profile->enabled || !parent) { 847 return; 848 } 849 850 parent_name = parent->name; 851 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); 852 profile->enabled = parent_enabled; 853 } 854 855 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 856 RISCVCPUProfile *profile) 857 { 858 CPURISCVState *env = &cpu->env; 859 const char *warn_msg = "Profile %s mandates disabled extension %s"; 860 bool send_warn = profile->user_set && profile->enabled; 861 bool profile_impl = true; 862 int i; 863 864 #ifndef CONFIG_USER_ONLY 865 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 866 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 867 send_warn); 868 } 869 #endif 870 871 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 872 profile->priv_spec > env->priv_ver) { 873 profile_impl = false; 874 875 if (send_warn) { 876 warn_report("Profile %s requires priv spec %s, " 877 "but priv ver %s was set", profile->name, 878 cpu_priv_ver_to_str(profile->priv_spec), 879 cpu_priv_ver_to_str(env->priv_ver)); 880 } 881 } 882 883 for (i = 0; misa_bits[i] != 0; i++) { 884 uint32_t bit = misa_bits[i]; 885 886 if (!(profile->misa_ext & bit)) { 887 continue; 888 } 889 890 if (!riscv_has_ext(&cpu->env, bit)) { 891 profile_impl = false; 892 893 if (send_warn) { 894 warn_report(warn_msg, profile->name, 895 riscv_get_misa_ext_name(bit)); 896 } 897 } 898 } 899 900 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 901 int ext_offset = profile->ext_offsets[i]; 902 903 if (!isa_ext_is_enabled(cpu, ext_offset)) { 904 profile_impl = false; 905 906 if (send_warn) { 907 warn_report(warn_msg, profile->name, 908 cpu_cfg_ext_get_name(ext_offset)); 909 } 910 } 911 } 912 913 profile->enabled = profile_impl; 914 915 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); 916 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); 917 } 918 919 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 920 { 921 for (int i = 0; riscv_profiles[i] != NULL; i++) { 922 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 923 } 924 } 925 926 static void riscv_cpu_init_implied_exts_rules(void) 927 { 928 RISCVCPUImpliedExtsRule *rule; 929 #ifndef CONFIG_USER_ONLY 930 MachineState *ms = MACHINE(qdev_get_machine()); 931 #endif 932 static bool initialized; 933 int i; 934 935 /* Implied rules only need to be initialized once. */ 936 if (initialized) { 937 return; 938 } 939 940 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 941 #ifndef CONFIG_USER_ONLY 942 rule->enabled = bitmap_new(ms->smp.cpus); 943 #endif 944 g_hash_table_insert(misa_ext_implied_rules, 945 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 946 } 947 948 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 949 #ifndef CONFIG_USER_ONLY 950 rule->enabled = bitmap_new(ms->smp.cpus); 951 #endif 952 g_hash_table_insert(multi_ext_implied_rules, 953 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 954 } 955 956 initialized = true; 957 } 958 959 static void cpu_enable_implied_rule(RISCVCPU *cpu, 960 RISCVCPUImpliedExtsRule *rule) 961 { 962 CPURISCVState *env = &cpu->env; 963 RISCVCPUImpliedExtsRule *ir; 964 bool enabled = false; 965 int i; 966 967 #ifndef CONFIG_USER_ONLY 968 enabled = test_bit(cpu->env.mhartid, rule->enabled); 969 #endif 970 971 if (!enabled) { 972 /* Enable the implied MISAs. */ 973 if (rule->implied_misa_exts) { 974 for (i = 0; misa_bits[i] != 0; i++) { 975 if (rule->implied_misa_exts & misa_bits[i]) { 976 /* 977 * If the user disabled the misa_bit do not re-enable it 978 * and do not apply any implied rules related to it. 979 */ 980 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 981 !(env->misa_ext & misa_bits[i])) { 982 continue; 983 } 984 985 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 986 ir = g_hash_table_lookup(misa_ext_implied_rules, 987 GUINT_TO_POINTER(misa_bits[i])); 988 989 if (ir) { 990 cpu_enable_implied_rule(cpu, ir); 991 } 992 } 993 } 994 } 995 996 /* Enable the implied extensions. */ 997 for (i = 0; 998 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 999 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 1000 1001 ir = g_hash_table_lookup(multi_ext_implied_rules, 1002 GUINT_TO_POINTER( 1003 rule->implied_multi_exts[i])); 1004 1005 if (ir) { 1006 cpu_enable_implied_rule(cpu, ir); 1007 } 1008 } 1009 1010 #ifndef CONFIG_USER_ONLY 1011 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 1012 #endif 1013 } 1014 } 1015 1016 /* Zc extension has special implied rules that need to be handled separately. */ 1017 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 1018 { 1019 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1020 CPURISCVState *env = &cpu->env; 1021 1022 if (cpu->cfg.ext_zce) { 1023 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 1024 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 1025 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 1026 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 1027 1028 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 1029 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 1030 } 1031 } 1032 1033 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 1034 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 1035 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 1036 1037 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 1038 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 1039 } 1040 1041 if (riscv_has_ext(env, RVD)) { 1042 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 1043 } 1044 } 1045 } 1046 1047 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 1048 { 1049 RISCVCPUImpliedExtsRule *rule; 1050 int i; 1051 1052 /* Enable the implied extensions for Zc. */ 1053 cpu_enable_zc_implied_rules(cpu); 1054 1055 /* Enable the implied MISAs. */ 1056 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 1057 if (riscv_has_ext(&cpu->env, rule->ext)) { 1058 cpu_enable_implied_rule(cpu, rule); 1059 } 1060 } 1061 1062 /* Enable the implied extensions. */ 1063 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 1064 if (isa_ext_is_enabled(cpu, rule->ext)) { 1065 cpu_enable_implied_rule(cpu, rule); 1066 } 1067 } 1068 } 1069 1070 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1071 { 1072 CPURISCVState *env = &cpu->env; 1073 Error *local_err = NULL; 1074 1075 riscv_cpu_init_implied_exts_rules(); 1076 riscv_cpu_enable_implied_rules(cpu); 1077 1078 riscv_cpu_validate_misa_priv(env, &local_err); 1079 if (local_err != NULL) { 1080 error_propagate(errp, local_err); 1081 return; 1082 } 1083 1084 riscv_cpu_update_named_features(cpu); 1085 riscv_cpu_validate_profiles(cpu); 1086 1087 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 1088 /* 1089 * Enhanced PMP should only be available 1090 * on harts with PMP support 1091 */ 1092 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 1093 return; 1094 } 1095 1096 riscv_cpu_validate_set_extensions(cpu, &local_err); 1097 if (local_err != NULL) { 1098 error_propagate(errp, local_err); 1099 return; 1100 } 1101 #ifndef CONFIG_USER_ONLY 1102 if (cpu->cfg.pmu_mask) { 1103 riscv_pmu_init(cpu, &local_err); 1104 if (local_err != NULL) { 1105 error_propagate(errp, local_err); 1106 return; 1107 } 1108 1109 if (cpu->cfg.ext_sscofpmf) { 1110 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1111 riscv_pmu_timer_cb, cpu); 1112 } 1113 } 1114 #endif 1115 } 1116 1117 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 1118 { 1119 GPtrArray *dynamic_decoders; 1120 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 1121 for (size_t i = 0; i < decoder_table_size; ++i) { 1122 if (decoder_table[i].guard_func && 1123 decoder_table[i].guard_func(&cpu->cfg)) { 1124 g_ptr_array_add(dynamic_decoders, 1125 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 1126 } 1127 } 1128 1129 cpu->decoders = dynamic_decoders; 1130 } 1131 1132 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 1133 { 1134 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1135 } 1136 1137 static bool riscv_cpu_is_generic(Object *cpu_obj) 1138 { 1139 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1140 } 1141 1142 /* 1143 * We'll get here via the following path: 1144 * 1145 * riscv_cpu_realize() 1146 * -> cpu_exec_realizefn() 1147 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1148 */ 1149 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1150 { 1151 RISCVCPU *cpu = RISCV_CPU(cs); 1152 1153 if (!riscv_cpu_tcg_compatible(cpu)) { 1154 g_autofree char *name = riscv_cpu_get_name(cpu); 1155 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1156 name); 1157 return false; 1158 } 1159 1160 #ifndef CONFIG_USER_ONLY 1161 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1162 1163 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1164 /* Missing 128-bit aligned atomics */ 1165 error_setg(errp, 1166 "128-bit RISC-V currently does not work with Multi " 1167 "Threaded TCG. Please use: -accel tcg,thread=single"); 1168 return false; 1169 } 1170 1171 CPURISCVState *env = &cpu->env; 1172 1173 tcg_cflags_set(CPU(cs), CF_PCREL); 1174 1175 if (cpu->cfg.ext_sstc) { 1176 riscv_timer_init(cpu); 1177 } 1178 1179 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1180 if (riscv_has_ext(env, RVH)) { 1181 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1182 } 1183 #endif 1184 1185 return true; 1186 } 1187 1188 typedef struct RISCVCPUMisaExtConfig { 1189 target_ulong misa_bit; 1190 bool enabled; 1191 } RISCVCPUMisaExtConfig; 1192 1193 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1194 void *opaque, Error **errp) 1195 { 1196 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1197 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1198 RISCVCPU *cpu = RISCV_CPU(obj); 1199 CPURISCVState *env = &cpu->env; 1200 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1201 bool prev_val, value; 1202 1203 if (!visit_type_bool(v, name, &value, errp)) { 1204 return; 1205 } 1206 1207 cpu_misa_ext_add_user_opt(misa_bit, value); 1208 1209 prev_val = env->misa_ext & misa_bit; 1210 1211 if (value == prev_val) { 1212 return; 1213 } 1214 1215 if (value) { 1216 if (vendor_cpu) { 1217 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1218 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1219 cpuname); 1220 return; 1221 } 1222 1223 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1224 /* 1225 * Note: the 'priv_spec' command line option, if present, 1226 * will take precedence over this priv_ver bump. 1227 */ 1228 env->priv_ver = PRIV_VERSION_1_12_0; 1229 } 1230 } 1231 1232 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1233 } 1234 1235 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1236 void *opaque, Error **errp) 1237 { 1238 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1239 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1240 RISCVCPU *cpu = RISCV_CPU(obj); 1241 CPURISCVState *env = &cpu->env; 1242 bool value; 1243 1244 value = env->misa_ext & misa_bit; 1245 1246 visit_type_bool(v, name, &value, errp); 1247 } 1248 1249 #define MISA_CFG(_bit, _enabled) \ 1250 {.misa_bit = _bit, .enabled = _enabled} 1251 1252 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1253 MISA_CFG(RVA, true), 1254 MISA_CFG(RVC, true), 1255 MISA_CFG(RVD, true), 1256 MISA_CFG(RVF, true), 1257 MISA_CFG(RVI, true), 1258 MISA_CFG(RVE, false), 1259 MISA_CFG(RVM, true), 1260 MISA_CFG(RVS, true), 1261 MISA_CFG(RVU, true), 1262 MISA_CFG(RVH, true), 1263 MISA_CFG(RVV, false), 1264 MISA_CFG(RVG, false), 1265 MISA_CFG(RVB, false), 1266 }; 1267 1268 /* 1269 * We do not support user choice tracking for MISA 1270 * extensions yet because, so far, we do not silently 1271 * change MISA bits during realize() (RVG enables MISA 1272 * bits but the user is warned about it). 1273 */ 1274 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1275 { 1276 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1277 int i; 1278 1279 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1280 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1281 int bit = misa_cfg->misa_bit; 1282 const char *name = riscv_get_misa_ext_name(bit); 1283 const char *desc = riscv_get_misa_ext_description(bit); 1284 1285 /* Check if KVM already created the property */ 1286 if (object_property_find(cpu_obj, name)) { 1287 continue; 1288 } 1289 1290 object_property_add(cpu_obj, name, "bool", 1291 cpu_get_misa_ext_cfg, 1292 cpu_set_misa_ext_cfg, 1293 NULL, (void *)misa_cfg); 1294 object_property_set_description(cpu_obj, name, desc); 1295 if (use_def_vals) { 1296 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1297 misa_cfg->enabled); 1298 } 1299 } 1300 } 1301 1302 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1303 void *opaque, Error **errp) 1304 { 1305 RISCVCPUProfile *profile = opaque; 1306 RISCVCPU *cpu = RISCV_CPU(obj); 1307 bool value; 1308 int i, ext_offset; 1309 1310 if (riscv_cpu_is_vendor(obj)) { 1311 error_setg(errp, "Profile %s is not available for vendor CPUs", 1312 profile->name); 1313 return; 1314 } 1315 1316 if (cpu->env.misa_mxl != MXL_RV64) { 1317 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1318 profile->name); 1319 return; 1320 } 1321 1322 if (!visit_type_bool(v, name, &value, errp)) { 1323 return; 1324 } 1325 1326 profile->user_set = true; 1327 profile->enabled = value; 1328 1329 if (profile->u_parent != NULL) { 1330 object_property_set_bool(obj, profile->u_parent->name, 1331 profile->enabled, NULL); 1332 } 1333 1334 if (profile->s_parent != NULL) { 1335 object_property_set_bool(obj, profile->s_parent->name, 1336 profile->enabled, NULL); 1337 } 1338 1339 if (profile->enabled) { 1340 cpu->env.priv_ver = profile->priv_spec; 1341 } 1342 1343 #ifndef CONFIG_USER_ONLY 1344 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1345 object_property_set_bool(obj, "mmu", true, NULL); 1346 const char *satp_prop = satp_mode_str(profile->satp_mode, 1347 riscv_cpu_is_32bit(cpu)); 1348 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1349 } 1350 #endif 1351 1352 for (i = 0; misa_bits[i] != 0; i++) { 1353 uint32_t bit = misa_bits[i]; 1354 1355 if (!(profile->misa_ext & bit)) { 1356 continue; 1357 } 1358 1359 if (bit == RVI && !profile->enabled) { 1360 /* 1361 * Disabling profiles will not disable the base 1362 * ISA RV64I. 1363 */ 1364 continue; 1365 } 1366 1367 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1368 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1369 } 1370 1371 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1372 ext_offset = profile->ext_offsets[i]; 1373 1374 if (profile->enabled) { 1375 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1376 riscv_cpu_enable_named_feat(cpu, ext_offset); 1377 } 1378 1379 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1380 } 1381 1382 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1383 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1384 } 1385 } 1386 1387 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1388 void *opaque, Error **errp) 1389 { 1390 RISCVCPUProfile *profile = opaque; 1391 bool value = profile->enabled; 1392 1393 visit_type_bool(v, name, &value, errp); 1394 } 1395 1396 static void riscv_cpu_add_profiles(Object *cpu_obj) 1397 { 1398 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1399 const RISCVCPUProfile *profile = riscv_profiles[i]; 1400 1401 object_property_add(cpu_obj, profile->name, "bool", 1402 cpu_get_profile, cpu_set_profile, 1403 NULL, (void *)profile); 1404 1405 /* 1406 * CPUs might enable a profile right from the start. 1407 * Enable its mandatory extensions right away in this 1408 * case. 1409 */ 1410 if (profile->enabled) { 1411 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1412 } 1413 } 1414 } 1415 1416 static bool cpu_ext_is_deprecated(const char *ext_name) 1417 { 1418 return isupper(ext_name[0]); 1419 } 1420 1421 /* 1422 * String will be allocated in the heap. Caller is responsible 1423 * for freeing it. 1424 */ 1425 static char *cpu_ext_to_lower(const char *ext_name) 1426 { 1427 char *ret = g_malloc0(strlen(ext_name) + 1); 1428 1429 strcpy(ret, ext_name); 1430 ret[0] = tolower(ret[0]); 1431 1432 return ret; 1433 } 1434 1435 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1436 void *opaque, Error **errp) 1437 { 1438 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1439 RISCVCPU *cpu = RISCV_CPU(obj); 1440 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1441 bool prev_val, value; 1442 1443 if (!visit_type_bool(v, name, &value, errp)) { 1444 return; 1445 } 1446 1447 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1448 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1449 1450 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1451 multi_ext_cfg->name, lower); 1452 } 1453 1454 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1455 1456 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1457 1458 if (value == prev_val) { 1459 return; 1460 } 1461 1462 if (value && vendor_cpu) { 1463 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1464 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1465 cpuname); 1466 return; 1467 } 1468 1469 if (value) { 1470 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1471 } 1472 1473 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1474 } 1475 1476 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1477 void *opaque, Error **errp) 1478 { 1479 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1480 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1481 1482 visit_type_bool(v, name, &value, errp); 1483 } 1484 1485 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1486 const RISCVCPUMultiExtConfig *multi_cfg) 1487 { 1488 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1489 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1490 1491 object_property_add(cpu_obj, multi_cfg->name, "bool", 1492 cpu_get_multi_ext_cfg, 1493 cpu_set_multi_ext_cfg, 1494 NULL, (void *)multi_cfg); 1495 1496 if (!generic_cpu || deprecated_ext) { 1497 return; 1498 } 1499 1500 /* 1501 * Set def val directly instead of using 1502 * object_property_set_bool() to save the set() 1503 * callback hash for user inputs. 1504 */ 1505 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1506 multi_cfg->enabled); 1507 } 1508 1509 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1510 const RISCVCPUMultiExtConfig *array) 1511 { 1512 const RISCVCPUMultiExtConfig *prop; 1513 1514 g_assert(array); 1515 1516 for (prop = array; prop && prop->name; prop++) { 1517 cpu_add_multi_ext_prop(obj, prop); 1518 } 1519 } 1520 1521 /* 1522 * Add CPU properties with user-facing flags. 1523 * 1524 * This will overwrite existing env->misa_ext values with the 1525 * defaults set via riscv_cpu_add_misa_properties(). 1526 */ 1527 static void riscv_cpu_add_user_properties(Object *obj) 1528 { 1529 #ifndef CONFIG_USER_ONLY 1530 riscv_add_satp_mode_properties(obj); 1531 #endif 1532 1533 riscv_cpu_add_misa_properties(obj); 1534 1535 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1536 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1537 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1538 1539 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1540 1541 riscv_cpu_add_profiles(obj); 1542 } 1543 1544 /* 1545 * The 'max' type CPU will have all possible ratified 1546 * non-vendor extensions enabled. 1547 */ 1548 static void riscv_init_max_cpu_extensions(Object *obj) 1549 { 1550 RISCVCPU *cpu = RISCV_CPU(obj); 1551 CPURISCVState *env = &cpu->env; 1552 const RISCVCPUMultiExtConfig *prop; 1553 1554 /* Enable RVG and RVV that are disabled by default */ 1555 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1556 1557 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1558 isa_ext_update_enabled(cpu, prop->offset, true); 1559 } 1560 1561 /* 1562 * Some extensions can't be added without backward compatibilty concerns. 1563 * Disable those, the user can still opt in to them on the command line. 1564 */ 1565 cpu->cfg.ext_svade = false; 1566 1567 /* set vector version */ 1568 env->vext_ver = VEXT_VERSION_1_00_0; 1569 1570 /* Zfinx is not compatible with F. Disable it */ 1571 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1572 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1573 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1574 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1575 1576 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1577 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1578 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1579 1580 if (env->misa_mxl != MXL_RV32) { 1581 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1582 } 1583 1584 /* 1585 * TODO: ext_smrnmi requires OpenSBI changes that our current 1586 * image does not have. Disable it for now. 1587 */ 1588 if (cpu->cfg.ext_smrnmi) { 1589 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1590 } 1591 1592 /* 1593 * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup 1594 * to avoid generating a double trap. OpenSBI does not currently support it, 1595 * disable it for now. 1596 */ 1597 if (cpu->cfg.ext_smdbltrp) { 1598 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1599 } 1600 } 1601 1602 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1603 { 1604 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1605 } 1606 1607 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1608 { 1609 RISCVCPU *cpu = RISCV_CPU(cs); 1610 Object *obj = OBJECT(cpu); 1611 1612 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1613 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1614 1615 if (!misa_ext_implied_rules) { 1616 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1617 } 1618 1619 if (!multi_ext_implied_rules) { 1620 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1621 } 1622 1623 riscv_cpu_add_user_properties(obj); 1624 1625 if (riscv_cpu_has_max_extensions(obj)) { 1626 riscv_init_max_cpu_extensions(obj); 1627 } 1628 } 1629 1630 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, const void *data) 1631 { 1632 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1633 1634 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1635 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1636 } 1637 1638 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1639 .name = ACCEL_CPU_NAME("tcg"), 1640 1641 .parent = TYPE_ACCEL_CPU, 1642 .class_init = riscv_tcg_cpu_accel_class_init, 1643 .abstract = true, 1644 }; 1645 1646 static void riscv_tcg_cpu_accel_register_types(void) 1647 { 1648 type_register_static(&riscv_tcg_cpu_accel_type_info); 1649 } 1650 type_init(riscv_tcg_cpu_accel_register_types); 1651