1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "exec/translation-block.h" 23 #include "tcg-cpu.h" 24 #include "cpu.h" 25 #include "exec/target_page.h" 26 #include "internals.h" 27 #include "pmu.h" 28 #include "time_helper.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "qemu/accel.h" 32 #include "qemu/error-report.h" 33 #include "qemu/log.h" 34 #include "accel/accel-cpu-target.h" 35 #include "accel/tcg/cpu-ops.h" 36 #include "tcg/tcg.h" 37 #ifndef CONFIG_USER_ONLY 38 #include "hw/boards.h" 39 #include "system/tcg.h" 40 #endif 41 42 /* Hash that stores user set extensions */ 43 static GHashTable *multi_ext_user_opts; 44 static GHashTable *misa_ext_user_opts; 45 46 static GHashTable *multi_ext_implied_rules; 47 static GHashTable *misa_ext_implied_rules; 48 49 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 50 { 51 return g_hash_table_contains(multi_ext_user_opts, 52 GUINT_TO_POINTER(ext_offset)); 53 } 54 55 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 56 { 57 return g_hash_table_contains(misa_ext_user_opts, 58 GUINT_TO_POINTER(misa_bit)); 59 } 60 61 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 62 { 63 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 64 (gpointer)value); 65 } 66 67 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 68 { 69 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 70 (gpointer)value); 71 } 72 73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 74 bool enabled) 75 { 76 CPURISCVState *env = &cpu->env; 77 78 if (enabled) { 79 env->misa_ext |= bit; 80 env->misa_ext_mask |= bit; 81 } else { 82 env->misa_ext &= ~bit; 83 env->misa_ext_mask &= ~bit; 84 } 85 } 86 87 static const char *cpu_priv_ver_to_str(int priv_ver) 88 { 89 const char *priv_spec_str = priv_spec_to_str(priv_ver); 90 91 g_assert(priv_spec_str); 92 93 return priv_spec_str; 94 } 95 96 static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) 97 { 98 return riscv_env_mmu_index(cpu_env(cs), ifetch); 99 } 100 101 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 102 const TranslationBlock *tb) 103 { 104 if (!(tb_cflags(tb) & CF_PCREL)) { 105 RISCVCPU *cpu = RISCV_CPU(cs); 106 CPURISCVState *env = &cpu->env; 107 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 108 109 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 110 111 if (xl == MXL_RV32) { 112 env->pc = (int32_t) tb->pc; 113 } else { 114 env->pc = tb->pc; 115 } 116 } 117 } 118 119 static void riscv_restore_state_to_opc(CPUState *cs, 120 const TranslationBlock *tb, 121 const uint64_t *data) 122 { 123 RISCVCPU *cpu = RISCV_CPU(cs); 124 CPURISCVState *env = &cpu->env; 125 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 126 target_ulong pc; 127 128 if (tb_cflags(tb) & CF_PCREL) { 129 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 130 } else { 131 pc = data[0]; 132 } 133 134 if (xl == MXL_RV32) { 135 env->pc = (int32_t)pc; 136 } else { 137 env->pc = pc; 138 } 139 env->bins = data[1]; 140 env->excp_uw2 = data[2]; 141 } 142 143 const TCGCPUOps riscv_tcg_ops = { 144 .mttcg_supported = true, 145 .guest_default_memory_order = 0, 146 147 .initialize = riscv_translate_init, 148 .translate_code = riscv_translate_code, 149 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 150 .restore_state_to_opc = riscv_restore_state_to_opc, 151 .mmu_index = riscv_cpu_mmu_index, 152 153 #ifndef CONFIG_USER_ONLY 154 .tlb_fill = riscv_cpu_tlb_fill, 155 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 156 .cpu_exec_halt = riscv_cpu_has_work, 157 .do_interrupt = riscv_cpu_do_interrupt, 158 .do_transaction_failed = riscv_cpu_do_transaction_failed, 159 .do_unaligned_access = riscv_cpu_do_unaligned_access, 160 .debug_excp_handler = riscv_cpu_debug_excp_handler, 161 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 162 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 163 #endif /* !CONFIG_USER_ONLY */ 164 }; 165 166 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 167 { 168 const RISCVIsaExtData *edata; 169 170 for (edata = isa_edata_arr; edata && edata->name; edata++) { 171 if (edata->ext_enable_offset != ext_offset) { 172 continue; 173 } 174 175 return edata->min_version; 176 } 177 178 g_assert_not_reached(); 179 } 180 181 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 182 { 183 const RISCVCPUMultiExtConfig *feat; 184 const RISCVIsaExtData *edata; 185 186 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 187 if (edata->ext_enable_offset == ext_offset) { 188 return edata->name; 189 } 190 } 191 192 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 193 if (feat->offset == ext_offset) { 194 return feat->name; 195 } 196 } 197 198 g_assert_not_reached(); 199 } 200 201 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 202 { 203 const RISCVCPUMultiExtConfig *feat; 204 205 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 206 if (feat->offset == ext_offset) { 207 return true; 208 } 209 } 210 211 return false; 212 } 213 214 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 215 { 216 /* 217 * All other named features are already enabled 218 * in riscv_tcg_cpu_instance_init(). 219 */ 220 switch (feat_offset) { 221 case CPU_CFG_OFFSET(ext_zic64b): 222 cpu->cfg.cbom_blocksize = 64; 223 cpu->cfg.cbop_blocksize = 64; 224 cpu->cfg.cboz_blocksize = 64; 225 break; 226 case CPU_CFG_OFFSET(ext_sha): 227 if (!cpu_misa_ext_is_user_set(RVH)) { 228 riscv_cpu_write_misa_bit(cpu, RVH, true); 229 } 230 /* fallthrough */ 231 case CPU_CFG_OFFSET(ext_ssstateen): 232 cpu->cfg.ext_smstateen = true; 233 break; 234 } 235 } 236 237 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 238 uint32_t ext_offset) 239 { 240 int ext_priv_ver; 241 242 if (env->priv_ver == PRIV_VERSION_LATEST) { 243 return; 244 } 245 246 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 247 248 if (env->priv_ver < ext_priv_ver) { 249 /* 250 * Note: the 'priv_spec' command line option, if present, 251 * will take precedence over this priv_ver bump. 252 */ 253 env->priv_ver = ext_priv_ver; 254 } 255 } 256 257 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 258 bool value) 259 { 260 CPURISCVState *env = &cpu->env; 261 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 262 int min_version; 263 264 if (prev_val == value) { 265 return; 266 } 267 268 if (cpu_cfg_ext_is_user_set(ext_offset)) { 269 return; 270 } 271 272 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 273 /* Do not enable it if priv_ver is older than min_version */ 274 min_version = cpu_cfg_ext_get_min_version(ext_offset); 275 if (env->priv_ver < min_version) { 276 return; 277 } 278 } 279 280 isa_ext_update_enabled(cpu, ext_offset, value); 281 } 282 283 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 284 { 285 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 286 error_setg(errp, "H extension requires priv spec 1.12.0"); 287 return; 288 } 289 } 290 291 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 292 Error **errp) 293 { 294 uint32_t vlen = cfg->vlenb << 3; 295 296 if (vlen > RV_VLEN_MAX || vlen < 128) { 297 error_setg(errp, 298 "Vector extension implementation only supports VLEN " 299 "in the range [128, %d]", RV_VLEN_MAX); 300 return; 301 } 302 303 if (cfg->elen > 64 || cfg->elen < 8) { 304 error_setg(errp, 305 "Vector extension implementation only supports ELEN " 306 "in the range [8, 64]"); 307 return; 308 } 309 } 310 311 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 312 { 313 CPURISCVState *env = &cpu->env; 314 const RISCVIsaExtData *edata; 315 316 /* Force disable extensions if priv spec version does not match */ 317 for (edata = isa_edata_arr; edata && edata->name; edata++) { 318 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 319 (env->priv_ver < edata->min_version)) { 320 /* 321 * These two extensions are always enabled as they were supported 322 * by QEMU before they were added as extensions in the ISA. 323 */ 324 if (!strcmp(edata->name, "zicntr") || 325 !strcmp(edata->name, "zihpm")) { 326 continue; 327 } 328 329 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 330 331 /* 332 * Do not show user warnings for named features that users 333 * can't enable/disable in the command line. See commit 334 * 68c9e54bea for more info. 335 */ 336 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 337 continue; 338 } 339 #ifndef CONFIG_USER_ONLY 340 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 341 " because privilege spec version does not match", 342 edata->name, env->mhartid); 343 #else 344 warn_report("disabling %s extension because " 345 "privilege spec version does not match", 346 edata->name); 347 #endif 348 } 349 } 350 } 351 352 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 353 { 354 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 355 cpu->cfg.has_priv_1_11 = true; 356 } 357 358 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 359 cpu->cfg.has_priv_1_12 = true; 360 } 361 362 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 363 cpu->cfg.has_priv_1_13 = true; 364 } 365 366 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 367 cpu->cfg.cbop_blocksize == 64 && 368 cpu->cfg.cboz_blocksize == 64; 369 370 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 371 372 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 373 cpu->cfg.ext_ssstateen; 374 375 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; 376 } 377 378 static void riscv_cpu_validate_g(RISCVCPU *cpu) 379 { 380 const char *warn_msg = "RVG mandates disabled extension %s"; 381 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 382 bool send_warn = cpu_misa_ext_is_user_set(RVG); 383 384 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 385 uint32_t bit = g_misa_bits[i]; 386 387 if (riscv_has_ext(&cpu->env, bit)) { 388 continue; 389 } 390 391 if (!cpu_misa_ext_is_user_set(bit)) { 392 riscv_cpu_write_misa_bit(cpu, bit, true); 393 continue; 394 } 395 396 if (send_warn) { 397 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 398 } 399 } 400 401 if (!cpu->cfg.ext_zicsr) { 402 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 403 cpu->cfg.ext_zicsr = true; 404 } else if (send_warn) { 405 warn_report(warn_msg, "zicsr"); 406 } 407 } 408 409 if (!cpu->cfg.ext_zifencei) { 410 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 411 cpu->cfg.ext_zifencei = true; 412 } else if (send_warn) { 413 warn_report(warn_msg, "zifencei"); 414 } 415 } 416 } 417 418 static void riscv_cpu_validate_b(RISCVCPU *cpu) 419 { 420 const char *warn_msg = "RVB mandates disabled extension %s"; 421 422 if (!cpu->cfg.ext_zba) { 423 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 424 cpu->cfg.ext_zba = true; 425 } else { 426 warn_report(warn_msg, "zba"); 427 } 428 } 429 430 if (!cpu->cfg.ext_zbb) { 431 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 432 cpu->cfg.ext_zbb = true; 433 } else { 434 warn_report(warn_msg, "zbb"); 435 } 436 } 437 438 if (!cpu->cfg.ext_zbs) { 439 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 440 cpu->cfg.ext_zbs = true; 441 } else { 442 warn_report(warn_msg, "zbs"); 443 } 444 } 445 } 446 447 /* 448 * Check consistency between chosen extensions while setting 449 * cpu->cfg accordingly. 450 */ 451 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 452 { 453 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 454 CPURISCVState *env = &cpu->env; 455 Error *local_err = NULL; 456 457 if (riscv_has_ext(env, RVG)) { 458 riscv_cpu_validate_g(cpu); 459 } 460 461 if (riscv_has_ext(env, RVB)) { 462 riscv_cpu_validate_b(cpu); 463 } 464 465 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 466 error_setg(errp, 467 "I and E extensions are incompatible"); 468 return; 469 } 470 471 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 472 error_setg(errp, 473 "Either I or E extension must be set"); 474 return; 475 } 476 477 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 478 error_setg(errp, 479 "Setting S extension without U extension is illegal"); 480 return; 481 } 482 483 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 484 error_setg(errp, 485 "H depends on an I base integer ISA with 32 x registers"); 486 return; 487 } 488 489 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 490 error_setg(errp, "H extension implicitly requires S-mode"); 491 return; 492 } 493 494 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 495 error_setg(errp, "F extension requires Zicsr"); 496 return; 497 } 498 499 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 500 error_setg(errp, "Zacas extension requires A extension"); 501 return; 502 } 503 504 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 505 error_setg(errp, "Zawrs extension requires A extension"); 506 return; 507 } 508 509 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 510 error_setg(errp, "Zfa extension requires F extension"); 511 return; 512 } 513 514 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 515 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 516 return; 517 } 518 519 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 520 error_setg(errp, "Zfbfmin extension depends on F extension"); 521 return; 522 } 523 524 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 525 error_setg(errp, "D extension requires F extension"); 526 return; 527 } 528 529 if (riscv_has_ext(env, RVV)) { 530 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 531 if (local_err != NULL) { 532 error_propagate(errp, local_err); 533 return; 534 } 535 } 536 537 /* The Zve64d extension depends on the Zve64f extension */ 538 if (cpu->cfg.ext_zve64d) { 539 if (!riscv_has_ext(env, RVD)) { 540 error_setg(errp, "Zve64d/V extensions require D extension"); 541 return; 542 } 543 } 544 545 /* The Zve32f extension depends on the Zve32x extension */ 546 if (cpu->cfg.ext_zve32f) { 547 if (!riscv_has_ext(env, RVF)) { 548 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 549 return; 550 } 551 } 552 553 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 554 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 555 return; 556 } 557 558 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 559 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 560 return; 561 } 562 563 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 564 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 565 return; 566 } 567 568 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 569 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 570 return; 571 } 572 573 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 574 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 575 return; 576 } 577 578 if (cpu->cfg.ext_zfinx) { 579 if (!cpu->cfg.ext_zicsr) { 580 error_setg(errp, "Zfinx extension requires Zicsr"); 581 return; 582 } 583 if (riscv_has_ext(env, RVF)) { 584 error_setg(errp, 585 "Zfinx cannot be supported together with F extension"); 586 return; 587 } 588 } 589 590 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 591 error_setg(errp, "Zcmop extensions require Zca"); 592 return; 593 } 594 595 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 596 error_setg(errp, "Zcf extension is only relevant to RV32"); 597 return; 598 } 599 600 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 601 error_setg(errp, "Zcf extension requires F extension"); 602 return; 603 } 604 605 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 606 error_setg(errp, "Zcd extension requires D extension"); 607 return; 608 } 609 610 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 611 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 612 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 613 "extension"); 614 return; 615 } 616 617 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 618 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 619 "Zcd extension"); 620 return; 621 } 622 623 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 624 error_setg(errp, "Zcmt extension requires Zicsr extension"); 625 return; 626 } 627 628 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 629 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 630 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 631 error_setg(errp, 632 "Vector crypto extensions require V or Zve* extensions"); 633 return; 634 } 635 636 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 637 error_setg( 638 errp, 639 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 640 return; 641 } 642 643 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 644 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 645 error_setg(errp, "zicntr requires zicsr"); 646 return; 647 } 648 cpu->cfg.ext_zicntr = false; 649 } 650 651 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 652 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 653 error_setg(errp, "zihpm requires zicsr"); 654 return; 655 } 656 cpu->cfg.ext_zihpm = false; 657 } 658 659 if (cpu->cfg.ext_zicfiss) { 660 if (!cpu->cfg.ext_zicsr) { 661 error_setg(errp, "zicfiss extension requires zicsr extension"); 662 return; 663 } 664 if (!riscv_has_ext(env, RVA)) { 665 error_setg(errp, "zicfiss extension requires A extension"); 666 return; 667 } 668 if (!riscv_has_ext(env, RVS)) { 669 error_setg(errp, "zicfiss extension requires S"); 670 return; 671 } 672 if (!cpu->cfg.ext_zimop) { 673 error_setg(errp, "zicfiss extension requires zimop extension"); 674 return; 675 } 676 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 677 error_setg(errp, "zicfiss with zca requires zcmop extension"); 678 return; 679 } 680 } 681 682 if (!cpu->cfg.ext_zihpm) { 683 cpu->cfg.pmu_mask = 0; 684 cpu->pmu_avail_ctrs = 0; 685 } 686 687 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 688 error_setg(errp, "zicfilp extension requires zicsr extension"); 689 return; 690 } 691 692 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 693 error_setg(errp, "svukte is not supported for RV32"); 694 return; 695 } 696 697 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && 698 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { 699 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || 700 cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { 701 error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"); 702 return; 703 } 704 cpu->cfg.ext_smctr = false; 705 cpu->cfg.ext_ssctr = false; 706 } 707 708 /* 709 * Disable isa extensions based on priv spec after we 710 * validated and set everything we need. 711 */ 712 riscv_cpu_disable_priv_spec_isa_exts(cpu); 713 } 714 715 #ifndef CONFIG_USER_ONLY 716 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 717 RISCVCPUProfile *profile, 718 bool send_warn) 719 { 720 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 721 722 if (profile->satp_mode > satp_max) { 723 if (send_warn) { 724 bool is_32bit = riscv_cpu_is_32bit(cpu); 725 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 726 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 727 728 warn_report("Profile %s requires satp mode %s, " 729 "but satp mode %s was set", profile->name, 730 req_satp, cur_satp); 731 } 732 733 return false; 734 } 735 736 return true; 737 } 738 #endif 739 740 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, 741 RISCVCPUProfile *profile, 742 RISCVCPUProfile *parent) 743 { 744 const char *parent_name; 745 bool parent_enabled; 746 747 if (!profile->enabled || !parent) { 748 return; 749 } 750 751 parent_name = parent->name; 752 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); 753 profile->enabled = parent_enabled; 754 } 755 756 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 757 RISCVCPUProfile *profile) 758 { 759 CPURISCVState *env = &cpu->env; 760 const char *warn_msg = "Profile %s mandates disabled extension %s"; 761 bool send_warn = profile->user_set && profile->enabled; 762 bool profile_impl = true; 763 int i; 764 765 #ifndef CONFIG_USER_ONLY 766 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 767 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 768 send_warn); 769 } 770 #endif 771 772 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 773 profile->priv_spec > env->priv_ver) { 774 profile_impl = false; 775 776 if (send_warn) { 777 warn_report("Profile %s requires priv spec %s, " 778 "but priv ver %s was set", profile->name, 779 cpu_priv_ver_to_str(profile->priv_spec), 780 cpu_priv_ver_to_str(env->priv_ver)); 781 } 782 } 783 784 for (i = 0; misa_bits[i] != 0; i++) { 785 uint32_t bit = misa_bits[i]; 786 787 if (!(profile->misa_ext & bit)) { 788 continue; 789 } 790 791 if (!riscv_has_ext(&cpu->env, bit)) { 792 profile_impl = false; 793 794 if (send_warn) { 795 warn_report(warn_msg, profile->name, 796 riscv_get_misa_ext_name(bit)); 797 } 798 } 799 } 800 801 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 802 int ext_offset = profile->ext_offsets[i]; 803 804 if (!isa_ext_is_enabled(cpu, ext_offset)) { 805 profile_impl = false; 806 807 if (send_warn) { 808 warn_report(warn_msg, profile->name, 809 cpu_cfg_ext_get_name(ext_offset)); 810 } 811 } 812 } 813 814 profile->enabled = profile_impl; 815 816 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); 817 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); 818 } 819 820 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 821 { 822 for (int i = 0; riscv_profiles[i] != NULL; i++) { 823 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 824 } 825 } 826 827 static void riscv_cpu_init_implied_exts_rules(void) 828 { 829 RISCVCPUImpliedExtsRule *rule; 830 #ifndef CONFIG_USER_ONLY 831 MachineState *ms = MACHINE(qdev_get_machine()); 832 #endif 833 static bool initialized; 834 int i; 835 836 /* Implied rules only need to be initialized once. */ 837 if (initialized) { 838 return; 839 } 840 841 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 842 #ifndef CONFIG_USER_ONLY 843 rule->enabled = bitmap_new(ms->smp.cpus); 844 #endif 845 g_hash_table_insert(misa_ext_implied_rules, 846 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 847 } 848 849 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 850 #ifndef CONFIG_USER_ONLY 851 rule->enabled = bitmap_new(ms->smp.cpus); 852 #endif 853 g_hash_table_insert(multi_ext_implied_rules, 854 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 855 } 856 857 initialized = true; 858 } 859 860 static void cpu_enable_implied_rule(RISCVCPU *cpu, 861 RISCVCPUImpliedExtsRule *rule) 862 { 863 CPURISCVState *env = &cpu->env; 864 RISCVCPUImpliedExtsRule *ir; 865 bool enabled = false; 866 int i; 867 868 #ifndef CONFIG_USER_ONLY 869 enabled = test_bit(cpu->env.mhartid, rule->enabled); 870 #endif 871 872 if (!enabled) { 873 /* Enable the implied MISAs. */ 874 if (rule->implied_misa_exts) { 875 for (i = 0; misa_bits[i] != 0; i++) { 876 if (rule->implied_misa_exts & misa_bits[i]) { 877 /* 878 * If the user disabled the misa_bit do not re-enable it 879 * and do not apply any implied rules related to it. 880 */ 881 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 882 !(env->misa_ext & misa_bits[i])) { 883 continue; 884 } 885 886 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 887 ir = g_hash_table_lookup(misa_ext_implied_rules, 888 GUINT_TO_POINTER(misa_bits[i])); 889 890 if (ir) { 891 cpu_enable_implied_rule(cpu, ir); 892 } 893 } 894 } 895 } 896 897 /* Enable the implied extensions. */ 898 for (i = 0; 899 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 900 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 901 902 ir = g_hash_table_lookup(multi_ext_implied_rules, 903 GUINT_TO_POINTER( 904 rule->implied_multi_exts[i])); 905 906 if (ir) { 907 cpu_enable_implied_rule(cpu, ir); 908 } 909 } 910 911 #ifndef CONFIG_USER_ONLY 912 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 913 #endif 914 } 915 } 916 917 /* Zc extension has special implied rules that need to be handled separately. */ 918 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 919 { 920 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 921 CPURISCVState *env = &cpu->env; 922 923 if (cpu->cfg.ext_zce) { 924 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 925 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 926 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 927 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 928 929 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 930 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 931 } 932 } 933 934 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 935 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 936 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 937 938 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 939 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 940 } 941 942 if (riscv_has_ext(env, RVD)) { 943 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 944 } 945 } 946 } 947 948 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 949 { 950 RISCVCPUImpliedExtsRule *rule; 951 int i; 952 953 /* Enable the implied extensions for Zc. */ 954 cpu_enable_zc_implied_rules(cpu); 955 956 /* Enable the implied MISAs. */ 957 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 958 if (riscv_has_ext(&cpu->env, rule->ext)) { 959 cpu_enable_implied_rule(cpu, rule); 960 } 961 } 962 963 /* Enable the implied extensions. */ 964 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 965 if (isa_ext_is_enabled(cpu, rule->ext)) { 966 cpu_enable_implied_rule(cpu, rule); 967 } 968 } 969 } 970 971 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 972 { 973 CPURISCVState *env = &cpu->env; 974 Error *local_err = NULL; 975 976 riscv_cpu_init_implied_exts_rules(); 977 riscv_cpu_enable_implied_rules(cpu); 978 979 riscv_cpu_validate_misa_priv(env, &local_err); 980 if (local_err != NULL) { 981 error_propagate(errp, local_err); 982 return; 983 } 984 985 riscv_cpu_update_named_features(cpu); 986 riscv_cpu_validate_profiles(cpu); 987 988 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 989 /* 990 * Enhanced PMP should only be available 991 * on harts with PMP support 992 */ 993 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 994 return; 995 } 996 997 riscv_cpu_validate_set_extensions(cpu, &local_err); 998 if (local_err != NULL) { 999 error_propagate(errp, local_err); 1000 return; 1001 } 1002 #ifndef CONFIG_USER_ONLY 1003 if (cpu->cfg.pmu_mask) { 1004 riscv_pmu_init(cpu, &local_err); 1005 if (local_err != NULL) { 1006 error_propagate(errp, local_err); 1007 return; 1008 } 1009 1010 if (cpu->cfg.ext_sscofpmf) { 1011 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1012 riscv_pmu_timer_cb, cpu); 1013 } 1014 } 1015 #endif 1016 } 1017 1018 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 1019 { 1020 GPtrArray *dynamic_decoders; 1021 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 1022 for (size_t i = 0; i < decoder_table_size; ++i) { 1023 if (decoder_table[i].guard_func && 1024 decoder_table[i].guard_func(&cpu->cfg)) { 1025 g_ptr_array_add(dynamic_decoders, 1026 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 1027 } 1028 } 1029 1030 cpu->decoders = dynamic_decoders; 1031 } 1032 1033 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 1034 { 1035 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1036 } 1037 1038 static bool riscv_cpu_is_generic(Object *cpu_obj) 1039 { 1040 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1041 } 1042 1043 /* 1044 * We'll get here via the following path: 1045 * 1046 * riscv_cpu_realize() 1047 * -> cpu_exec_realizefn() 1048 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1049 */ 1050 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1051 { 1052 RISCVCPU *cpu = RISCV_CPU(cs); 1053 1054 if (!riscv_cpu_tcg_compatible(cpu)) { 1055 g_autofree char *name = riscv_cpu_get_name(cpu); 1056 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1057 name); 1058 return false; 1059 } 1060 1061 #ifndef CONFIG_USER_ONLY 1062 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1063 1064 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1065 /* Missing 128-bit aligned atomics */ 1066 error_setg(errp, 1067 "128-bit RISC-V currently does not work with Multi " 1068 "Threaded TCG. Please use: -accel tcg,thread=single"); 1069 return false; 1070 } 1071 1072 CPURISCVState *env = &cpu->env; 1073 1074 tcg_cflags_set(CPU(cs), CF_PCREL); 1075 1076 if (cpu->cfg.ext_sstc) { 1077 riscv_timer_init(cpu); 1078 } 1079 1080 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1081 if (riscv_has_ext(env, RVH)) { 1082 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1083 } 1084 #endif 1085 1086 return true; 1087 } 1088 1089 typedef struct RISCVCPUMisaExtConfig { 1090 target_ulong misa_bit; 1091 bool enabled; 1092 } RISCVCPUMisaExtConfig; 1093 1094 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1095 void *opaque, Error **errp) 1096 { 1097 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1098 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1099 RISCVCPU *cpu = RISCV_CPU(obj); 1100 CPURISCVState *env = &cpu->env; 1101 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1102 bool prev_val, value; 1103 1104 if (!visit_type_bool(v, name, &value, errp)) { 1105 return; 1106 } 1107 1108 cpu_misa_ext_add_user_opt(misa_bit, value); 1109 1110 prev_val = env->misa_ext & misa_bit; 1111 1112 if (value == prev_val) { 1113 return; 1114 } 1115 1116 if (value) { 1117 if (vendor_cpu) { 1118 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1119 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1120 cpuname); 1121 return; 1122 } 1123 1124 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1125 /* 1126 * Note: the 'priv_spec' command line option, if present, 1127 * will take precedence over this priv_ver bump. 1128 */ 1129 env->priv_ver = PRIV_VERSION_1_12_0; 1130 } 1131 } 1132 1133 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1134 } 1135 1136 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1137 void *opaque, Error **errp) 1138 { 1139 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1140 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1141 RISCVCPU *cpu = RISCV_CPU(obj); 1142 CPURISCVState *env = &cpu->env; 1143 bool value; 1144 1145 value = env->misa_ext & misa_bit; 1146 1147 visit_type_bool(v, name, &value, errp); 1148 } 1149 1150 #define MISA_CFG(_bit, _enabled) \ 1151 {.misa_bit = _bit, .enabled = _enabled} 1152 1153 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1154 MISA_CFG(RVA, true), 1155 MISA_CFG(RVC, true), 1156 MISA_CFG(RVD, true), 1157 MISA_CFG(RVF, true), 1158 MISA_CFG(RVI, true), 1159 MISA_CFG(RVE, false), 1160 MISA_CFG(RVM, true), 1161 MISA_CFG(RVS, true), 1162 MISA_CFG(RVU, true), 1163 MISA_CFG(RVH, true), 1164 MISA_CFG(RVV, false), 1165 MISA_CFG(RVG, false), 1166 MISA_CFG(RVB, false), 1167 }; 1168 1169 /* 1170 * We do not support user choice tracking for MISA 1171 * extensions yet because, so far, we do not silently 1172 * change MISA bits during realize() (RVG enables MISA 1173 * bits but the user is warned about it). 1174 */ 1175 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1176 { 1177 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1178 int i; 1179 1180 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1181 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1182 int bit = misa_cfg->misa_bit; 1183 const char *name = riscv_get_misa_ext_name(bit); 1184 const char *desc = riscv_get_misa_ext_description(bit); 1185 1186 /* Check if KVM already created the property */ 1187 if (object_property_find(cpu_obj, name)) { 1188 continue; 1189 } 1190 1191 object_property_add(cpu_obj, name, "bool", 1192 cpu_get_misa_ext_cfg, 1193 cpu_set_misa_ext_cfg, 1194 NULL, (void *)misa_cfg); 1195 object_property_set_description(cpu_obj, name, desc); 1196 if (use_def_vals) { 1197 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1198 misa_cfg->enabled); 1199 } 1200 } 1201 } 1202 1203 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1204 void *opaque, Error **errp) 1205 { 1206 RISCVCPUProfile *profile = opaque; 1207 RISCVCPU *cpu = RISCV_CPU(obj); 1208 bool value; 1209 int i, ext_offset; 1210 1211 if (riscv_cpu_is_vendor(obj)) { 1212 error_setg(errp, "Profile %s is not available for vendor CPUs", 1213 profile->name); 1214 return; 1215 } 1216 1217 if (cpu->env.misa_mxl != MXL_RV64) { 1218 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1219 profile->name); 1220 return; 1221 } 1222 1223 if (!visit_type_bool(v, name, &value, errp)) { 1224 return; 1225 } 1226 1227 profile->user_set = true; 1228 profile->enabled = value; 1229 1230 if (profile->u_parent != NULL) { 1231 object_property_set_bool(obj, profile->u_parent->name, 1232 profile->enabled, NULL); 1233 } 1234 1235 if (profile->s_parent != NULL) { 1236 object_property_set_bool(obj, profile->s_parent->name, 1237 profile->enabled, NULL); 1238 } 1239 1240 if (profile->enabled) { 1241 cpu->env.priv_ver = profile->priv_spec; 1242 } 1243 1244 #ifndef CONFIG_USER_ONLY 1245 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1246 object_property_set_bool(obj, "mmu", true, NULL); 1247 const char *satp_prop = satp_mode_str(profile->satp_mode, 1248 riscv_cpu_is_32bit(cpu)); 1249 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1250 } 1251 #endif 1252 1253 for (i = 0; misa_bits[i] != 0; i++) { 1254 uint32_t bit = misa_bits[i]; 1255 1256 if (!(profile->misa_ext & bit)) { 1257 continue; 1258 } 1259 1260 if (bit == RVI && !profile->enabled) { 1261 /* 1262 * Disabling profiles will not disable the base 1263 * ISA RV64I. 1264 */ 1265 continue; 1266 } 1267 1268 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1269 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1270 } 1271 1272 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1273 ext_offset = profile->ext_offsets[i]; 1274 1275 if (profile->enabled) { 1276 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1277 riscv_cpu_enable_named_feat(cpu, ext_offset); 1278 } 1279 1280 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1281 } 1282 1283 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1284 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1285 } 1286 } 1287 1288 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1289 void *opaque, Error **errp) 1290 { 1291 RISCVCPUProfile *profile = opaque; 1292 bool value = profile->enabled; 1293 1294 visit_type_bool(v, name, &value, errp); 1295 } 1296 1297 static void riscv_cpu_add_profiles(Object *cpu_obj) 1298 { 1299 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1300 const RISCVCPUProfile *profile = riscv_profiles[i]; 1301 1302 object_property_add(cpu_obj, profile->name, "bool", 1303 cpu_get_profile, cpu_set_profile, 1304 NULL, (void *)profile); 1305 1306 /* 1307 * CPUs might enable a profile right from the start. 1308 * Enable its mandatory extensions right away in this 1309 * case. 1310 */ 1311 if (profile->enabled) { 1312 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1313 } 1314 } 1315 } 1316 1317 static bool cpu_ext_is_deprecated(const char *ext_name) 1318 { 1319 return isupper(ext_name[0]); 1320 } 1321 1322 /* 1323 * String will be allocated in the heap. Caller is responsible 1324 * for freeing it. 1325 */ 1326 static char *cpu_ext_to_lower(const char *ext_name) 1327 { 1328 char *ret = g_malloc0(strlen(ext_name) + 1); 1329 1330 strcpy(ret, ext_name); 1331 ret[0] = tolower(ret[0]); 1332 1333 return ret; 1334 } 1335 1336 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1337 void *opaque, Error **errp) 1338 { 1339 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1340 RISCVCPU *cpu = RISCV_CPU(obj); 1341 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1342 bool prev_val, value; 1343 1344 if (!visit_type_bool(v, name, &value, errp)) { 1345 return; 1346 } 1347 1348 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1349 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1350 1351 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1352 multi_ext_cfg->name, lower); 1353 } 1354 1355 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1356 1357 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1358 1359 if (value == prev_val) { 1360 return; 1361 } 1362 1363 if (value && vendor_cpu) { 1364 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1365 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1366 cpuname); 1367 return; 1368 } 1369 1370 if (value) { 1371 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1372 } 1373 1374 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1375 } 1376 1377 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1378 void *opaque, Error **errp) 1379 { 1380 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1381 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1382 1383 visit_type_bool(v, name, &value, errp); 1384 } 1385 1386 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1387 const RISCVCPUMultiExtConfig *multi_cfg) 1388 { 1389 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1390 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1391 1392 object_property_add(cpu_obj, multi_cfg->name, "bool", 1393 cpu_get_multi_ext_cfg, 1394 cpu_set_multi_ext_cfg, 1395 NULL, (void *)multi_cfg); 1396 1397 if (!generic_cpu || deprecated_ext) { 1398 return; 1399 } 1400 1401 /* 1402 * Set def val directly instead of using 1403 * object_property_set_bool() to save the set() 1404 * callback hash for user inputs. 1405 */ 1406 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1407 multi_cfg->enabled); 1408 } 1409 1410 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1411 const RISCVCPUMultiExtConfig *array) 1412 { 1413 const RISCVCPUMultiExtConfig *prop; 1414 1415 g_assert(array); 1416 1417 for (prop = array; prop && prop->name; prop++) { 1418 cpu_add_multi_ext_prop(obj, prop); 1419 } 1420 } 1421 1422 /* 1423 * Add CPU properties with user-facing flags. 1424 * 1425 * This will overwrite existing env->misa_ext values with the 1426 * defaults set via riscv_cpu_add_misa_properties(). 1427 */ 1428 static void riscv_cpu_add_user_properties(Object *obj) 1429 { 1430 #ifndef CONFIG_USER_ONLY 1431 riscv_add_satp_mode_properties(obj); 1432 #endif 1433 1434 riscv_cpu_add_misa_properties(obj); 1435 1436 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1437 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1438 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1439 1440 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1441 1442 riscv_cpu_add_profiles(obj); 1443 } 1444 1445 /* 1446 * The 'max' type CPU will have all possible ratified 1447 * non-vendor extensions enabled. 1448 */ 1449 static void riscv_init_max_cpu_extensions(Object *obj) 1450 { 1451 RISCVCPU *cpu = RISCV_CPU(obj); 1452 CPURISCVState *env = &cpu->env; 1453 const RISCVCPUMultiExtConfig *prop; 1454 1455 /* Enable RVG and RVV that are disabled by default */ 1456 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1457 1458 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1459 isa_ext_update_enabled(cpu, prop->offset, true); 1460 } 1461 1462 /* 1463 * Some extensions can't be added without backward compatibilty concerns. 1464 * Disable those, the user can still opt in to them on the command line. 1465 */ 1466 cpu->cfg.ext_svade = false; 1467 1468 /* set vector version */ 1469 env->vext_ver = VEXT_VERSION_1_00_0; 1470 1471 /* Zfinx is not compatible with F. Disable it */ 1472 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1473 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1474 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1475 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1476 1477 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1478 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1479 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1480 1481 if (env->misa_mxl != MXL_RV32) { 1482 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1483 } 1484 1485 /* 1486 * TODO: ext_smrnmi requires OpenSBI changes that our current 1487 * image does not have. Disable it for now. 1488 */ 1489 if (cpu->cfg.ext_smrnmi) { 1490 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1491 } 1492 1493 /* 1494 * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup 1495 * to avoid generating a double trap. OpenSBI does not currently support it, 1496 * disable it for now. 1497 */ 1498 if (cpu->cfg.ext_smdbltrp) { 1499 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1500 } 1501 } 1502 1503 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1504 { 1505 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1506 } 1507 1508 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1509 { 1510 RISCVCPU *cpu = RISCV_CPU(cs); 1511 Object *obj = OBJECT(cpu); 1512 1513 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1514 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1515 1516 if (!misa_ext_implied_rules) { 1517 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1518 } 1519 1520 if (!multi_ext_implied_rules) { 1521 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1522 } 1523 1524 riscv_cpu_add_user_properties(obj); 1525 1526 if (riscv_cpu_has_max_extensions(obj)) { 1527 riscv_init_max_cpu_extensions(obj); 1528 } 1529 } 1530 1531 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, const void *data) 1532 { 1533 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1534 1535 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1536 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1537 } 1538 1539 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1540 .name = ACCEL_CPU_NAME("tcg"), 1541 1542 .parent = TYPE_ACCEL_CPU, 1543 .class_init = riscv_tcg_cpu_accel_class_init, 1544 .abstract = true, 1545 }; 1546 1547 static void riscv_tcg_cpu_accel_register_types(void) 1548 { 1549 type_register_static(&riscv_tcg_cpu_accel_type_info); 1550 } 1551 type_init(riscv_tcg_cpu_accel_register_types); 1552