1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "exec/translation-block.h" 23 #include "tcg-cpu.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "pmu.h" 27 #include "time_helper.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/accel.h" 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "hw/core/accel-cpu.h" 34 #include "hw/core/tcg-cpu-ops.h" 35 #include "tcg/tcg.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "hw/boards.h" 38 #endif 39 40 /* Hash that stores user set extensions */ 41 static GHashTable *multi_ext_user_opts; 42 static GHashTable *misa_ext_user_opts; 43 44 static GHashTable *multi_ext_implied_rules; 45 static GHashTable *misa_ext_implied_rules; 46 47 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 48 { 49 return g_hash_table_contains(multi_ext_user_opts, 50 GUINT_TO_POINTER(ext_offset)); 51 } 52 53 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 54 { 55 return g_hash_table_contains(misa_ext_user_opts, 56 GUINT_TO_POINTER(misa_bit)); 57 } 58 59 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 60 { 61 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 62 (gpointer)value); 63 } 64 65 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 66 { 67 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 68 (gpointer)value); 69 } 70 71 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 72 bool enabled) 73 { 74 CPURISCVState *env = &cpu->env; 75 76 if (enabled) { 77 env->misa_ext |= bit; 78 env->misa_ext_mask |= bit; 79 } else { 80 env->misa_ext &= ~bit; 81 env->misa_ext_mask &= ~bit; 82 } 83 } 84 85 static const char *cpu_priv_ver_to_str(int priv_ver) 86 { 87 const char *priv_spec_str = priv_spec_to_str(priv_ver); 88 89 g_assert(priv_spec_str); 90 91 return priv_spec_str; 92 } 93 94 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 95 const TranslationBlock *tb) 96 { 97 if (!(tb_cflags(tb) & CF_PCREL)) { 98 RISCVCPU *cpu = RISCV_CPU(cs); 99 CPURISCVState *env = &cpu->env; 100 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 101 102 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 103 104 if (xl == MXL_RV32) { 105 env->pc = (int32_t) tb->pc; 106 } else { 107 env->pc = tb->pc; 108 } 109 } 110 } 111 112 static void riscv_restore_state_to_opc(CPUState *cs, 113 const TranslationBlock *tb, 114 const uint64_t *data) 115 { 116 RISCVCPU *cpu = RISCV_CPU(cs); 117 CPURISCVState *env = &cpu->env; 118 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 119 target_ulong pc; 120 121 if (tb_cflags(tb) & CF_PCREL) { 122 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 123 } else { 124 pc = data[0]; 125 } 126 127 if (xl == MXL_RV32) { 128 env->pc = (int32_t)pc; 129 } else { 130 env->pc = pc; 131 } 132 env->bins = data[1]; 133 env->excp_uw2 = data[2]; 134 } 135 136 static const TCGCPUOps riscv_tcg_ops = { 137 .initialize = riscv_translate_init, 138 .translate_code = riscv_translate_code, 139 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 140 .restore_state_to_opc = riscv_restore_state_to_opc, 141 142 #ifndef CONFIG_USER_ONLY 143 .tlb_fill = riscv_cpu_tlb_fill, 144 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 145 .cpu_exec_halt = riscv_cpu_has_work, 146 .do_interrupt = riscv_cpu_do_interrupt, 147 .do_transaction_failed = riscv_cpu_do_transaction_failed, 148 .do_unaligned_access = riscv_cpu_do_unaligned_access, 149 .debug_excp_handler = riscv_cpu_debug_excp_handler, 150 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 151 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 152 #endif /* !CONFIG_USER_ONLY */ 153 }; 154 155 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 156 { 157 const RISCVIsaExtData *edata; 158 159 for (edata = isa_edata_arr; edata && edata->name; edata++) { 160 if (edata->ext_enable_offset != ext_offset) { 161 continue; 162 } 163 164 return edata->min_version; 165 } 166 167 g_assert_not_reached(); 168 } 169 170 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 171 { 172 const RISCVCPUMultiExtConfig *feat; 173 const RISCVIsaExtData *edata; 174 175 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 176 if (edata->ext_enable_offset == ext_offset) { 177 return edata->name; 178 } 179 } 180 181 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 182 if (feat->offset == ext_offset) { 183 return feat->name; 184 } 185 } 186 187 g_assert_not_reached(); 188 } 189 190 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 191 { 192 const RISCVCPUMultiExtConfig *feat; 193 194 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 195 if (feat->offset == ext_offset) { 196 return true; 197 } 198 } 199 200 return false; 201 } 202 203 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 204 { 205 /* 206 * All other named features are already enabled 207 * in riscv_tcg_cpu_instance_init(). 208 */ 209 switch (feat_offset) { 210 case CPU_CFG_OFFSET(ext_zic64b): 211 cpu->cfg.cbom_blocksize = 64; 212 cpu->cfg.cbop_blocksize = 64; 213 cpu->cfg.cboz_blocksize = 64; 214 break; 215 case CPU_CFG_OFFSET(ext_sha): 216 if (!cpu_misa_ext_is_user_set(RVH)) { 217 riscv_cpu_write_misa_bit(cpu, RVH, true); 218 } 219 /* fallthrough */ 220 case CPU_CFG_OFFSET(ext_ssstateen): 221 cpu->cfg.ext_smstateen = true; 222 break; 223 } 224 } 225 226 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 227 uint32_t ext_offset) 228 { 229 int ext_priv_ver; 230 231 if (env->priv_ver == PRIV_VERSION_LATEST) { 232 return; 233 } 234 235 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 236 237 if (env->priv_ver < ext_priv_ver) { 238 /* 239 * Note: the 'priv_spec' command line option, if present, 240 * will take precedence over this priv_ver bump. 241 */ 242 env->priv_ver = ext_priv_ver; 243 } 244 } 245 246 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 247 bool value) 248 { 249 CPURISCVState *env = &cpu->env; 250 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 251 int min_version; 252 253 if (prev_val == value) { 254 return; 255 } 256 257 if (cpu_cfg_ext_is_user_set(ext_offset)) { 258 return; 259 } 260 261 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 262 /* Do not enable it if priv_ver is older than min_version */ 263 min_version = cpu_cfg_ext_get_min_version(ext_offset); 264 if (env->priv_ver < min_version) { 265 return; 266 } 267 } 268 269 isa_ext_update_enabled(cpu, ext_offset, value); 270 } 271 272 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 273 { 274 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 275 error_setg(errp, "H extension requires priv spec 1.12.0"); 276 return; 277 } 278 } 279 280 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 281 Error **errp) 282 { 283 uint32_t vlen = cfg->vlenb << 3; 284 285 if (vlen > RV_VLEN_MAX || vlen < 128) { 286 error_setg(errp, 287 "Vector extension implementation only supports VLEN " 288 "in the range [128, %d]", RV_VLEN_MAX); 289 return; 290 } 291 292 if (cfg->elen > 64 || cfg->elen < 8) { 293 error_setg(errp, 294 "Vector extension implementation only supports ELEN " 295 "in the range [8, 64]"); 296 return; 297 } 298 } 299 300 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 301 { 302 CPURISCVState *env = &cpu->env; 303 const RISCVIsaExtData *edata; 304 305 /* Force disable extensions if priv spec version does not match */ 306 for (edata = isa_edata_arr; edata && edata->name; edata++) { 307 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 308 (env->priv_ver < edata->min_version)) { 309 /* 310 * These two extensions are always enabled as they were supported 311 * by QEMU before they were added as extensions in the ISA. 312 */ 313 if (!strcmp(edata->name, "zicntr") || 314 !strcmp(edata->name, "zihpm")) { 315 continue; 316 } 317 318 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 319 320 /* 321 * Do not show user warnings for named features that users 322 * can't enable/disable in the command line. See commit 323 * 68c9e54bea for more info. 324 */ 325 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 326 continue; 327 } 328 #ifndef CONFIG_USER_ONLY 329 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 330 " because privilege spec version does not match", 331 edata->name, env->mhartid); 332 #else 333 warn_report("disabling %s extension because " 334 "privilege spec version does not match", 335 edata->name); 336 #endif 337 } 338 } 339 } 340 341 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 342 { 343 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 344 cpu->cfg.has_priv_1_11 = true; 345 } 346 347 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 348 cpu->cfg.has_priv_1_12 = true; 349 } 350 351 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 352 cpu->cfg.has_priv_1_13 = true; 353 } 354 355 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 356 cpu->cfg.cbop_blocksize == 64 && 357 cpu->cfg.cboz_blocksize == 64; 358 359 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 360 361 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 362 cpu->cfg.ext_ssstateen; 363 } 364 365 static void riscv_cpu_validate_g(RISCVCPU *cpu) 366 { 367 const char *warn_msg = "RVG mandates disabled extension %s"; 368 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 369 bool send_warn = cpu_misa_ext_is_user_set(RVG); 370 371 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 372 uint32_t bit = g_misa_bits[i]; 373 374 if (riscv_has_ext(&cpu->env, bit)) { 375 continue; 376 } 377 378 if (!cpu_misa_ext_is_user_set(bit)) { 379 riscv_cpu_write_misa_bit(cpu, bit, true); 380 continue; 381 } 382 383 if (send_warn) { 384 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 385 } 386 } 387 388 if (!cpu->cfg.ext_zicsr) { 389 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 390 cpu->cfg.ext_zicsr = true; 391 } else if (send_warn) { 392 warn_report(warn_msg, "zicsr"); 393 } 394 } 395 396 if (!cpu->cfg.ext_zifencei) { 397 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 398 cpu->cfg.ext_zifencei = true; 399 } else if (send_warn) { 400 warn_report(warn_msg, "zifencei"); 401 } 402 } 403 } 404 405 static void riscv_cpu_validate_b(RISCVCPU *cpu) 406 { 407 const char *warn_msg = "RVB mandates disabled extension %s"; 408 409 if (!cpu->cfg.ext_zba) { 410 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 411 cpu->cfg.ext_zba = true; 412 } else { 413 warn_report(warn_msg, "zba"); 414 } 415 } 416 417 if (!cpu->cfg.ext_zbb) { 418 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 419 cpu->cfg.ext_zbb = true; 420 } else { 421 warn_report(warn_msg, "zbb"); 422 } 423 } 424 425 if (!cpu->cfg.ext_zbs) { 426 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 427 cpu->cfg.ext_zbs = true; 428 } else { 429 warn_report(warn_msg, "zbs"); 430 } 431 } 432 } 433 434 /* 435 * Check consistency between chosen extensions while setting 436 * cpu->cfg accordingly. 437 */ 438 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 439 { 440 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 441 CPURISCVState *env = &cpu->env; 442 Error *local_err = NULL; 443 444 if (riscv_has_ext(env, RVG)) { 445 riscv_cpu_validate_g(cpu); 446 } 447 448 if (riscv_has_ext(env, RVB)) { 449 riscv_cpu_validate_b(cpu); 450 } 451 452 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 453 error_setg(errp, 454 "I and E extensions are incompatible"); 455 return; 456 } 457 458 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 459 error_setg(errp, 460 "Either I or E extension must be set"); 461 return; 462 } 463 464 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 465 error_setg(errp, 466 "Setting S extension without U extension is illegal"); 467 return; 468 } 469 470 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 471 error_setg(errp, 472 "H depends on an I base integer ISA with 32 x registers"); 473 return; 474 } 475 476 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 477 error_setg(errp, "H extension implicitly requires S-mode"); 478 return; 479 } 480 481 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 482 error_setg(errp, "F extension requires Zicsr"); 483 return; 484 } 485 486 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 487 error_setg(errp, "Zacas extension requires A extension"); 488 return; 489 } 490 491 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 492 error_setg(errp, "Zawrs extension requires A extension"); 493 return; 494 } 495 496 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 497 error_setg(errp, "Zfa extension requires F extension"); 498 return; 499 } 500 501 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 502 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 503 return; 504 } 505 506 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 507 error_setg(errp, "Zfbfmin extension depends on F extension"); 508 return; 509 } 510 511 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 512 error_setg(errp, "D extension requires F extension"); 513 return; 514 } 515 516 if (riscv_has_ext(env, RVV)) { 517 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 518 if (local_err != NULL) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 } 523 524 /* The Zve64d extension depends on the Zve64f extension */ 525 if (cpu->cfg.ext_zve64d) { 526 if (!riscv_has_ext(env, RVD)) { 527 error_setg(errp, "Zve64d/V extensions require D extension"); 528 return; 529 } 530 } 531 532 /* The Zve32f extension depends on the Zve32x extension */ 533 if (cpu->cfg.ext_zve32f) { 534 if (!riscv_has_ext(env, RVF)) { 535 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 536 return; 537 } 538 } 539 540 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 541 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 542 return; 543 } 544 545 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 546 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 547 return; 548 } 549 550 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 551 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 552 return; 553 } 554 555 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 556 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 557 return; 558 } 559 560 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 561 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 562 return; 563 } 564 565 if (cpu->cfg.ext_zfinx) { 566 if (!cpu->cfg.ext_zicsr) { 567 error_setg(errp, "Zfinx extension requires Zicsr"); 568 return; 569 } 570 if (riscv_has_ext(env, RVF)) { 571 error_setg(errp, 572 "Zfinx cannot be supported together with F extension"); 573 return; 574 } 575 } 576 577 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 578 error_setg(errp, "Zcmop extensions require Zca"); 579 return; 580 } 581 582 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 583 error_setg(errp, "Zcf extension is only relevant to RV32"); 584 return; 585 } 586 587 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 588 error_setg(errp, "Zcf extension requires F extension"); 589 return; 590 } 591 592 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 593 error_setg(errp, "Zcd extension requires D extension"); 594 return; 595 } 596 597 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 598 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 599 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 600 "extension"); 601 return; 602 } 603 604 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 605 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 606 "Zcd extension"); 607 return; 608 } 609 610 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 611 error_setg(errp, "Zcmt extension requires Zicsr extension"); 612 return; 613 } 614 615 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 616 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 617 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 618 error_setg(errp, 619 "Vector crypto extensions require V or Zve* extensions"); 620 return; 621 } 622 623 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 624 error_setg( 625 errp, 626 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 627 return; 628 } 629 630 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 631 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 632 error_setg(errp, "zicntr requires zicsr"); 633 return; 634 } 635 cpu->cfg.ext_zicntr = false; 636 } 637 638 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 639 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 640 error_setg(errp, "zihpm requires zicsr"); 641 return; 642 } 643 cpu->cfg.ext_zihpm = false; 644 } 645 646 if (cpu->cfg.ext_zicfiss) { 647 if (!cpu->cfg.ext_zicsr) { 648 error_setg(errp, "zicfiss extension requires zicsr extension"); 649 return; 650 } 651 if (!riscv_has_ext(env, RVA)) { 652 error_setg(errp, "zicfiss extension requires A extension"); 653 return; 654 } 655 if (!riscv_has_ext(env, RVS)) { 656 error_setg(errp, "zicfiss extension requires S"); 657 return; 658 } 659 if (!cpu->cfg.ext_zimop) { 660 error_setg(errp, "zicfiss extension requires zimop extension"); 661 return; 662 } 663 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 664 error_setg(errp, "zicfiss with zca requires zcmop extension"); 665 return; 666 } 667 } 668 669 if (!cpu->cfg.ext_zihpm) { 670 cpu->cfg.pmu_mask = 0; 671 cpu->pmu_avail_ctrs = 0; 672 } 673 674 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 675 error_setg(errp, "zicfilp extension requires zicsr extension"); 676 return; 677 } 678 679 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 680 error_setg(errp, "svukte is not supported for RV32"); 681 return; 682 } 683 684 /* 685 * Disable isa extensions based on priv spec after we 686 * validated and set everything we need. 687 */ 688 riscv_cpu_disable_priv_spec_isa_exts(cpu); 689 } 690 691 #ifndef CONFIG_USER_ONLY 692 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 693 RISCVCPUProfile *profile, 694 bool send_warn) 695 { 696 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 697 698 if (profile->satp_mode > satp_max) { 699 if (send_warn) { 700 bool is_32bit = riscv_cpu_is_32bit(cpu); 701 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 702 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 703 704 warn_report("Profile %s requires satp mode %s, " 705 "but satp mode %s was set", profile->name, 706 req_satp, cur_satp); 707 } 708 709 return false; 710 } 711 712 return true; 713 } 714 #endif 715 716 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, 717 RISCVCPUProfile *profile, 718 RISCVCPUProfile *parent) 719 { 720 const char *parent_name; 721 bool parent_enabled; 722 723 if (!profile->enabled || !parent) { 724 return; 725 } 726 727 parent_name = parent->name; 728 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); 729 profile->enabled = parent_enabled; 730 } 731 732 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 733 RISCVCPUProfile *profile) 734 { 735 CPURISCVState *env = &cpu->env; 736 const char *warn_msg = "Profile %s mandates disabled extension %s"; 737 bool send_warn = profile->user_set && profile->enabled; 738 bool profile_impl = true; 739 int i; 740 741 #ifndef CONFIG_USER_ONLY 742 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 743 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 744 send_warn); 745 } 746 #endif 747 748 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 749 profile->priv_spec > env->priv_ver) { 750 profile_impl = false; 751 752 if (send_warn) { 753 warn_report("Profile %s requires priv spec %s, " 754 "but priv ver %s was set", profile->name, 755 cpu_priv_ver_to_str(profile->priv_spec), 756 cpu_priv_ver_to_str(env->priv_ver)); 757 } 758 } 759 760 for (i = 0; misa_bits[i] != 0; i++) { 761 uint32_t bit = misa_bits[i]; 762 763 if (!(profile->misa_ext & bit)) { 764 continue; 765 } 766 767 if (!riscv_has_ext(&cpu->env, bit)) { 768 profile_impl = false; 769 770 if (send_warn) { 771 warn_report(warn_msg, profile->name, 772 riscv_get_misa_ext_name(bit)); 773 } 774 } 775 } 776 777 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 778 int ext_offset = profile->ext_offsets[i]; 779 780 if (!isa_ext_is_enabled(cpu, ext_offset)) { 781 profile_impl = false; 782 783 if (send_warn) { 784 warn_report(warn_msg, profile->name, 785 cpu_cfg_ext_get_name(ext_offset)); 786 } 787 } 788 } 789 790 profile->enabled = profile_impl; 791 792 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); 793 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); 794 } 795 796 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 797 { 798 for (int i = 0; riscv_profiles[i] != NULL; i++) { 799 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 800 } 801 } 802 803 static void riscv_cpu_init_implied_exts_rules(void) 804 { 805 RISCVCPUImpliedExtsRule *rule; 806 #ifndef CONFIG_USER_ONLY 807 MachineState *ms = MACHINE(qdev_get_machine()); 808 #endif 809 static bool initialized; 810 int i; 811 812 /* Implied rules only need to be initialized once. */ 813 if (initialized) { 814 return; 815 } 816 817 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 818 #ifndef CONFIG_USER_ONLY 819 rule->enabled = bitmap_new(ms->smp.cpus); 820 #endif 821 g_hash_table_insert(misa_ext_implied_rules, 822 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 823 } 824 825 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 826 #ifndef CONFIG_USER_ONLY 827 rule->enabled = bitmap_new(ms->smp.cpus); 828 #endif 829 g_hash_table_insert(multi_ext_implied_rules, 830 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 831 } 832 833 initialized = true; 834 } 835 836 static void cpu_enable_implied_rule(RISCVCPU *cpu, 837 RISCVCPUImpliedExtsRule *rule) 838 { 839 CPURISCVState *env = &cpu->env; 840 RISCVCPUImpliedExtsRule *ir; 841 bool enabled = false; 842 int i; 843 844 #ifndef CONFIG_USER_ONLY 845 enabled = test_bit(cpu->env.mhartid, rule->enabled); 846 #endif 847 848 if (!enabled) { 849 /* Enable the implied MISAs. */ 850 if (rule->implied_misa_exts) { 851 for (i = 0; misa_bits[i] != 0; i++) { 852 if (rule->implied_misa_exts & misa_bits[i]) { 853 /* 854 * If the user disabled the misa_bit do not re-enable it 855 * and do not apply any implied rules related to it. 856 */ 857 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 858 !(env->misa_ext & misa_bits[i])) { 859 continue; 860 } 861 862 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 863 ir = g_hash_table_lookup(misa_ext_implied_rules, 864 GUINT_TO_POINTER(misa_bits[i])); 865 866 if (ir) { 867 cpu_enable_implied_rule(cpu, ir); 868 } 869 } 870 } 871 } 872 873 /* Enable the implied extensions. */ 874 for (i = 0; 875 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 876 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 877 878 ir = g_hash_table_lookup(multi_ext_implied_rules, 879 GUINT_TO_POINTER( 880 rule->implied_multi_exts[i])); 881 882 if (ir) { 883 cpu_enable_implied_rule(cpu, ir); 884 } 885 } 886 887 #ifndef CONFIG_USER_ONLY 888 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 889 #endif 890 } 891 } 892 893 /* Zc extension has special implied rules that need to be handled separately. */ 894 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 895 { 896 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 897 CPURISCVState *env = &cpu->env; 898 899 if (cpu->cfg.ext_zce) { 900 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 901 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 902 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 903 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 904 905 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 906 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 907 } 908 } 909 910 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 911 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 912 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 913 914 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 915 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 916 } 917 918 if (riscv_has_ext(env, RVD)) { 919 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 920 } 921 } 922 } 923 924 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 925 { 926 RISCVCPUImpliedExtsRule *rule; 927 int i; 928 929 /* Enable the implied extensions for Zc. */ 930 cpu_enable_zc_implied_rules(cpu); 931 932 /* Enable the implied MISAs. */ 933 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 934 if (riscv_has_ext(&cpu->env, rule->ext)) { 935 cpu_enable_implied_rule(cpu, rule); 936 } 937 } 938 939 /* Enable the implied extensions. */ 940 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 941 if (isa_ext_is_enabled(cpu, rule->ext)) { 942 cpu_enable_implied_rule(cpu, rule); 943 } 944 } 945 } 946 947 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 948 { 949 CPURISCVState *env = &cpu->env; 950 Error *local_err = NULL; 951 952 riscv_cpu_init_implied_exts_rules(); 953 riscv_cpu_enable_implied_rules(cpu); 954 955 riscv_cpu_validate_misa_priv(env, &local_err); 956 if (local_err != NULL) { 957 error_propagate(errp, local_err); 958 return; 959 } 960 961 riscv_cpu_update_named_features(cpu); 962 riscv_cpu_validate_profiles(cpu); 963 964 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 965 /* 966 * Enhanced PMP should only be available 967 * on harts with PMP support 968 */ 969 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 970 return; 971 } 972 973 riscv_cpu_validate_set_extensions(cpu, &local_err); 974 if (local_err != NULL) { 975 error_propagate(errp, local_err); 976 return; 977 } 978 #ifndef CONFIG_USER_ONLY 979 if (cpu->cfg.pmu_mask) { 980 riscv_pmu_init(cpu, &local_err); 981 if (local_err != NULL) { 982 error_propagate(errp, local_err); 983 return; 984 } 985 986 if (cpu->cfg.ext_sscofpmf) { 987 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 988 riscv_pmu_timer_cb, cpu); 989 } 990 } 991 #endif 992 } 993 994 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 995 { 996 GPtrArray *dynamic_decoders; 997 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 998 for (size_t i = 0; i < decoder_table_size; ++i) { 999 if (decoder_table[i].guard_func && 1000 decoder_table[i].guard_func(&cpu->cfg)) { 1001 g_ptr_array_add(dynamic_decoders, 1002 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 1003 } 1004 } 1005 1006 cpu->decoders = dynamic_decoders; 1007 } 1008 1009 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 1010 { 1011 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1012 } 1013 1014 static bool riscv_cpu_is_generic(Object *cpu_obj) 1015 { 1016 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1017 } 1018 1019 /* 1020 * We'll get here via the following path: 1021 * 1022 * riscv_cpu_realize() 1023 * -> cpu_exec_realizefn() 1024 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1025 */ 1026 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1027 { 1028 RISCVCPU *cpu = RISCV_CPU(cs); 1029 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1030 1031 if (!riscv_cpu_tcg_compatible(cpu)) { 1032 g_autofree char *name = riscv_cpu_get_name(cpu); 1033 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1034 name); 1035 return false; 1036 } 1037 1038 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1039 /* Missing 128-bit aligned atomics */ 1040 error_setg(errp, 1041 "128-bit RISC-V currently does not work with Multi " 1042 "Threaded TCG. Please use: -accel tcg,thread=single"); 1043 return false; 1044 } 1045 1046 #ifndef CONFIG_USER_ONLY 1047 CPURISCVState *env = &cpu->env; 1048 1049 tcg_cflags_set(CPU(cs), CF_PCREL); 1050 1051 if (cpu->cfg.ext_sstc) { 1052 riscv_timer_init(cpu); 1053 } 1054 1055 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1056 if (riscv_has_ext(env, RVH)) { 1057 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1058 } 1059 #endif 1060 1061 return true; 1062 } 1063 1064 typedef struct RISCVCPUMisaExtConfig { 1065 target_ulong misa_bit; 1066 bool enabled; 1067 } RISCVCPUMisaExtConfig; 1068 1069 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1070 void *opaque, Error **errp) 1071 { 1072 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1073 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1074 RISCVCPU *cpu = RISCV_CPU(obj); 1075 CPURISCVState *env = &cpu->env; 1076 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1077 bool prev_val, value; 1078 1079 if (!visit_type_bool(v, name, &value, errp)) { 1080 return; 1081 } 1082 1083 cpu_misa_ext_add_user_opt(misa_bit, value); 1084 1085 prev_val = env->misa_ext & misa_bit; 1086 1087 if (value == prev_val) { 1088 return; 1089 } 1090 1091 if (value) { 1092 if (vendor_cpu) { 1093 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1094 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1095 cpuname); 1096 return; 1097 } 1098 1099 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1100 /* 1101 * Note: the 'priv_spec' command line option, if present, 1102 * will take precedence over this priv_ver bump. 1103 */ 1104 env->priv_ver = PRIV_VERSION_1_12_0; 1105 } 1106 } 1107 1108 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1109 } 1110 1111 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1112 void *opaque, Error **errp) 1113 { 1114 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1115 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1116 RISCVCPU *cpu = RISCV_CPU(obj); 1117 CPURISCVState *env = &cpu->env; 1118 bool value; 1119 1120 value = env->misa_ext & misa_bit; 1121 1122 visit_type_bool(v, name, &value, errp); 1123 } 1124 1125 #define MISA_CFG(_bit, _enabled) \ 1126 {.misa_bit = _bit, .enabled = _enabled} 1127 1128 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1129 MISA_CFG(RVA, true), 1130 MISA_CFG(RVC, true), 1131 MISA_CFG(RVD, true), 1132 MISA_CFG(RVF, true), 1133 MISA_CFG(RVI, true), 1134 MISA_CFG(RVE, false), 1135 MISA_CFG(RVM, true), 1136 MISA_CFG(RVS, true), 1137 MISA_CFG(RVU, true), 1138 MISA_CFG(RVH, true), 1139 MISA_CFG(RVV, false), 1140 MISA_CFG(RVG, false), 1141 MISA_CFG(RVB, false), 1142 }; 1143 1144 /* 1145 * We do not support user choice tracking for MISA 1146 * extensions yet because, so far, we do not silently 1147 * change MISA bits during realize() (RVG enables MISA 1148 * bits but the user is warned about it). 1149 */ 1150 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1151 { 1152 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1153 int i; 1154 1155 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1156 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1157 int bit = misa_cfg->misa_bit; 1158 const char *name = riscv_get_misa_ext_name(bit); 1159 const char *desc = riscv_get_misa_ext_description(bit); 1160 1161 /* Check if KVM already created the property */ 1162 if (object_property_find(cpu_obj, name)) { 1163 continue; 1164 } 1165 1166 object_property_add(cpu_obj, name, "bool", 1167 cpu_get_misa_ext_cfg, 1168 cpu_set_misa_ext_cfg, 1169 NULL, (void *)misa_cfg); 1170 object_property_set_description(cpu_obj, name, desc); 1171 if (use_def_vals) { 1172 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1173 misa_cfg->enabled); 1174 } 1175 } 1176 } 1177 1178 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1179 void *opaque, Error **errp) 1180 { 1181 RISCVCPUProfile *profile = opaque; 1182 RISCVCPU *cpu = RISCV_CPU(obj); 1183 bool value; 1184 int i, ext_offset; 1185 1186 if (riscv_cpu_is_vendor(obj)) { 1187 error_setg(errp, "Profile %s is not available for vendor CPUs", 1188 profile->name); 1189 return; 1190 } 1191 1192 if (cpu->env.misa_mxl != MXL_RV64) { 1193 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1194 profile->name); 1195 return; 1196 } 1197 1198 if (!visit_type_bool(v, name, &value, errp)) { 1199 return; 1200 } 1201 1202 profile->user_set = true; 1203 profile->enabled = value; 1204 1205 if (profile->u_parent != NULL) { 1206 object_property_set_bool(obj, profile->u_parent->name, 1207 profile->enabled, NULL); 1208 } 1209 1210 if (profile->s_parent != NULL) { 1211 object_property_set_bool(obj, profile->s_parent->name, 1212 profile->enabled, NULL); 1213 } 1214 1215 if (profile->enabled) { 1216 cpu->env.priv_ver = profile->priv_spec; 1217 } 1218 1219 #ifndef CONFIG_USER_ONLY 1220 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1221 object_property_set_bool(obj, "mmu", true, NULL); 1222 const char *satp_prop = satp_mode_str(profile->satp_mode, 1223 riscv_cpu_is_32bit(cpu)); 1224 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1225 } 1226 #endif 1227 1228 for (i = 0; misa_bits[i] != 0; i++) { 1229 uint32_t bit = misa_bits[i]; 1230 1231 if (!(profile->misa_ext & bit)) { 1232 continue; 1233 } 1234 1235 if (bit == RVI && !profile->enabled) { 1236 /* 1237 * Disabling profiles will not disable the base 1238 * ISA RV64I. 1239 */ 1240 continue; 1241 } 1242 1243 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1244 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1245 } 1246 1247 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1248 ext_offset = profile->ext_offsets[i]; 1249 1250 if (profile->enabled) { 1251 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1252 riscv_cpu_enable_named_feat(cpu, ext_offset); 1253 } 1254 1255 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1256 } 1257 1258 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1259 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1260 } 1261 } 1262 1263 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1264 void *opaque, Error **errp) 1265 { 1266 RISCVCPUProfile *profile = opaque; 1267 bool value = profile->enabled; 1268 1269 visit_type_bool(v, name, &value, errp); 1270 } 1271 1272 static void riscv_cpu_add_profiles(Object *cpu_obj) 1273 { 1274 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1275 const RISCVCPUProfile *profile = riscv_profiles[i]; 1276 1277 object_property_add(cpu_obj, profile->name, "bool", 1278 cpu_get_profile, cpu_set_profile, 1279 NULL, (void *)profile); 1280 1281 /* 1282 * CPUs might enable a profile right from the start. 1283 * Enable its mandatory extensions right away in this 1284 * case. 1285 */ 1286 if (profile->enabled) { 1287 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1288 } 1289 } 1290 } 1291 1292 static bool cpu_ext_is_deprecated(const char *ext_name) 1293 { 1294 return isupper(ext_name[0]); 1295 } 1296 1297 /* 1298 * String will be allocated in the heap. Caller is responsible 1299 * for freeing it. 1300 */ 1301 static char *cpu_ext_to_lower(const char *ext_name) 1302 { 1303 char *ret = g_malloc0(strlen(ext_name) + 1); 1304 1305 strcpy(ret, ext_name); 1306 ret[0] = tolower(ret[0]); 1307 1308 return ret; 1309 } 1310 1311 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1312 void *opaque, Error **errp) 1313 { 1314 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1315 RISCVCPU *cpu = RISCV_CPU(obj); 1316 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1317 bool prev_val, value; 1318 1319 if (!visit_type_bool(v, name, &value, errp)) { 1320 return; 1321 } 1322 1323 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1324 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1325 1326 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1327 multi_ext_cfg->name, lower); 1328 } 1329 1330 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1331 1332 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1333 1334 if (value == prev_val) { 1335 return; 1336 } 1337 1338 if (value && vendor_cpu) { 1339 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1340 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1341 cpuname); 1342 return; 1343 } 1344 1345 if (value) { 1346 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1347 } 1348 1349 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1350 } 1351 1352 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1353 void *opaque, Error **errp) 1354 { 1355 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1356 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1357 1358 visit_type_bool(v, name, &value, errp); 1359 } 1360 1361 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1362 const RISCVCPUMultiExtConfig *multi_cfg) 1363 { 1364 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1365 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1366 1367 object_property_add(cpu_obj, multi_cfg->name, "bool", 1368 cpu_get_multi_ext_cfg, 1369 cpu_set_multi_ext_cfg, 1370 NULL, (void *)multi_cfg); 1371 1372 if (!generic_cpu || deprecated_ext) { 1373 return; 1374 } 1375 1376 /* 1377 * Set def val directly instead of using 1378 * object_property_set_bool() to save the set() 1379 * callback hash for user inputs. 1380 */ 1381 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1382 multi_cfg->enabled); 1383 } 1384 1385 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1386 const RISCVCPUMultiExtConfig *array) 1387 { 1388 const RISCVCPUMultiExtConfig *prop; 1389 1390 g_assert(array); 1391 1392 for (prop = array; prop && prop->name; prop++) { 1393 cpu_add_multi_ext_prop(obj, prop); 1394 } 1395 } 1396 1397 /* 1398 * Add CPU properties with user-facing flags. 1399 * 1400 * This will overwrite existing env->misa_ext values with the 1401 * defaults set via riscv_cpu_add_misa_properties(). 1402 */ 1403 static void riscv_cpu_add_user_properties(Object *obj) 1404 { 1405 #ifndef CONFIG_USER_ONLY 1406 riscv_add_satp_mode_properties(obj); 1407 #endif 1408 1409 riscv_cpu_add_misa_properties(obj); 1410 1411 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1412 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1413 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1414 1415 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1416 1417 riscv_cpu_add_profiles(obj); 1418 } 1419 1420 /* 1421 * The 'max' type CPU will have all possible ratified 1422 * non-vendor extensions enabled. 1423 */ 1424 static void riscv_init_max_cpu_extensions(Object *obj) 1425 { 1426 RISCVCPU *cpu = RISCV_CPU(obj); 1427 CPURISCVState *env = &cpu->env; 1428 const RISCVCPUMultiExtConfig *prop; 1429 1430 /* Enable RVG and RVV that are disabled by default */ 1431 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1432 1433 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1434 isa_ext_update_enabled(cpu, prop->offset, true); 1435 } 1436 1437 /* 1438 * Some extensions can't be added without backward compatibilty concerns. 1439 * Disable those, the user can still opt in to them on the command line. 1440 */ 1441 cpu->cfg.ext_svade = false; 1442 1443 /* set vector version */ 1444 env->vext_ver = VEXT_VERSION_1_00_0; 1445 1446 /* Zfinx is not compatible with F. Disable it */ 1447 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1448 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1449 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1450 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1451 1452 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1453 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1454 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1455 1456 if (env->misa_mxl != MXL_RV32) { 1457 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1458 } 1459 1460 /* 1461 * ext_smrnmi requires OpenSBI changes that our current 1462 * image does not have. Disable it for now. 1463 */ 1464 if (cpu->cfg.ext_smrnmi) { 1465 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1466 qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); 1467 } 1468 1469 /* 1470 * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to 1471 * avoid generating a double trap. OpenSBI does not currently support it, 1472 * disable it for now. 1473 */ 1474 if (cpu->cfg.ext_smdbltrp) { 1475 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1476 qemu_log("Smdbltrp is disabled in the 'max' type CPU\n"); 1477 } 1478 } 1479 1480 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1481 { 1482 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1483 } 1484 1485 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1486 { 1487 RISCVCPU *cpu = RISCV_CPU(cs); 1488 Object *obj = OBJECT(cpu); 1489 1490 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1491 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1492 1493 if (!misa_ext_implied_rules) { 1494 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1495 } 1496 1497 if (!multi_ext_implied_rules) { 1498 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1499 } 1500 1501 riscv_cpu_add_user_properties(obj); 1502 1503 if (riscv_cpu_has_max_extensions(obj)) { 1504 riscv_init_max_cpu_extensions(obj); 1505 } 1506 } 1507 1508 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1509 { 1510 /* 1511 * All cpus use the same set of operations. 1512 */ 1513 cc->tcg_ops = &riscv_tcg_ops; 1514 } 1515 1516 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1517 { 1518 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1519 } 1520 1521 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1522 { 1523 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1524 1525 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1526 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1527 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1528 } 1529 1530 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1531 .name = ACCEL_CPU_NAME("tcg"), 1532 1533 .parent = TYPE_ACCEL_CPU, 1534 .class_init = riscv_tcg_cpu_accel_class_init, 1535 .abstract = true, 1536 }; 1537 1538 static void riscv_tcg_cpu_accel_register_types(void) 1539 { 1540 type_register_static(&riscv_tcg_cpu_accel_type_info); 1541 } 1542 type_init(riscv_tcg_cpu_accel_register_types); 1543