1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "exec/translation-block.h" 23 #include "tcg-cpu.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "pmu.h" 27 #include "time_helper.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/accel.h" 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "accel/accel-cpu-target.h" 34 #include "accel/tcg/cpu-ops.h" 35 #include "tcg/tcg.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "hw/boards.h" 38 #endif 39 40 /* Hash that stores user set extensions */ 41 static GHashTable *multi_ext_user_opts; 42 static GHashTable *misa_ext_user_opts; 43 44 static GHashTable *multi_ext_implied_rules; 45 static GHashTable *misa_ext_implied_rules; 46 47 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 48 { 49 return g_hash_table_contains(multi_ext_user_opts, 50 GUINT_TO_POINTER(ext_offset)); 51 } 52 53 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 54 { 55 return g_hash_table_contains(misa_ext_user_opts, 56 GUINT_TO_POINTER(misa_bit)); 57 } 58 59 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 60 { 61 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 62 (gpointer)value); 63 } 64 65 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 66 { 67 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 68 (gpointer)value); 69 } 70 71 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 72 bool enabled) 73 { 74 CPURISCVState *env = &cpu->env; 75 76 if (enabled) { 77 env->misa_ext |= bit; 78 env->misa_ext_mask |= bit; 79 } else { 80 env->misa_ext &= ~bit; 81 env->misa_ext_mask &= ~bit; 82 } 83 } 84 85 static const char *cpu_priv_ver_to_str(int priv_ver) 86 { 87 const char *priv_spec_str = priv_spec_to_str(priv_ver); 88 89 g_assert(priv_spec_str); 90 91 return priv_spec_str; 92 } 93 94 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 95 const TranslationBlock *tb) 96 { 97 if (!(tb_cflags(tb) & CF_PCREL)) { 98 RISCVCPU *cpu = RISCV_CPU(cs); 99 CPURISCVState *env = &cpu->env; 100 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 101 102 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 103 104 if (xl == MXL_RV32) { 105 env->pc = (int32_t) tb->pc; 106 } else { 107 env->pc = tb->pc; 108 } 109 } 110 } 111 112 static void riscv_restore_state_to_opc(CPUState *cs, 113 const TranslationBlock *tb, 114 const uint64_t *data) 115 { 116 RISCVCPU *cpu = RISCV_CPU(cs); 117 CPURISCVState *env = &cpu->env; 118 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 119 target_ulong pc; 120 121 if (tb_cflags(tb) & CF_PCREL) { 122 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 123 } else { 124 pc = data[0]; 125 } 126 127 if (xl == MXL_RV32) { 128 env->pc = (int32_t)pc; 129 } else { 130 env->pc = pc; 131 } 132 env->bins = data[1]; 133 env->excp_uw2 = data[2]; 134 } 135 136 static const TCGCPUOps riscv_tcg_ops = { 137 .initialize = riscv_translate_init, 138 .translate_code = riscv_translate_code, 139 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 140 .restore_state_to_opc = riscv_restore_state_to_opc, 141 142 #ifndef CONFIG_USER_ONLY 143 .tlb_fill = riscv_cpu_tlb_fill, 144 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 145 .cpu_exec_halt = riscv_cpu_has_work, 146 .do_interrupt = riscv_cpu_do_interrupt, 147 .do_transaction_failed = riscv_cpu_do_transaction_failed, 148 .do_unaligned_access = riscv_cpu_do_unaligned_access, 149 .debug_excp_handler = riscv_cpu_debug_excp_handler, 150 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 151 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 152 #endif /* !CONFIG_USER_ONLY */ 153 }; 154 155 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 156 { 157 const RISCVIsaExtData *edata; 158 159 for (edata = isa_edata_arr; edata && edata->name; edata++) { 160 if (edata->ext_enable_offset != ext_offset) { 161 continue; 162 } 163 164 return edata->min_version; 165 } 166 167 g_assert_not_reached(); 168 } 169 170 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 171 { 172 const RISCVCPUMultiExtConfig *feat; 173 const RISCVIsaExtData *edata; 174 175 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 176 if (edata->ext_enable_offset == ext_offset) { 177 return edata->name; 178 } 179 } 180 181 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 182 if (feat->offset == ext_offset) { 183 return feat->name; 184 } 185 } 186 187 g_assert_not_reached(); 188 } 189 190 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 191 { 192 const RISCVCPUMultiExtConfig *feat; 193 194 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 195 if (feat->offset == ext_offset) { 196 return true; 197 } 198 } 199 200 return false; 201 } 202 203 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 204 { 205 /* 206 * All other named features are already enabled 207 * in riscv_tcg_cpu_instance_init(). 208 */ 209 switch (feat_offset) { 210 case CPU_CFG_OFFSET(ext_zic64b): 211 cpu->cfg.cbom_blocksize = 64; 212 cpu->cfg.cbop_blocksize = 64; 213 cpu->cfg.cboz_blocksize = 64; 214 break; 215 case CPU_CFG_OFFSET(ext_sha): 216 if (!cpu_misa_ext_is_user_set(RVH)) { 217 riscv_cpu_write_misa_bit(cpu, RVH, true); 218 } 219 /* fallthrough */ 220 case CPU_CFG_OFFSET(ext_ssstateen): 221 cpu->cfg.ext_smstateen = true; 222 break; 223 } 224 } 225 226 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 227 uint32_t ext_offset) 228 { 229 int ext_priv_ver; 230 231 if (env->priv_ver == PRIV_VERSION_LATEST) { 232 return; 233 } 234 235 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 236 237 if (env->priv_ver < ext_priv_ver) { 238 /* 239 * Note: the 'priv_spec' command line option, if present, 240 * will take precedence over this priv_ver bump. 241 */ 242 env->priv_ver = ext_priv_ver; 243 } 244 } 245 246 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 247 bool value) 248 { 249 CPURISCVState *env = &cpu->env; 250 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 251 int min_version; 252 253 if (prev_val == value) { 254 return; 255 } 256 257 if (cpu_cfg_ext_is_user_set(ext_offset)) { 258 return; 259 } 260 261 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 262 /* Do not enable it if priv_ver is older than min_version */ 263 min_version = cpu_cfg_ext_get_min_version(ext_offset); 264 if (env->priv_ver < min_version) { 265 return; 266 } 267 } 268 269 isa_ext_update_enabled(cpu, ext_offset, value); 270 } 271 272 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 273 { 274 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 275 error_setg(errp, "H extension requires priv spec 1.12.0"); 276 return; 277 } 278 } 279 280 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 281 Error **errp) 282 { 283 uint32_t vlen = cfg->vlenb << 3; 284 285 if (vlen > RV_VLEN_MAX || vlen < 128) { 286 error_setg(errp, 287 "Vector extension implementation only supports VLEN " 288 "in the range [128, %d]", RV_VLEN_MAX); 289 return; 290 } 291 292 if (cfg->elen > 64 || cfg->elen < 8) { 293 error_setg(errp, 294 "Vector extension implementation only supports ELEN " 295 "in the range [8, 64]"); 296 return; 297 } 298 } 299 300 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 301 { 302 CPURISCVState *env = &cpu->env; 303 const RISCVIsaExtData *edata; 304 305 /* Force disable extensions if priv spec version does not match */ 306 for (edata = isa_edata_arr; edata && edata->name; edata++) { 307 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 308 (env->priv_ver < edata->min_version)) { 309 /* 310 * These two extensions are always enabled as they were supported 311 * by QEMU before they were added as extensions in the ISA. 312 */ 313 if (!strcmp(edata->name, "zicntr") || 314 !strcmp(edata->name, "zihpm")) { 315 continue; 316 } 317 318 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 319 320 /* 321 * Do not show user warnings for named features that users 322 * can't enable/disable in the command line. See commit 323 * 68c9e54bea for more info. 324 */ 325 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 326 continue; 327 } 328 #ifndef CONFIG_USER_ONLY 329 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 330 " because privilege spec version does not match", 331 edata->name, env->mhartid); 332 #else 333 warn_report("disabling %s extension because " 334 "privilege spec version does not match", 335 edata->name); 336 #endif 337 } 338 } 339 } 340 341 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 342 { 343 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 344 cpu->cfg.has_priv_1_11 = true; 345 } 346 347 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 348 cpu->cfg.has_priv_1_12 = true; 349 } 350 351 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 352 cpu->cfg.has_priv_1_13 = true; 353 } 354 355 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 356 cpu->cfg.cbop_blocksize == 64 && 357 cpu->cfg.cboz_blocksize == 64; 358 359 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 360 361 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 362 cpu->cfg.ext_ssstateen; 363 364 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; 365 } 366 367 static void riscv_cpu_validate_g(RISCVCPU *cpu) 368 { 369 const char *warn_msg = "RVG mandates disabled extension %s"; 370 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 371 bool send_warn = cpu_misa_ext_is_user_set(RVG); 372 373 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 374 uint32_t bit = g_misa_bits[i]; 375 376 if (riscv_has_ext(&cpu->env, bit)) { 377 continue; 378 } 379 380 if (!cpu_misa_ext_is_user_set(bit)) { 381 riscv_cpu_write_misa_bit(cpu, bit, true); 382 continue; 383 } 384 385 if (send_warn) { 386 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 387 } 388 } 389 390 if (!cpu->cfg.ext_zicsr) { 391 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 392 cpu->cfg.ext_zicsr = true; 393 } else if (send_warn) { 394 warn_report(warn_msg, "zicsr"); 395 } 396 } 397 398 if (!cpu->cfg.ext_zifencei) { 399 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 400 cpu->cfg.ext_zifencei = true; 401 } else if (send_warn) { 402 warn_report(warn_msg, "zifencei"); 403 } 404 } 405 } 406 407 static void riscv_cpu_validate_b(RISCVCPU *cpu) 408 { 409 const char *warn_msg = "RVB mandates disabled extension %s"; 410 411 if (!cpu->cfg.ext_zba) { 412 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 413 cpu->cfg.ext_zba = true; 414 } else { 415 warn_report(warn_msg, "zba"); 416 } 417 } 418 419 if (!cpu->cfg.ext_zbb) { 420 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 421 cpu->cfg.ext_zbb = true; 422 } else { 423 warn_report(warn_msg, "zbb"); 424 } 425 } 426 427 if (!cpu->cfg.ext_zbs) { 428 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 429 cpu->cfg.ext_zbs = true; 430 } else { 431 warn_report(warn_msg, "zbs"); 432 } 433 } 434 } 435 436 /* 437 * Check consistency between chosen extensions while setting 438 * cpu->cfg accordingly. 439 */ 440 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 441 { 442 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 443 CPURISCVState *env = &cpu->env; 444 Error *local_err = NULL; 445 446 if (riscv_has_ext(env, RVG)) { 447 riscv_cpu_validate_g(cpu); 448 } 449 450 if (riscv_has_ext(env, RVB)) { 451 riscv_cpu_validate_b(cpu); 452 } 453 454 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 455 error_setg(errp, 456 "I and E extensions are incompatible"); 457 return; 458 } 459 460 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 461 error_setg(errp, 462 "Either I or E extension must be set"); 463 return; 464 } 465 466 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 467 error_setg(errp, 468 "Setting S extension without U extension is illegal"); 469 return; 470 } 471 472 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 473 error_setg(errp, 474 "H depends on an I base integer ISA with 32 x registers"); 475 return; 476 } 477 478 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 479 error_setg(errp, "H extension implicitly requires S-mode"); 480 return; 481 } 482 483 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 484 error_setg(errp, "F extension requires Zicsr"); 485 return; 486 } 487 488 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 489 error_setg(errp, "Zacas extension requires A extension"); 490 return; 491 } 492 493 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 494 error_setg(errp, "Zawrs extension requires A extension"); 495 return; 496 } 497 498 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 499 error_setg(errp, "Zfa extension requires F extension"); 500 return; 501 } 502 503 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 504 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 505 return; 506 } 507 508 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 509 error_setg(errp, "Zfbfmin extension depends on F extension"); 510 return; 511 } 512 513 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 514 error_setg(errp, "D extension requires F extension"); 515 return; 516 } 517 518 if (riscv_has_ext(env, RVV)) { 519 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 520 if (local_err != NULL) { 521 error_propagate(errp, local_err); 522 return; 523 } 524 } 525 526 /* The Zve64d extension depends on the Zve64f extension */ 527 if (cpu->cfg.ext_zve64d) { 528 if (!riscv_has_ext(env, RVD)) { 529 error_setg(errp, "Zve64d/V extensions require D extension"); 530 return; 531 } 532 } 533 534 /* The Zve32f extension depends on the Zve32x extension */ 535 if (cpu->cfg.ext_zve32f) { 536 if (!riscv_has_ext(env, RVF)) { 537 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 538 return; 539 } 540 } 541 542 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 543 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 544 return; 545 } 546 547 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 548 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 549 return; 550 } 551 552 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 553 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 554 return; 555 } 556 557 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 558 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 559 return; 560 } 561 562 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 563 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 564 return; 565 } 566 567 if (cpu->cfg.ext_zfinx) { 568 if (!cpu->cfg.ext_zicsr) { 569 error_setg(errp, "Zfinx extension requires Zicsr"); 570 return; 571 } 572 if (riscv_has_ext(env, RVF)) { 573 error_setg(errp, 574 "Zfinx cannot be supported together with F extension"); 575 return; 576 } 577 } 578 579 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 580 error_setg(errp, "Zcmop extensions require Zca"); 581 return; 582 } 583 584 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 585 error_setg(errp, "Zcf extension is only relevant to RV32"); 586 return; 587 } 588 589 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 590 error_setg(errp, "Zcf extension requires F extension"); 591 return; 592 } 593 594 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 595 error_setg(errp, "Zcd extension requires D extension"); 596 return; 597 } 598 599 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 600 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 601 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 602 "extension"); 603 return; 604 } 605 606 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 607 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 608 "Zcd extension"); 609 return; 610 } 611 612 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 613 error_setg(errp, "Zcmt extension requires Zicsr extension"); 614 return; 615 } 616 617 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 618 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 619 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 620 error_setg(errp, 621 "Vector crypto extensions require V or Zve* extensions"); 622 return; 623 } 624 625 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 626 error_setg( 627 errp, 628 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 629 return; 630 } 631 632 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 633 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 634 error_setg(errp, "zicntr requires zicsr"); 635 return; 636 } 637 cpu->cfg.ext_zicntr = false; 638 } 639 640 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 641 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 642 error_setg(errp, "zihpm requires zicsr"); 643 return; 644 } 645 cpu->cfg.ext_zihpm = false; 646 } 647 648 if (cpu->cfg.ext_zicfiss) { 649 if (!cpu->cfg.ext_zicsr) { 650 error_setg(errp, "zicfiss extension requires zicsr extension"); 651 return; 652 } 653 if (!riscv_has_ext(env, RVA)) { 654 error_setg(errp, "zicfiss extension requires A extension"); 655 return; 656 } 657 if (!riscv_has_ext(env, RVS)) { 658 error_setg(errp, "zicfiss extension requires S"); 659 return; 660 } 661 if (!cpu->cfg.ext_zimop) { 662 error_setg(errp, "zicfiss extension requires zimop extension"); 663 return; 664 } 665 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 666 error_setg(errp, "zicfiss with zca requires zcmop extension"); 667 return; 668 } 669 } 670 671 if (!cpu->cfg.ext_zihpm) { 672 cpu->cfg.pmu_mask = 0; 673 cpu->pmu_avail_ctrs = 0; 674 } 675 676 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 677 error_setg(errp, "zicfilp extension requires zicsr extension"); 678 return; 679 } 680 681 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 682 error_setg(errp, "svukte is not supported for RV32"); 683 return; 684 } 685 686 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && 687 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { 688 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || 689 cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { 690 error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"); 691 return; 692 } 693 cpu->cfg.ext_smctr = false; 694 cpu->cfg.ext_ssctr = false; 695 } 696 697 /* 698 * Disable isa extensions based on priv spec after we 699 * validated and set everything we need. 700 */ 701 riscv_cpu_disable_priv_spec_isa_exts(cpu); 702 } 703 704 #ifndef CONFIG_USER_ONLY 705 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 706 RISCVCPUProfile *profile, 707 bool send_warn) 708 { 709 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 710 711 if (profile->satp_mode > satp_max) { 712 if (send_warn) { 713 bool is_32bit = riscv_cpu_is_32bit(cpu); 714 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 715 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 716 717 warn_report("Profile %s requires satp mode %s, " 718 "but satp mode %s was set", profile->name, 719 req_satp, cur_satp); 720 } 721 722 return false; 723 } 724 725 return true; 726 } 727 #endif 728 729 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, 730 RISCVCPUProfile *profile, 731 RISCVCPUProfile *parent) 732 { 733 const char *parent_name; 734 bool parent_enabled; 735 736 if (!profile->enabled || !parent) { 737 return; 738 } 739 740 parent_name = parent->name; 741 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); 742 profile->enabled = parent_enabled; 743 } 744 745 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 746 RISCVCPUProfile *profile) 747 { 748 CPURISCVState *env = &cpu->env; 749 const char *warn_msg = "Profile %s mandates disabled extension %s"; 750 bool send_warn = profile->user_set && profile->enabled; 751 bool profile_impl = true; 752 int i; 753 754 #ifndef CONFIG_USER_ONLY 755 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 756 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 757 send_warn); 758 } 759 #endif 760 761 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 762 profile->priv_spec > env->priv_ver) { 763 profile_impl = false; 764 765 if (send_warn) { 766 warn_report("Profile %s requires priv spec %s, " 767 "but priv ver %s was set", profile->name, 768 cpu_priv_ver_to_str(profile->priv_spec), 769 cpu_priv_ver_to_str(env->priv_ver)); 770 } 771 } 772 773 for (i = 0; misa_bits[i] != 0; i++) { 774 uint32_t bit = misa_bits[i]; 775 776 if (!(profile->misa_ext & bit)) { 777 continue; 778 } 779 780 if (!riscv_has_ext(&cpu->env, bit)) { 781 profile_impl = false; 782 783 if (send_warn) { 784 warn_report(warn_msg, profile->name, 785 riscv_get_misa_ext_name(bit)); 786 } 787 } 788 } 789 790 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 791 int ext_offset = profile->ext_offsets[i]; 792 793 if (!isa_ext_is_enabled(cpu, ext_offset)) { 794 profile_impl = false; 795 796 if (send_warn) { 797 warn_report(warn_msg, profile->name, 798 cpu_cfg_ext_get_name(ext_offset)); 799 } 800 } 801 } 802 803 profile->enabled = profile_impl; 804 805 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); 806 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); 807 } 808 809 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 810 { 811 for (int i = 0; riscv_profiles[i] != NULL; i++) { 812 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 813 } 814 } 815 816 static void riscv_cpu_init_implied_exts_rules(void) 817 { 818 RISCVCPUImpliedExtsRule *rule; 819 #ifndef CONFIG_USER_ONLY 820 MachineState *ms = MACHINE(qdev_get_machine()); 821 #endif 822 static bool initialized; 823 int i; 824 825 /* Implied rules only need to be initialized once. */ 826 if (initialized) { 827 return; 828 } 829 830 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 831 #ifndef CONFIG_USER_ONLY 832 rule->enabled = bitmap_new(ms->smp.cpus); 833 #endif 834 g_hash_table_insert(misa_ext_implied_rules, 835 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 836 } 837 838 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 839 #ifndef CONFIG_USER_ONLY 840 rule->enabled = bitmap_new(ms->smp.cpus); 841 #endif 842 g_hash_table_insert(multi_ext_implied_rules, 843 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 844 } 845 846 initialized = true; 847 } 848 849 static void cpu_enable_implied_rule(RISCVCPU *cpu, 850 RISCVCPUImpliedExtsRule *rule) 851 { 852 CPURISCVState *env = &cpu->env; 853 RISCVCPUImpliedExtsRule *ir; 854 bool enabled = false; 855 int i; 856 857 #ifndef CONFIG_USER_ONLY 858 enabled = test_bit(cpu->env.mhartid, rule->enabled); 859 #endif 860 861 if (!enabled) { 862 /* Enable the implied MISAs. */ 863 if (rule->implied_misa_exts) { 864 for (i = 0; misa_bits[i] != 0; i++) { 865 if (rule->implied_misa_exts & misa_bits[i]) { 866 /* 867 * If the user disabled the misa_bit do not re-enable it 868 * and do not apply any implied rules related to it. 869 */ 870 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 871 !(env->misa_ext & misa_bits[i])) { 872 continue; 873 } 874 875 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 876 ir = g_hash_table_lookup(misa_ext_implied_rules, 877 GUINT_TO_POINTER(misa_bits[i])); 878 879 if (ir) { 880 cpu_enable_implied_rule(cpu, ir); 881 } 882 } 883 } 884 } 885 886 /* Enable the implied extensions. */ 887 for (i = 0; 888 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 889 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 890 891 ir = g_hash_table_lookup(multi_ext_implied_rules, 892 GUINT_TO_POINTER( 893 rule->implied_multi_exts[i])); 894 895 if (ir) { 896 cpu_enable_implied_rule(cpu, ir); 897 } 898 } 899 900 #ifndef CONFIG_USER_ONLY 901 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 902 #endif 903 } 904 } 905 906 /* Zc extension has special implied rules that need to be handled separately. */ 907 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 908 { 909 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 910 CPURISCVState *env = &cpu->env; 911 912 if (cpu->cfg.ext_zce) { 913 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 914 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 915 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 916 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 917 918 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 919 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 920 } 921 } 922 923 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 924 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 925 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 926 927 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 928 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 929 } 930 931 if (riscv_has_ext(env, RVD)) { 932 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 933 } 934 } 935 } 936 937 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 938 { 939 RISCVCPUImpliedExtsRule *rule; 940 int i; 941 942 /* Enable the implied extensions for Zc. */ 943 cpu_enable_zc_implied_rules(cpu); 944 945 /* Enable the implied MISAs. */ 946 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 947 if (riscv_has_ext(&cpu->env, rule->ext)) { 948 cpu_enable_implied_rule(cpu, rule); 949 } 950 } 951 952 /* Enable the implied extensions. */ 953 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 954 if (isa_ext_is_enabled(cpu, rule->ext)) { 955 cpu_enable_implied_rule(cpu, rule); 956 } 957 } 958 } 959 960 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 961 { 962 CPURISCVState *env = &cpu->env; 963 Error *local_err = NULL; 964 965 riscv_cpu_init_implied_exts_rules(); 966 riscv_cpu_enable_implied_rules(cpu); 967 968 riscv_cpu_validate_misa_priv(env, &local_err); 969 if (local_err != NULL) { 970 error_propagate(errp, local_err); 971 return; 972 } 973 974 riscv_cpu_update_named_features(cpu); 975 riscv_cpu_validate_profiles(cpu); 976 977 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 978 /* 979 * Enhanced PMP should only be available 980 * on harts with PMP support 981 */ 982 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 983 return; 984 } 985 986 riscv_cpu_validate_set_extensions(cpu, &local_err); 987 if (local_err != NULL) { 988 error_propagate(errp, local_err); 989 return; 990 } 991 #ifndef CONFIG_USER_ONLY 992 if (cpu->cfg.pmu_mask) { 993 riscv_pmu_init(cpu, &local_err); 994 if (local_err != NULL) { 995 error_propagate(errp, local_err); 996 return; 997 } 998 999 if (cpu->cfg.ext_sscofpmf) { 1000 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1001 riscv_pmu_timer_cb, cpu); 1002 } 1003 } 1004 #endif 1005 } 1006 1007 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 1008 { 1009 GPtrArray *dynamic_decoders; 1010 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 1011 for (size_t i = 0; i < decoder_table_size; ++i) { 1012 if (decoder_table[i].guard_func && 1013 decoder_table[i].guard_func(&cpu->cfg)) { 1014 g_ptr_array_add(dynamic_decoders, 1015 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 1016 } 1017 } 1018 1019 cpu->decoders = dynamic_decoders; 1020 } 1021 1022 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 1023 { 1024 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1025 } 1026 1027 static bool riscv_cpu_is_generic(Object *cpu_obj) 1028 { 1029 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1030 } 1031 1032 /* 1033 * We'll get here via the following path: 1034 * 1035 * riscv_cpu_realize() 1036 * -> cpu_exec_realizefn() 1037 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1038 */ 1039 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1040 { 1041 RISCVCPU *cpu = RISCV_CPU(cs); 1042 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1043 1044 if (!riscv_cpu_tcg_compatible(cpu)) { 1045 g_autofree char *name = riscv_cpu_get_name(cpu); 1046 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1047 name); 1048 return false; 1049 } 1050 1051 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1052 /* Missing 128-bit aligned atomics */ 1053 error_setg(errp, 1054 "128-bit RISC-V currently does not work with Multi " 1055 "Threaded TCG. Please use: -accel tcg,thread=single"); 1056 return false; 1057 } 1058 1059 #ifndef CONFIG_USER_ONLY 1060 CPURISCVState *env = &cpu->env; 1061 1062 tcg_cflags_set(CPU(cs), CF_PCREL); 1063 1064 if (cpu->cfg.ext_sstc) { 1065 riscv_timer_init(cpu); 1066 } 1067 1068 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1069 if (riscv_has_ext(env, RVH)) { 1070 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1071 } 1072 #endif 1073 1074 return true; 1075 } 1076 1077 typedef struct RISCVCPUMisaExtConfig { 1078 target_ulong misa_bit; 1079 bool enabled; 1080 } RISCVCPUMisaExtConfig; 1081 1082 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1083 void *opaque, Error **errp) 1084 { 1085 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1086 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1087 RISCVCPU *cpu = RISCV_CPU(obj); 1088 CPURISCVState *env = &cpu->env; 1089 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1090 bool prev_val, value; 1091 1092 if (!visit_type_bool(v, name, &value, errp)) { 1093 return; 1094 } 1095 1096 cpu_misa_ext_add_user_opt(misa_bit, value); 1097 1098 prev_val = env->misa_ext & misa_bit; 1099 1100 if (value == prev_val) { 1101 return; 1102 } 1103 1104 if (value) { 1105 if (vendor_cpu) { 1106 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1107 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1108 cpuname); 1109 return; 1110 } 1111 1112 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1113 /* 1114 * Note: the 'priv_spec' command line option, if present, 1115 * will take precedence over this priv_ver bump. 1116 */ 1117 env->priv_ver = PRIV_VERSION_1_12_0; 1118 } 1119 } 1120 1121 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1122 } 1123 1124 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1125 void *opaque, Error **errp) 1126 { 1127 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1128 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1129 RISCVCPU *cpu = RISCV_CPU(obj); 1130 CPURISCVState *env = &cpu->env; 1131 bool value; 1132 1133 value = env->misa_ext & misa_bit; 1134 1135 visit_type_bool(v, name, &value, errp); 1136 } 1137 1138 #define MISA_CFG(_bit, _enabled) \ 1139 {.misa_bit = _bit, .enabled = _enabled} 1140 1141 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1142 MISA_CFG(RVA, true), 1143 MISA_CFG(RVC, true), 1144 MISA_CFG(RVD, true), 1145 MISA_CFG(RVF, true), 1146 MISA_CFG(RVI, true), 1147 MISA_CFG(RVE, false), 1148 MISA_CFG(RVM, true), 1149 MISA_CFG(RVS, true), 1150 MISA_CFG(RVU, true), 1151 MISA_CFG(RVH, true), 1152 MISA_CFG(RVV, false), 1153 MISA_CFG(RVG, false), 1154 MISA_CFG(RVB, false), 1155 }; 1156 1157 /* 1158 * We do not support user choice tracking for MISA 1159 * extensions yet because, so far, we do not silently 1160 * change MISA bits during realize() (RVG enables MISA 1161 * bits but the user is warned about it). 1162 */ 1163 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1164 { 1165 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1166 int i; 1167 1168 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1169 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1170 int bit = misa_cfg->misa_bit; 1171 const char *name = riscv_get_misa_ext_name(bit); 1172 const char *desc = riscv_get_misa_ext_description(bit); 1173 1174 /* Check if KVM already created the property */ 1175 if (object_property_find(cpu_obj, name)) { 1176 continue; 1177 } 1178 1179 object_property_add(cpu_obj, name, "bool", 1180 cpu_get_misa_ext_cfg, 1181 cpu_set_misa_ext_cfg, 1182 NULL, (void *)misa_cfg); 1183 object_property_set_description(cpu_obj, name, desc); 1184 if (use_def_vals) { 1185 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1186 misa_cfg->enabled); 1187 } 1188 } 1189 } 1190 1191 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1192 void *opaque, Error **errp) 1193 { 1194 RISCVCPUProfile *profile = opaque; 1195 RISCVCPU *cpu = RISCV_CPU(obj); 1196 bool value; 1197 int i, ext_offset; 1198 1199 if (riscv_cpu_is_vendor(obj)) { 1200 error_setg(errp, "Profile %s is not available for vendor CPUs", 1201 profile->name); 1202 return; 1203 } 1204 1205 if (cpu->env.misa_mxl != MXL_RV64) { 1206 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1207 profile->name); 1208 return; 1209 } 1210 1211 if (!visit_type_bool(v, name, &value, errp)) { 1212 return; 1213 } 1214 1215 profile->user_set = true; 1216 profile->enabled = value; 1217 1218 if (profile->u_parent != NULL) { 1219 object_property_set_bool(obj, profile->u_parent->name, 1220 profile->enabled, NULL); 1221 } 1222 1223 if (profile->s_parent != NULL) { 1224 object_property_set_bool(obj, profile->s_parent->name, 1225 profile->enabled, NULL); 1226 } 1227 1228 if (profile->enabled) { 1229 cpu->env.priv_ver = profile->priv_spec; 1230 } 1231 1232 #ifndef CONFIG_USER_ONLY 1233 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1234 object_property_set_bool(obj, "mmu", true, NULL); 1235 const char *satp_prop = satp_mode_str(profile->satp_mode, 1236 riscv_cpu_is_32bit(cpu)); 1237 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1238 } 1239 #endif 1240 1241 for (i = 0; misa_bits[i] != 0; i++) { 1242 uint32_t bit = misa_bits[i]; 1243 1244 if (!(profile->misa_ext & bit)) { 1245 continue; 1246 } 1247 1248 if (bit == RVI && !profile->enabled) { 1249 /* 1250 * Disabling profiles will not disable the base 1251 * ISA RV64I. 1252 */ 1253 continue; 1254 } 1255 1256 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1257 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1258 } 1259 1260 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1261 ext_offset = profile->ext_offsets[i]; 1262 1263 if (profile->enabled) { 1264 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1265 riscv_cpu_enable_named_feat(cpu, ext_offset); 1266 } 1267 1268 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1269 } 1270 1271 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1272 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1273 } 1274 } 1275 1276 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1277 void *opaque, Error **errp) 1278 { 1279 RISCVCPUProfile *profile = opaque; 1280 bool value = profile->enabled; 1281 1282 visit_type_bool(v, name, &value, errp); 1283 } 1284 1285 static void riscv_cpu_add_profiles(Object *cpu_obj) 1286 { 1287 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1288 const RISCVCPUProfile *profile = riscv_profiles[i]; 1289 1290 object_property_add(cpu_obj, profile->name, "bool", 1291 cpu_get_profile, cpu_set_profile, 1292 NULL, (void *)profile); 1293 1294 /* 1295 * CPUs might enable a profile right from the start. 1296 * Enable its mandatory extensions right away in this 1297 * case. 1298 */ 1299 if (profile->enabled) { 1300 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1301 } 1302 } 1303 } 1304 1305 static bool cpu_ext_is_deprecated(const char *ext_name) 1306 { 1307 return isupper(ext_name[0]); 1308 } 1309 1310 /* 1311 * String will be allocated in the heap. Caller is responsible 1312 * for freeing it. 1313 */ 1314 static char *cpu_ext_to_lower(const char *ext_name) 1315 { 1316 char *ret = g_malloc0(strlen(ext_name) + 1); 1317 1318 strcpy(ret, ext_name); 1319 ret[0] = tolower(ret[0]); 1320 1321 return ret; 1322 } 1323 1324 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1325 void *opaque, Error **errp) 1326 { 1327 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1328 RISCVCPU *cpu = RISCV_CPU(obj); 1329 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1330 bool prev_val, value; 1331 1332 if (!visit_type_bool(v, name, &value, errp)) { 1333 return; 1334 } 1335 1336 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1337 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1338 1339 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1340 multi_ext_cfg->name, lower); 1341 } 1342 1343 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1344 1345 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1346 1347 if (value == prev_val) { 1348 return; 1349 } 1350 1351 if (value && vendor_cpu) { 1352 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1353 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1354 cpuname); 1355 return; 1356 } 1357 1358 if (value) { 1359 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1360 } 1361 1362 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1363 } 1364 1365 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1366 void *opaque, Error **errp) 1367 { 1368 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1369 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1370 1371 visit_type_bool(v, name, &value, errp); 1372 } 1373 1374 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1375 const RISCVCPUMultiExtConfig *multi_cfg) 1376 { 1377 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1378 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1379 1380 object_property_add(cpu_obj, multi_cfg->name, "bool", 1381 cpu_get_multi_ext_cfg, 1382 cpu_set_multi_ext_cfg, 1383 NULL, (void *)multi_cfg); 1384 1385 if (!generic_cpu || deprecated_ext) { 1386 return; 1387 } 1388 1389 /* 1390 * Set def val directly instead of using 1391 * object_property_set_bool() to save the set() 1392 * callback hash for user inputs. 1393 */ 1394 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1395 multi_cfg->enabled); 1396 } 1397 1398 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1399 const RISCVCPUMultiExtConfig *array) 1400 { 1401 const RISCVCPUMultiExtConfig *prop; 1402 1403 g_assert(array); 1404 1405 for (prop = array; prop && prop->name; prop++) { 1406 cpu_add_multi_ext_prop(obj, prop); 1407 } 1408 } 1409 1410 /* 1411 * Add CPU properties with user-facing flags. 1412 * 1413 * This will overwrite existing env->misa_ext values with the 1414 * defaults set via riscv_cpu_add_misa_properties(). 1415 */ 1416 static void riscv_cpu_add_user_properties(Object *obj) 1417 { 1418 #ifndef CONFIG_USER_ONLY 1419 riscv_add_satp_mode_properties(obj); 1420 #endif 1421 1422 riscv_cpu_add_misa_properties(obj); 1423 1424 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1425 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1426 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1427 1428 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1429 1430 riscv_cpu_add_profiles(obj); 1431 } 1432 1433 /* 1434 * The 'max' type CPU will have all possible ratified 1435 * non-vendor extensions enabled. 1436 */ 1437 static void riscv_init_max_cpu_extensions(Object *obj) 1438 { 1439 RISCVCPU *cpu = RISCV_CPU(obj); 1440 CPURISCVState *env = &cpu->env; 1441 const RISCVCPUMultiExtConfig *prop; 1442 1443 /* Enable RVG and RVV that are disabled by default */ 1444 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1445 1446 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1447 isa_ext_update_enabled(cpu, prop->offset, true); 1448 } 1449 1450 /* 1451 * Some extensions can't be added without backward compatibilty concerns. 1452 * Disable those, the user can still opt in to them on the command line. 1453 */ 1454 cpu->cfg.ext_svade = false; 1455 1456 /* set vector version */ 1457 env->vext_ver = VEXT_VERSION_1_00_0; 1458 1459 /* Zfinx is not compatible with F. Disable it */ 1460 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1461 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1462 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1463 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1464 1465 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1466 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1467 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1468 1469 if (env->misa_mxl != MXL_RV32) { 1470 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1471 } 1472 1473 /* 1474 * TODO: ext_smrnmi requires OpenSBI changes that our current 1475 * image does not have. Disable it for now. 1476 */ 1477 if (cpu->cfg.ext_smrnmi) { 1478 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1479 } 1480 1481 /* 1482 * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup 1483 * to avoid generating a double trap. OpenSBI does not currently support it, 1484 * disable it for now. 1485 */ 1486 if (cpu->cfg.ext_smdbltrp) { 1487 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1488 } 1489 } 1490 1491 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1492 { 1493 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1494 } 1495 1496 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1497 { 1498 RISCVCPU *cpu = RISCV_CPU(cs); 1499 Object *obj = OBJECT(cpu); 1500 1501 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1502 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1503 1504 if (!misa_ext_implied_rules) { 1505 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1506 } 1507 1508 if (!multi_ext_implied_rules) { 1509 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1510 } 1511 1512 riscv_cpu_add_user_properties(obj); 1513 1514 if (riscv_cpu_has_max_extensions(obj)) { 1515 riscv_init_max_cpu_extensions(obj); 1516 } 1517 } 1518 1519 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1520 { 1521 /* 1522 * All cpus use the same set of operations. 1523 */ 1524 cc->tcg_ops = &riscv_tcg_ops; 1525 } 1526 1527 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1528 { 1529 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1530 } 1531 1532 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1533 { 1534 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1535 1536 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1537 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1538 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1539 } 1540 1541 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1542 .name = ACCEL_CPU_NAME("tcg"), 1543 1544 .parent = TYPE_ACCEL_CPU, 1545 .class_init = riscv_tcg_cpu_accel_class_init, 1546 .abstract = true, 1547 }; 1548 1549 static void riscv_tcg_cpu_accel_register_types(void) 1550 { 1551 type_register_static(&riscv_tcg_cpu_accel_type_info); 1552 } 1553 type_init(riscv_tcg_cpu_accel_register_types); 1554