xref: /qemu/target/riscv/pmu.h (revision 14664483457b21235be42fbfb534e5ea881508b8)
13780e337SAtish Patra /*
23780e337SAtish Patra  * RISC-V PMU header file.
33780e337SAtish Patra  *
43780e337SAtish Patra  * Copyright (c) 2021 Western Digital Corporation or its affiliates.
53780e337SAtish Patra  *
63780e337SAtish Patra  * This program is free software; you can redistribute it and/or modify it
73780e337SAtish Patra  * under the terms and conditions of the GNU General Public License,
83780e337SAtish Patra  * version 2 or later, as published by the Free Software Foundation.
93780e337SAtish Patra  *
103780e337SAtish Patra  * This program is distributed in the hope it will be useful, but WITHOUT
113780e337SAtish Patra  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
123780e337SAtish Patra  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
133780e337SAtish Patra  * more details.
143780e337SAtish Patra  *
153780e337SAtish Patra  * You should have received a copy of the GNU General Public License along with
163780e337SAtish Patra  * this program.  If not, see <http://www.gnu.org/licenses/>.
173780e337SAtish Patra  */
183780e337SAtish Patra 
193780e337SAtish Patra #include "qemu/osdep.h"
203780e337SAtish Patra #include "qemu/log.h"
213780e337SAtish Patra #include "cpu.h"
223780e337SAtish Patra #include "qemu/main-loop.h"
233780e337SAtish Patra #include "exec/exec-all.h"
243780e337SAtish Patra 
253780e337SAtish Patra bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
263780e337SAtish Patra                                         uint32_t target_ctr);
273780e337SAtish Patra bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
283780e337SAtish Patra                                   uint32_t target_ctr);
29*14664483SAtish Patra void riscv_pmu_timer_cb(void *priv);
30*14664483SAtish Patra int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
31*14664483SAtish Patra int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
32*14664483SAtish Patra                                uint32_t ctr_idx);
33*14664483SAtish Patra int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
34*14664483SAtish Patra int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
35*14664483SAtish Patra                           uint32_t ctr_idx);
36