xref: /qemu/target/riscv/op_helper.c (revision 3b472e71d50fe33f2e0dfdd447dde5910ddf0761) 
1  /*
2   * RISC-V Emulation Helpers for QEMU.
3   *
4   * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5   * Copyright (c) 2017-2018 SiFive, Inc.
6   *
7   * This program is free software; you can redistribute it and/or modify it
8   * under the terms and conditions of the GNU General Public License,
9   * version 2 or later, as published by the Free Software Foundation.
10   *
11   * This program is distributed in the hope it will be useful, but WITHOUT
12   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13   * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14   * more details.
15   *
16   * You should have received a copy of the GNU General Public License along with
17   * this program.  If not, see <http://www.gnu.org/licenses/>.
18   */
19  
20  #include "qemu/osdep.h"
21  #include "qemu/log.h"
22  #include "cpu.h"
23  #include "qemu/main-loop.h"
24  #include "exec/exec-all.h"
25  #include "exec/helper-proto.h"
26  
27  /* Exceptions processing helpers */
28  void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
29                                            uint32_t exception, uintptr_t pc)
30  {
31      CPUState *cs = env_cpu(env);
32      cs->exception_index = exception;
33      cpu_loop_exit_restore(cs, pc);
34  }
35  
36  void helper_raise_exception(CPURISCVState *env, uint32_t exception)
37  {
38      riscv_raise_exception(env, exception, 0);
39  }
40  
41  target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
42          target_ulong csr)
43  {
44      target_ulong val = 0;
45      int ret = riscv_csrrw(env, csr, &val, src, -1);
46  
47      if (ret < 0) {
48          riscv_raise_exception(env, -ret, GETPC());
49      }
50      return val;
51  }
52  
53  target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
54          target_ulong csr, target_ulong rs1_pass)
55  {
56      target_ulong val = 0;
57      int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
58  
59      if (ret < 0) {
60          riscv_raise_exception(env, -ret, GETPC());
61      }
62      return val;
63  }
64  
65  target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
66          target_ulong csr, target_ulong rs1_pass)
67  {
68      target_ulong val = 0;
69      int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
70  
71      if (ret < 0) {
72          riscv_raise_exception(env, -ret, GETPC());
73      }
74      return val;
75  }
76  
77  #ifndef CONFIG_USER_ONLY
78  
79  target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
80  {
81      uint64_t mstatus;
82      target_ulong prev_priv, prev_virt;
83  
84      if (!(env->priv >= PRV_S)) {
85          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
86      }
87  
88      target_ulong retpc = env->sepc;
89      if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
90          riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
91      }
92  
93      if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
94          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
95      }
96  
97      if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
98          get_field(env->hstatus, HSTATUS_VTSR)) {
99          riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
100      }
101  
102      mstatus = env->mstatus;
103  
104      if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
105          /* We support Hypervisor extensions and virtulisation is disabled */
106          target_ulong hstatus = env->hstatus;
107  
108          prev_priv = get_field(mstatus, MSTATUS_SPP);
109          prev_virt = get_field(hstatus, HSTATUS_SPV);
110  
111          hstatus = set_field(hstatus, HSTATUS_SPV, 0);
112          mstatus = set_field(mstatus, MSTATUS_SPP, 0);
113          mstatus = set_field(mstatus, SSTATUS_SIE,
114                              get_field(mstatus, SSTATUS_SPIE));
115          mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
116  
117          env->mstatus = mstatus;
118          env->hstatus = hstatus;
119  
120          if (prev_virt) {
121              riscv_cpu_swap_hypervisor_regs(env);
122          }
123  
124          riscv_cpu_set_virt_enabled(env, prev_virt);
125      } else {
126          prev_priv = get_field(mstatus, MSTATUS_SPP);
127  
128          mstatus = set_field(mstatus, MSTATUS_SIE,
129                              get_field(mstatus, MSTATUS_SPIE));
130          mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
131          mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
132          env->mstatus = mstatus;
133      }
134  
135      riscv_cpu_set_mode(env, prev_priv);
136  
137      return retpc;
138  }
139  
140  target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
141  {
142      if (!(env->priv >= PRV_M)) {
143          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
144      }
145  
146      target_ulong retpc = env->mepc;
147      if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
148          riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
149      }
150  
151      uint64_t mstatus = env->mstatus;
152      target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
153  
154      if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
155          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
156      }
157  
158      target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
159      mstatus = set_field(mstatus, MSTATUS_MIE,
160                          get_field(mstatus, MSTATUS_MPIE));
161      mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
162      mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
163      mstatus = set_field(mstatus, MSTATUS_MPV, 0);
164      env->mstatus = mstatus;
165      riscv_cpu_set_mode(env, prev_priv);
166  
167      if (riscv_has_ext(env, RVH)) {
168          if (prev_virt) {
169              riscv_cpu_swap_hypervisor_regs(env);
170          }
171  
172          riscv_cpu_set_virt_enabled(env, prev_virt);
173      }
174  
175      return retpc;
176  }
177  
178  void helper_wfi(CPURISCVState *env)
179  {
180      CPUState *cs = env_cpu(env);
181  
182      if ((env->priv == PRV_S &&
183          get_field(env->mstatus, MSTATUS_TW)) ||
184          riscv_cpu_virt_enabled(env)) {
185          riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
186      } else {
187          cs->halted = 1;
188          cs->exception_index = EXCP_HLT;
189          cpu_loop_exit(cs);
190      }
191  }
192  
193  void helper_tlb_flush(CPURISCVState *env)
194  {
195      CPUState *cs = env_cpu(env);
196      if (!(env->priv >= PRV_S) ||
197          (env->priv == PRV_S &&
198           get_field(env->mstatus, MSTATUS_TVM))) {
199          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
200      } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
201                 get_field(env->hstatus, HSTATUS_VTVM)) {
202          riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
203      } else {
204          tlb_flush(cs);
205      }
206  }
207  
208  void helper_hyp_tlb_flush(CPURISCVState *env)
209  {
210      CPUState *cs = env_cpu(env);
211  
212      if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
213          riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
214      }
215  
216      if (env->priv == PRV_M ||
217          (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
218          tlb_flush(cs);
219          return;
220      }
221  
222      riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
223  }
224  
225  void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
226  {
227      if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
228          get_field(env->mstatus, MSTATUS_TVM)) {
229          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
230      }
231  
232      helper_hyp_tlb_flush(env);
233  }
234  
235  target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
236  {
237      int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
238  
239      return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
240  }
241  
242  target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
243  {
244      int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
245  
246      return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
247  }
248  
249  #endif /* !CONFIG_USER_ONLY */
250