1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 76 { 77 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 78 } 79 80 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 81 { 82 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 83 } 84 85 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 86 KVM_REG_RISCV_CORE_REG(name)) 87 88 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 89 KVM_REG_RISCV_CSR_REG(name)) 90 91 #define RISCV_CONFIG_REG(env, name) \ 92 kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \ 93 KVM_REG_RISCV_CONFIG_REG(name)) 94 95 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 96 KVM_REG_RISCV_TIMER_REG(name)) 97 98 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 99 100 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 101 102 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 103 do { \ 104 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 105 if (_ret) { \ 106 return _ret; \ 107 } \ 108 } while (0) 109 110 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 111 do { \ 112 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 113 if (_ret) { \ 114 return _ret; \ 115 } \ 116 } while (0) 117 118 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 119 do { \ 120 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 121 if (ret) { \ 122 abort(); \ 123 } \ 124 } while (0) 125 126 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 127 do { \ 128 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 129 if (ret) { \ 130 abort(); \ 131 } \ 132 } while (0) 133 134 typedef struct KVMCPUConfig { 135 const char *name; 136 const char *description; 137 target_ulong offset; 138 int kvm_reg_id; 139 bool user_set; 140 bool supported; 141 } KVMCPUConfig; 142 143 #define KVM_MISA_CFG(_bit, _reg_id) \ 144 {.offset = _bit, .kvm_reg_id = _reg_id} 145 146 /* KVM ISA extensions */ 147 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 148 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 149 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 150 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 151 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 152 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 153 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 154 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 155 }; 156 157 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 158 const char *name, 159 void *opaque, Error **errp) 160 { 161 KVMCPUConfig *misa_ext_cfg = opaque; 162 target_ulong misa_bit = misa_ext_cfg->offset; 163 RISCVCPU *cpu = RISCV_CPU(obj); 164 CPURISCVState *env = &cpu->env; 165 bool value = env->misa_ext_mask & misa_bit; 166 167 visit_type_bool(v, name, &value, errp); 168 } 169 170 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 171 const char *name, 172 void *opaque, Error **errp) 173 { 174 KVMCPUConfig *misa_ext_cfg = opaque; 175 target_ulong misa_bit = misa_ext_cfg->offset; 176 RISCVCPU *cpu = RISCV_CPU(obj); 177 CPURISCVState *env = &cpu->env; 178 bool value, host_bit; 179 180 if (!visit_type_bool(v, name, &value, errp)) { 181 return; 182 } 183 184 host_bit = env->misa_ext_mask & misa_bit; 185 186 if (value == host_bit) { 187 return; 188 } 189 190 if (!value) { 191 misa_ext_cfg->user_set = true; 192 return; 193 } 194 195 /* 196 * Forbid users to enable extensions that aren't 197 * available in the hart. 198 */ 199 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 200 "enabled in the host", misa_ext_cfg->name); 201 } 202 203 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 204 { 205 CPURISCVState *env = &cpu->env; 206 uint64_t id, reg; 207 int i, ret; 208 209 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 210 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 211 target_ulong misa_bit = misa_cfg->offset; 212 213 if (!misa_cfg->user_set) { 214 continue; 215 } 216 217 /* If we're here we're going to disable the MISA bit */ 218 reg = 0; 219 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 220 misa_cfg->kvm_reg_id); 221 ret = kvm_set_one_reg(cs, id, ®); 222 if (ret != 0) { 223 /* 224 * We're not checking for -EINVAL because if the bit is about 225 * to be disabled, it means that it was already enabled by 226 * KVM. We determined that by fetching the 'isa' register 227 * during init() time. Any error at this point is worth 228 * aborting. 229 */ 230 error_report("Unable to set KVM reg %s, error %d", 231 misa_cfg->name, ret); 232 exit(EXIT_FAILURE); 233 } 234 env->misa_ext &= ~misa_bit; 235 } 236 } 237 238 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 239 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 240 .kvm_reg_id = _reg_id} 241 242 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 243 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 244 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 245 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 246 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 247 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 248 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 249 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 250 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 251 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 252 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 253 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 254 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 255 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 256 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 257 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 258 }; 259 260 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 261 { 262 return (void *)&cpu->cfg + kvmcfg->offset; 263 } 264 265 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 266 uint32_t val) 267 { 268 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 269 270 *ext_enabled = val; 271 } 272 273 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 274 KVMCPUConfig *multi_ext) 275 { 276 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 277 278 return *ext_enabled; 279 } 280 281 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 282 const char *name, 283 void *opaque, Error **errp) 284 { 285 KVMCPUConfig *multi_ext_cfg = opaque; 286 RISCVCPU *cpu = RISCV_CPU(obj); 287 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 288 289 visit_type_bool(v, name, &value, errp); 290 } 291 292 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 293 const char *name, 294 void *opaque, Error **errp) 295 { 296 KVMCPUConfig *multi_ext_cfg = opaque; 297 RISCVCPU *cpu = RISCV_CPU(obj); 298 bool value, host_val; 299 300 if (!visit_type_bool(v, name, &value, errp)) { 301 return; 302 } 303 304 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 305 306 /* 307 * Ignore if the user is setting the same value 308 * as the host. 309 */ 310 if (value == host_val) { 311 return; 312 } 313 314 if (!multi_ext_cfg->supported) { 315 /* 316 * Error out if the user is trying to enable an 317 * extension that KVM doesn't support. Ignore 318 * option otherwise. 319 */ 320 if (value) { 321 error_setg(errp, "KVM does not support disabling extension %s", 322 multi_ext_cfg->name); 323 } 324 325 return; 326 } 327 328 multi_ext_cfg->user_set = true; 329 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 330 } 331 332 static KVMCPUConfig kvm_cbom_blocksize = { 333 .name = "cbom_blocksize", 334 .offset = CPU_CFG_OFFSET(cbom_blocksize), 335 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 336 }; 337 338 static KVMCPUConfig kvm_cboz_blocksize = { 339 .name = "cboz_blocksize", 340 .offset = CPU_CFG_OFFSET(cboz_blocksize), 341 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 342 }; 343 344 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 345 const char *name, 346 void *opaque, Error **errp) 347 { 348 KVMCPUConfig *cbomz_cfg = opaque; 349 RISCVCPU *cpu = RISCV_CPU(obj); 350 uint16_t value, *host_val; 351 352 if (!visit_type_uint16(v, name, &value, errp)) { 353 return; 354 } 355 356 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 357 358 if (value != *host_val) { 359 error_report("Unable to set %s to a different value than " 360 "the host (%u)", 361 cbomz_cfg->name, *host_val); 362 exit(EXIT_FAILURE); 363 } 364 365 cbomz_cfg->user_set = true; 366 } 367 368 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 369 { 370 CPURISCVState *env = &cpu->env; 371 uint64_t id, reg; 372 int i, ret; 373 374 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 375 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 376 377 if (!multi_ext_cfg->user_set) { 378 continue; 379 } 380 381 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 382 multi_ext_cfg->kvm_reg_id); 383 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 384 ret = kvm_set_one_reg(cs, id, ®); 385 if (ret != 0) { 386 error_report("Unable to %s extension %s in KVM, error %d", 387 reg ? "enable" : "disable", 388 multi_ext_cfg->name, ret); 389 exit(EXIT_FAILURE); 390 } 391 } 392 } 393 394 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 395 const char *name, 396 void *opaque, Error **errp) 397 { 398 bool value = false; 399 400 visit_type_bool(v, name, &value, errp); 401 } 402 403 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 404 const char *name, 405 void *opaque, Error **errp) 406 { 407 const char *propname = opaque; 408 bool value; 409 410 if (!visit_type_bool(v, name, &value, errp)) { 411 return; 412 } 413 414 if (value) { 415 error_setg(errp, "extension %s is not available with KVM", 416 propname); 417 } 418 } 419 420 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 421 { 422 /* Check if KVM created the property already */ 423 if (object_property_find(obj, prop_name)) { 424 return; 425 } 426 427 /* 428 * Set the default to disabled for every extension 429 * unknown to KVM and error out if the user attempts 430 * to enable any of them. 431 */ 432 object_property_add(obj, prop_name, "bool", 433 cpu_get_cfg_unavailable, 434 cpu_set_cfg_unavailable, 435 NULL, (void *)prop_name); 436 } 437 438 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 439 const RISCVCPUMultiExtConfig *array) 440 { 441 const RISCVCPUMultiExtConfig *prop; 442 443 g_assert(array); 444 445 for (prop = array; prop && prop->name; prop++) { 446 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 447 } 448 } 449 450 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 451 { 452 int i; 453 454 riscv_add_satp_mode_properties(cpu_obj); 455 456 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 457 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 458 int bit = misa_cfg->offset; 459 460 misa_cfg->name = riscv_get_misa_ext_name(bit); 461 misa_cfg->description = riscv_get_misa_ext_description(bit); 462 463 object_property_add(cpu_obj, misa_cfg->name, "bool", 464 kvm_cpu_get_misa_ext_cfg, 465 kvm_cpu_set_misa_ext_cfg, 466 NULL, misa_cfg); 467 object_property_set_description(cpu_obj, misa_cfg->name, 468 misa_cfg->description); 469 } 470 471 for (i = 0; misa_bits[i] != 0; i++) { 472 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 473 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 474 } 475 476 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 477 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 478 479 object_property_add(cpu_obj, multi_cfg->name, "bool", 480 kvm_cpu_get_multi_ext_cfg, 481 kvm_cpu_set_multi_ext_cfg, 482 NULL, multi_cfg); 483 } 484 485 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 486 NULL, kvm_cpu_set_cbomz_blksize, 487 NULL, &kvm_cbom_blocksize); 488 489 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 490 NULL, kvm_cpu_set_cbomz_blksize, 491 NULL, &kvm_cboz_blocksize); 492 493 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 494 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 495 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 496 } 497 498 static int kvm_riscv_get_regs_core(CPUState *cs) 499 { 500 int ret = 0; 501 int i; 502 target_ulong reg; 503 CPURISCVState *env = &RISCV_CPU(cs)->env; 504 505 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 506 if (ret) { 507 return ret; 508 } 509 env->pc = reg; 510 511 for (i = 1; i < 32; i++) { 512 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 513 ret = kvm_get_one_reg(cs, id, ®); 514 if (ret) { 515 return ret; 516 } 517 env->gpr[i] = reg; 518 } 519 520 return ret; 521 } 522 523 static int kvm_riscv_put_regs_core(CPUState *cs) 524 { 525 int ret = 0; 526 int i; 527 target_ulong reg; 528 CPURISCVState *env = &RISCV_CPU(cs)->env; 529 530 reg = env->pc; 531 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 532 if (ret) { 533 return ret; 534 } 535 536 for (i = 1; i < 32; i++) { 537 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 538 reg = env->gpr[i]; 539 ret = kvm_set_one_reg(cs, id, ®); 540 if (ret) { 541 return ret; 542 } 543 } 544 545 return ret; 546 } 547 548 static int kvm_riscv_get_regs_csr(CPUState *cs) 549 { 550 CPURISCVState *env = &RISCV_CPU(cs)->env; 551 552 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 553 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 554 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 555 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 556 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 557 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 558 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 559 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 560 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 561 562 return 0; 563 } 564 565 static int kvm_riscv_put_regs_csr(CPUState *cs) 566 { 567 CPURISCVState *env = &RISCV_CPU(cs)->env; 568 569 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 570 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 571 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 572 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 573 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 574 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 575 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 576 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 577 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 578 579 return 0; 580 } 581 582 static int kvm_riscv_get_regs_fp(CPUState *cs) 583 { 584 int ret = 0; 585 int i; 586 CPURISCVState *env = &RISCV_CPU(cs)->env; 587 588 if (riscv_has_ext(env, RVD)) { 589 uint64_t reg; 590 for (i = 0; i < 32; i++) { 591 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 592 if (ret) { 593 return ret; 594 } 595 env->fpr[i] = reg; 596 } 597 return ret; 598 } 599 600 if (riscv_has_ext(env, RVF)) { 601 uint32_t reg; 602 for (i = 0; i < 32; i++) { 603 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 604 if (ret) { 605 return ret; 606 } 607 env->fpr[i] = reg; 608 } 609 return ret; 610 } 611 612 return ret; 613 } 614 615 static int kvm_riscv_put_regs_fp(CPUState *cs) 616 { 617 int ret = 0; 618 int i; 619 CPURISCVState *env = &RISCV_CPU(cs)->env; 620 621 if (riscv_has_ext(env, RVD)) { 622 uint64_t reg; 623 for (i = 0; i < 32; i++) { 624 reg = env->fpr[i]; 625 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 626 if (ret) { 627 return ret; 628 } 629 } 630 return ret; 631 } 632 633 if (riscv_has_ext(env, RVF)) { 634 uint32_t reg; 635 for (i = 0; i < 32; i++) { 636 reg = env->fpr[i]; 637 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 638 if (ret) { 639 return ret; 640 } 641 } 642 return ret; 643 } 644 645 return ret; 646 } 647 648 static void kvm_riscv_get_regs_timer(CPUState *cs) 649 { 650 CPURISCVState *env = &RISCV_CPU(cs)->env; 651 652 if (env->kvm_timer_dirty) { 653 return; 654 } 655 656 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 657 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 658 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 659 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 660 661 env->kvm_timer_dirty = true; 662 } 663 664 static void kvm_riscv_put_regs_timer(CPUState *cs) 665 { 666 uint64_t reg; 667 CPURISCVState *env = &RISCV_CPU(cs)->env; 668 669 if (!env->kvm_timer_dirty) { 670 return; 671 } 672 673 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 674 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 675 676 /* 677 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 678 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 679 * doesn't matter that adaping in QEMU now. 680 * TODO If KVM changes, adapt here. 681 */ 682 if (env->kvm_timer_state) { 683 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 684 } 685 686 /* 687 * For now, migration will not work between Hosts with different timer 688 * frequency. Therefore, we should check whether they are the same here 689 * during the migration. 690 */ 691 if (migration_is_running(migrate_get_current()->state)) { 692 KVM_RISCV_GET_TIMER(cs, frequency, reg); 693 if (reg != env->kvm_timer_frequency) { 694 error_report("Dst Hosts timer frequency != Src Hosts"); 695 } 696 } 697 698 env->kvm_timer_dirty = false; 699 } 700 701 typedef struct KVMScratchCPU { 702 int kvmfd; 703 int vmfd; 704 int cpufd; 705 } KVMScratchCPU; 706 707 /* 708 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 709 * from target/arm/kvm.c. 710 */ 711 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 712 { 713 int kvmfd = -1, vmfd = -1, cpufd = -1; 714 715 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 716 if (kvmfd < 0) { 717 goto err; 718 } 719 do { 720 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 721 } while (vmfd == -1 && errno == EINTR); 722 if (vmfd < 0) { 723 goto err; 724 } 725 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 726 if (cpufd < 0) { 727 goto err; 728 } 729 730 scratch->kvmfd = kvmfd; 731 scratch->vmfd = vmfd; 732 scratch->cpufd = cpufd; 733 734 return true; 735 736 err: 737 if (cpufd >= 0) { 738 close(cpufd); 739 } 740 if (vmfd >= 0) { 741 close(vmfd); 742 } 743 if (kvmfd >= 0) { 744 close(kvmfd); 745 } 746 747 return false; 748 } 749 750 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 751 { 752 close(scratch->cpufd); 753 close(scratch->vmfd); 754 close(scratch->kvmfd); 755 } 756 757 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 758 { 759 CPURISCVState *env = &cpu->env; 760 struct kvm_one_reg reg; 761 int ret; 762 763 reg.id = RISCV_CONFIG_REG(env, mvendorid); 764 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 765 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 766 if (ret != 0) { 767 error_report("Unable to retrieve mvendorid from host, error %d", ret); 768 } 769 770 reg.id = RISCV_CONFIG_REG(env, marchid); 771 reg.addr = (uint64_t)&cpu->cfg.marchid; 772 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 773 if (ret != 0) { 774 error_report("Unable to retrieve marchid from host, error %d", ret); 775 } 776 777 reg.id = RISCV_CONFIG_REG(env, mimpid); 778 reg.addr = (uint64_t)&cpu->cfg.mimpid; 779 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 780 if (ret != 0) { 781 error_report("Unable to retrieve mimpid from host, error %d", ret); 782 } 783 } 784 785 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 786 KVMScratchCPU *kvmcpu) 787 { 788 CPURISCVState *env = &cpu->env; 789 struct kvm_one_reg reg; 790 int ret; 791 792 reg.id = RISCV_CONFIG_REG(env, isa); 793 reg.addr = (uint64_t)&env->misa_ext_mask; 794 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 795 796 if (ret) { 797 error_report("Unable to fetch ISA register from KVM, " 798 "error %d", ret); 799 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 800 exit(EXIT_FAILURE); 801 } 802 803 env->misa_ext = env->misa_ext_mask; 804 } 805 806 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 807 KVMCPUConfig *cbomz_cfg) 808 { 809 CPURISCVState *env = &cpu->env; 810 struct kvm_one_reg reg; 811 int ret; 812 813 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 814 cbomz_cfg->kvm_reg_id); 815 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 816 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 817 if (ret != 0) { 818 error_report("Unable to read KVM reg %s, error %d", 819 cbomz_cfg->name, ret); 820 exit(EXIT_FAILURE); 821 } 822 } 823 824 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 825 KVMScratchCPU *kvmcpu) 826 { 827 CPURISCVState *env = &cpu->env; 828 uint64_t val; 829 int i, ret; 830 831 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 832 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 833 struct kvm_one_reg reg; 834 835 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 836 multi_ext_cfg->kvm_reg_id); 837 reg.addr = (uint64_t)&val; 838 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 839 if (ret != 0) { 840 if (errno == EINVAL) { 841 /* Silently default to 'false' if KVM does not support it. */ 842 multi_ext_cfg->supported = false; 843 val = false; 844 } else { 845 error_report("Unable to read ISA_EXT KVM register %s: %s", 846 multi_ext_cfg->name, strerror(errno)); 847 exit(EXIT_FAILURE); 848 } 849 } else { 850 multi_ext_cfg->supported = true; 851 } 852 853 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 854 } 855 856 if (cpu->cfg.ext_zicbom) { 857 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 858 } 859 860 if (cpu->cfg.ext_zicboz) { 861 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 862 } 863 } 864 865 static int uint64_cmp(const void *a, const void *b) 866 { 867 uint64_t val1 = *(const uint64_t *)a; 868 uint64_t val2 = *(const uint64_t *)b; 869 870 if (val1 < val2) { 871 return -1; 872 } 873 874 if (val1 > val2) { 875 return 1; 876 } 877 878 return 0; 879 } 880 881 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 882 { 883 KVMCPUConfig *multi_ext_cfg; 884 struct kvm_one_reg reg; 885 struct kvm_reg_list rl_struct; 886 struct kvm_reg_list *reglist; 887 uint64_t val, reg_id, *reg_search; 888 int i, ret; 889 890 rl_struct.n = 0; 891 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 892 893 /* 894 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 895 * (EINVAL). Use read_legacy() in this case. 896 */ 897 if (errno == EINVAL) { 898 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 899 } else if (errno != E2BIG) { 900 /* 901 * E2BIG is an expected error message for the API since we 902 * don't know the number of registers. The right amount will 903 * be written in rl_struct.n. 904 * 905 * Error out if we get any other errno. 906 */ 907 error_report("Error when accessing get-reg-list: %s", 908 strerror(errno)); 909 exit(EXIT_FAILURE); 910 } 911 912 reglist = g_malloc(sizeof(struct kvm_reg_list) + 913 rl_struct.n * sizeof(uint64_t)); 914 reglist->n = rl_struct.n; 915 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 916 if (ret) { 917 error_report("Error when reading KVM_GET_REG_LIST: %s", 918 strerror(errno)); 919 exit(EXIT_FAILURE); 920 } 921 922 /* sort reglist to use bsearch() */ 923 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 924 925 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 926 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 927 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 928 multi_ext_cfg->kvm_reg_id); 929 reg_search = bsearch(®_id, reglist->reg, reglist->n, 930 sizeof(uint64_t), uint64_cmp); 931 if (!reg_search) { 932 continue; 933 } 934 935 reg.id = reg_id; 936 reg.addr = (uint64_t)&val; 937 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 938 if (ret != 0) { 939 error_report("Unable to read ISA_EXT KVM register %s: %s", 940 multi_ext_cfg->name, strerror(errno)); 941 exit(EXIT_FAILURE); 942 } 943 944 multi_ext_cfg->supported = true; 945 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 946 } 947 948 if (cpu->cfg.ext_zicbom) { 949 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 950 } 951 952 if (cpu->cfg.ext_zicboz) { 953 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 954 } 955 } 956 957 static void riscv_init_kvm_registers(Object *cpu_obj) 958 { 959 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 960 KVMScratchCPU kvmcpu; 961 962 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 963 return; 964 } 965 966 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 967 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 968 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 969 970 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 971 } 972 973 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 974 KVM_CAP_LAST_INFO 975 }; 976 977 int kvm_arch_get_registers(CPUState *cs) 978 { 979 int ret = 0; 980 981 ret = kvm_riscv_get_regs_core(cs); 982 if (ret) { 983 return ret; 984 } 985 986 ret = kvm_riscv_get_regs_csr(cs); 987 if (ret) { 988 return ret; 989 } 990 991 ret = kvm_riscv_get_regs_fp(cs); 992 if (ret) { 993 return ret; 994 } 995 996 return ret; 997 } 998 999 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1000 { 1001 if (cap_has_mp_state) { 1002 struct kvm_mp_state mp_state = { 1003 .mp_state = state 1004 }; 1005 1006 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1007 if (ret) { 1008 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1009 __func__, ret, strerror(-ret)); 1010 return -1; 1011 } 1012 } 1013 1014 return 0; 1015 } 1016 1017 int kvm_arch_put_registers(CPUState *cs, int level) 1018 { 1019 int ret = 0; 1020 1021 ret = kvm_riscv_put_regs_core(cs); 1022 if (ret) { 1023 return ret; 1024 } 1025 1026 ret = kvm_riscv_put_regs_csr(cs); 1027 if (ret) { 1028 return ret; 1029 } 1030 1031 ret = kvm_riscv_put_regs_fp(cs); 1032 if (ret) { 1033 return ret; 1034 } 1035 1036 if (KVM_PUT_RESET_STATE == level) { 1037 RISCVCPU *cpu = RISCV_CPU(cs); 1038 if (cs->cpu_index == 0) { 1039 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1040 } else { 1041 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1042 } 1043 if (ret) { 1044 return ret; 1045 } 1046 } 1047 1048 return ret; 1049 } 1050 1051 int kvm_arch_release_virq_post(int virq) 1052 { 1053 return 0; 1054 } 1055 1056 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1057 uint64_t address, uint32_t data, PCIDevice *dev) 1058 { 1059 return 0; 1060 } 1061 1062 int kvm_arch_destroy_vcpu(CPUState *cs) 1063 { 1064 return 0; 1065 } 1066 1067 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1068 { 1069 return cpu->cpu_index; 1070 } 1071 1072 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1073 RunState state) 1074 { 1075 CPUState *cs = opaque; 1076 1077 if (running) { 1078 kvm_riscv_put_regs_timer(cs); 1079 } else { 1080 kvm_riscv_get_regs_timer(cs); 1081 } 1082 } 1083 1084 void kvm_arch_init_irq_routing(KVMState *s) 1085 { 1086 } 1087 1088 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1089 { 1090 CPURISCVState *env = &cpu->env; 1091 target_ulong reg; 1092 uint64_t id; 1093 int ret; 1094 1095 id = RISCV_CONFIG_REG(env, mvendorid); 1096 /* 1097 * cfg.mvendorid is an uint32 but a target_ulong will 1098 * be written. Assign it to a target_ulong var to avoid 1099 * writing pieces of other cpu->cfg fields in the reg. 1100 */ 1101 reg = cpu->cfg.mvendorid; 1102 ret = kvm_set_one_reg(cs, id, ®); 1103 if (ret != 0) { 1104 return ret; 1105 } 1106 1107 id = RISCV_CONFIG_REG(env, marchid); 1108 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1109 if (ret != 0) { 1110 return ret; 1111 } 1112 1113 id = RISCV_CONFIG_REG(env, mimpid); 1114 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1115 1116 return ret; 1117 } 1118 1119 int kvm_arch_init_vcpu(CPUState *cs) 1120 { 1121 int ret = 0; 1122 RISCVCPU *cpu = RISCV_CPU(cs); 1123 1124 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1125 1126 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1127 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1128 if (ret != 0) { 1129 return ret; 1130 } 1131 } 1132 1133 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1134 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1135 1136 return ret; 1137 } 1138 1139 int kvm_arch_msi_data_to_gsi(uint32_t data) 1140 { 1141 abort(); 1142 } 1143 1144 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1145 int vector, PCIDevice *dev) 1146 { 1147 return 0; 1148 } 1149 1150 int kvm_arch_get_default_type(MachineState *ms) 1151 { 1152 return 0; 1153 } 1154 1155 int kvm_arch_init(MachineState *ms, KVMState *s) 1156 { 1157 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1158 return 0; 1159 } 1160 1161 int kvm_arch_irqchip_create(KVMState *s) 1162 { 1163 if (kvm_kernel_irqchip_split()) { 1164 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1165 exit(1); 1166 } 1167 1168 /* 1169 * We can create the VAIA using the newer device control API. 1170 */ 1171 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1172 } 1173 1174 int kvm_arch_process_async_events(CPUState *cs) 1175 { 1176 return 0; 1177 } 1178 1179 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1180 { 1181 } 1182 1183 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1184 { 1185 return MEMTXATTRS_UNSPECIFIED; 1186 } 1187 1188 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1189 { 1190 return true; 1191 } 1192 1193 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1194 { 1195 int ret = 0; 1196 unsigned char ch; 1197 switch (run->riscv_sbi.extension_id) { 1198 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1199 ch = run->riscv_sbi.args[0]; 1200 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1201 break; 1202 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1203 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1204 if (ret == sizeof(ch)) { 1205 run->riscv_sbi.ret[0] = ch; 1206 } else { 1207 run->riscv_sbi.ret[0] = -1; 1208 } 1209 ret = 0; 1210 break; 1211 default: 1212 qemu_log_mask(LOG_UNIMP, 1213 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1214 __func__, run->riscv_sbi.extension_id); 1215 ret = -1; 1216 break; 1217 } 1218 return ret; 1219 } 1220 1221 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1222 { 1223 int ret = 0; 1224 switch (run->exit_reason) { 1225 case KVM_EXIT_RISCV_SBI: 1226 ret = kvm_riscv_handle_sbi(cs, run); 1227 break; 1228 default: 1229 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1230 __func__, run->exit_reason); 1231 ret = -1; 1232 break; 1233 } 1234 return ret; 1235 } 1236 1237 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1238 { 1239 CPURISCVState *env = &cpu->env; 1240 int i; 1241 1242 if (!kvm_enabled()) { 1243 return; 1244 } 1245 for (i = 0; i < 32; i++) { 1246 env->gpr[i] = 0; 1247 } 1248 env->pc = cpu->env.kernel_addr; 1249 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1250 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1251 env->satp = 0; 1252 env->mie = 0; 1253 env->stvec = 0; 1254 env->sscratch = 0; 1255 env->sepc = 0; 1256 env->scause = 0; 1257 env->stval = 0; 1258 env->mip = 0; 1259 } 1260 1261 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1262 { 1263 int ret; 1264 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1265 1266 if (irq != IRQ_S_EXT) { 1267 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1268 abort(); 1269 } 1270 1271 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1272 if (ret < 0) { 1273 perror("Set irq failed"); 1274 abort(); 1275 } 1276 } 1277 1278 bool kvm_arch_cpu_check_are_resettable(void) 1279 { 1280 return true; 1281 } 1282 1283 static int aia_mode; 1284 1285 static const char *kvm_aia_mode_str(uint64_t mode) 1286 { 1287 switch (mode) { 1288 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1289 return "emul"; 1290 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1291 return "hwaccel"; 1292 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1293 default: 1294 return "auto"; 1295 }; 1296 } 1297 1298 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1299 { 1300 return g_strdup(kvm_aia_mode_str(aia_mode)); 1301 } 1302 1303 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1304 { 1305 if (!strcmp(val, "emul")) { 1306 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1307 } else if (!strcmp(val, "hwaccel")) { 1308 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1309 } else if (!strcmp(val, "auto")) { 1310 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1311 } else { 1312 error_setg(errp, "Invalid KVM AIA mode"); 1313 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1314 } 1315 } 1316 1317 void kvm_arch_accel_class_init(ObjectClass *oc) 1318 { 1319 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1320 riscv_set_kvm_aia); 1321 object_class_property_set_description(oc, "riscv-aia", 1322 "Set KVM AIA mode. Valid values are " 1323 "emul, hwaccel, and auto. Default " 1324 "is auto."); 1325 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1326 "auto"); 1327 } 1328 1329 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1330 uint64_t aia_irq_num, uint64_t aia_msi_num, 1331 uint64_t aplic_base, uint64_t imsic_base, 1332 uint64_t guest_num) 1333 { 1334 int ret, i; 1335 int aia_fd = -1; 1336 uint64_t default_aia_mode; 1337 uint64_t socket_count = riscv_socket_count(machine); 1338 uint64_t max_hart_per_socket = 0; 1339 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1340 uint64_t socket_bits, hart_bits, guest_bits; 1341 1342 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1343 1344 if (aia_fd < 0) { 1345 error_report("Unable to create in-kernel irqchip"); 1346 exit(1); 1347 } 1348 1349 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1350 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1351 &default_aia_mode, false, NULL); 1352 if (ret < 0) { 1353 error_report("KVM AIA: failed to get current KVM AIA mode"); 1354 exit(1); 1355 } 1356 qemu_log("KVM AIA: default mode is %s\n", 1357 kvm_aia_mode_str(default_aia_mode)); 1358 1359 if (default_aia_mode != aia_mode) { 1360 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1361 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1362 &aia_mode, true, NULL); 1363 if (ret < 0) 1364 warn_report("KVM AIA: failed to set KVM AIA mode"); 1365 else 1366 qemu_log("KVM AIA: set current mode to %s\n", 1367 kvm_aia_mode_str(aia_mode)); 1368 } 1369 1370 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1371 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1372 &aia_irq_num, true, NULL); 1373 if (ret < 0) { 1374 error_report("KVM AIA: failed to set number of input irq lines"); 1375 exit(1); 1376 } 1377 1378 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1379 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1380 &aia_msi_num, true, NULL); 1381 if (ret < 0) { 1382 error_report("KVM AIA: failed to set number of msi"); 1383 exit(1); 1384 } 1385 1386 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1387 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1388 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1389 &socket_bits, true, NULL); 1390 if (ret < 0) { 1391 error_report("KVM AIA: failed to set group_bits"); 1392 exit(1); 1393 } 1394 1395 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1396 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1397 &group_shift, true, NULL); 1398 if (ret < 0) { 1399 error_report("KVM AIA: failed to set group_shift"); 1400 exit(1); 1401 } 1402 1403 guest_bits = guest_num == 0 ? 0 : 1404 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1405 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1406 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1407 &guest_bits, true, NULL); 1408 if (ret < 0) { 1409 error_report("KVM AIA: failed to set guest_bits"); 1410 exit(1); 1411 } 1412 1413 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1414 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1415 &aplic_base, true, NULL); 1416 if (ret < 0) { 1417 error_report("KVM AIA: failed to set the base address of APLIC"); 1418 exit(1); 1419 } 1420 1421 for (socket = 0; socket < socket_count; socket++) { 1422 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1423 hart_count = riscv_socket_hart_count(machine, socket); 1424 base_hart = riscv_socket_first_hartid(machine, socket); 1425 1426 if (max_hart_per_socket < hart_count) { 1427 max_hart_per_socket = hart_count; 1428 } 1429 1430 for (i = 0; i < hart_count; i++) { 1431 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1432 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1433 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1434 &imsic_addr, true, NULL); 1435 if (ret < 0) { 1436 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1437 exit(1); 1438 } 1439 } 1440 } 1441 1442 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1443 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1444 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1445 &hart_bits, true, NULL); 1446 if (ret < 0) { 1447 error_report("KVM AIA: failed to set hart_bits"); 1448 exit(1); 1449 } 1450 1451 if (kvm_has_gsi_routing()) { 1452 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1453 /* KVM AIA only has one APLIC instance */ 1454 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1455 } 1456 kvm_gsi_routing_allowed = true; 1457 kvm_irqchip_commit_routes(kvm_state); 1458 } 1459 1460 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1461 KVM_DEV_RISCV_AIA_CTRL_INIT, 1462 NULL, true, NULL); 1463 if (ret < 0) { 1464 error_report("KVM AIA: initialized fail"); 1465 exit(1); 1466 } 1467 1468 kvm_msi_via_irqfd_allowed = true; 1469 } 1470 1471 static void kvm_cpu_instance_init(CPUState *cs) 1472 { 1473 Object *obj = OBJECT(RISCV_CPU(cs)); 1474 DeviceState *dev = DEVICE(obj); 1475 1476 riscv_init_kvm_registers(obj); 1477 1478 kvm_riscv_add_cpu_user_properties(obj); 1479 1480 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1481 /* Check if we have a specific KVM handler for the option */ 1482 if (object_property_find(obj, prop->name)) { 1483 continue; 1484 } 1485 qdev_property_add_static(dev, prop); 1486 } 1487 } 1488 1489 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1490 { 1491 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1492 1493 acc->cpu_instance_init = kvm_cpu_instance_init; 1494 } 1495 1496 static const TypeInfo kvm_cpu_accel_type_info = { 1497 .name = ACCEL_CPU_NAME("kvm"), 1498 1499 .parent = TYPE_ACCEL_CPU, 1500 .class_init = kvm_cpu_accel_class_init, 1501 .abstract = true, 1502 }; 1503 static void kvm_cpu_accel_register_types(void) 1504 { 1505 type_register_static(&kvm_cpu_accel_type_info); 1506 } 1507 type_init(kvm_cpu_accel_register_types); 1508 1509 static void riscv_host_cpu_init(Object *obj) 1510 { 1511 CPURISCVState *env = &RISCV_CPU(obj)->env; 1512 1513 #if defined(TARGET_RISCV32) 1514 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1515 #elif defined(TARGET_RISCV64) 1516 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1517 #endif 1518 } 1519 1520 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1521 { 1522 .name = TYPE_RISCV_CPU_HOST, 1523 .parent = TYPE_RISCV_CPU, 1524 .instance_init = riscv_host_cpu_init, 1525 } 1526 }; 1527 1528 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1529