1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 278 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 279 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 280 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 281 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 282 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 283 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 284 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 285 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 286 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 287 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 288 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 289 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 290 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 291 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 292 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 293 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 294 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 295 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 296 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 297 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 298 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 299 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 300 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 301 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 302 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 303 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 304 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 305 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 306 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 307 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 308 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 309 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 310 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 311 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 312 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 313 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 314 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 315 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 316 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 317 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 318 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 319 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 320 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 321 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 322 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 323 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 324 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 325 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 326 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 327 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 328 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 329 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 330 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 331 }; 332 333 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 334 { 335 return (void *)&cpu->cfg + kvmcfg->offset; 336 } 337 338 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 339 uint32_t val) 340 { 341 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 342 343 *ext_enabled = val; 344 } 345 346 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 347 KVMCPUConfig *multi_ext) 348 { 349 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 350 351 return *ext_enabled; 352 } 353 354 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 355 const char *name, 356 void *opaque, Error **errp) 357 { 358 KVMCPUConfig *multi_ext_cfg = opaque; 359 RISCVCPU *cpu = RISCV_CPU(obj); 360 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 361 362 visit_type_bool(v, name, &value, errp); 363 } 364 365 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 366 const char *name, 367 void *opaque, Error **errp) 368 { 369 KVMCPUConfig *multi_ext_cfg = opaque; 370 RISCVCPU *cpu = RISCV_CPU(obj); 371 bool value, host_val; 372 373 if (!visit_type_bool(v, name, &value, errp)) { 374 return; 375 } 376 377 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 378 379 /* 380 * Ignore if the user is setting the same value 381 * as the host. 382 */ 383 if (value == host_val) { 384 return; 385 } 386 387 if (!multi_ext_cfg->supported) { 388 /* 389 * Error out if the user is trying to enable an 390 * extension that KVM doesn't support. Ignore 391 * option otherwise. 392 */ 393 if (value) { 394 error_setg(errp, "KVM does not support disabling extension %s", 395 multi_ext_cfg->name); 396 } 397 398 return; 399 } 400 401 multi_ext_cfg->user_set = true; 402 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 403 } 404 405 static KVMCPUConfig kvm_cbom_blocksize = { 406 .name = "cbom_blocksize", 407 .offset = CPU_CFG_OFFSET(cbom_blocksize), 408 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 409 }; 410 411 static KVMCPUConfig kvm_cboz_blocksize = { 412 .name = "cboz_blocksize", 413 .offset = CPU_CFG_OFFSET(cboz_blocksize), 414 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 415 }; 416 417 static KVMCPUConfig kvm_v_vlenb = { 418 .name = "vlenb", 419 .offset = CPU_CFG_OFFSET(vlenb), 420 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 421 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 422 }; 423 424 static KVMCPUConfig kvm_sbi_dbcn = { 425 .name = "sbi_dbcn", 426 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 427 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 428 }; 429 430 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 431 { 432 CPURISCVState *env = &cpu->env; 433 uint64_t id, reg; 434 int i, ret; 435 436 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 437 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 438 439 if (!multi_ext_cfg->user_set) { 440 continue; 441 } 442 443 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 444 multi_ext_cfg->kvm_reg_id); 445 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 446 ret = kvm_set_one_reg(cs, id, ®); 447 if (ret != 0) { 448 if (!reg && ret == -EINVAL) { 449 warn_report("KVM cannot disable extension %s", 450 multi_ext_cfg->name); 451 } else { 452 error_report("Unable to enable extension %s in KVM, error %d", 453 multi_ext_cfg->name, ret); 454 exit(EXIT_FAILURE); 455 } 456 } 457 } 458 } 459 460 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 461 const char *name, 462 void *opaque, Error **errp) 463 { 464 bool value = false; 465 466 visit_type_bool(v, name, &value, errp); 467 } 468 469 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 470 const char *name, 471 void *opaque, Error **errp) 472 { 473 const char *propname = opaque; 474 bool value; 475 476 if (!visit_type_bool(v, name, &value, errp)) { 477 return; 478 } 479 480 if (value) { 481 error_setg(errp, "'%s' is not available with KVM", 482 propname); 483 } 484 } 485 486 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 487 { 488 /* Check if KVM created the property already */ 489 if (object_property_find(obj, prop_name)) { 490 return; 491 } 492 493 /* 494 * Set the default to disabled for every extension 495 * unknown to KVM and error out if the user attempts 496 * to enable any of them. 497 */ 498 object_property_add(obj, prop_name, "bool", 499 cpu_get_cfg_unavailable, 500 cpu_set_cfg_unavailable, 501 NULL, (void *)prop_name); 502 } 503 504 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 505 const RISCVCPUMultiExtConfig *array) 506 { 507 const RISCVCPUMultiExtConfig *prop; 508 509 g_assert(array); 510 511 for (prop = array; prop && prop->name; prop++) { 512 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 513 } 514 } 515 516 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 517 { 518 int i; 519 520 riscv_add_satp_mode_properties(cpu_obj); 521 522 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 523 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 524 int bit = misa_cfg->offset; 525 526 misa_cfg->name = riscv_get_misa_ext_name(bit); 527 misa_cfg->description = riscv_get_misa_ext_description(bit); 528 529 object_property_add(cpu_obj, misa_cfg->name, "bool", 530 kvm_cpu_get_misa_ext_cfg, 531 kvm_cpu_set_misa_ext_cfg, 532 NULL, misa_cfg); 533 object_property_set_description(cpu_obj, misa_cfg->name, 534 misa_cfg->description); 535 } 536 537 for (i = 0; misa_bits[i] != 0; i++) { 538 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 539 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 540 } 541 542 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 543 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 544 545 object_property_add(cpu_obj, multi_cfg->name, "bool", 546 kvm_cpu_get_multi_ext_cfg, 547 kvm_cpu_set_multi_ext_cfg, 548 NULL, multi_cfg); 549 } 550 551 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 552 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 553 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 554 555 /* We don't have the needed KVM support for profiles */ 556 for (i = 0; riscv_profiles[i] != NULL; i++) { 557 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 558 } 559 } 560 561 static int kvm_riscv_get_regs_core(CPUState *cs) 562 { 563 int ret = 0; 564 int i; 565 target_ulong reg; 566 CPURISCVState *env = &RISCV_CPU(cs)->env; 567 568 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 569 if (ret) { 570 return ret; 571 } 572 env->pc = reg; 573 574 for (i = 1; i < 32; i++) { 575 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 576 ret = kvm_get_one_reg(cs, id, ®); 577 if (ret) { 578 return ret; 579 } 580 env->gpr[i] = reg; 581 } 582 583 return ret; 584 } 585 586 static int kvm_riscv_put_regs_core(CPUState *cs) 587 { 588 int ret = 0; 589 int i; 590 target_ulong reg; 591 CPURISCVState *env = &RISCV_CPU(cs)->env; 592 593 reg = env->pc; 594 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 595 if (ret) { 596 return ret; 597 } 598 599 for (i = 1; i < 32; i++) { 600 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 601 reg = env->gpr[i]; 602 ret = kvm_set_one_reg(cs, id, ®); 603 if (ret) { 604 return ret; 605 } 606 } 607 608 return ret; 609 } 610 611 static int kvm_riscv_get_regs_csr(CPUState *cs) 612 { 613 CPURISCVState *env = &RISCV_CPU(cs)->env; 614 615 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 616 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 617 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 618 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 619 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 620 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 621 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 622 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 623 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 624 625 return 0; 626 } 627 628 static int kvm_riscv_put_regs_csr(CPUState *cs) 629 { 630 CPURISCVState *env = &RISCV_CPU(cs)->env; 631 632 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 633 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 634 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 635 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 636 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 637 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 638 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 639 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 640 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 641 642 return 0; 643 } 644 645 static int kvm_riscv_get_regs_fp(CPUState *cs) 646 { 647 int ret = 0; 648 int i; 649 CPURISCVState *env = &RISCV_CPU(cs)->env; 650 651 if (riscv_has_ext(env, RVD)) { 652 uint64_t reg; 653 for (i = 0; i < 32; i++) { 654 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 655 if (ret) { 656 return ret; 657 } 658 env->fpr[i] = reg; 659 } 660 return ret; 661 } 662 663 if (riscv_has_ext(env, RVF)) { 664 uint32_t reg; 665 for (i = 0; i < 32; i++) { 666 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 667 if (ret) { 668 return ret; 669 } 670 env->fpr[i] = reg; 671 } 672 return ret; 673 } 674 675 return ret; 676 } 677 678 static int kvm_riscv_put_regs_fp(CPUState *cs) 679 { 680 int ret = 0; 681 int i; 682 CPURISCVState *env = &RISCV_CPU(cs)->env; 683 684 if (riscv_has_ext(env, RVD)) { 685 uint64_t reg; 686 for (i = 0; i < 32; i++) { 687 reg = env->fpr[i]; 688 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 689 if (ret) { 690 return ret; 691 } 692 } 693 return ret; 694 } 695 696 if (riscv_has_ext(env, RVF)) { 697 uint32_t reg; 698 for (i = 0; i < 32; i++) { 699 reg = env->fpr[i]; 700 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 701 if (ret) { 702 return ret; 703 } 704 } 705 return ret; 706 } 707 708 return ret; 709 } 710 711 static void kvm_riscv_get_regs_timer(CPUState *cs) 712 { 713 CPURISCVState *env = &RISCV_CPU(cs)->env; 714 715 if (env->kvm_timer_dirty) { 716 return; 717 } 718 719 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 720 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 721 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 722 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 723 724 env->kvm_timer_dirty = true; 725 } 726 727 static void kvm_riscv_put_regs_timer(CPUState *cs) 728 { 729 uint64_t reg; 730 CPURISCVState *env = &RISCV_CPU(cs)->env; 731 732 if (!env->kvm_timer_dirty) { 733 return; 734 } 735 736 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 737 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 738 739 /* 740 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 741 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 742 * doesn't matter that adaping in QEMU now. 743 * TODO If KVM changes, adapt here. 744 */ 745 if (env->kvm_timer_state) { 746 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 747 } 748 749 /* 750 * For now, migration will not work between Hosts with different timer 751 * frequency. Therefore, we should check whether they are the same here 752 * during the migration. 753 */ 754 if (migration_is_running()) { 755 KVM_RISCV_GET_TIMER(cs, frequency, reg); 756 if (reg != env->kvm_timer_frequency) { 757 error_report("Dst Hosts timer frequency != Src Hosts"); 758 } 759 } 760 761 env->kvm_timer_dirty = false; 762 } 763 764 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 765 { 766 uint64_t reg; 767 768 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 769 770 return reg; 771 } 772 773 static int kvm_riscv_get_regs_vector(CPUState *cs) 774 { 775 RISCVCPU *cpu = RISCV_CPU(cs); 776 CPURISCVState *env = &cpu->env; 777 target_ulong reg; 778 uint64_t vreg_id; 779 int vreg_idx, ret = 0; 780 781 if (!riscv_has_ext(env, RVV)) { 782 return 0; 783 } 784 785 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 786 if (ret) { 787 return ret; 788 } 789 env->vstart = reg; 790 791 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 792 if (ret) { 793 return ret; 794 } 795 env->vl = reg; 796 797 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 798 if (ret) { 799 return ret; 800 } 801 env->vtype = reg; 802 803 if (kvm_v_vlenb.supported) { 804 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 805 if (ret) { 806 return ret; 807 } 808 cpu->cfg.vlenb = reg; 809 810 for (int i = 0; i < 32; i++) { 811 /* 812 * vreg[] is statically allocated using RV_VLEN_MAX. 813 * Use it instead of vlenb to calculate vreg_idx for 814 * simplicity. 815 */ 816 vreg_idx = i * RV_VLEN_MAX / 64; 817 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 818 819 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 820 if (ret) { 821 return ret; 822 } 823 } 824 } 825 826 return 0; 827 } 828 829 static int kvm_riscv_put_regs_vector(CPUState *cs) 830 { 831 RISCVCPU *cpu = RISCV_CPU(cs); 832 CPURISCVState *env = &cpu->env; 833 target_ulong reg; 834 uint64_t vreg_id; 835 int vreg_idx, ret = 0; 836 837 if (!riscv_has_ext(env, RVV)) { 838 return 0; 839 } 840 841 reg = env->vstart; 842 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 843 if (ret) { 844 return ret; 845 } 846 847 reg = env->vl; 848 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 849 if (ret) { 850 return ret; 851 } 852 853 reg = env->vtype; 854 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 855 if (ret) { 856 return ret; 857 } 858 859 if (kvm_v_vlenb.supported) { 860 reg = cpu->cfg.vlenb; 861 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 862 863 for (int i = 0; i < 32; i++) { 864 /* 865 * vreg[] is statically allocated using RV_VLEN_MAX. 866 * Use it instead of vlenb to calculate vreg_idx for 867 * simplicity. 868 */ 869 vreg_idx = i * RV_VLEN_MAX / 64; 870 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 871 872 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 873 if (ret) { 874 return ret; 875 } 876 } 877 } 878 879 return ret; 880 } 881 882 typedef struct KVMScratchCPU { 883 int kvmfd; 884 int vmfd; 885 int cpufd; 886 } KVMScratchCPU; 887 888 /* 889 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 890 * from target/arm/kvm.c. 891 */ 892 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 893 { 894 int kvmfd = -1, vmfd = -1, cpufd = -1; 895 896 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 897 if (kvmfd < 0) { 898 goto err; 899 } 900 do { 901 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 902 } while (vmfd == -1 && errno == EINTR); 903 if (vmfd < 0) { 904 goto err; 905 } 906 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 907 if (cpufd < 0) { 908 goto err; 909 } 910 911 scratch->kvmfd = kvmfd; 912 scratch->vmfd = vmfd; 913 scratch->cpufd = cpufd; 914 915 return true; 916 917 err: 918 if (cpufd >= 0) { 919 close(cpufd); 920 } 921 if (vmfd >= 0) { 922 close(vmfd); 923 } 924 if (kvmfd >= 0) { 925 close(kvmfd); 926 } 927 928 return false; 929 } 930 931 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 932 { 933 close(scratch->cpufd); 934 close(scratch->vmfd); 935 close(scratch->kvmfd); 936 } 937 938 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 939 { 940 CPURISCVState *env = &cpu->env; 941 struct kvm_one_reg reg; 942 int ret; 943 944 reg.id = RISCV_CONFIG_REG(env, mvendorid); 945 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 946 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 947 if (ret != 0) { 948 error_report("Unable to retrieve mvendorid from host, error %d", ret); 949 } 950 951 reg.id = RISCV_CONFIG_REG(env, marchid); 952 reg.addr = (uint64_t)&cpu->cfg.marchid; 953 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 954 if (ret != 0) { 955 error_report("Unable to retrieve marchid from host, error %d", ret); 956 } 957 958 reg.id = RISCV_CONFIG_REG(env, mimpid); 959 reg.addr = (uint64_t)&cpu->cfg.mimpid; 960 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 961 if (ret != 0) { 962 error_report("Unable to retrieve mimpid from host, error %d", ret); 963 } 964 } 965 966 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 967 KVMScratchCPU *kvmcpu) 968 { 969 CPURISCVState *env = &cpu->env; 970 struct kvm_one_reg reg; 971 int ret; 972 973 reg.id = RISCV_CONFIG_REG(env, isa); 974 reg.addr = (uint64_t)&env->misa_ext_mask; 975 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 976 977 if (ret) { 978 error_report("Unable to fetch ISA register from KVM, " 979 "error %d", ret); 980 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 981 exit(EXIT_FAILURE); 982 } 983 984 env->misa_ext = env->misa_ext_mask; 985 } 986 987 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 988 KVMCPUConfig *cbomz_cfg) 989 { 990 CPURISCVState *env = &cpu->env; 991 struct kvm_one_reg reg; 992 int ret; 993 994 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 995 cbomz_cfg->kvm_reg_id); 996 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 997 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 998 if (ret != 0) { 999 error_report("Unable to read KVM reg %s, error %d", 1000 cbomz_cfg->name, ret); 1001 exit(EXIT_FAILURE); 1002 } 1003 } 1004 1005 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1006 KVMScratchCPU *kvmcpu) 1007 { 1008 CPURISCVState *env = &cpu->env; 1009 uint64_t val; 1010 int i, ret; 1011 1012 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1013 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1014 struct kvm_one_reg reg; 1015 1016 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1017 multi_ext_cfg->kvm_reg_id); 1018 reg.addr = (uint64_t)&val; 1019 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1020 if (ret != 0) { 1021 if (errno == EINVAL) { 1022 /* Silently default to 'false' if KVM does not support it. */ 1023 multi_ext_cfg->supported = false; 1024 val = false; 1025 } else { 1026 error_report("Unable to read ISA_EXT KVM register %s: %s", 1027 multi_ext_cfg->name, strerror(errno)); 1028 exit(EXIT_FAILURE); 1029 } 1030 } else { 1031 multi_ext_cfg->supported = true; 1032 } 1033 1034 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1035 } 1036 1037 if (cpu->cfg.ext_zicbom) { 1038 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1039 } 1040 1041 if (cpu->cfg.ext_zicboz) { 1042 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1043 } 1044 } 1045 1046 static int uint64_cmp(const void *a, const void *b) 1047 { 1048 uint64_t val1 = *(const uint64_t *)a; 1049 uint64_t val2 = *(const uint64_t *)b; 1050 1051 if (val1 < val2) { 1052 return -1; 1053 } 1054 1055 if (val1 > val2) { 1056 return 1; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1063 KVMScratchCPU *kvmcpu, 1064 struct kvm_reg_list *reglist) 1065 { 1066 struct kvm_reg_list *reg_search; 1067 1068 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1069 sizeof(uint64_t), uint64_cmp); 1070 1071 if (reg_search) { 1072 kvm_sbi_dbcn.supported = true; 1073 } 1074 } 1075 1076 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1077 struct kvm_reg_list *reglist) 1078 { 1079 struct kvm_one_reg reg; 1080 struct kvm_reg_list *reg_search; 1081 uint64_t val; 1082 int ret; 1083 1084 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1085 sizeof(uint64_t), uint64_cmp); 1086 1087 if (reg_search) { 1088 reg.id = kvm_v_vlenb.kvm_reg_id; 1089 reg.addr = (uint64_t)&val; 1090 1091 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1092 if (ret != 0) { 1093 error_report("Unable to read vlenb register, error code: %d", 1094 errno); 1095 exit(EXIT_FAILURE); 1096 } 1097 1098 kvm_v_vlenb.supported = true; 1099 cpu->cfg.vlenb = val; 1100 } 1101 } 1102 1103 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1104 { 1105 KVMCPUConfig *multi_ext_cfg; 1106 struct kvm_one_reg reg; 1107 struct kvm_reg_list rl_struct; 1108 struct kvm_reg_list *reglist; 1109 uint64_t val, reg_id, *reg_search; 1110 int i, ret; 1111 1112 rl_struct.n = 0; 1113 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1114 1115 /* 1116 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1117 * (EINVAL). Use read_legacy() in this case. 1118 */ 1119 if (errno == EINVAL) { 1120 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1121 } else if (errno != E2BIG) { 1122 /* 1123 * E2BIG is an expected error message for the API since we 1124 * don't know the number of registers. The right amount will 1125 * be written in rl_struct.n. 1126 * 1127 * Error out if we get any other errno. 1128 */ 1129 error_report("Error when accessing get-reg-list: %s", 1130 strerror(errno)); 1131 exit(EXIT_FAILURE); 1132 } 1133 1134 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1135 rl_struct.n * sizeof(uint64_t)); 1136 reglist->n = rl_struct.n; 1137 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1138 if (ret) { 1139 error_report("Error when reading KVM_GET_REG_LIST: %s", 1140 strerror(errno)); 1141 exit(EXIT_FAILURE); 1142 } 1143 1144 /* sort reglist to use bsearch() */ 1145 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1146 1147 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1148 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1149 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1150 multi_ext_cfg->kvm_reg_id); 1151 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1152 sizeof(uint64_t), uint64_cmp); 1153 if (!reg_search) { 1154 continue; 1155 } 1156 1157 reg.id = reg_id; 1158 reg.addr = (uint64_t)&val; 1159 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1160 if (ret != 0) { 1161 error_report("Unable to read ISA_EXT KVM register %s: %s", 1162 multi_ext_cfg->name, strerror(errno)); 1163 exit(EXIT_FAILURE); 1164 } 1165 1166 multi_ext_cfg->supported = true; 1167 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1168 } 1169 1170 if (cpu->cfg.ext_zicbom) { 1171 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1172 } 1173 1174 if (cpu->cfg.ext_zicboz) { 1175 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1176 } 1177 1178 if (riscv_has_ext(&cpu->env, RVV)) { 1179 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1180 } 1181 1182 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1183 } 1184 1185 static void riscv_init_kvm_registers(Object *cpu_obj) 1186 { 1187 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1188 KVMScratchCPU kvmcpu; 1189 1190 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1191 return; 1192 } 1193 1194 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1195 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1196 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1197 1198 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1199 } 1200 1201 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1202 KVM_CAP_LAST_INFO 1203 }; 1204 1205 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1206 { 1207 int ret = 0; 1208 1209 ret = kvm_riscv_get_regs_core(cs); 1210 if (ret) { 1211 return ret; 1212 } 1213 1214 ret = kvm_riscv_get_regs_csr(cs); 1215 if (ret) { 1216 return ret; 1217 } 1218 1219 ret = kvm_riscv_get_regs_fp(cs); 1220 if (ret) { 1221 return ret; 1222 } 1223 1224 ret = kvm_riscv_get_regs_vector(cs); 1225 if (ret) { 1226 return ret; 1227 } 1228 1229 return ret; 1230 } 1231 1232 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1233 { 1234 if (cap_has_mp_state) { 1235 struct kvm_mp_state mp_state = { 1236 .mp_state = state 1237 }; 1238 1239 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1240 if (ret) { 1241 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1242 __func__, ret, strerror(-ret)); 1243 return -1; 1244 } 1245 } 1246 1247 return 0; 1248 } 1249 1250 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1251 { 1252 int ret = 0; 1253 1254 ret = kvm_riscv_put_regs_core(cs); 1255 if (ret) { 1256 return ret; 1257 } 1258 1259 ret = kvm_riscv_put_regs_csr(cs); 1260 if (ret) { 1261 return ret; 1262 } 1263 1264 ret = kvm_riscv_put_regs_fp(cs); 1265 if (ret) { 1266 return ret; 1267 } 1268 1269 ret = kvm_riscv_put_regs_vector(cs); 1270 if (ret) { 1271 return ret; 1272 } 1273 1274 if (KVM_PUT_RESET_STATE == level) { 1275 RISCVCPU *cpu = RISCV_CPU(cs); 1276 if (cs->cpu_index == 0) { 1277 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1278 } else { 1279 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1280 } 1281 if (ret) { 1282 return ret; 1283 } 1284 } 1285 1286 return ret; 1287 } 1288 1289 int kvm_arch_release_virq_post(int virq) 1290 { 1291 return 0; 1292 } 1293 1294 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1295 uint64_t address, uint32_t data, PCIDevice *dev) 1296 { 1297 return 0; 1298 } 1299 1300 int kvm_arch_destroy_vcpu(CPUState *cs) 1301 { 1302 return 0; 1303 } 1304 1305 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1306 { 1307 return cpu->cpu_index; 1308 } 1309 1310 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1311 RunState state) 1312 { 1313 CPUState *cs = opaque; 1314 1315 if (running) { 1316 kvm_riscv_put_regs_timer(cs); 1317 } else { 1318 kvm_riscv_get_regs_timer(cs); 1319 } 1320 } 1321 1322 void kvm_arch_init_irq_routing(KVMState *s) 1323 { 1324 } 1325 1326 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1327 { 1328 CPURISCVState *env = &cpu->env; 1329 target_ulong reg; 1330 uint64_t id; 1331 int ret; 1332 1333 id = RISCV_CONFIG_REG(env, mvendorid); 1334 /* 1335 * cfg.mvendorid is an uint32 but a target_ulong will 1336 * be written. Assign it to a target_ulong var to avoid 1337 * writing pieces of other cpu->cfg fields in the reg. 1338 */ 1339 reg = cpu->cfg.mvendorid; 1340 ret = kvm_set_one_reg(cs, id, ®); 1341 if (ret != 0) { 1342 return ret; 1343 } 1344 1345 id = RISCV_CONFIG_REG(env, marchid); 1346 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1347 if (ret != 0) { 1348 return ret; 1349 } 1350 1351 id = RISCV_CONFIG_REG(env, mimpid); 1352 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1353 1354 return ret; 1355 } 1356 1357 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1358 { 1359 target_ulong reg = 1; 1360 1361 if (!kvm_sbi_dbcn.supported) { 1362 return 0; 1363 } 1364 1365 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1366 } 1367 1368 int kvm_arch_init_vcpu(CPUState *cs) 1369 { 1370 int ret = 0; 1371 RISCVCPU *cpu = RISCV_CPU(cs); 1372 1373 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1374 1375 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1376 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1377 if (ret != 0) { 1378 return ret; 1379 } 1380 } 1381 1382 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1383 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1384 1385 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1386 1387 return ret; 1388 } 1389 1390 int kvm_arch_msi_data_to_gsi(uint32_t data) 1391 { 1392 abort(); 1393 } 1394 1395 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1396 int vector, PCIDevice *dev) 1397 { 1398 return 0; 1399 } 1400 1401 int kvm_arch_get_default_type(MachineState *ms) 1402 { 1403 return 0; 1404 } 1405 1406 int kvm_arch_init(MachineState *ms, KVMState *s) 1407 { 1408 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1409 return 0; 1410 } 1411 1412 int kvm_arch_irqchip_create(KVMState *s) 1413 { 1414 /* 1415 * We can create the VAIA using the newer device control API. 1416 */ 1417 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1418 } 1419 1420 int kvm_arch_process_async_events(CPUState *cs) 1421 { 1422 return 0; 1423 } 1424 1425 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1426 { 1427 } 1428 1429 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1430 { 1431 return MEMTXATTRS_UNSPECIFIED; 1432 } 1433 1434 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1435 { 1436 return true; 1437 } 1438 1439 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1440 { 1441 g_autofree uint8_t *buf = NULL; 1442 RISCVCPU *cpu = RISCV_CPU(cs); 1443 target_ulong num_bytes; 1444 uint64_t addr; 1445 unsigned char ch; 1446 int ret; 1447 1448 switch (run->riscv_sbi.function_id) { 1449 case SBI_EXT_DBCN_CONSOLE_READ: 1450 case SBI_EXT_DBCN_CONSOLE_WRITE: 1451 num_bytes = run->riscv_sbi.args[0]; 1452 1453 if (num_bytes == 0) { 1454 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1455 run->riscv_sbi.ret[1] = 0; 1456 break; 1457 } 1458 1459 addr = run->riscv_sbi.args[1]; 1460 1461 /* 1462 * Handle the case where a 32 bit CPU is running in a 1463 * 64 bit addressing env. 1464 */ 1465 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1466 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1467 } 1468 1469 buf = g_malloc0(num_bytes); 1470 1471 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1472 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1473 if (ret < 0) { 1474 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1475 "reading chardev"); 1476 exit(1); 1477 } 1478 1479 cpu_physical_memory_write(addr, buf, ret); 1480 } else { 1481 cpu_physical_memory_read(addr, buf, num_bytes); 1482 1483 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1484 if (ret < 0) { 1485 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1486 "writing chardev"); 1487 exit(1); 1488 } 1489 } 1490 1491 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1492 run->riscv_sbi.ret[1] = ret; 1493 break; 1494 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1495 ch = run->riscv_sbi.args[0]; 1496 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1497 1498 if (ret < 0) { 1499 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1500 "writing chardev"); 1501 exit(1); 1502 } 1503 1504 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1505 run->riscv_sbi.ret[1] = 0; 1506 break; 1507 default: 1508 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1509 } 1510 } 1511 1512 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1513 { 1514 int ret = 0; 1515 unsigned char ch; 1516 switch (run->riscv_sbi.extension_id) { 1517 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1518 ch = run->riscv_sbi.args[0]; 1519 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1520 break; 1521 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1522 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1523 if (ret == sizeof(ch)) { 1524 run->riscv_sbi.ret[0] = ch; 1525 } else { 1526 run->riscv_sbi.ret[0] = -1; 1527 } 1528 ret = 0; 1529 break; 1530 case SBI_EXT_DBCN: 1531 kvm_riscv_handle_sbi_dbcn(cs, run); 1532 break; 1533 default: 1534 qemu_log_mask(LOG_UNIMP, 1535 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1536 __func__, run->riscv_sbi.extension_id); 1537 ret = -1; 1538 break; 1539 } 1540 return ret; 1541 } 1542 1543 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1544 { 1545 target_ulong csr_num = run->riscv_csr.csr_num; 1546 target_ulong new_value = run->riscv_csr.new_value; 1547 target_ulong write_mask = run->riscv_csr.write_mask; 1548 int ret = 0; 1549 1550 switch (csr_num) { 1551 case CSR_SEED: 1552 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1553 break; 1554 default: 1555 qemu_log_mask(LOG_UNIMP, 1556 "%s: un-handled CSR EXIT for CSR %lx\n", 1557 __func__, csr_num); 1558 ret = -1; 1559 break; 1560 } 1561 1562 return ret; 1563 } 1564 1565 static bool kvm_riscv_handle_debug(CPUState *cs) 1566 { 1567 RISCVCPU *cpu = RISCV_CPU(cs); 1568 CPURISCVState *env = &cpu->env; 1569 1570 /* Ensure PC is synchronised */ 1571 kvm_cpu_synchronize_state(cs); 1572 1573 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1574 return true; 1575 } 1576 1577 return false; 1578 } 1579 1580 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1581 { 1582 int ret = 0; 1583 switch (run->exit_reason) { 1584 case KVM_EXIT_RISCV_SBI: 1585 ret = kvm_riscv_handle_sbi(cs, run); 1586 break; 1587 case KVM_EXIT_RISCV_CSR: 1588 ret = kvm_riscv_handle_csr(cs, run); 1589 break; 1590 case KVM_EXIT_DEBUG: 1591 if (kvm_riscv_handle_debug(cs)) { 1592 ret = EXCP_DEBUG; 1593 } 1594 break; 1595 default: 1596 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1597 __func__, run->exit_reason); 1598 ret = -1; 1599 break; 1600 } 1601 return ret; 1602 } 1603 1604 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1605 { 1606 CPURISCVState *env = &cpu->env; 1607 int i; 1608 1609 if (!kvm_enabled()) { 1610 return; 1611 } 1612 for (i = 0; i < 32; i++) { 1613 env->gpr[i] = 0; 1614 } 1615 env->pc = cpu->env.kernel_addr; 1616 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1617 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1618 env->satp = 0; 1619 env->mie = 0; 1620 env->stvec = 0; 1621 env->sscratch = 0; 1622 env->sepc = 0; 1623 env->scause = 0; 1624 env->stval = 0; 1625 env->mip = 0; 1626 } 1627 1628 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1629 { 1630 int ret; 1631 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1632 1633 if (irq != IRQ_S_EXT) { 1634 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1635 abort(); 1636 } 1637 1638 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1639 if (ret < 0) { 1640 perror("Set irq failed"); 1641 abort(); 1642 } 1643 } 1644 1645 static int aia_mode; 1646 1647 static const char *kvm_aia_mode_str(uint64_t mode) 1648 { 1649 switch (mode) { 1650 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1651 return "emul"; 1652 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1653 return "hwaccel"; 1654 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1655 default: 1656 return "auto"; 1657 }; 1658 } 1659 1660 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1661 { 1662 return g_strdup(kvm_aia_mode_str(aia_mode)); 1663 } 1664 1665 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1666 { 1667 if (!strcmp(val, "emul")) { 1668 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1669 } else if (!strcmp(val, "hwaccel")) { 1670 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1671 } else if (!strcmp(val, "auto")) { 1672 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1673 } else { 1674 error_setg(errp, "Invalid KVM AIA mode"); 1675 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1676 } 1677 } 1678 1679 void kvm_arch_accel_class_init(ObjectClass *oc) 1680 { 1681 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1682 riscv_set_kvm_aia); 1683 object_class_property_set_description(oc, "riscv-aia", 1684 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1685 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1686 "if the host supports it"); 1687 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1688 "auto"); 1689 } 1690 1691 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1692 uint64_t aia_irq_num, uint64_t aia_msi_num, 1693 uint64_t aplic_base, uint64_t imsic_base, 1694 uint64_t guest_num) 1695 { 1696 int ret, i; 1697 int aia_fd = -1; 1698 uint64_t default_aia_mode; 1699 uint64_t socket_count = riscv_socket_count(machine); 1700 uint64_t max_hart_per_socket = 0; 1701 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1702 uint64_t socket_bits, hart_bits, guest_bits; 1703 uint64_t max_group_id; 1704 1705 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1706 1707 if (aia_fd < 0) { 1708 error_report("Unable to create in-kernel irqchip"); 1709 exit(1); 1710 } 1711 1712 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1713 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1714 &default_aia_mode, false, NULL); 1715 if (ret < 0) { 1716 error_report("KVM AIA: failed to get current KVM AIA mode"); 1717 exit(1); 1718 } 1719 1720 if (default_aia_mode != aia_mode) { 1721 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1722 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1723 &aia_mode, true, NULL); 1724 if (ret < 0) { 1725 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1726 "default host mode '%s'", 1727 kvm_aia_mode_str(aia_mode), 1728 kvm_aia_mode_str(default_aia_mode)); 1729 1730 /* failed to change AIA mode, use default */ 1731 aia_mode = default_aia_mode; 1732 } 1733 } 1734 1735 /* 1736 * Skip APLIC creation in KVM if we're running split mode. 1737 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1738 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1739 * since KVM won't be using it. 1740 */ 1741 if (!kvm_kernel_irqchip_split()) { 1742 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1743 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1744 &aia_irq_num, true, NULL); 1745 if (ret < 0) { 1746 error_report("KVM AIA: failed to set number of input irq lines"); 1747 exit(1); 1748 } 1749 1750 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1751 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1752 &aplic_base, true, NULL); 1753 if (ret < 0) { 1754 error_report("KVM AIA: failed to set the base address of APLIC"); 1755 exit(1); 1756 } 1757 } 1758 1759 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1760 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1761 &aia_msi_num, true, NULL); 1762 if (ret < 0) { 1763 error_report("KVM AIA: failed to set number of msi"); 1764 exit(1); 1765 } 1766 1767 1768 if (socket_count > 1) { 1769 max_group_id = socket_count - 1; 1770 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1771 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1772 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1773 &socket_bits, true, NULL); 1774 if (ret < 0) { 1775 error_report("KVM AIA: failed to set group_bits"); 1776 exit(1); 1777 } 1778 1779 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1780 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1781 &group_shift, true, NULL); 1782 if (ret < 0) { 1783 error_report("KVM AIA: failed to set group_shift"); 1784 exit(1); 1785 } 1786 } 1787 1788 guest_bits = guest_num == 0 ? 0 : 1789 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1790 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1791 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1792 &guest_bits, true, NULL); 1793 if (ret < 0) { 1794 error_report("KVM AIA: failed to set guest_bits"); 1795 exit(1); 1796 } 1797 1798 for (socket = 0; socket < socket_count; socket++) { 1799 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1800 hart_count = riscv_socket_hart_count(machine, socket); 1801 base_hart = riscv_socket_first_hartid(machine, socket); 1802 1803 if (max_hart_per_socket < hart_count) { 1804 max_hart_per_socket = hart_count; 1805 } 1806 1807 for (i = 0; i < hart_count; i++) { 1808 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1809 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1810 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1811 &imsic_addr, true, NULL); 1812 if (ret < 0) { 1813 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1814 exit(1); 1815 } 1816 } 1817 } 1818 1819 1820 if (max_hart_per_socket > 1) { 1821 max_hart_per_socket--; 1822 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1823 } else { 1824 hart_bits = 0; 1825 } 1826 1827 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1828 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1829 &hart_bits, true, NULL); 1830 if (ret < 0) { 1831 error_report("KVM AIA: failed to set hart_bits"); 1832 exit(1); 1833 } 1834 1835 if (kvm_has_gsi_routing()) { 1836 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1837 /* KVM AIA only has one APLIC instance */ 1838 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1839 } 1840 kvm_gsi_routing_allowed = true; 1841 kvm_irqchip_commit_routes(kvm_state); 1842 } 1843 1844 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1845 KVM_DEV_RISCV_AIA_CTRL_INIT, 1846 NULL, true, NULL); 1847 if (ret < 0) { 1848 error_report("KVM AIA: initialized fail"); 1849 exit(1); 1850 } 1851 1852 kvm_msi_via_irqfd_allowed = true; 1853 } 1854 1855 static void kvm_cpu_instance_init(CPUState *cs) 1856 { 1857 Object *obj = OBJECT(RISCV_CPU(cs)); 1858 1859 riscv_init_kvm_registers(obj); 1860 1861 kvm_riscv_add_cpu_user_properties(obj); 1862 } 1863 1864 /* 1865 * We'll get here via the following path: 1866 * 1867 * riscv_cpu_realize() 1868 * -> cpu_exec_realizefn() 1869 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1870 */ 1871 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1872 { 1873 RISCVCPU *cpu = RISCV_CPU(cs); 1874 int ret; 1875 1876 if (riscv_has_ext(&cpu->env, RVV)) { 1877 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1878 if (ret) { 1879 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1880 strerrorname_np(errno)); 1881 return false; 1882 } 1883 } 1884 1885 return true; 1886 } 1887 1888 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1889 { 1890 CPURISCVState *env = &cpu->env; 1891 KVMScratchCPU kvmcpu; 1892 struct kvm_one_reg reg; 1893 uint64_t val; 1894 int ret; 1895 1896 /* short-circuit without spinning the scratch CPU */ 1897 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1898 !riscv_has_ext(env, RVV)) { 1899 return; 1900 } 1901 1902 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1903 error_setg(errp, "Unable to create scratch KVM cpu"); 1904 return; 1905 } 1906 1907 if (cpu->cfg.ext_zicbom && 1908 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1909 1910 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1911 kvm_cbom_blocksize.kvm_reg_id); 1912 reg.addr = (uint64_t)&val; 1913 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1914 if (ret != 0) { 1915 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1916 return; 1917 } 1918 1919 if (cpu->cfg.cbom_blocksize != val) { 1920 error_setg(errp, "Unable to set cbom_blocksize to a different " 1921 "value than the host (%lu)", val); 1922 return; 1923 } 1924 } 1925 1926 if (cpu->cfg.ext_zicboz && 1927 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1928 1929 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1930 kvm_cboz_blocksize.kvm_reg_id); 1931 reg.addr = (uint64_t)&val; 1932 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1933 if (ret != 0) { 1934 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1935 return; 1936 } 1937 1938 if (cpu->cfg.cboz_blocksize != val) { 1939 error_setg(errp, "Unable to set cboz_blocksize to a different " 1940 "value than the host (%lu)", val); 1941 return; 1942 } 1943 } 1944 1945 /* Users are setting vlen, not vlenb */ 1946 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1947 if (!kvm_v_vlenb.supported) { 1948 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1949 return; 1950 } 1951 1952 reg.id = kvm_v_vlenb.kvm_reg_id; 1953 reg.addr = (uint64_t)&val; 1954 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1955 if (ret != 0) { 1956 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1957 return; 1958 } 1959 1960 if (cpu->cfg.vlenb != val) { 1961 error_setg(errp, "Unable to set 'vlen' to a different " 1962 "value than the host (%lu)", val * 8); 1963 return; 1964 } 1965 } 1966 1967 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1968 } 1969 1970 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1971 { 1972 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1973 1974 acc->cpu_instance_init = kvm_cpu_instance_init; 1975 acc->cpu_target_realize = kvm_cpu_realize; 1976 } 1977 1978 static const TypeInfo kvm_cpu_accel_type_info = { 1979 .name = ACCEL_CPU_NAME("kvm"), 1980 1981 .parent = TYPE_ACCEL_CPU, 1982 .class_init = kvm_cpu_accel_class_init, 1983 .abstract = true, 1984 }; 1985 static void kvm_cpu_accel_register_types(void) 1986 { 1987 type_register_static(&kvm_cpu_accel_type_info); 1988 } 1989 type_init(kvm_cpu_accel_register_types); 1990 1991 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 1992 { 1993 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1994 1995 #if defined(TARGET_RISCV32) 1996 mcc->misa_mxl_max = MXL_RV32; 1997 #elif defined(TARGET_RISCV64) 1998 mcc->misa_mxl_max = MXL_RV64; 1999 #endif 2000 } 2001 2002 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2003 { 2004 .name = TYPE_RISCV_CPU_HOST, 2005 .parent = TYPE_RISCV_CPU, 2006 .class_init = riscv_host_cpu_class_init, 2007 } 2008 }; 2009 2010 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2011 2012 static const uint32_t ebreak_insn = 0x00100073; 2013 static const uint16_t c_ebreak_insn = 0x9002; 2014 2015 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2016 { 2017 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2018 return -EINVAL; 2019 } 2020 2021 if ((bp->saved_insn & 0x3) == 0x3) { 2022 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2023 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2024 return -EINVAL; 2025 } 2026 } else { 2027 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2028 return -EINVAL; 2029 } 2030 } 2031 2032 return 0; 2033 } 2034 2035 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2036 { 2037 uint32_t ebreak; 2038 uint16_t c_ebreak; 2039 2040 if ((bp->saved_insn & 0x3) == 0x3) { 2041 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2042 ebreak != ebreak_insn || 2043 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2044 return -EINVAL; 2045 } 2046 } else { 2047 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2048 c_ebreak != c_ebreak_insn || 2049 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2050 return -EINVAL; 2051 } 2052 } 2053 2054 return 0; 2055 } 2056 2057 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2058 { 2059 /* TODO; To be implemented later. */ 2060 return -EINVAL; 2061 } 2062 2063 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2064 { 2065 /* TODO; To be implemented later. */ 2066 return -EINVAL; 2067 } 2068 2069 void kvm_arch_remove_all_hw_breakpoints(void) 2070 { 2071 /* TODO; To be implemented later. */ 2072 } 2073 2074 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2075 { 2076 if (kvm_sw_breakpoints_active(cs)) { 2077 dbg->control |= KVM_GUESTDBG_ENABLE; 2078 } 2079 } 2080