1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value, host_bit; 152 153 if (!visit_type_bool(v, name, &value, errp)) { 154 return; 155 } 156 157 host_bit = env->misa_ext_mask & misa_bit; 158 159 if (value == host_bit) { 160 return; 161 } 162 163 if (!value) { 164 misa_ext_cfg->user_set = true; 165 return; 166 } 167 168 /* 169 * Forbid users to enable extensions that aren't 170 * available in the hart. 171 */ 172 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 173 "enabled in the host", misa_ext_cfg->name); 174 } 175 176 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 177 { 178 CPURISCVState *env = &cpu->env; 179 uint64_t id, reg; 180 int i, ret; 181 182 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 183 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 184 target_ulong misa_bit = misa_cfg->offset; 185 186 if (!misa_cfg->user_set) { 187 continue; 188 } 189 190 /* If we're here we're going to disable the MISA bit */ 191 reg = 0; 192 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 193 misa_cfg->kvm_reg_id); 194 ret = kvm_set_one_reg(cs, id, ®); 195 if (ret != 0) { 196 /* 197 * We're not checking for -EINVAL because if the bit is about 198 * to be disabled, it means that it was already enabled by 199 * KVM. We determined that by fetching the 'isa' register 200 * during init() time. Any error at this point is worth 201 * aborting. 202 */ 203 error_report("Unable to set KVM reg %s, error %d", 204 misa_cfg->name, ret); 205 exit(EXIT_FAILURE); 206 } 207 env->misa_ext &= ~misa_bit; 208 } 209 } 210 211 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 212 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 213 .kvm_reg_id = _reg_id} 214 215 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 216 KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM), 217 KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ), 218 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 219 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 220 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 221 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 222 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 223 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 224 }; 225 226 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 227 { 228 return (void *)&cpu->cfg + kvmcfg->offset; 229 } 230 231 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 232 uint32_t val) 233 { 234 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 235 236 *ext_enabled = val; 237 } 238 239 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 240 KVMCPUConfig *multi_ext) 241 { 242 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 243 244 return *ext_enabled; 245 } 246 247 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 248 const char *name, 249 void *opaque, Error **errp) 250 { 251 KVMCPUConfig *multi_ext_cfg = opaque; 252 RISCVCPU *cpu = RISCV_CPU(obj); 253 bool value, host_val; 254 255 if (!visit_type_bool(v, name, &value, errp)) { 256 return; 257 } 258 259 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 260 261 /* 262 * Ignore if the user is setting the same value 263 * as the host. 264 */ 265 if (value == host_val) { 266 return; 267 } 268 269 if (!multi_ext_cfg->supported) { 270 /* 271 * Error out if the user is trying to enable an 272 * extension that KVM doesn't support. Ignore 273 * option otherwise. 274 */ 275 if (value) { 276 error_setg(errp, "KVM does not support disabling extension %s", 277 multi_ext_cfg->name); 278 } 279 280 return; 281 } 282 283 multi_ext_cfg->user_set = true; 284 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 285 } 286 287 static KVMCPUConfig kvm_cbom_blocksize = { 288 .name = "cbom_blocksize", 289 .offset = CPU_CFG_OFFSET(cbom_blocksize), 290 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 291 }; 292 293 static KVMCPUConfig kvm_cboz_blocksize = { 294 .name = "cboz_blocksize", 295 .offset = CPU_CFG_OFFSET(cboz_blocksize), 296 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 297 }; 298 299 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 300 const char *name, 301 void *opaque, Error **errp) 302 { 303 KVMCPUConfig *cbomz_cfg = opaque; 304 RISCVCPU *cpu = RISCV_CPU(obj); 305 uint16_t value, *host_val; 306 307 if (!visit_type_uint16(v, name, &value, errp)) { 308 return; 309 } 310 311 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 312 313 if (value != *host_val) { 314 error_report("Unable to set %s to a different value than " 315 "the host (%u)", 316 cbomz_cfg->name, *host_val); 317 exit(EXIT_FAILURE); 318 } 319 320 cbomz_cfg->user_set = true; 321 } 322 323 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 324 { 325 CPURISCVState *env = &cpu->env; 326 uint64_t id, reg; 327 int i, ret; 328 329 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 330 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 331 332 if (!multi_ext_cfg->user_set) { 333 continue; 334 } 335 336 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 337 multi_ext_cfg->kvm_reg_id); 338 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 339 ret = kvm_set_one_reg(cs, id, ®); 340 if (ret != 0) { 341 error_report("Unable to %s extension %s in KVM, error %d", 342 reg ? "enable" : "disable", 343 multi_ext_cfg->name, ret); 344 exit(EXIT_FAILURE); 345 } 346 } 347 } 348 349 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 350 const char *name, 351 void *opaque, Error **errp) 352 { 353 const char *propname = opaque; 354 bool value; 355 356 if (!visit_type_bool(v, name, &value, errp)) { 357 return; 358 } 359 360 if (value) { 361 error_setg(errp, "extension %s is not available with KVM", 362 propname); 363 } 364 } 365 366 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 367 { 368 /* Check if KVM created the property already */ 369 if (object_property_find(obj, prop_name)) { 370 return; 371 } 372 373 /* 374 * Set the default to disabled for every extension 375 * unknown to KVM and error out if the user attempts 376 * to enable any of them. 377 */ 378 object_property_add(obj, prop_name, "bool", 379 NULL, cpu_set_cfg_unavailable, 380 NULL, (void *)prop_name); 381 } 382 383 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 384 const RISCVCPUMultiExtConfig *array) 385 { 386 const RISCVCPUMultiExtConfig *prop; 387 388 g_assert(array); 389 390 for (prop = array; prop && prop->name; prop++) { 391 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 392 } 393 } 394 395 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 396 { 397 int i; 398 399 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 400 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 401 int bit = misa_cfg->offset; 402 403 misa_cfg->name = riscv_get_misa_ext_name(bit); 404 misa_cfg->description = riscv_get_misa_ext_description(bit); 405 406 object_property_add(cpu_obj, misa_cfg->name, "bool", 407 NULL, 408 kvm_cpu_set_misa_ext_cfg, 409 NULL, misa_cfg); 410 object_property_set_description(cpu_obj, misa_cfg->name, 411 misa_cfg->description); 412 } 413 414 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 415 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 416 417 object_property_add(cpu_obj, multi_cfg->name, "bool", 418 NULL, 419 kvm_cpu_set_multi_ext_cfg, 420 NULL, multi_cfg); 421 } 422 423 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 424 NULL, kvm_cpu_set_cbomz_blksize, 425 NULL, &kvm_cbom_blocksize); 426 427 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 428 NULL, kvm_cpu_set_cbomz_blksize, 429 NULL, &kvm_cboz_blocksize); 430 } 431 432 static int kvm_riscv_get_regs_core(CPUState *cs) 433 { 434 int ret = 0; 435 int i; 436 target_ulong reg; 437 CPURISCVState *env = &RISCV_CPU(cs)->env; 438 439 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 440 if (ret) { 441 return ret; 442 } 443 env->pc = reg; 444 445 for (i = 1; i < 32; i++) { 446 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 447 ret = kvm_get_one_reg(cs, id, ®); 448 if (ret) { 449 return ret; 450 } 451 env->gpr[i] = reg; 452 } 453 454 return ret; 455 } 456 457 static int kvm_riscv_put_regs_core(CPUState *cs) 458 { 459 int ret = 0; 460 int i; 461 target_ulong reg; 462 CPURISCVState *env = &RISCV_CPU(cs)->env; 463 464 reg = env->pc; 465 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 466 if (ret) { 467 return ret; 468 } 469 470 for (i = 1; i < 32; i++) { 471 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 472 reg = env->gpr[i]; 473 ret = kvm_set_one_reg(cs, id, ®); 474 if (ret) { 475 return ret; 476 } 477 } 478 479 return ret; 480 } 481 482 static int kvm_riscv_get_regs_csr(CPUState *cs) 483 { 484 int ret = 0; 485 CPURISCVState *env = &RISCV_CPU(cs)->env; 486 487 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 488 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 489 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 490 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 491 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 492 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 493 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 494 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 495 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 496 return ret; 497 } 498 499 static int kvm_riscv_put_regs_csr(CPUState *cs) 500 { 501 int ret = 0; 502 CPURISCVState *env = &RISCV_CPU(cs)->env; 503 504 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 505 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 506 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 507 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 508 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 509 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 510 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 511 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 512 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 513 514 return ret; 515 } 516 517 static int kvm_riscv_get_regs_fp(CPUState *cs) 518 { 519 int ret = 0; 520 int i; 521 CPURISCVState *env = &RISCV_CPU(cs)->env; 522 523 if (riscv_has_ext(env, RVD)) { 524 uint64_t reg; 525 for (i = 0; i < 32; i++) { 526 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 527 if (ret) { 528 return ret; 529 } 530 env->fpr[i] = reg; 531 } 532 return ret; 533 } 534 535 if (riscv_has_ext(env, RVF)) { 536 uint32_t reg; 537 for (i = 0; i < 32; i++) { 538 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 539 if (ret) { 540 return ret; 541 } 542 env->fpr[i] = reg; 543 } 544 return ret; 545 } 546 547 return ret; 548 } 549 550 static int kvm_riscv_put_regs_fp(CPUState *cs) 551 { 552 int ret = 0; 553 int i; 554 CPURISCVState *env = &RISCV_CPU(cs)->env; 555 556 if (riscv_has_ext(env, RVD)) { 557 uint64_t reg; 558 for (i = 0; i < 32; i++) { 559 reg = env->fpr[i]; 560 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 561 if (ret) { 562 return ret; 563 } 564 } 565 return ret; 566 } 567 568 if (riscv_has_ext(env, RVF)) { 569 uint32_t reg; 570 for (i = 0; i < 32; i++) { 571 reg = env->fpr[i]; 572 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 573 if (ret) { 574 return ret; 575 } 576 } 577 return ret; 578 } 579 580 return ret; 581 } 582 583 static void kvm_riscv_get_regs_timer(CPUState *cs) 584 { 585 CPURISCVState *env = &RISCV_CPU(cs)->env; 586 587 if (env->kvm_timer_dirty) { 588 return; 589 } 590 591 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 592 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 593 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 594 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 595 596 env->kvm_timer_dirty = true; 597 } 598 599 static void kvm_riscv_put_regs_timer(CPUState *cs) 600 { 601 uint64_t reg; 602 CPURISCVState *env = &RISCV_CPU(cs)->env; 603 604 if (!env->kvm_timer_dirty) { 605 return; 606 } 607 608 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 609 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 610 611 /* 612 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 613 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 614 * doesn't matter that adaping in QEMU now. 615 * TODO If KVM changes, adapt here. 616 */ 617 if (env->kvm_timer_state) { 618 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 619 } 620 621 /* 622 * For now, migration will not work between Hosts with different timer 623 * frequency. Therefore, we should check whether they are the same here 624 * during the migration. 625 */ 626 if (migration_is_running(migrate_get_current()->state)) { 627 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 628 if (reg != env->kvm_timer_frequency) { 629 error_report("Dst Hosts timer frequency != Src Hosts"); 630 } 631 } 632 633 env->kvm_timer_dirty = false; 634 } 635 636 typedef struct KVMScratchCPU { 637 int kvmfd; 638 int vmfd; 639 int cpufd; 640 } KVMScratchCPU; 641 642 /* 643 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 644 * from target/arm/kvm.c. 645 */ 646 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 647 { 648 int kvmfd = -1, vmfd = -1, cpufd = -1; 649 650 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 651 if (kvmfd < 0) { 652 goto err; 653 } 654 do { 655 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 656 } while (vmfd == -1 && errno == EINTR); 657 if (vmfd < 0) { 658 goto err; 659 } 660 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 661 if (cpufd < 0) { 662 goto err; 663 } 664 665 scratch->kvmfd = kvmfd; 666 scratch->vmfd = vmfd; 667 scratch->cpufd = cpufd; 668 669 return true; 670 671 err: 672 if (cpufd >= 0) { 673 close(cpufd); 674 } 675 if (vmfd >= 0) { 676 close(vmfd); 677 } 678 if (kvmfd >= 0) { 679 close(kvmfd); 680 } 681 682 return false; 683 } 684 685 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 686 { 687 close(scratch->cpufd); 688 close(scratch->vmfd); 689 close(scratch->kvmfd); 690 } 691 692 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 693 { 694 CPURISCVState *env = &cpu->env; 695 struct kvm_one_reg reg; 696 int ret; 697 698 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 699 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 700 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 701 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 702 if (ret != 0) { 703 error_report("Unable to retrieve mvendorid from host, error %d", ret); 704 } 705 706 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 707 KVM_REG_RISCV_CONFIG_REG(marchid)); 708 reg.addr = (uint64_t)&cpu->cfg.marchid; 709 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 710 if (ret != 0) { 711 error_report("Unable to retrieve marchid from host, error %d", ret); 712 } 713 714 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 715 KVM_REG_RISCV_CONFIG_REG(mimpid)); 716 reg.addr = (uint64_t)&cpu->cfg.mimpid; 717 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 718 if (ret != 0) { 719 error_report("Unable to retrieve mimpid from host, error %d", ret); 720 } 721 } 722 723 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 724 KVMScratchCPU *kvmcpu) 725 { 726 CPURISCVState *env = &cpu->env; 727 struct kvm_one_reg reg; 728 int ret; 729 730 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 731 KVM_REG_RISCV_CONFIG_REG(isa)); 732 reg.addr = (uint64_t)&env->misa_ext_mask; 733 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 734 735 if (ret) { 736 error_report("Unable to fetch ISA register from KVM, " 737 "error %d", ret); 738 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 739 exit(EXIT_FAILURE); 740 } 741 742 env->misa_ext = env->misa_ext_mask; 743 } 744 745 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 746 KVMCPUConfig *cbomz_cfg) 747 { 748 CPURISCVState *env = &cpu->env; 749 struct kvm_one_reg reg; 750 int ret; 751 752 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 753 cbomz_cfg->kvm_reg_id); 754 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 755 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 756 if (ret != 0) { 757 error_report("Unable to read KVM reg %s, error %d", 758 cbomz_cfg->name, ret); 759 exit(EXIT_FAILURE); 760 } 761 } 762 763 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 764 { 765 CPURISCVState *env = &cpu->env; 766 uint64_t val; 767 int i, ret; 768 769 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 770 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 771 struct kvm_one_reg reg; 772 773 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 774 multi_ext_cfg->kvm_reg_id); 775 reg.addr = (uint64_t)&val; 776 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 777 if (ret != 0) { 778 if (errno == EINVAL) { 779 /* Silently default to 'false' if KVM does not support it. */ 780 multi_ext_cfg->supported = false; 781 val = false; 782 } else { 783 error_report("Unable to read ISA_EXT KVM register %s, " 784 "error %d", multi_ext_cfg->name, ret); 785 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 786 exit(EXIT_FAILURE); 787 } 788 } else { 789 multi_ext_cfg->supported = true; 790 } 791 792 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 793 } 794 795 if (cpu->cfg.ext_icbom) { 796 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 797 } 798 799 if (cpu->cfg.ext_icboz) { 800 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 801 } 802 } 803 804 static void riscv_init_user_properties(Object *cpu_obj) 805 { 806 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 807 KVMScratchCPU kvmcpu; 808 809 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 810 return; 811 } 812 813 kvm_riscv_add_cpu_user_properties(cpu_obj); 814 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 815 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 816 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 817 818 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 819 } 820 821 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 822 KVM_CAP_LAST_INFO 823 }; 824 825 int kvm_arch_get_registers(CPUState *cs) 826 { 827 int ret = 0; 828 829 ret = kvm_riscv_get_regs_core(cs); 830 if (ret) { 831 return ret; 832 } 833 834 ret = kvm_riscv_get_regs_csr(cs); 835 if (ret) { 836 return ret; 837 } 838 839 ret = kvm_riscv_get_regs_fp(cs); 840 if (ret) { 841 return ret; 842 } 843 844 return ret; 845 } 846 847 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 848 { 849 if (cap_has_mp_state) { 850 struct kvm_mp_state mp_state = { 851 .mp_state = state 852 }; 853 854 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 855 if (ret) { 856 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 857 __func__, ret, strerror(-ret)); 858 return -1; 859 } 860 } 861 862 return 0; 863 } 864 865 int kvm_arch_put_registers(CPUState *cs, int level) 866 { 867 int ret = 0; 868 869 ret = kvm_riscv_put_regs_core(cs); 870 if (ret) { 871 return ret; 872 } 873 874 ret = kvm_riscv_put_regs_csr(cs); 875 if (ret) { 876 return ret; 877 } 878 879 ret = kvm_riscv_put_regs_fp(cs); 880 if (ret) { 881 return ret; 882 } 883 884 if (KVM_PUT_RESET_STATE == level) { 885 RISCVCPU *cpu = RISCV_CPU(cs); 886 if (cs->cpu_index == 0) { 887 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 888 } else { 889 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 890 } 891 if (ret) { 892 return ret; 893 } 894 } 895 896 return ret; 897 } 898 899 int kvm_arch_release_virq_post(int virq) 900 { 901 return 0; 902 } 903 904 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 905 uint64_t address, uint32_t data, PCIDevice *dev) 906 { 907 return 0; 908 } 909 910 int kvm_arch_destroy_vcpu(CPUState *cs) 911 { 912 return 0; 913 } 914 915 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 916 { 917 return cpu->cpu_index; 918 } 919 920 static void kvm_riscv_vm_state_change(void *opaque, bool running, 921 RunState state) 922 { 923 CPUState *cs = opaque; 924 925 if (running) { 926 kvm_riscv_put_regs_timer(cs); 927 } else { 928 kvm_riscv_get_regs_timer(cs); 929 } 930 } 931 932 void kvm_arch_init_irq_routing(KVMState *s) 933 { 934 } 935 936 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 937 { 938 CPURISCVState *env = &cpu->env; 939 target_ulong reg; 940 uint64_t id; 941 int ret; 942 943 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 944 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 945 /* 946 * cfg.mvendorid is an uint32 but a target_ulong will 947 * be written. Assign it to a target_ulong var to avoid 948 * writing pieces of other cpu->cfg fields in the reg. 949 */ 950 reg = cpu->cfg.mvendorid; 951 ret = kvm_set_one_reg(cs, id, ®); 952 if (ret != 0) { 953 return ret; 954 } 955 956 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 957 KVM_REG_RISCV_CONFIG_REG(marchid)); 958 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 959 if (ret != 0) { 960 return ret; 961 } 962 963 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 964 KVM_REG_RISCV_CONFIG_REG(mimpid)); 965 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 966 967 return ret; 968 } 969 970 int kvm_arch_init_vcpu(CPUState *cs) 971 { 972 int ret = 0; 973 RISCVCPU *cpu = RISCV_CPU(cs); 974 975 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 976 977 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 978 ret = kvm_vcpu_set_machine_ids(cpu, cs); 979 if (ret != 0) { 980 return ret; 981 } 982 } 983 984 kvm_riscv_update_cpu_misa_ext(cpu, cs); 985 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 986 987 return ret; 988 } 989 990 int kvm_arch_msi_data_to_gsi(uint32_t data) 991 { 992 abort(); 993 } 994 995 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 996 int vector, PCIDevice *dev) 997 { 998 return 0; 999 } 1000 1001 int kvm_arch_get_default_type(MachineState *ms) 1002 { 1003 return 0; 1004 } 1005 1006 int kvm_arch_init(MachineState *ms, KVMState *s) 1007 { 1008 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1009 return 0; 1010 } 1011 1012 int kvm_arch_irqchip_create(KVMState *s) 1013 { 1014 if (kvm_kernel_irqchip_split()) { 1015 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1016 exit(1); 1017 } 1018 1019 /* 1020 * We can create the VAIA using the newer device control API. 1021 */ 1022 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1023 } 1024 1025 int kvm_arch_process_async_events(CPUState *cs) 1026 { 1027 return 0; 1028 } 1029 1030 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1031 { 1032 } 1033 1034 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1035 { 1036 return MEMTXATTRS_UNSPECIFIED; 1037 } 1038 1039 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1040 { 1041 return true; 1042 } 1043 1044 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1045 { 1046 int ret = 0; 1047 unsigned char ch; 1048 switch (run->riscv_sbi.extension_id) { 1049 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1050 ch = run->riscv_sbi.args[0]; 1051 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1052 break; 1053 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1054 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1055 if (ret == sizeof(ch)) { 1056 run->riscv_sbi.ret[0] = ch; 1057 } else { 1058 run->riscv_sbi.ret[0] = -1; 1059 } 1060 ret = 0; 1061 break; 1062 default: 1063 qemu_log_mask(LOG_UNIMP, 1064 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1065 __func__, run->riscv_sbi.extension_id); 1066 ret = -1; 1067 break; 1068 } 1069 return ret; 1070 } 1071 1072 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1073 { 1074 int ret = 0; 1075 switch (run->exit_reason) { 1076 case KVM_EXIT_RISCV_SBI: 1077 ret = kvm_riscv_handle_sbi(cs, run); 1078 break; 1079 default: 1080 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1081 __func__, run->exit_reason); 1082 ret = -1; 1083 break; 1084 } 1085 return ret; 1086 } 1087 1088 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1089 { 1090 CPURISCVState *env = &cpu->env; 1091 int i; 1092 1093 if (!kvm_enabled()) { 1094 return; 1095 } 1096 for (i = 0; i < 32; i++) { 1097 env->gpr[i] = 0; 1098 } 1099 env->pc = cpu->env.kernel_addr; 1100 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1101 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1102 env->satp = 0; 1103 env->mie = 0; 1104 env->stvec = 0; 1105 env->sscratch = 0; 1106 env->sepc = 0; 1107 env->scause = 0; 1108 env->stval = 0; 1109 env->mip = 0; 1110 } 1111 1112 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1113 { 1114 int ret; 1115 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1116 1117 if (irq != IRQ_S_EXT) { 1118 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1119 abort(); 1120 } 1121 1122 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1123 if (ret < 0) { 1124 perror("Set irq failed"); 1125 abort(); 1126 } 1127 } 1128 1129 bool kvm_arch_cpu_check_are_resettable(void) 1130 { 1131 return true; 1132 } 1133 1134 static int aia_mode; 1135 1136 static const char *kvm_aia_mode_str(uint64_t mode) 1137 { 1138 switch (mode) { 1139 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1140 return "emul"; 1141 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1142 return "hwaccel"; 1143 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1144 default: 1145 return "auto"; 1146 }; 1147 } 1148 1149 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1150 { 1151 return g_strdup(kvm_aia_mode_str(aia_mode)); 1152 } 1153 1154 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1155 { 1156 if (!strcmp(val, "emul")) { 1157 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1158 } else if (!strcmp(val, "hwaccel")) { 1159 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1160 } else if (!strcmp(val, "auto")) { 1161 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1162 } else { 1163 error_setg(errp, "Invalid KVM AIA mode"); 1164 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1165 } 1166 } 1167 1168 void kvm_arch_accel_class_init(ObjectClass *oc) 1169 { 1170 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1171 riscv_set_kvm_aia); 1172 object_class_property_set_description(oc, "riscv-aia", 1173 "Set KVM AIA mode. Valid values are " 1174 "emul, hwaccel, and auto. Default " 1175 "is auto."); 1176 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1177 "auto"); 1178 } 1179 1180 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1181 uint64_t aia_irq_num, uint64_t aia_msi_num, 1182 uint64_t aplic_base, uint64_t imsic_base, 1183 uint64_t guest_num) 1184 { 1185 int ret, i; 1186 int aia_fd = -1; 1187 uint64_t default_aia_mode; 1188 uint64_t socket_count = riscv_socket_count(machine); 1189 uint64_t max_hart_per_socket = 0; 1190 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1191 uint64_t socket_bits, hart_bits, guest_bits; 1192 1193 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1194 1195 if (aia_fd < 0) { 1196 error_report("Unable to create in-kernel irqchip"); 1197 exit(1); 1198 } 1199 1200 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1201 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1202 &default_aia_mode, false, NULL); 1203 if (ret < 0) { 1204 error_report("KVM AIA: failed to get current KVM AIA mode"); 1205 exit(1); 1206 } 1207 qemu_log("KVM AIA: default mode is %s\n", 1208 kvm_aia_mode_str(default_aia_mode)); 1209 1210 if (default_aia_mode != aia_mode) { 1211 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1212 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1213 &aia_mode, true, NULL); 1214 if (ret < 0) 1215 warn_report("KVM AIA: failed to set KVM AIA mode"); 1216 else 1217 qemu_log("KVM AIA: set current mode to %s\n", 1218 kvm_aia_mode_str(aia_mode)); 1219 } 1220 1221 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1222 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1223 &aia_irq_num, true, NULL); 1224 if (ret < 0) { 1225 error_report("KVM AIA: failed to set number of input irq lines"); 1226 exit(1); 1227 } 1228 1229 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1230 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1231 &aia_msi_num, true, NULL); 1232 if (ret < 0) { 1233 error_report("KVM AIA: failed to set number of msi"); 1234 exit(1); 1235 } 1236 1237 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1238 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1239 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1240 &socket_bits, true, NULL); 1241 if (ret < 0) { 1242 error_report("KVM AIA: failed to set group_bits"); 1243 exit(1); 1244 } 1245 1246 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1247 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1248 &group_shift, true, NULL); 1249 if (ret < 0) { 1250 error_report("KVM AIA: failed to set group_shift"); 1251 exit(1); 1252 } 1253 1254 guest_bits = guest_num == 0 ? 0 : 1255 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1256 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1257 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1258 &guest_bits, true, NULL); 1259 if (ret < 0) { 1260 error_report("KVM AIA: failed to set guest_bits"); 1261 exit(1); 1262 } 1263 1264 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1265 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1266 &aplic_base, true, NULL); 1267 if (ret < 0) { 1268 error_report("KVM AIA: failed to set the base address of APLIC"); 1269 exit(1); 1270 } 1271 1272 for (socket = 0; socket < socket_count; socket++) { 1273 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1274 hart_count = riscv_socket_hart_count(machine, socket); 1275 base_hart = riscv_socket_first_hartid(machine, socket); 1276 1277 if (max_hart_per_socket < hart_count) { 1278 max_hart_per_socket = hart_count; 1279 } 1280 1281 for (i = 0; i < hart_count; i++) { 1282 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1283 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1284 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1285 &imsic_addr, true, NULL); 1286 if (ret < 0) { 1287 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1288 exit(1); 1289 } 1290 } 1291 } 1292 1293 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1294 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1295 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1296 &hart_bits, true, NULL); 1297 if (ret < 0) { 1298 error_report("KVM AIA: failed to set hart_bits"); 1299 exit(1); 1300 } 1301 1302 if (kvm_has_gsi_routing()) { 1303 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1304 /* KVM AIA only has one APLIC instance */ 1305 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1306 } 1307 kvm_gsi_routing_allowed = true; 1308 kvm_irqchip_commit_routes(kvm_state); 1309 } 1310 1311 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1312 KVM_DEV_RISCV_AIA_CTRL_INIT, 1313 NULL, true, NULL); 1314 if (ret < 0) { 1315 error_report("KVM AIA: initialized fail"); 1316 exit(1); 1317 } 1318 1319 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 1320 } 1321 1322 static void kvm_cpu_instance_init(CPUState *cs) 1323 { 1324 Object *obj = OBJECT(RISCV_CPU(cs)); 1325 DeviceState *dev = DEVICE(obj); 1326 1327 riscv_init_user_properties(obj); 1328 riscv_add_satp_mode_properties(obj); 1329 riscv_cpu_add_misa_properties(obj); 1330 1331 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); 1332 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); 1333 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); 1334 1335 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1336 /* Check if we have a specific KVM handler for the option */ 1337 if (object_property_find(obj, prop->name)) { 1338 continue; 1339 } 1340 qdev_property_add_static(dev, prop); 1341 } 1342 } 1343 1344 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1345 { 1346 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1347 1348 acc->cpu_instance_init = kvm_cpu_instance_init; 1349 } 1350 1351 static const TypeInfo kvm_cpu_accel_type_info = { 1352 .name = ACCEL_CPU_NAME("kvm"), 1353 1354 .parent = TYPE_ACCEL_CPU, 1355 .class_init = kvm_cpu_accel_class_init, 1356 .abstract = true, 1357 }; 1358 static void kvm_cpu_accel_register_types(void) 1359 { 1360 type_register_static(&kvm_cpu_accel_type_info); 1361 } 1362 type_init(kvm_cpu_accel_register_types); 1363 1364 static void riscv_host_cpu_init(Object *obj) 1365 { 1366 CPURISCVState *env = &RISCV_CPU(obj)->env; 1367 1368 #if defined(TARGET_RISCV32) 1369 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1370 #elif defined(TARGET_RISCV64) 1371 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1372 #endif 1373 } 1374 1375 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1376 { 1377 .name = TYPE_RISCV_CPU_HOST, 1378 .parent = TYPE_RISCV_CPU, 1379 .instance_init = riscv_host_cpu_init, 1380 } 1381 }; 1382 1383 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1384