1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value = env->misa_ext_mask & misa_bit; 152 153 visit_type_bool(v, name, &value, errp); 154 } 155 156 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 157 const char *name, 158 void *opaque, Error **errp) 159 { 160 KVMCPUConfig *misa_ext_cfg = opaque; 161 target_ulong misa_bit = misa_ext_cfg->offset; 162 RISCVCPU *cpu = RISCV_CPU(obj); 163 CPURISCVState *env = &cpu->env; 164 bool value, host_bit; 165 166 if (!visit_type_bool(v, name, &value, errp)) { 167 return; 168 } 169 170 host_bit = env->misa_ext_mask & misa_bit; 171 172 if (value == host_bit) { 173 return; 174 } 175 176 if (!value) { 177 misa_ext_cfg->user_set = true; 178 return; 179 } 180 181 /* 182 * Forbid users to enable extensions that aren't 183 * available in the hart. 184 */ 185 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 186 "enabled in the host", misa_ext_cfg->name); 187 } 188 189 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 190 { 191 CPURISCVState *env = &cpu->env; 192 uint64_t id, reg; 193 int i, ret; 194 195 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 196 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 197 target_ulong misa_bit = misa_cfg->offset; 198 199 if (!misa_cfg->user_set) { 200 continue; 201 } 202 203 /* If we're here we're going to disable the MISA bit */ 204 reg = 0; 205 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 206 misa_cfg->kvm_reg_id); 207 ret = kvm_set_one_reg(cs, id, ®); 208 if (ret != 0) { 209 /* 210 * We're not checking for -EINVAL because if the bit is about 211 * to be disabled, it means that it was already enabled by 212 * KVM. We determined that by fetching the 'isa' register 213 * during init() time. Any error at this point is worth 214 * aborting. 215 */ 216 error_report("Unable to set KVM reg %s, error %d", 217 misa_cfg->name, ret); 218 exit(EXIT_FAILURE); 219 } 220 env->misa_ext &= ~misa_bit; 221 } 222 } 223 224 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 225 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 226 .kvm_reg_id = _reg_id} 227 228 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 229 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 230 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 231 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 232 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 233 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 234 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 235 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 236 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 237 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 238 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 239 }; 240 241 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 242 { 243 return (void *)&cpu->cfg + kvmcfg->offset; 244 } 245 246 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 247 uint32_t val) 248 { 249 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 250 251 *ext_enabled = val; 252 } 253 254 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 255 KVMCPUConfig *multi_ext) 256 { 257 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 258 259 return *ext_enabled; 260 } 261 262 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 263 const char *name, 264 void *opaque, Error **errp) 265 { 266 KVMCPUConfig *multi_ext_cfg = opaque; 267 RISCVCPU *cpu = RISCV_CPU(obj); 268 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 269 270 visit_type_bool(v, name, &value, errp); 271 } 272 273 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 274 const char *name, 275 void *opaque, Error **errp) 276 { 277 KVMCPUConfig *multi_ext_cfg = opaque; 278 RISCVCPU *cpu = RISCV_CPU(obj); 279 bool value, host_val; 280 281 if (!visit_type_bool(v, name, &value, errp)) { 282 return; 283 } 284 285 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 286 287 /* 288 * Ignore if the user is setting the same value 289 * as the host. 290 */ 291 if (value == host_val) { 292 return; 293 } 294 295 if (!multi_ext_cfg->supported) { 296 /* 297 * Error out if the user is trying to enable an 298 * extension that KVM doesn't support. Ignore 299 * option otherwise. 300 */ 301 if (value) { 302 error_setg(errp, "KVM does not support disabling extension %s", 303 multi_ext_cfg->name); 304 } 305 306 return; 307 } 308 309 multi_ext_cfg->user_set = true; 310 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 311 } 312 313 static KVMCPUConfig kvm_cbom_blocksize = { 314 .name = "cbom_blocksize", 315 .offset = CPU_CFG_OFFSET(cbom_blocksize), 316 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 317 }; 318 319 static KVMCPUConfig kvm_cboz_blocksize = { 320 .name = "cboz_blocksize", 321 .offset = CPU_CFG_OFFSET(cboz_blocksize), 322 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 323 }; 324 325 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 326 const char *name, 327 void *opaque, Error **errp) 328 { 329 KVMCPUConfig *cbomz_cfg = opaque; 330 RISCVCPU *cpu = RISCV_CPU(obj); 331 uint16_t value, *host_val; 332 333 if (!visit_type_uint16(v, name, &value, errp)) { 334 return; 335 } 336 337 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 338 339 if (value != *host_val) { 340 error_report("Unable to set %s to a different value than " 341 "the host (%u)", 342 cbomz_cfg->name, *host_val); 343 exit(EXIT_FAILURE); 344 } 345 346 cbomz_cfg->user_set = true; 347 } 348 349 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 350 { 351 CPURISCVState *env = &cpu->env; 352 uint64_t id, reg; 353 int i, ret; 354 355 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 356 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 357 358 if (!multi_ext_cfg->user_set) { 359 continue; 360 } 361 362 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 363 multi_ext_cfg->kvm_reg_id); 364 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 365 ret = kvm_set_one_reg(cs, id, ®); 366 if (ret != 0) { 367 error_report("Unable to %s extension %s in KVM, error %d", 368 reg ? "enable" : "disable", 369 multi_ext_cfg->name, ret); 370 exit(EXIT_FAILURE); 371 } 372 } 373 } 374 375 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 376 const char *name, 377 void *opaque, Error **errp) 378 { 379 bool value = false; 380 381 visit_type_bool(v, name, &value, errp); 382 } 383 384 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 385 const char *name, 386 void *opaque, Error **errp) 387 { 388 const char *propname = opaque; 389 bool value; 390 391 if (!visit_type_bool(v, name, &value, errp)) { 392 return; 393 } 394 395 if (value) { 396 error_setg(errp, "extension %s is not available with KVM", 397 propname); 398 } 399 } 400 401 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 402 { 403 /* Check if KVM created the property already */ 404 if (object_property_find(obj, prop_name)) { 405 return; 406 } 407 408 /* 409 * Set the default to disabled for every extension 410 * unknown to KVM and error out if the user attempts 411 * to enable any of them. 412 */ 413 object_property_add(obj, prop_name, "bool", 414 cpu_get_cfg_unavailable, 415 cpu_set_cfg_unavailable, 416 NULL, (void *)prop_name); 417 } 418 419 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 420 const RISCVCPUMultiExtConfig *array) 421 { 422 const RISCVCPUMultiExtConfig *prop; 423 424 g_assert(array); 425 426 for (prop = array; prop && prop->name; prop++) { 427 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 428 } 429 } 430 431 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 432 { 433 int i; 434 435 riscv_add_satp_mode_properties(cpu_obj); 436 437 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 438 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 439 int bit = misa_cfg->offset; 440 441 misa_cfg->name = riscv_get_misa_ext_name(bit); 442 misa_cfg->description = riscv_get_misa_ext_description(bit); 443 444 object_property_add(cpu_obj, misa_cfg->name, "bool", 445 kvm_cpu_get_misa_ext_cfg, 446 kvm_cpu_set_misa_ext_cfg, 447 NULL, misa_cfg); 448 object_property_set_description(cpu_obj, misa_cfg->name, 449 misa_cfg->description); 450 } 451 452 for (i = 0; misa_bits[i] != 0; i++) { 453 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 454 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 455 } 456 457 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 458 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 459 460 object_property_add(cpu_obj, multi_cfg->name, "bool", 461 kvm_cpu_get_multi_ext_cfg, 462 kvm_cpu_set_multi_ext_cfg, 463 NULL, multi_cfg); 464 } 465 466 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 467 NULL, kvm_cpu_set_cbomz_blksize, 468 NULL, &kvm_cbom_blocksize); 469 470 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 471 NULL, kvm_cpu_set_cbomz_blksize, 472 NULL, &kvm_cboz_blocksize); 473 474 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 475 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 476 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 477 } 478 479 static int kvm_riscv_get_regs_core(CPUState *cs) 480 { 481 int ret = 0; 482 int i; 483 target_ulong reg; 484 CPURISCVState *env = &RISCV_CPU(cs)->env; 485 486 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 487 if (ret) { 488 return ret; 489 } 490 env->pc = reg; 491 492 for (i = 1; i < 32; i++) { 493 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 494 ret = kvm_get_one_reg(cs, id, ®); 495 if (ret) { 496 return ret; 497 } 498 env->gpr[i] = reg; 499 } 500 501 return ret; 502 } 503 504 static int kvm_riscv_put_regs_core(CPUState *cs) 505 { 506 int ret = 0; 507 int i; 508 target_ulong reg; 509 CPURISCVState *env = &RISCV_CPU(cs)->env; 510 511 reg = env->pc; 512 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 513 if (ret) { 514 return ret; 515 } 516 517 for (i = 1; i < 32; i++) { 518 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 519 reg = env->gpr[i]; 520 ret = kvm_set_one_reg(cs, id, ®); 521 if (ret) { 522 return ret; 523 } 524 } 525 526 return ret; 527 } 528 529 static int kvm_riscv_get_regs_csr(CPUState *cs) 530 { 531 int ret = 0; 532 CPURISCVState *env = &RISCV_CPU(cs)->env; 533 534 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 535 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 536 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 537 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 538 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 539 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 540 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 541 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 542 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 543 return ret; 544 } 545 546 static int kvm_riscv_put_regs_csr(CPUState *cs) 547 { 548 int ret = 0; 549 CPURISCVState *env = &RISCV_CPU(cs)->env; 550 551 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 552 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 553 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 554 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 555 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 556 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 557 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 558 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 559 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 560 561 return ret; 562 } 563 564 static int kvm_riscv_get_regs_fp(CPUState *cs) 565 { 566 int ret = 0; 567 int i; 568 CPURISCVState *env = &RISCV_CPU(cs)->env; 569 570 if (riscv_has_ext(env, RVD)) { 571 uint64_t reg; 572 for (i = 0; i < 32; i++) { 573 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 574 if (ret) { 575 return ret; 576 } 577 env->fpr[i] = reg; 578 } 579 return ret; 580 } 581 582 if (riscv_has_ext(env, RVF)) { 583 uint32_t reg; 584 for (i = 0; i < 32; i++) { 585 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 586 if (ret) { 587 return ret; 588 } 589 env->fpr[i] = reg; 590 } 591 return ret; 592 } 593 594 return ret; 595 } 596 597 static int kvm_riscv_put_regs_fp(CPUState *cs) 598 { 599 int ret = 0; 600 int i; 601 CPURISCVState *env = &RISCV_CPU(cs)->env; 602 603 if (riscv_has_ext(env, RVD)) { 604 uint64_t reg; 605 for (i = 0; i < 32; i++) { 606 reg = env->fpr[i]; 607 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 608 if (ret) { 609 return ret; 610 } 611 } 612 return ret; 613 } 614 615 if (riscv_has_ext(env, RVF)) { 616 uint32_t reg; 617 for (i = 0; i < 32; i++) { 618 reg = env->fpr[i]; 619 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 620 if (ret) { 621 return ret; 622 } 623 } 624 return ret; 625 } 626 627 return ret; 628 } 629 630 static void kvm_riscv_get_regs_timer(CPUState *cs) 631 { 632 CPURISCVState *env = &RISCV_CPU(cs)->env; 633 634 if (env->kvm_timer_dirty) { 635 return; 636 } 637 638 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 639 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 640 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 641 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 642 643 env->kvm_timer_dirty = true; 644 } 645 646 static void kvm_riscv_put_regs_timer(CPUState *cs) 647 { 648 uint64_t reg; 649 CPURISCVState *env = &RISCV_CPU(cs)->env; 650 651 if (!env->kvm_timer_dirty) { 652 return; 653 } 654 655 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 656 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 657 658 /* 659 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 660 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 661 * doesn't matter that adaping in QEMU now. 662 * TODO If KVM changes, adapt here. 663 */ 664 if (env->kvm_timer_state) { 665 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 666 } 667 668 /* 669 * For now, migration will not work between Hosts with different timer 670 * frequency. Therefore, we should check whether they are the same here 671 * during the migration. 672 */ 673 if (migration_is_running(migrate_get_current()->state)) { 674 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 675 if (reg != env->kvm_timer_frequency) { 676 error_report("Dst Hosts timer frequency != Src Hosts"); 677 } 678 } 679 680 env->kvm_timer_dirty = false; 681 } 682 683 typedef struct KVMScratchCPU { 684 int kvmfd; 685 int vmfd; 686 int cpufd; 687 } KVMScratchCPU; 688 689 /* 690 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 691 * from target/arm/kvm.c. 692 */ 693 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 694 { 695 int kvmfd = -1, vmfd = -1, cpufd = -1; 696 697 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 698 if (kvmfd < 0) { 699 goto err; 700 } 701 do { 702 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 703 } while (vmfd == -1 && errno == EINTR); 704 if (vmfd < 0) { 705 goto err; 706 } 707 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 708 if (cpufd < 0) { 709 goto err; 710 } 711 712 scratch->kvmfd = kvmfd; 713 scratch->vmfd = vmfd; 714 scratch->cpufd = cpufd; 715 716 return true; 717 718 err: 719 if (cpufd >= 0) { 720 close(cpufd); 721 } 722 if (vmfd >= 0) { 723 close(vmfd); 724 } 725 if (kvmfd >= 0) { 726 close(kvmfd); 727 } 728 729 return false; 730 } 731 732 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 733 { 734 close(scratch->cpufd); 735 close(scratch->vmfd); 736 close(scratch->kvmfd); 737 } 738 739 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 740 { 741 CPURISCVState *env = &cpu->env; 742 struct kvm_one_reg reg; 743 int ret; 744 745 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 746 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 747 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 748 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 749 if (ret != 0) { 750 error_report("Unable to retrieve mvendorid from host, error %d", ret); 751 } 752 753 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 754 KVM_REG_RISCV_CONFIG_REG(marchid)); 755 reg.addr = (uint64_t)&cpu->cfg.marchid; 756 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 757 if (ret != 0) { 758 error_report("Unable to retrieve marchid from host, error %d", ret); 759 } 760 761 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 762 KVM_REG_RISCV_CONFIG_REG(mimpid)); 763 reg.addr = (uint64_t)&cpu->cfg.mimpid; 764 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 765 if (ret != 0) { 766 error_report("Unable to retrieve mimpid from host, error %d", ret); 767 } 768 } 769 770 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 771 KVMScratchCPU *kvmcpu) 772 { 773 CPURISCVState *env = &cpu->env; 774 struct kvm_one_reg reg; 775 int ret; 776 777 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 778 KVM_REG_RISCV_CONFIG_REG(isa)); 779 reg.addr = (uint64_t)&env->misa_ext_mask; 780 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 781 782 if (ret) { 783 error_report("Unable to fetch ISA register from KVM, " 784 "error %d", ret); 785 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 786 exit(EXIT_FAILURE); 787 } 788 789 env->misa_ext = env->misa_ext_mask; 790 } 791 792 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 793 KVMCPUConfig *cbomz_cfg) 794 { 795 CPURISCVState *env = &cpu->env; 796 struct kvm_one_reg reg; 797 int ret; 798 799 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 800 cbomz_cfg->kvm_reg_id); 801 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 802 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 803 if (ret != 0) { 804 error_report("Unable to read KVM reg %s, error %d", 805 cbomz_cfg->name, ret); 806 exit(EXIT_FAILURE); 807 } 808 } 809 810 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 811 KVMScratchCPU *kvmcpu) 812 { 813 CPURISCVState *env = &cpu->env; 814 uint64_t val; 815 int i, ret; 816 817 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 818 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 819 struct kvm_one_reg reg; 820 821 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 822 multi_ext_cfg->kvm_reg_id); 823 reg.addr = (uint64_t)&val; 824 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 825 if (ret != 0) { 826 if (errno == EINVAL) { 827 /* Silently default to 'false' if KVM does not support it. */ 828 multi_ext_cfg->supported = false; 829 val = false; 830 } else { 831 error_report("Unable to read ISA_EXT KVM register %s, " 832 "error code: %s", multi_ext_cfg->name, 833 strerrorname_np(errno)); 834 exit(EXIT_FAILURE); 835 } 836 } else { 837 multi_ext_cfg->supported = true; 838 } 839 840 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 841 } 842 843 if (cpu->cfg.ext_zicbom) { 844 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 845 } 846 847 if (cpu->cfg.ext_zicboz) { 848 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 849 } 850 } 851 852 static int uint64_cmp(const void *a, const void *b) 853 { 854 uint64_t val1 = *(const uint64_t *)a; 855 uint64_t val2 = *(const uint64_t *)b; 856 857 if (val1 < val2) { 858 return -1; 859 } 860 861 if (val1 > val2) { 862 return 1; 863 } 864 865 return 0; 866 } 867 868 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 869 { 870 KVMCPUConfig *multi_ext_cfg; 871 struct kvm_one_reg reg; 872 struct kvm_reg_list rl_struct; 873 struct kvm_reg_list *reglist; 874 uint64_t val, reg_id, *reg_search; 875 int i, ret; 876 877 rl_struct.n = 0; 878 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 879 880 /* 881 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 882 * (EINVAL). Use read_legacy() in this case. 883 */ 884 if (errno == EINVAL) { 885 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 886 } else if (errno != E2BIG) { 887 /* 888 * E2BIG is an expected error message for the API since we 889 * don't know the number of registers. The right amount will 890 * be written in rl_struct.n. 891 * 892 * Error out if we get any other errno. 893 */ 894 error_report("Error when accessing get-reg-list, code: %s", 895 strerrorname_np(errno)); 896 exit(EXIT_FAILURE); 897 } 898 899 reglist = g_malloc(sizeof(struct kvm_reg_list) + 900 rl_struct.n * sizeof(uint64_t)); 901 reglist->n = rl_struct.n; 902 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 903 if (ret) { 904 error_report("Error when reading KVM_GET_REG_LIST, code %s ", 905 strerrorname_np(errno)); 906 exit(EXIT_FAILURE); 907 } 908 909 /* sort reglist to use bsearch() */ 910 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 911 912 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 913 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 914 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 915 multi_ext_cfg->kvm_reg_id); 916 reg_search = bsearch(®_id, reglist->reg, reglist->n, 917 sizeof(uint64_t), uint64_cmp); 918 if (!reg_search) { 919 continue; 920 } 921 922 reg.id = reg_id; 923 reg.addr = (uint64_t)&val; 924 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 925 if (ret != 0) { 926 error_report("Unable to read ISA_EXT KVM register %s, " 927 "error code: %s", multi_ext_cfg->name, 928 strerrorname_np(errno)); 929 exit(EXIT_FAILURE); 930 } 931 932 multi_ext_cfg->supported = true; 933 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 934 } 935 936 if (cpu->cfg.ext_zicbom) { 937 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 938 } 939 940 if (cpu->cfg.ext_zicboz) { 941 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 942 } 943 } 944 945 static void riscv_init_kvm_registers(Object *cpu_obj) 946 { 947 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 948 KVMScratchCPU kvmcpu; 949 950 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 951 return; 952 } 953 954 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 955 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 956 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 957 958 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 959 } 960 961 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 962 KVM_CAP_LAST_INFO 963 }; 964 965 int kvm_arch_get_registers(CPUState *cs) 966 { 967 int ret = 0; 968 969 ret = kvm_riscv_get_regs_core(cs); 970 if (ret) { 971 return ret; 972 } 973 974 ret = kvm_riscv_get_regs_csr(cs); 975 if (ret) { 976 return ret; 977 } 978 979 ret = kvm_riscv_get_regs_fp(cs); 980 if (ret) { 981 return ret; 982 } 983 984 return ret; 985 } 986 987 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 988 { 989 if (cap_has_mp_state) { 990 struct kvm_mp_state mp_state = { 991 .mp_state = state 992 }; 993 994 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 995 if (ret) { 996 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 997 __func__, ret, strerror(-ret)); 998 return -1; 999 } 1000 } 1001 1002 return 0; 1003 } 1004 1005 int kvm_arch_put_registers(CPUState *cs, int level) 1006 { 1007 int ret = 0; 1008 1009 ret = kvm_riscv_put_regs_core(cs); 1010 if (ret) { 1011 return ret; 1012 } 1013 1014 ret = kvm_riscv_put_regs_csr(cs); 1015 if (ret) { 1016 return ret; 1017 } 1018 1019 ret = kvm_riscv_put_regs_fp(cs); 1020 if (ret) { 1021 return ret; 1022 } 1023 1024 if (KVM_PUT_RESET_STATE == level) { 1025 RISCVCPU *cpu = RISCV_CPU(cs); 1026 if (cs->cpu_index == 0) { 1027 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1028 } else { 1029 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1030 } 1031 if (ret) { 1032 return ret; 1033 } 1034 } 1035 1036 return ret; 1037 } 1038 1039 int kvm_arch_release_virq_post(int virq) 1040 { 1041 return 0; 1042 } 1043 1044 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1045 uint64_t address, uint32_t data, PCIDevice *dev) 1046 { 1047 return 0; 1048 } 1049 1050 int kvm_arch_destroy_vcpu(CPUState *cs) 1051 { 1052 return 0; 1053 } 1054 1055 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1056 { 1057 return cpu->cpu_index; 1058 } 1059 1060 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1061 RunState state) 1062 { 1063 CPUState *cs = opaque; 1064 1065 if (running) { 1066 kvm_riscv_put_regs_timer(cs); 1067 } else { 1068 kvm_riscv_get_regs_timer(cs); 1069 } 1070 } 1071 1072 void kvm_arch_init_irq_routing(KVMState *s) 1073 { 1074 } 1075 1076 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1077 { 1078 CPURISCVState *env = &cpu->env; 1079 target_ulong reg; 1080 uint64_t id; 1081 int ret; 1082 1083 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1084 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1085 /* 1086 * cfg.mvendorid is an uint32 but a target_ulong will 1087 * be written. Assign it to a target_ulong var to avoid 1088 * writing pieces of other cpu->cfg fields in the reg. 1089 */ 1090 reg = cpu->cfg.mvendorid; 1091 ret = kvm_set_one_reg(cs, id, ®); 1092 if (ret != 0) { 1093 return ret; 1094 } 1095 1096 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1097 KVM_REG_RISCV_CONFIG_REG(marchid)); 1098 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1099 if (ret != 0) { 1100 return ret; 1101 } 1102 1103 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1104 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1105 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1106 1107 return ret; 1108 } 1109 1110 int kvm_arch_init_vcpu(CPUState *cs) 1111 { 1112 int ret = 0; 1113 RISCVCPU *cpu = RISCV_CPU(cs); 1114 1115 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1116 1117 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1118 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1119 if (ret != 0) { 1120 return ret; 1121 } 1122 } 1123 1124 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1125 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1126 1127 return ret; 1128 } 1129 1130 int kvm_arch_msi_data_to_gsi(uint32_t data) 1131 { 1132 abort(); 1133 } 1134 1135 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1136 int vector, PCIDevice *dev) 1137 { 1138 return 0; 1139 } 1140 1141 int kvm_arch_get_default_type(MachineState *ms) 1142 { 1143 return 0; 1144 } 1145 1146 int kvm_arch_init(MachineState *ms, KVMState *s) 1147 { 1148 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1149 return 0; 1150 } 1151 1152 int kvm_arch_irqchip_create(KVMState *s) 1153 { 1154 if (kvm_kernel_irqchip_split()) { 1155 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1156 exit(1); 1157 } 1158 1159 /* 1160 * We can create the VAIA using the newer device control API. 1161 */ 1162 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1163 } 1164 1165 int kvm_arch_process_async_events(CPUState *cs) 1166 { 1167 return 0; 1168 } 1169 1170 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1171 { 1172 } 1173 1174 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1175 { 1176 return MEMTXATTRS_UNSPECIFIED; 1177 } 1178 1179 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1180 { 1181 return true; 1182 } 1183 1184 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1185 { 1186 int ret = 0; 1187 unsigned char ch; 1188 switch (run->riscv_sbi.extension_id) { 1189 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1190 ch = run->riscv_sbi.args[0]; 1191 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1192 break; 1193 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1194 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1195 if (ret == sizeof(ch)) { 1196 run->riscv_sbi.ret[0] = ch; 1197 } else { 1198 run->riscv_sbi.ret[0] = -1; 1199 } 1200 ret = 0; 1201 break; 1202 default: 1203 qemu_log_mask(LOG_UNIMP, 1204 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1205 __func__, run->riscv_sbi.extension_id); 1206 ret = -1; 1207 break; 1208 } 1209 return ret; 1210 } 1211 1212 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1213 { 1214 int ret = 0; 1215 switch (run->exit_reason) { 1216 case KVM_EXIT_RISCV_SBI: 1217 ret = kvm_riscv_handle_sbi(cs, run); 1218 break; 1219 default: 1220 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1221 __func__, run->exit_reason); 1222 ret = -1; 1223 break; 1224 } 1225 return ret; 1226 } 1227 1228 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1229 { 1230 CPURISCVState *env = &cpu->env; 1231 int i; 1232 1233 if (!kvm_enabled()) { 1234 return; 1235 } 1236 for (i = 0; i < 32; i++) { 1237 env->gpr[i] = 0; 1238 } 1239 env->pc = cpu->env.kernel_addr; 1240 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1241 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1242 env->satp = 0; 1243 env->mie = 0; 1244 env->stvec = 0; 1245 env->sscratch = 0; 1246 env->sepc = 0; 1247 env->scause = 0; 1248 env->stval = 0; 1249 env->mip = 0; 1250 } 1251 1252 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1253 { 1254 int ret; 1255 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1256 1257 if (irq != IRQ_S_EXT) { 1258 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1259 abort(); 1260 } 1261 1262 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1263 if (ret < 0) { 1264 perror("Set irq failed"); 1265 abort(); 1266 } 1267 } 1268 1269 bool kvm_arch_cpu_check_are_resettable(void) 1270 { 1271 return true; 1272 } 1273 1274 static int aia_mode; 1275 1276 static const char *kvm_aia_mode_str(uint64_t mode) 1277 { 1278 switch (mode) { 1279 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1280 return "emul"; 1281 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1282 return "hwaccel"; 1283 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1284 default: 1285 return "auto"; 1286 }; 1287 } 1288 1289 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1290 { 1291 return g_strdup(kvm_aia_mode_str(aia_mode)); 1292 } 1293 1294 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1295 { 1296 if (!strcmp(val, "emul")) { 1297 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1298 } else if (!strcmp(val, "hwaccel")) { 1299 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1300 } else if (!strcmp(val, "auto")) { 1301 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1302 } else { 1303 error_setg(errp, "Invalid KVM AIA mode"); 1304 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1305 } 1306 } 1307 1308 void kvm_arch_accel_class_init(ObjectClass *oc) 1309 { 1310 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1311 riscv_set_kvm_aia); 1312 object_class_property_set_description(oc, "riscv-aia", 1313 "Set KVM AIA mode. Valid values are " 1314 "emul, hwaccel, and auto. Default " 1315 "is auto."); 1316 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1317 "auto"); 1318 } 1319 1320 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1321 uint64_t aia_irq_num, uint64_t aia_msi_num, 1322 uint64_t aplic_base, uint64_t imsic_base, 1323 uint64_t guest_num) 1324 { 1325 int ret, i; 1326 int aia_fd = -1; 1327 uint64_t default_aia_mode; 1328 uint64_t socket_count = riscv_socket_count(machine); 1329 uint64_t max_hart_per_socket = 0; 1330 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1331 uint64_t socket_bits, hart_bits, guest_bits; 1332 1333 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1334 1335 if (aia_fd < 0) { 1336 error_report("Unable to create in-kernel irqchip"); 1337 exit(1); 1338 } 1339 1340 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1341 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1342 &default_aia_mode, false, NULL); 1343 if (ret < 0) { 1344 error_report("KVM AIA: failed to get current KVM AIA mode"); 1345 exit(1); 1346 } 1347 qemu_log("KVM AIA: default mode is %s\n", 1348 kvm_aia_mode_str(default_aia_mode)); 1349 1350 if (default_aia_mode != aia_mode) { 1351 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1352 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1353 &aia_mode, true, NULL); 1354 if (ret < 0) 1355 warn_report("KVM AIA: failed to set KVM AIA mode"); 1356 else 1357 qemu_log("KVM AIA: set current mode to %s\n", 1358 kvm_aia_mode_str(aia_mode)); 1359 } 1360 1361 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1362 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1363 &aia_irq_num, true, NULL); 1364 if (ret < 0) { 1365 error_report("KVM AIA: failed to set number of input irq lines"); 1366 exit(1); 1367 } 1368 1369 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1370 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1371 &aia_msi_num, true, NULL); 1372 if (ret < 0) { 1373 error_report("KVM AIA: failed to set number of msi"); 1374 exit(1); 1375 } 1376 1377 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1378 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1379 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1380 &socket_bits, true, NULL); 1381 if (ret < 0) { 1382 error_report("KVM AIA: failed to set group_bits"); 1383 exit(1); 1384 } 1385 1386 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1387 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1388 &group_shift, true, NULL); 1389 if (ret < 0) { 1390 error_report("KVM AIA: failed to set group_shift"); 1391 exit(1); 1392 } 1393 1394 guest_bits = guest_num == 0 ? 0 : 1395 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1396 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1397 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1398 &guest_bits, true, NULL); 1399 if (ret < 0) { 1400 error_report("KVM AIA: failed to set guest_bits"); 1401 exit(1); 1402 } 1403 1404 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1405 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1406 &aplic_base, true, NULL); 1407 if (ret < 0) { 1408 error_report("KVM AIA: failed to set the base address of APLIC"); 1409 exit(1); 1410 } 1411 1412 for (socket = 0; socket < socket_count; socket++) { 1413 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1414 hart_count = riscv_socket_hart_count(machine, socket); 1415 base_hart = riscv_socket_first_hartid(machine, socket); 1416 1417 if (max_hart_per_socket < hart_count) { 1418 max_hart_per_socket = hart_count; 1419 } 1420 1421 for (i = 0; i < hart_count; i++) { 1422 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1423 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1424 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1425 &imsic_addr, true, NULL); 1426 if (ret < 0) { 1427 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1428 exit(1); 1429 } 1430 } 1431 } 1432 1433 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1434 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1435 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1436 &hart_bits, true, NULL); 1437 if (ret < 0) { 1438 error_report("KVM AIA: failed to set hart_bits"); 1439 exit(1); 1440 } 1441 1442 if (kvm_has_gsi_routing()) { 1443 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1444 /* KVM AIA only has one APLIC instance */ 1445 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1446 } 1447 kvm_gsi_routing_allowed = true; 1448 kvm_irqchip_commit_routes(kvm_state); 1449 } 1450 1451 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1452 KVM_DEV_RISCV_AIA_CTRL_INIT, 1453 NULL, true, NULL); 1454 if (ret < 0) { 1455 error_report("KVM AIA: initialized fail"); 1456 exit(1); 1457 } 1458 1459 kvm_msi_via_irqfd_allowed = true; 1460 } 1461 1462 static void kvm_cpu_instance_init(CPUState *cs) 1463 { 1464 Object *obj = OBJECT(RISCV_CPU(cs)); 1465 DeviceState *dev = DEVICE(obj); 1466 1467 riscv_init_kvm_registers(obj); 1468 1469 kvm_riscv_add_cpu_user_properties(obj); 1470 1471 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1472 /* Check if we have a specific KVM handler for the option */ 1473 if (object_property_find(obj, prop->name)) { 1474 continue; 1475 } 1476 qdev_property_add_static(dev, prop); 1477 } 1478 } 1479 1480 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1481 { 1482 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1483 1484 acc->cpu_instance_init = kvm_cpu_instance_init; 1485 } 1486 1487 static const TypeInfo kvm_cpu_accel_type_info = { 1488 .name = ACCEL_CPU_NAME("kvm"), 1489 1490 .parent = TYPE_ACCEL_CPU, 1491 .class_init = kvm_cpu_accel_class_init, 1492 .abstract = true, 1493 }; 1494 static void kvm_cpu_accel_register_types(void) 1495 { 1496 type_register_static(&kvm_cpu_accel_type_info); 1497 } 1498 type_init(kvm_cpu_accel_register_types); 1499 1500 static void riscv_host_cpu_init(Object *obj) 1501 { 1502 CPURISCVState *env = &RISCV_CPU(obj)->env; 1503 1504 #if defined(TARGET_RISCV32) 1505 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1506 #elif defined(TARGET_RISCV64) 1507 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1508 #endif 1509 } 1510 1511 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1512 { 1513 .name = TYPE_RISCV_CPU_HOST, 1514 .parent = TYPE_RISCV_CPU, 1515 .instance_init = riscv_host_cpu_init, 1516 } 1517 }; 1518 1519 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1520