1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value = env->misa_ext_mask & misa_bit; 152 153 visit_type_bool(v, name, &value, errp); 154 } 155 156 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 157 const char *name, 158 void *opaque, Error **errp) 159 { 160 KVMCPUConfig *misa_ext_cfg = opaque; 161 target_ulong misa_bit = misa_ext_cfg->offset; 162 RISCVCPU *cpu = RISCV_CPU(obj); 163 CPURISCVState *env = &cpu->env; 164 bool value, host_bit; 165 166 if (!visit_type_bool(v, name, &value, errp)) { 167 return; 168 } 169 170 host_bit = env->misa_ext_mask & misa_bit; 171 172 if (value == host_bit) { 173 return; 174 } 175 176 if (!value) { 177 misa_ext_cfg->user_set = true; 178 return; 179 } 180 181 /* 182 * Forbid users to enable extensions that aren't 183 * available in the hart. 184 */ 185 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 186 "enabled in the host", misa_ext_cfg->name); 187 } 188 189 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 190 { 191 CPURISCVState *env = &cpu->env; 192 uint64_t id, reg; 193 int i, ret; 194 195 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 196 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 197 target_ulong misa_bit = misa_cfg->offset; 198 199 if (!misa_cfg->user_set) { 200 continue; 201 } 202 203 /* If we're here we're going to disable the MISA bit */ 204 reg = 0; 205 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 206 misa_cfg->kvm_reg_id); 207 ret = kvm_set_one_reg(cs, id, ®); 208 if (ret != 0) { 209 /* 210 * We're not checking for -EINVAL because if the bit is about 211 * to be disabled, it means that it was already enabled by 212 * KVM. We determined that by fetching the 'isa' register 213 * during init() time. Any error at this point is worth 214 * aborting. 215 */ 216 error_report("Unable to set KVM reg %s, error %d", 217 misa_cfg->name, ret); 218 exit(EXIT_FAILURE); 219 } 220 env->misa_ext &= ~misa_bit; 221 } 222 } 223 224 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 225 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 226 .kvm_reg_id = _reg_id} 227 228 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 229 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 230 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 231 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 232 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 233 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 234 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 235 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 236 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 237 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 238 }; 239 240 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 241 { 242 return (void *)&cpu->cfg + kvmcfg->offset; 243 } 244 245 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 246 uint32_t val) 247 { 248 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 249 250 *ext_enabled = val; 251 } 252 253 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 254 KVMCPUConfig *multi_ext) 255 { 256 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 257 258 return *ext_enabled; 259 } 260 261 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 262 const char *name, 263 void *opaque, Error **errp) 264 { 265 KVMCPUConfig *multi_ext_cfg = opaque; 266 RISCVCPU *cpu = RISCV_CPU(obj); 267 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 268 269 visit_type_bool(v, name, &value, errp); 270 } 271 272 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 273 const char *name, 274 void *opaque, Error **errp) 275 { 276 KVMCPUConfig *multi_ext_cfg = opaque; 277 RISCVCPU *cpu = RISCV_CPU(obj); 278 bool value, host_val; 279 280 if (!visit_type_bool(v, name, &value, errp)) { 281 return; 282 } 283 284 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 285 286 /* 287 * Ignore if the user is setting the same value 288 * as the host. 289 */ 290 if (value == host_val) { 291 return; 292 } 293 294 if (!multi_ext_cfg->supported) { 295 /* 296 * Error out if the user is trying to enable an 297 * extension that KVM doesn't support. Ignore 298 * option otherwise. 299 */ 300 if (value) { 301 error_setg(errp, "KVM does not support disabling extension %s", 302 multi_ext_cfg->name); 303 } 304 305 return; 306 } 307 308 multi_ext_cfg->user_set = true; 309 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 310 } 311 312 static KVMCPUConfig kvm_cbom_blocksize = { 313 .name = "cbom_blocksize", 314 .offset = CPU_CFG_OFFSET(cbom_blocksize), 315 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 316 }; 317 318 static KVMCPUConfig kvm_cboz_blocksize = { 319 .name = "cboz_blocksize", 320 .offset = CPU_CFG_OFFSET(cboz_blocksize), 321 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 322 }; 323 324 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 325 const char *name, 326 void *opaque, Error **errp) 327 { 328 KVMCPUConfig *cbomz_cfg = opaque; 329 RISCVCPU *cpu = RISCV_CPU(obj); 330 uint16_t value, *host_val; 331 332 if (!visit_type_uint16(v, name, &value, errp)) { 333 return; 334 } 335 336 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 337 338 if (value != *host_val) { 339 error_report("Unable to set %s to a different value than " 340 "the host (%u)", 341 cbomz_cfg->name, *host_val); 342 exit(EXIT_FAILURE); 343 } 344 345 cbomz_cfg->user_set = true; 346 } 347 348 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 349 { 350 CPURISCVState *env = &cpu->env; 351 uint64_t id, reg; 352 int i, ret; 353 354 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 355 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 356 357 if (!multi_ext_cfg->user_set) { 358 continue; 359 } 360 361 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 362 multi_ext_cfg->kvm_reg_id); 363 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 364 ret = kvm_set_one_reg(cs, id, ®); 365 if (ret != 0) { 366 error_report("Unable to %s extension %s in KVM, error %d", 367 reg ? "enable" : "disable", 368 multi_ext_cfg->name, ret); 369 exit(EXIT_FAILURE); 370 } 371 } 372 } 373 374 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 375 const char *name, 376 void *opaque, Error **errp) 377 { 378 bool value = false; 379 380 visit_type_bool(v, name, &value, errp); 381 } 382 383 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 384 const char *name, 385 void *opaque, Error **errp) 386 { 387 const char *propname = opaque; 388 bool value; 389 390 if (!visit_type_bool(v, name, &value, errp)) { 391 return; 392 } 393 394 if (value) { 395 error_setg(errp, "extension %s is not available with KVM", 396 propname); 397 } 398 } 399 400 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 401 { 402 /* Check if KVM created the property already */ 403 if (object_property_find(obj, prop_name)) { 404 return; 405 } 406 407 /* 408 * Set the default to disabled for every extension 409 * unknown to KVM and error out if the user attempts 410 * to enable any of them. 411 */ 412 object_property_add(obj, prop_name, "bool", 413 cpu_get_cfg_unavailable, 414 cpu_set_cfg_unavailable, 415 NULL, (void *)prop_name); 416 } 417 418 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 419 const RISCVCPUMultiExtConfig *array) 420 { 421 const RISCVCPUMultiExtConfig *prop; 422 423 g_assert(array); 424 425 for (prop = array; prop && prop->name; prop++) { 426 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 427 } 428 } 429 430 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 431 { 432 int i; 433 434 riscv_add_satp_mode_properties(cpu_obj); 435 436 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 437 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 438 int bit = misa_cfg->offset; 439 440 misa_cfg->name = riscv_get_misa_ext_name(bit); 441 misa_cfg->description = riscv_get_misa_ext_description(bit); 442 443 object_property_add(cpu_obj, misa_cfg->name, "bool", 444 kvm_cpu_get_misa_ext_cfg, 445 kvm_cpu_set_misa_ext_cfg, 446 NULL, misa_cfg); 447 object_property_set_description(cpu_obj, misa_cfg->name, 448 misa_cfg->description); 449 } 450 451 for (i = 0; misa_bits[i] != 0; i++) { 452 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 453 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 454 } 455 456 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 457 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 458 459 object_property_add(cpu_obj, multi_cfg->name, "bool", 460 kvm_cpu_get_multi_ext_cfg, 461 kvm_cpu_set_multi_ext_cfg, 462 NULL, multi_cfg); 463 } 464 465 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 466 NULL, kvm_cpu_set_cbomz_blksize, 467 NULL, &kvm_cbom_blocksize); 468 469 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 470 NULL, kvm_cpu_set_cbomz_blksize, 471 NULL, &kvm_cboz_blocksize); 472 473 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 474 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 475 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 476 } 477 478 static int kvm_riscv_get_regs_core(CPUState *cs) 479 { 480 int ret = 0; 481 int i; 482 target_ulong reg; 483 CPURISCVState *env = &RISCV_CPU(cs)->env; 484 485 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 486 if (ret) { 487 return ret; 488 } 489 env->pc = reg; 490 491 for (i = 1; i < 32; i++) { 492 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 493 ret = kvm_get_one_reg(cs, id, ®); 494 if (ret) { 495 return ret; 496 } 497 env->gpr[i] = reg; 498 } 499 500 return ret; 501 } 502 503 static int kvm_riscv_put_regs_core(CPUState *cs) 504 { 505 int ret = 0; 506 int i; 507 target_ulong reg; 508 CPURISCVState *env = &RISCV_CPU(cs)->env; 509 510 reg = env->pc; 511 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 512 if (ret) { 513 return ret; 514 } 515 516 for (i = 1; i < 32; i++) { 517 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 518 reg = env->gpr[i]; 519 ret = kvm_set_one_reg(cs, id, ®); 520 if (ret) { 521 return ret; 522 } 523 } 524 525 return ret; 526 } 527 528 static int kvm_riscv_get_regs_csr(CPUState *cs) 529 { 530 int ret = 0; 531 CPURISCVState *env = &RISCV_CPU(cs)->env; 532 533 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 534 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 535 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 536 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 537 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 538 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 539 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 540 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 541 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 542 return ret; 543 } 544 545 static int kvm_riscv_put_regs_csr(CPUState *cs) 546 { 547 int ret = 0; 548 CPURISCVState *env = &RISCV_CPU(cs)->env; 549 550 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 551 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 552 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 553 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 554 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 555 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 556 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 557 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 558 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 559 560 return ret; 561 } 562 563 static int kvm_riscv_get_regs_fp(CPUState *cs) 564 { 565 int ret = 0; 566 int i; 567 CPURISCVState *env = &RISCV_CPU(cs)->env; 568 569 if (riscv_has_ext(env, RVD)) { 570 uint64_t reg; 571 for (i = 0; i < 32; i++) { 572 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 573 if (ret) { 574 return ret; 575 } 576 env->fpr[i] = reg; 577 } 578 return ret; 579 } 580 581 if (riscv_has_ext(env, RVF)) { 582 uint32_t reg; 583 for (i = 0; i < 32; i++) { 584 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 585 if (ret) { 586 return ret; 587 } 588 env->fpr[i] = reg; 589 } 590 return ret; 591 } 592 593 return ret; 594 } 595 596 static int kvm_riscv_put_regs_fp(CPUState *cs) 597 { 598 int ret = 0; 599 int i; 600 CPURISCVState *env = &RISCV_CPU(cs)->env; 601 602 if (riscv_has_ext(env, RVD)) { 603 uint64_t reg; 604 for (i = 0; i < 32; i++) { 605 reg = env->fpr[i]; 606 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 607 if (ret) { 608 return ret; 609 } 610 } 611 return ret; 612 } 613 614 if (riscv_has_ext(env, RVF)) { 615 uint32_t reg; 616 for (i = 0; i < 32; i++) { 617 reg = env->fpr[i]; 618 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 619 if (ret) { 620 return ret; 621 } 622 } 623 return ret; 624 } 625 626 return ret; 627 } 628 629 static void kvm_riscv_get_regs_timer(CPUState *cs) 630 { 631 CPURISCVState *env = &RISCV_CPU(cs)->env; 632 633 if (env->kvm_timer_dirty) { 634 return; 635 } 636 637 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 638 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 639 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 640 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 641 642 env->kvm_timer_dirty = true; 643 } 644 645 static void kvm_riscv_put_regs_timer(CPUState *cs) 646 { 647 uint64_t reg; 648 CPURISCVState *env = &RISCV_CPU(cs)->env; 649 650 if (!env->kvm_timer_dirty) { 651 return; 652 } 653 654 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 655 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 656 657 /* 658 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 659 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 660 * doesn't matter that adaping in QEMU now. 661 * TODO If KVM changes, adapt here. 662 */ 663 if (env->kvm_timer_state) { 664 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 665 } 666 667 /* 668 * For now, migration will not work between Hosts with different timer 669 * frequency. Therefore, we should check whether they are the same here 670 * during the migration. 671 */ 672 if (migration_is_running(migrate_get_current()->state)) { 673 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 674 if (reg != env->kvm_timer_frequency) { 675 error_report("Dst Hosts timer frequency != Src Hosts"); 676 } 677 } 678 679 env->kvm_timer_dirty = false; 680 } 681 682 typedef struct KVMScratchCPU { 683 int kvmfd; 684 int vmfd; 685 int cpufd; 686 } KVMScratchCPU; 687 688 /* 689 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 690 * from target/arm/kvm.c. 691 */ 692 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 693 { 694 int kvmfd = -1, vmfd = -1, cpufd = -1; 695 696 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 697 if (kvmfd < 0) { 698 goto err; 699 } 700 do { 701 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 702 } while (vmfd == -1 && errno == EINTR); 703 if (vmfd < 0) { 704 goto err; 705 } 706 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 707 if (cpufd < 0) { 708 goto err; 709 } 710 711 scratch->kvmfd = kvmfd; 712 scratch->vmfd = vmfd; 713 scratch->cpufd = cpufd; 714 715 return true; 716 717 err: 718 if (cpufd >= 0) { 719 close(cpufd); 720 } 721 if (vmfd >= 0) { 722 close(vmfd); 723 } 724 if (kvmfd >= 0) { 725 close(kvmfd); 726 } 727 728 return false; 729 } 730 731 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 732 { 733 close(scratch->cpufd); 734 close(scratch->vmfd); 735 close(scratch->kvmfd); 736 } 737 738 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 739 { 740 CPURISCVState *env = &cpu->env; 741 struct kvm_one_reg reg; 742 int ret; 743 744 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 745 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 746 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 747 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 748 if (ret != 0) { 749 error_report("Unable to retrieve mvendorid from host, error %d", ret); 750 } 751 752 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 753 KVM_REG_RISCV_CONFIG_REG(marchid)); 754 reg.addr = (uint64_t)&cpu->cfg.marchid; 755 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 756 if (ret != 0) { 757 error_report("Unable to retrieve marchid from host, error %d", ret); 758 } 759 760 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 761 KVM_REG_RISCV_CONFIG_REG(mimpid)); 762 reg.addr = (uint64_t)&cpu->cfg.mimpid; 763 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 764 if (ret != 0) { 765 error_report("Unable to retrieve mimpid from host, error %d", ret); 766 } 767 } 768 769 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 770 KVMScratchCPU *kvmcpu) 771 { 772 CPURISCVState *env = &cpu->env; 773 struct kvm_one_reg reg; 774 int ret; 775 776 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 777 KVM_REG_RISCV_CONFIG_REG(isa)); 778 reg.addr = (uint64_t)&env->misa_ext_mask; 779 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 780 781 if (ret) { 782 error_report("Unable to fetch ISA register from KVM, " 783 "error %d", ret); 784 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 785 exit(EXIT_FAILURE); 786 } 787 788 env->misa_ext = env->misa_ext_mask; 789 } 790 791 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 792 KVMCPUConfig *cbomz_cfg) 793 { 794 CPURISCVState *env = &cpu->env; 795 struct kvm_one_reg reg; 796 int ret; 797 798 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 799 cbomz_cfg->kvm_reg_id); 800 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 801 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 802 if (ret != 0) { 803 error_report("Unable to read KVM reg %s, error %d", 804 cbomz_cfg->name, ret); 805 exit(EXIT_FAILURE); 806 } 807 } 808 809 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 810 KVMScratchCPU *kvmcpu) 811 { 812 CPURISCVState *env = &cpu->env; 813 uint64_t val; 814 int i, ret; 815 816 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 817 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 818 struct kvm_one_reg reg; 819 820 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 821 multi_ext_cfg->kvm_reg_id); 822 reg.addr = (uint64_t)&val; 823 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 824 if (ret != 0) { 825 if (errno == EINVAL) { 826 /* Silently default to 'false' if KVM does not support it. */ 827 multi_ext_cfg->supported = false; 828 val = false; 829 } else { 830 error_report("Unable to read ISA_EXT KVM register %s, " 831 "error code: %s", multi_ext_cfg->name, 832 strerrorname_np(errno)); 833 exit(EXIT_FAILURE); 834 } 835 } else { 836 multi_ext_cfg->supported = true; 837 } 838 839 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 840 } 841 842 if (cpu->cfg.ext_zicbom) { 843 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 844 } 845 846 if (cpu->cfg.ext_zicboz) { 847 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 848 } 849 } 850 851 static int uint64_cmp(const void *a, const void *b) 852 { 853 uint64_t val1 = *(const uint64_t *)a; 854 uint64_t val2 = *(const uint64_t *)b; 855 856 if (val1 < val2) { 857 return -1; 858 } 859 860 if (val1 > val2) { 861 return 1; 862 } 863 864 return 0; 865 } 866 867 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 868 { 869 KVMCPUConfig *multi_ext_cfg; 870 struct kvm_one_reg reg; 871 struct kvm_reg_list rl_struct; 872 struct kvm_reg_list *reglist; 873 uint64_t val, reg_id, *reg_search; 874 int i, ret; 875 876 rl_struct.n = 0; 877 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 878 879 /* 880 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 881 * (EINVAL). Use read_legacy() in this case. 882 */ 883 if (errno == EINVAL) { 884 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 885 } else if (errno != E2BIG) { 886 /* 887 * E2BIG is an expected error message for the API since we 888 * don't know the number of registers. The right amount will 889 * be written in rl_struct.n. 890 * 891 * Error out if we get any other errno. 892 */ 893 error_report("Error when accessing get-reg-list, code: %s", 894 strerrorname_np(errno)); 895 exit(EXIT_FAILURE); 896 } 897 898 reglist = g_malloc(sizeof(struct kvm_reg_list) + 899 rl_struct.n * sizeof(uint64_t)); 900 reglist->n = rl_struct.n; 901 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 902 if (ret) { 903 error_report("Error when reading KVM_GET_REG_LIST, code %s ", 904 strerrorname_np(errno)); 905 exit(EXIT_FAILURE); 906 } 907 908 /* sort reglist to use bsearch() */ 909 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 910 911 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 912 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 913 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 914 multi_ext_cfg->kvm_reg_id); 915 reg_search = bsearch(®_id, reglist->reg, reglist->n, 916 sizeof(uint64_t), uint64_cmp); 917 if (!reg_search) { 918 continue; 919 } 920 921 reg.id = reg_id; 922 reg.addr = (uint64_t)&val; 923 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 924 if (ret != 0) { 925 error_report("Unable to read ISA_EXT KVM register %s, " 926 "error code: %s", multi_ext_cfg->name, 927 strerrorname_np(errno)); 928 exit(EXIT_FAILURE); 929 } 930 931 multi_ext_cfg->supported = true; 932 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 933 } 934 935 if (cpu->cfg.ext_zicbom) { 936 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 937 } 938 939 if (cpu->cfg.ext_zicboz) { 940 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 941 } 942 } 943 944 static void riscv_init_kvm_registers(Object *cpu_obj) 945 { 946 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 947 KVMScratchCPU kvmcpu; 948 949 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 950 return; 951 } 952 953 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 954 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 955 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 956 957 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 958 } 959 960 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 961 KVM_CAP_LAST_INFO 962 }; 963 964 int kvm_arch_get_registers(CPUState *cs) 965 { 966 int ret = 0; 967 968 ret = kvm_riscv_get_regs_core(cs); 969 if (ret) { 970 return ret; 971 } 972 973 ret = kvm_riscv_get_regs_csr(cs); 974 if (ret) { 975 return ret; 976 } 977 978 ret = kvm_riscv_get_regs_fp(cs); 979 if (ret) { 980 return ret; 981 } 982 983 return ret; 984 } 985 986 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 987 { 988 if (cap_has_mp_state) { 989 struct kvm_mp_state mp_state = { 990 .mp_state = state 991 }; 992 993 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 994 if (ret) { 995 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 996 __func__, ret, strerror(-ret)); 997 return -1; 998 } 999 } 1000 1001 return 0; 1002 } 1003 1004 int kvm_arch_put_registers(CPUState *cs, int level) 1005 { 1006 int ret = 0; 1007 1008 ret = kvm_riscv_put_regs_core(cs); 1009 if (ret) { 1010 return ret; 1011 } 1012 1013 ret = kvm_riscv_put_regs_csr(cs); 1014 if (ret) { 1015 return ret; 1016 } 1017 1018 ret = kvm_riscv_put_regs_fp(cs); 1019 if (ret) { 1020 return ret; 1021 } 1022 1023 if (KVM_PUT_RESET_STATE == level) { 1024 RISCVCPU *cpu = RISCV_CPU(cs); 1025 if (cs->cpu_index == 0) { 1026 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1027 } else { 1028 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1029 } 1030 if (ret) { 1031 return ret; 1032 } 1033 } 1034 1035 return ret; 1036 } 1037 1038 int kvm_arch_release_virq_post(int virq) 1039 { 1040 return 0; 1041 } 1042 1043 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1044 uint64_t address, uint32_t data, PCIDevice *dev) 1045 { 1046 return 0; 1047 } 1048 1049 int kvm_arch_destroy_vcpu(CPUState *cs) 1050 { 1051 return 0; 1052 } 1053 1054 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1055 { 1056 return cpu->cpu_index; 1057 } 1058 1059 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1060 RunState state) 1061 { 1062 CPUState *cs = opaque; 1063 1064 if (running) { 1065 kvm_riscv_put_regs_timer(cs); 1066 } else { 1067 kvm_riscv_get_regs_timer(cs); 1068 } 1069 } 1070 1071 void kvm_arch_init_irq_routing(KVMState *s) 1072 { 1073 } 1074 1075 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1076 { 1077 CPURISCVState *env = &cpu->env; 1078 target_ulong reg; 1079 uint64_t id; 1080 int ret; 1081 1082 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1083 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1084 /* 1085 * cfg.mvendorid is an uint32 but a target_ulong will 1086 * be written. Assign it to a target_ulong var to avoid 1087 * writing pieces of other cpu->cfg fields in the reg. 1088 */ 1089 reg = cpu->cfg.mvendorid; 1090 ret = kvm_set_one_reg(cs, id, ®); 1091 if (ret != 0) { 1092 return ret; 1093 } 1094 1095 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1096 KVM_REG_RISCV_CONFIG_REG(marchid)); 1097 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1098 if (ret != 0) { 1099 return ret; 1100 } 1101 1102 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1103 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1104 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1105 1106 return ret; 1107 } 1108 1109 int kvm_arch_init_vcpu(CPUState *cs) 1110 { 1111 int ret = 0; 1112 RISCVCPU *cpu = RISCV_CPU(cs); 1113 1114 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1115 1116 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1117 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1118 if (ret != 0) { 1119 return ret; 1120 } 1121 } 1122 1123 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1124 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1125 1126 return ret; 1127 } 1128 1129 int kvm_arch_msi_data_to_gsi(uint32_t data) 1130 { 1131 abort(); 1132 } 1133 1134 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1135 int vector, PCIDevice *dev) 1136 { 1137 return 0; 1138 } 1139 1140 int kvm_arch_get_default_type(MachineState *ms) 1141 { 1142 return 0; 1143 } 1144 1145 int kvm_arch_init(MachineState *ms, KVMState *s) 1146 { 1147 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1148 return 0; 1149 } 1150 1151 int kvm_arch_irqchip_create(KVMState *s) 1152 { 1153 if (kvm_kernel_irqchip_split()) { 1154 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1155 exit(1); 1156 } 1157 1158 /* 1159 * We can create the VAIA using the newer device control API. 1160 */ 1161 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1162 } 1163 1164 int kvm_arch_process_async_events(CPUState *cs) 1165 { 1166 return 0; 1167 } 1168 1169 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1170 { 1171 } 1172 1173 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1174 { 1175 return MEMTXATTRS_UNSPECIFIED; 1176 } 1177 1178 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1179 { 1180 return true; 1181 } 1182 1183 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1184 { 1185 int ret = 0; 1186 unsigned char ch; 1187 switch (run->riscv_sbi.extension_id) { 1188 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1189 ch = run->riscv_sbi.args[0]; 1190 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1191 break; 1192 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1193 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1194 if (ret == sizeof(ch)) { 1195 run->riscv_sbi.ret[0] = ch; 1196 } else { 1197 run->riscv_sbi.ret[0] = -1; 1198 } 1199 ret = 0; 1200 break; 1201 default: 1202 qemu_log_mask(LOG_UNIMP, 1203 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1204 __func__, run->riscv_sbi.extension_id); 1205 ret = -1; 1206 break; 1207 } 1208 return ret; 1209 } 1210 1211 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1212 { 1213 int ret = 0; 1214 switch (run->exit_reason) { 1215 case KVM_EXIT_RISCV_SBI: 1216 ret = kvm_riscv_handle_sbi(cs, run); 1217 break; 1218 default: 1219 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1220 __func__, run->exit_reason); 1221 ret = -1; 1222 break; 1223 } 1224 return ret; 1225 } 1226 1227 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1228 { 1229 CPURISCVState *env = &cpu->env; 1230 int i; 1231 1232 if (!kvm_enabled()) { 1233 return; 1234 } 1235 for (i = 0; i < 32; i++) { 1236 env->gpr[i] = 0; 1237 } 1238 env->pc = cpu->env.kernel_addr; 1239 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1240 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1241 env->satp = 0; 1242 env->mie = 0; 1243 env->stvec = 0; 1244 env->sscratch = 0; 1245 env->sepc = 0; 1246 env->scause = 0; 1247 env->stval = 0; 1248 env->mip = 0; 1249 } 1250 1251 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1252 { 1253 int ret; 1254 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1255 1256 if (irq != IRQ_S_EXT) { 1257 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1258 abort(); 1259 } 1260 1261 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1262 if (ret < 0) { 1263 perror("Set irq failed"); 1264 abort(); 1265 } 1266 } 1267 1268 bool kvm_arch_cpu_check_are_resettable(void) 1269 { 1270 return true; 1271 } 1272 1273 static int aia_mode; 1274 1275 static const char *kvm_aia_mode_str(uint64_t mode) 1276 { 1277 switch (mode) { 1278 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1279 return "emul"; 1280 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1281 return "hwaccel"; 1282 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1283 default: 1284 return "auto"; 1285 }; 1286 } 1287 1288 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1289 { 1290 return g_strdup(kvm_aia_mode_str(aia_mode)); 1291 } 1292 1293 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1294 { 1295 if (!strcmp(val, "emul")) { 1296 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1297 } else if (!strcmp(val, "hwaccel")) { 1298 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1299 } else if (!strcmp(val, "auto")) { 1300 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1301 } else { 1302 error_setg(errp, "Invalid KVM AIA mode"); 1303 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1304 } 1305 } 1306 1307 void kvm_arch_accel_class_init(ObjectClass *oc) 1308 { 1309 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1310 riscv_set_kvm_aia); 1311 object_class_property_set_description(oc, "riscv-aia", 1312 "Set KVM AIA mode. Valid values are " 1313 "emul, hwaccel, and auto. Default " 1314 "is auto."); 1315 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1316 "auto"); 1317 } 1318 1319 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1320 uint64_t aia_irq_num, uint64_t aia_msi_num, 1321 uint64_t aplic_base, uint64_t imsic_base, 1322 uint64_t guest_num) 1323 { 1324 int ret, i; 1325 int aia_fd = -1; 1326 uint64_t default_aia_mode; 1327 uint64_t socket_count = riscv_socket_count(machine); 1328 uint64_t max_hart_per_socket = 0; 1329 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1330 uint64_t socket_bits, hart_bits, guest_bits; 1331 1332 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1333 1334 if (aia_fd < 0) { 1335 error_report("Unable to create in-kernel irqchip"); 1336 exit(1); 1337 } 1338 1339 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1340 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1341 &default_aia_mode, false, NULL); 1342 if (ret < 0) { 1343 error_report("KVM AIA: failed to get current KVM AIA mode"); 1344 exit(1); 1345 } 1346 qemu_log("KVM AIA: default mode is %s\n", 1347 kvm_aia_mode_str(default_aia_mode)); 1348 1349 if (default_aia_mode != aia_mode) { 1350 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1351 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1352 &aia_mode, true, NULL); 1353 if (ret < 0) 1354 warn_report("KVM AIA: failed to set KVM AIA mode"); 1355 else 1356 qemu_log("KVM AIA: set current mode to %s\n", 1357 kvm_aia_mode_str(aia_mode)); 1358 } 1359 1360 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1361 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1362 &aia_irq_num, true, NULL); 1363 if (ret < 0) { 1364 error_report("KVM AIA: failed to set number of input irq lines"); 1365 exit(1); 1366 } 1367 1368 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1369 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1370 &aia_msi_num, true, NULL); 1371 if (ret < 0) { 1372 error_report("KVM AIA: failed to set number of msi"); 1373 exit(1); 1374 } 1375 1376 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1377 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1378 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1379 &socket_bits, true, NULL); 1380 if (ret < 0) { 1381 error_report("KVM AIA: failed to set group_bits"); 1382 exit(1); 1383 } 1384 1385 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1386 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1387 &group_shift, true, NULL); 1388 if (ret < 0) { 1389 error_report("KVM AIA: failed to set group_shift"); 1390 exit(1); 1391 } 1392 1393 guest_bits = guest_num == 0 ? 0 : 1394 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1395 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1396 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1397 &guest_bits, true, NULL); 1398 if (ret < 0) { 1399 error_report("KVM AIA: failed to set guest_bits"); 1400 exit(1); 1401 } 1402 1403 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1404 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1405 &aplic_base, true, NULL); 1406 if (ret < 0) { 1407 error_report("KVM AIA: failed to set the base address of APLIC"); 1408 exit(1); 1409 } 1410 1411 for (socket = 0; socket < socket_count; socket++) { 1412 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1413 hart_count = riscv_socket_hart_count(machine, socket); 1414 base_hart = riscv_socket_first_hartid(machine, socket); 1415 1416 if (max_hart_per_socket < hart_count) { 1417 max_hart_per_socket = hart_count; 1418 } 1419 1420 for (i = 0; i < hart_count; i++) { 1421 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1422 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1423 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1424 &imsic_addr, true, NULL); 1425 if (ret < 0) { 1426 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1427 exit(1); 1428 } 1429 } 1430 } 1431 1432 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1433 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1434 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1435 &hart_bits, true, NULL); 1436 if (ret < 0) { 1437 error_report("KVM AIA: failed to set hart_bits"); 1438 exit(1); 1439 } 1440 1441 if (kvm_has_gsi_routing()) { 1442 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1443 /* KVM AIA only has one APLIC instance */ 1444 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1445 } 1446 kvm_gsi_routing_allowed = true; 1447 kvm_irqchip_commit_routes(kvm_state); 1448 } 1449 1450 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1451 KVM_DEV_RISCV_AIA_CTRL_INIT, 1452 NULL, true, NULL); 1453 if (ret < 0) { 1454 error_report("KVM AIA: initialized fail"); 1455 exit(1); 1456 } 1457 1458 kvm_msi_via_irqfd_allowed = true; 1459 } 1460 1461 static void kvm_cpu_instance_init(CPUState *cs) 1462 { 1463 Object *obj = OBJECT(RISCV_CPU(cs)); 1464 DeviceState *dev = DEVICE(obj); 1465 1466 riscv_init_kvm_registers(obj); 1467 1468 kvm_riscv_add_cpu_user_properties(obj); 1469 1470 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1471 /* Check if we have a specific KVM handler for the option */ 1472 if (object_property_find(obj, prop->name)) { 1473 continue; 1474 } 1475 qdev_property_add_static(dev, prop); 1476 } 1477 } 1478 1479 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1480 { 1481 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1482 1483 acc->cpu_instance_init = kvm_cpu_instance_init; 1484 } 1485 1486 static const TypeInfo kvm_cpu_accel_type_info = { 1487 .name = ACCEL_CPU_NAME("kvm"), 1488 1489 .parent = TYPE_ACCEL_CPU, 1490 .class_init = kvm_cpu_accel_class_init, 1491 .abstract = true, 1492 }; 1493 static void kvm_cpu_accel_register_types(void) 1494 { 1495 type_register_static(&kvm_cpu_accel_type_info); 1496 } 1497 type_init(kvm_cpu_accel_register_types); 1498 1499 static void riscv_host_cpu_init(Object *obj) 1500 { 1501 CPURISCVState *env = &RISCV_CPU(obj)->env; 1502 1503 #if defined(TARGET_RISCV32) 1504 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1505 #elif defined(TARGET_RISCV64) 1506 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1507 #endif 1508 } 1509 1510 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1511 { 1512 .name = TYPE_RISCV_CPU_HOST, 1513 .parent = TYPE_RISCV_CPU, 1514 .instance_init = riscv_host_cpu_init, 1515 } 1516 }; 1517 1518 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1519