1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 278 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 279 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 280 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 281 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 282 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 283 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 284 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 285 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 286 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 287 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 288 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 289 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 290 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 291 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 292 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 293 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 294 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 295 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 296 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 297 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 298 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 299 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 300 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 301 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 302 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 303 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 304 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 305 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 306 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 307 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 308 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 309 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 310 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 311 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 312 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 313 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 314 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 315 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 316 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 317 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 318 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 319 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 320 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 321 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 322 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 323 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 324 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 325 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 326 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 327 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 328 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 329 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 330 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 331 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 332 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 333 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 334 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 335 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 336 }; 337 338 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 339 { 340 return (void *)&cpu->cfg + kvmcfg->offset; 341 } 342 343 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 344 uint32_t val) 345 { 346 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 347 348 *ext_enabled = val; 349 } 350 351 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 352 KVMCPUConfig *multi_ext) 353 { 354 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 355 356 return *ext_enabled; 357 } 358 359 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 360 const char *name, 361 void *opaque, Error **errp) 362 { 363 KVMCPUConfig *multi_ext_cfg = opaque; 364 RISCVCPU *cpu = RISCV_CPU(obj); 365 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 366 367 visit_type_bool(v, name, &value, errp); 368 } 369 370 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 371 const char *name, 372 void *opaque, Error **errp) 373 { 374 KVMCPUConfig *multi_ext_cfg = opaque; 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 bool value, host_val; 377 378 if (!visit_type_bool(v, name, &value, errp)) { 379 return; 380 } 381 382 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 383 384 /* 385 * Ignore if the user is setting the same value 386 * as the host. 387 */ 388 if (value == host_val) { 389 return; 390 } 391 392 if (!multi_ext_cfg->supported) { 393 /* 394 * Error out if the user is trying to enable an 395 * extension that KVM doesn't support. Ignore 396 * option otherwise. 397 */ 398 if (value) { 399 error_setg(errp, "KVM does not support disabling extension %s", 400 multi_ext_cfg->name); 401 } 402 403 return; 404 } 405 406 multi_ext_cfg->user_set = true; 407 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 408 } 409 410 static KVMCPUConfig kvm_cbom_blocksize = { 411 .name = "cbom_blocksize", 412 .offset = CPU_CFG_OFFSET(cbom_blocksize), 413 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 414 }; 415 416 static KVMCPUConfig kvm_cboz_blocksize = { 417 .name = "cboz_blocksize", 418 .offset = CPU_CFG_OFFSET(cboz_blocksize), 419 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 420 }; 421 422 static KVMCPUConfig kvm_v_vlenb = { 423 .name = "vlenb", 424 .offset = CPU_CFG_OFFSET(vlenb), 425 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 426 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 427 }; 428 429 static KVMCPUConfig kvm_sbi_dbcn = { 430 .name = "sbi_dbcn", 431 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 432 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 433 }; 434 435 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 436 { 437 CPURISCVState *env = &cpu->env; 438 uint64_t id, reg; 439 int i, ret; 440 441 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 442 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 443 444 if (!multi_ext_cfg->user_set) { 445 continue; 446 } 447 448 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 449 multi_ext_cfg->kvm_reg_id); 450 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 451 ret = kvm_set_one_reg(cs, id, ®); 452 if (ret != 0) { 453 if (!reg && ret == -EINVAL) { 454 warn_report("KVM cannot disable extension %s", 455 multi_ext_cfg->name); 456 } else { 457 error_report("Unable to enable extension %s in KVM, error %d", 458 multi_ext_cfg->name, ret); 459 exit(EXIT_FAILURE); 460 } 461 } 462 } 463 } 464 465 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 466 const char *name, 467 void *opaque, Error **errp) 468 { 469 bool value = false; 470 471 visit_type_bool(v, name, &value, errp); 472 } 473 474 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 475 const char *name, 476 void *opaque, Error **errp) 477 { 478 const char *propname = opaque; 479 bool value; 480 481 if (!visit_type_bool(v, name, &value, errp)) { 482 return; 483 } 484 485 if (value) { 486 error_setg(errp, "'%s' is not available with KVM", 487 propname); 488 } 489 } 490 491 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 492 { 493 /* Check if KVM created the property already */ 494 if (object_property_find(obj, prop_name)) { 495 return; 496 } 497 498 /* 499 * Set the default to disabled for every extension 500 * unknown to KVM and error out if the user attempts 501 * to enable any of them. 502 */ 503 object_property_add(obj, prop_name, "bool", 504 cpu_get_cfg_unavailable, 505 cpu_set_cfg_unavailable, 506 NULL, (void *)prop_name); 507 } 508 509 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 510 const RISCVCPUMultiExtConfig *array) 511 { 512 const RISCVCPUMultiExtConfig *prop; 513 514 g_assert(array); 515 516 for (prop = array; prop && prop->name; prop++) { 517 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 518 } 519 } 520 521 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 522 { 523 int i; 524 525 riscv_add_satp_mode_properties(cpu_obj); 526 527 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 528 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 529 int bit = misa_cfg->offset; 530 531 misa_cfg->name = riscv_get_misa_ext_name(bit); 532 misa_cfg->description = riscv_get_misa_ext_description(bit); 533 534 object_property_add(cpu_obj, misa_cfg->name, "bool", 535 kvm_cpu_get_misa_ext_cfg, 536 kvm_cpu_set_misa_ext_cfg, 537 NULL, misa_cfg); 538 object_property_set_description(cpu_obj, misa_cfg->name, 539 misa_cfg->description); 540 } 541 542 for (i = 0; misa_bits[i] != 0; i++) { 543 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 544 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 545 } 546 547 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 548 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 549 550 object_property_add(cpu_obj, multi_cfg->name, "bool", 551 kvm_cpu_get_multi_ext_cfg, 552 kvm_cpu_set_multi_ext_cfg, 553 NULL, multi_cfg); 554 } 555 556 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 557 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 558 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 559 560 /* We don't have the needed KVM support for profiles */ 561 for (i = 0; riscv_profiles[i] != NULL; i++) { 562 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 563 } 564 } 565 566 static int kvm_riscv_get_regs_core(CPUState *cs) 567 { 568 int ret = 0; 569 int i; 570 target_ulong reg; 571 CPURISCVState *env = &RISCV_CPU(cs)->env; 572 573 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 574 if (ret) { 575 return ret; 576 } 577 env->pc = reg; 578 579 for (i = 1; i < 32; i++) { 580 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 581 ret = kvm_get_one_reg(cs, id, ®); 582 if (ret) { 583 return ret; 584 } 585 env->gpr[i] = reg; 586 } 587 588 return ret; 589 } 590 591 static int kvm_riscv_put_regs_core(CPUState *cs) 592 { 593 int ret = 0; 594 int i; 595 target_ulong reg; 596 CPURISCVState *env = &RISCV_CPU(cs)->env; 597 598 reg = env->pc; 599 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 600 if (ret) { 601 return ret; 602 } 603 604 for (i = 1; i < 32; i++) { 605 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 606 reg = env->gpr[i]; 607 ret = kvm_set_one_reg(cs, id, ®); 608 if (ret) { 609 return ret; 610 } 611 } 612 613 return ret; 614 } 615 616 static void kvm_riscv_reset_regs_csr(CPURISCVState *env) 617 { 618 env->mstatus = 0; 619 env->mie = 0; 620 env->stvec = 0; 621 env->sscratch = 0; 622 env->sepc = 0; 623 env->scause = 0; 624 env->stval = 0; 625 env->mip = 0; 626 env->satp = 0; 627 } 628 629 static int kvm_riscv_get_regs_csr(CPUState *cs) 630 { 631 CPURISCVState *env = &RISCV_CPU(cs)->env; 632 633 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 634 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 635 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 636 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 637 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 638 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 639 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 640 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 641 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 642 643 return 0; 644 } 645 646 static int kvm_riscv_put_regs_csr(CPUState *cs) 647 { 648 CPURISCVState *env = &RISCV_CPU(cs)->env; 649 650 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 651 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 652 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 653 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 654 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 655 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 656 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 657 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 658 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 659 660 return 0; 661 } 662 663 static int kvm_riscv_get_regs_fp(CPUState *cs) 664 { 665 int ret = 0; 666 int i; 667 CPURISCVState *env = &RISCV_CPU(cs)->env; 668 669 if (riscv_has_ext(env, RVD)) { 670 uint64_t reg; 671 for (i = 0; i < 32; i++) { 672 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 673 if (ret) { 674 return ret; 675 } 676 env->fpr[i] = reg; 677 } 678 return ret; 679 } 680 681 if (riscv_has_ext(env, RVF)) { 682 uint32_t reg; 683 for (i = 0; i < 32; i++) { 684 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 685 if (ret) { 686 return ret; 687 } 688 env->fpr[i] = reg; 689 } 690 return ret; 691 } 692 693 return ret; 694 } 695 696 static int kvm_riscv_put_regs_fp(CPUState *cs) 697 { 698 int ret = 0; 699 int i; 700 CPURISCVState *env = &RISCV_CPU(cs)->env; 701 702 if (riscv_has_ext(env, RVD)) { 703 uint64_t reg; 704 for (i = 0; i < 32; i++) { 705 reg = env->fpr[i]; 706 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 707 if (ret) { 708 return ret; 709 } 710 } 711 return ret; 712 } 713 714 if (riscv_has_ext(env, RVF)) { 715 uint32_t reg; 716 for (i = 0; i < 32; i++) { 717 reg = env->fpr[i]; 718 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 719 if (ret) { 720 return ret; 721 } 722 } 723 return ret; 724 } 725 726 return ret; 727 } 728 729 static void kvm_riscv_get_regs_timer(CPUState *cs) 730 { 731 CPURISCVState *env = &RISCV_CPU(cs)->env; 732 733 if (env->kvm_timer_dirty) { 734 return; 735 } 736 737 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 738 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 739 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 740 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 741 742 env->kvm_timer_dirty = true; 743 } 744 745 static void kvm_riscv_put_regs_timer(CPUState *cs) 746 { 747 uint64_t reg; 748 CPURISCVState *env = &RISCV_CPU(cs)->env; 749 750 if (!env->kvm_timer_dirty) { 751 return; 752 } 753 754 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 755 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 756 757 /* 758 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 759 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 760 * doesn't matter that adaping in QEMU now. 761 * TODO If KVM changes, adapt here. 762 */ 763 if (env->kvm_timer_state) { 764 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 765 } 766 767 /* 768 * For now, migration will not work between Hosts with different timer 769 * frequency. Therefore, we should check whether they are the same here 770 * during the migration. 771 */ 772 if (migration_is_running()) { 773 KVM_RISCV_GET_TIMER(cs, frequency, reg); 774 if (reg != env->kvm_timer_frequency) { 775 error_report("Dst Hosts timer frequency != Src Hosts"); 776 } 777 } 778 779 env->kvm_timer_dirty = false; 780 } 781 782 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 783 { 784 uint64_t reg; 785 786 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 787 788 return reg; 789 } 790 791 static int kvm_riscv_get_regs_vector(CPUState *cs) 792 { 793 RISCVCPU *cpu = RISCV_CPU(cs); 794 CPURISCVState *env = &cpu->env; 795 target_ulong reg; 796 uint64_t vreg_id; 797 int vreg_idx, ret = 0; 798 799 if (!riscv_has_ext(env, RVV)) { 800 return 0; 801 } 802 803 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 804 if (ret) { 805 return ret; 806 } 807 env->vstart = reg; 808 809 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 810 if (ret) { 811 return ret; 812 } 813 env->vl = reg; 814 815 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 816 if (ret) { 817 return ret; 818 } 819 env->vtype = reg; 820 821 if (kvm_v_vlenb.supported) { 822 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 823 if (ret) { 824 return ret; 825 } 826 cpu->cfg.vlenb = reg; 827 828 for (int i = 0; i < 32; i++) { 829 /* 830 * vreg[] is statically allocated using RV_VLEN_MAX. 831 * Use it instead of vlenb to calculate vreg_idx for 832 * simplicity. 833 */ 834 vreg_idx = i * RV_VLEN_MAX / 64; 835 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 836 837 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 838 if (ret) { 839 return ret; 840 } 841 } 842 } 843 844 return 0; 845 } 846 847 static int kvm_riscv_put_regs_vector(CPUState *cs) 848 { 849 RISCVCPU *cpu = RISCV_CPU(cs); 850 CPURISCVState *env = &cpu->env; 851 target_ulong reg; 852 uint64_t vreg_id; 853 int vreg_idx, ret = 0; 854 855 if (!riscv_has_ext(env, RVV)) { 856 return 0; 857 } 858 859 reg = env->vstart; 860 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 861 if (ret) { 862 return ret; 863 } 864 865 reg = env->vl; 866 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 867 if (ret) { 868 return ret; 869 } 870 871 reg = env->vtype; 872 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 873 if (ret) { 874 return ret; 875 } 876 877 if (kvm_v_vlenb.supported) { 878 reg = cpu->cfg.vlenb; 879 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 880 881 for (int i = 0; i < 32; i++) { 882 /* 883 * vreg[] is statically allocated using RV_VLEN_MAX. 884 * Use it instead of vlenb to calculate vreg_idx for 885 * simplicity. 886 */ 887 vreg_idx = i * RV_VLEN_MAX / 64; 888 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 889 890 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 891 if (ret) { 892 return ret; 893 } 894 } 895 } 896 897 return ret; 898 } 899 900 typedef struct KVMScratchCPU { 901 int kvmfd; 902 int vmfd; 903 int cpufd; 904 } KVMScratchCPU; 905 906 /* 907 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 908 * from target/arm/kvm.c. 909 */ 910 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 911 { 912 int kvmfd = -1, vmfd = -1, cpufd = -1; 913 914 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 915 if (kvmfd < 0) { 916 goto err; 917 } 918 do { 919 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 920 } while (vmfd == -1 && errno == EINTR); 921 if (vmfd < 0) { 922 goto err; 923 } 924 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 925 if (cpufd < 0) { 926 goto err; 927 } 928 929 scratch->kvmfd = kvmfd; 930 scratch->vmfd = vmfd; 931 scratch->cpufd = cpufd; 932 933 return true; 934 935 err: 936 if (cpufd >= 0) { 937 close(cpufd); 938 } 939 if (vmfd >= 0) { 940 close(vmfd); 941 } 942 if (kvmfd >= 0) { 943 close(kvmfd); 944 } 945 946 return false; 947 } 948 949 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 950 { 951 close(scratch->cpufd); 952 close(scratch->vmfd); 953 close(scratch->kvmfd); 954 } 955 956 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 957 { 958 CPURISCVState *env = &cpu->env; 959 struct kvm_one_reg reg; 960 int ret; 961 962 reg.id = RISCV_CONFIG_REG(env, mvendorid); 963 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 964 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 965 if (ret != 0) { 966 error_report("Unable to retrieve mvendorid from host, error %d", ret); 967 } 968 969 reg.id = RISCV_CONFIG_REG(env, marchid); 970 reg.addr = (uint64_t)&cpu->cfg.marchid; 971 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 972 if (ret != 0) { 973 error_report("Unable to retrieve marchid from host, error %d", ret); 974 } 975 976 reg.id = RISCV_CONFIG_REG(env, mimpid); 977 reg.addr = (uint64_t)&cpu->cfg.mimpid; 978 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 979 if (ret != 0) { 980 error_report("Unable to retrieve mimpid from host, error %d", ret); 981 } 982 } 983 984 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 985 KVMScratchCPU *kvmcpu) 986 { 987 CPURISCVState *env = &cpu->env; 988 struct kvm_one_reg reg; 989 int ret; 990 991 reg.id = RISCV_CONFIG_REG(env, isa); 992 reg.addr = (uint64_t)&env->misa_ext_mask; 993 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 994 995 if (ret) { 996 error_report("Unable to fetch ISA register from KVM, " 997 "error %d", ret); 998 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 999 exit(EXIT_FAILURE); 1000 } 1001 1002 env->misa_ext = env->misa_ext_mask; 1003 } 1004 1005 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1006 KVMCPUConfig *cbomz_cfg) 1007 { 1008 CPURISCVState *env = &cpu->env; 1009 struct kvm_one_reg reg; 1010 int ret; 1011 1012 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1013 cbomz_cfg->kvm_reg_id); 1014 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 1015 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1016 if (ret != 0) { 1017 error_report("Unable to read KVM reg %s, error %d", 1018 cbomz_cfg->name, ret); 1019 exit(EXIT_FAILURE); 1020 } 1021 } 1022 1023 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1024 KVMScratchCPU *kvmcpu) 1025 { 1026 CPURISCVState *env = &cpu->env; 1027 uint64_t val; 1028 int i, ret; 1029 1030 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1031 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1032 struct kvm_one_reg reg; 1033 1034 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1035 multi_ext_cfg->kvm_reg_id); 1036 reg.addr = (uint64_t)&val; 1037 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1038 if (ret != 0) { 1039 if (errno == EINVAL) { 1040 /* Silently default to 'false' if KVM does not support it. */ 1041 multi_ext_cfg->supported = false; 1042 val = false; 1043 } else { 1044 error_report("Unable to read ISA_EXT KVM register %s: %s", 1045 multi_ext_cfg->name, strerror(errno)); 1046 exit(EXIT_FAILURE); 1047 } 1048 } else { 1049 multi_ext_cfg->supported = true; 1050 } 1051 1052 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1053 } 1054 1055 if (cpu->cfg.ext_zicbom) { 1056 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1057 } 1058 1059 if (cpu->cfg.ext_zicboz) { 1060 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1061 } 1062 } 1063 1064 static int uint64_cmp(const void *a, const void *b) 1065 { 1066 uint64_t val1 = *(const uint64_t *)a; 1067 uint64_t val2 = *(const uint64_t *)b; 1068 1069 if (val1 < val2) { 1070 return -1; 1071 } 1072 1073 if (val1 > val2) { 1074 return 1; 1075 } 1076 1077 return 0; 1078 } 1079 1080 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1081 KVMScratchCPU *kvmcpu, 1082 struct kvm_reg_list *reglist) 1083 { 1084 struct kvm_reg_list *reg_search; 1085 1086 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1087 sizeof(uint64_t), uint64_cmp); 1088 1089 if (reg_search) { 1090 kvm_sbi_dbcn.supported = true; 1091 } 1092 } 1093 1094 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1095 struct kvm_reg_list *reglist) 1096 { 1097 struct kvm_one_reg reg; 1098 struct kvm_reg_list *reg_search; 1099 uint64_t val; 1100 int ret; 1101 1102 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1103 sizeof(uint64_t), uint64_cmp); 1104 1105 if (reg_search) { 1106 reg.id = kvm_v_vlenb.kvm_reg_id; 1107 reg.addr = (uint64_t)&val; 1108 1109 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1110 if (ret != 0) { 1111 error_report("Unable to read vlenb register, error code: %d", 1112 errno); 1113 exit(EXIT_FAILURE); 1114 } 1115 1116 kvm_v_vlenb.supported = true; 1117 cpu->cfg.vlenb = val; 1118 } 1119 } 1120 1121 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1122 { 1123 KVMCPUConfig *multi_ext_cfg; 1124 struct kvm_one_reg reg; 1125 struct kvm_reg_list rl_struct; 1126 struct kvm_reg_list *reglist; 1127 uint64_t val, reg_id, *reg_search; 1128 int i, ret; 1129 1130 rl_struct.n = 0; 1131 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1132 1133 /* 1134 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1135 * (EINVAL). Use read_legacy() in this case. 1136 */ 1137 if (errno == EINVAL) { 1138 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1139 } else if (errno != E2BIG) { 1140 /* 1141 * E2BIG is an expected error message for the API since we 1142 * don't know the number of registers. The right amount will 1143 * be written in rl_struct.n. 1144 * 1145 * Error out if we get any other errno. 1146 */ 1147 error_report("Error when accessing get-reg-list: %s", 1148 strerror(errno)); 1149 exit(EXIT_FAILURE); 1150 } 1151 1152 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1153 rl_struct.n * sizeof(uint64_t)); 1154 reglist->n = rl_struct.n; 1155 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1156 if (ret) { 1157 error_report("Error when reading KVM_GET_REG_LIST: %s", 1158 strerror(errno)); 1159 exit(EXIT_FAILURE); 1160 } 1161 1162 /* sort reglist to use bsearch() */ 1163 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1164 1165 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1166 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1167 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1168 multi_ext_cfg->kvm_reg_id); 1169 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1170 sizeof(uint64_t), uint64_cmp); 1171 if (!reg_search) { 1172 continue; 1173 } 1174 1175 reg.id = reg_id; 1176 reg.addr = (uint64_t)&val; 1177 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1178 if (ret != 0) { 1179 error_report("Unable to read ISA_EXT KVM register %s: %s", 1180 multi_ext_cfg->name, strerror(errno)); 1181 exit(EXIT_FAILURE); 1182 } 1183 1184 multi_ext_cfg->supported = true; 1185 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1186 } 1187 1188 if (cpu->cfg.ext_zicbom) { 1189 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1190 } 1191 1192 if (cpu->cfg.ext_zicboz) { 1193 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1194 } 1195 1196 if (riscv_has_ext(&cpu->env, RVV)) { 1197 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1198 } 1199 1200 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1201 } 1202 1203 static void riscv_init_kvm_registers(Object *cpu_obj) 1204 { 1205 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1206 KVMScratchCPU kvmcpu; 1207 1208 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1209 return; 1210 } 1211 1212 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1213 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1214 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1215 1216 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1217 } 1218 1219 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1220 KVM_CAP_LAST_INFO 1221 }; 1222 1223 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1224 { 1225 int ret = 0; 1226 1227 ret = kvm_riscv_get_regs_core(cs); 1228 if (ret) { 1229 return ret; 1230 } 1231 1232 ret = kvm_riscv_get_regs_csr(cs); 1233 if (ret) { 1234 return ret; 1235 } 1236 1237 ret = kvm_riscv_get_regs_fp(cs); 1238 if (ret) { 1239 return ret; 1240 } 1241 1242 ret = kvm_riscv_get_regs_vector(cs); 1243 if (ret) { 1244 return ret; 1245 } 1246 1247 return ret; 1248 } 1249 1250 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1251 { 1252 if (cap_has_mp_state) { 1253 struct kvm_mp_state mp_state = { 1254 .mp_state = state 1255 }; 1256 1257 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1258 if (ret) { 1259 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1260 __func__, ret, strerror(-ret)); 1261 return -1; 1262 } 1263 } 1264 1265 return 0; 1266 } 1267 1268 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1269 { 1270 int ret = 0; 1271 1272 ret = kvm_riscv_put_regs_core(cs); 1273 if (ret) { 1274 return ret; 1275 } 1276 1277 ret = kvm_riscv_put_regs_csr(cs); 1278 if (ret) { 1279 return ret; 1280 } 1281 1282 ret = kvm_riscv_put_regs_fp(cs); 1283 if (ret) { 1284 return ret; 1285 } 1286 1287 ret = kvm_riscv_put_regs_vector(cs); 1288 if (ret) { 1289 return ret; 1290 } 1291 1292 if (KVM_PUT_RESET_STATE == level) { 1293 RISCVCPU *cpu = RISCV_CPU(cs); 1294 if (cs->cpu_index == 0) { 1295 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1296 } else { 1297 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1298 } 1299 if (ret) { 1300 return ret; 1301 } 1302 } 1303 1304 return ret; 1305 } 1306 1307 int kvm_arch_release_virq_post(int virq) 1308 { 1309 return 0; 1310 } 1311 1312 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1313 uint64_t address, uint32_t data, PCIDevice *dev) 1314 { 1315 return 0; 1316 } 1317 1318 int kvm_arch_destroy_vcpu(CPUState *cs) 1319 { 1320 return 0; 1321 } 1322 1323 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1324 { 1325 return cpu->cpu_index; 1326 } 1327 1328 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1329 RunState state) 1330 { 1331 CPUState *cs = opaque; 1332 1333 if (running) { 1334 kvm_riscv_put_regs_timer(cs); 1335 } else { 1336 kvm_riscv_get_regs_timer(cs); 1337 } 1338 } 1339 1340 void kvm_arch_init_irq_routing(KVMState *s) 1341 { 1342 } 1343 1344 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1345 { 1346 CPURISCVState *env = &cpu->env; 1347 target_ulong reg; 1348 uint64_t id; 1349 int ret; 1350 1351 id = RISCV_CONFIG_REG(env, mvendorid); 1352 /* 1353 * cfg.mvendorid is an uint32 but a target_ulong will 1354 * be written. Assign it to a target_ulong var to avoid 1355 * writing pieces of other cpu->cfg fields in the reg. 1356 */ 1357 reg = cpu->cfg.mvendorid; 1358 ret = kvm_set_one_reg(cs, id, ®); 1359 if (ret != 0) { 1360 return ret; 1361 } 1362 1363 id = RISCV_CONFIG_REG(env, marchid); 1364 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1365 if (ret != 0) { 1366 return ret; 1367 } 1368 1369 id = RISCV_CONFIG_REG(env, mimpid); 1370 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1371 1372 return ret; 1373 } 1374 1375 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1376 { 1377 target_ulong reg = 1; 1378 1379 if (!kvm_sbi_dbcn.supported) { 1380 return 0; 1381 } 1382 1383 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1384 } 1385 1386 int kvm_arch_init_vcpu(CPUState *cs) 1387 { 1388 int ret = 0; 1389 RISCVCPU *cpu = RISCV_CPU(cs); 1390 1391 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1392 1393 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1394 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1395 if (ret != 0) { 1396 return ret; 1397 } 1398 } 1399 1400 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1401 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1402 1403 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1404 1405 return ret; 1406 } 1407 1408 int kvm_arch_msi_data_to_gsi(uint32_t data) 1409 { 1410 abort(); 1411 } 1412 1413 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1414 int vector, PCIDevice *dev) 1415 { 1416 return 0; 1417 } 1418 1419 int kvm_arch_get_default_type(MachineState *ms) 1420 { 1421 return 0; 1422 } 1423 1424 int kvm_arch_init(MachineState *ms, KVMState *s) 1425 { 1426 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1427 return 0; 1428 } 1429 1430 int kvm_arch_irqchip_create(KVMState *s) 1431 { 1432 /* 1433 * We can create the VAIA using the newer device control API. 1434 */ 1435 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1436 } 1437 1438 int kvm_arch_process_async_events(CPUState *cs) 1439 { 1440 return 0; 1441 } 1442 1443 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1444 { 1445 } 1446 1447 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1448 { 1449 return MEMTXATTRS_UNSPECIFIED; 1450 } 1451 1452 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1453 { 1454 return true; 1455 } 1456 1457 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1458 { 1459 g_autofree uint8_t *buf = NULL; 1460 RISCVCPU *cpu = RISCV_CPU(cs); 1461 target_ulong num_bytes; 1462 uint64_t addr; 1463 unsigned char ch; 1464 int ret; 1465 1466 switch (run->riscv_sbi.function_id) { 1467 case SBI_EXT_DBCN_CONSOLE_READ: 1468 case SBI_EXT_DBCN_CONSOLE_WRITE: 1469 num_bytes = run->riscv_sbi.args[0]; 1470 1471 if (num_bytes == 0) { 1472 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1473 run->riscv_sbi.ret[1] = 0; 1474 break; 1475 } 1476 1477 addr = run->riscv_sbi.args[1]; 1478 1479 /* 1480 * Handle the case where a 32 bit CPU is running in a 1481 * 64 bit addressing env. 1482 */ 1483 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1484 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1485 } 1486 1487 buf = g_malloc0(num_bytes); 1488 1489 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1490 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1491 if (ret < 0) { 1492 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1493 "reading chardev"); 1494 exit(1); 1495 } 1496 1497 cpu_physical_memory_write(addr, buf, ret); 1498 } else { 1499 cpu_physical_memory_read(addr, buf, num_bytes); 1500 1501 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1502 if (ret < 0) { 1503 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1504 "writing chardev"); 1505 exit(1); 1506 } 1507 } 1508 1509 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1510 run->riscv_sbi.ret[1] = ret; 1511 break; 1512 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1513 ch = run->riscv_sbi.args[0]; 1514 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1515 1516 if (ret < 0) { 1517 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1518 "writing chardev"); 1519 exit(1); 1520 } 1521 1522 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1523 run->riscv_sbi.ret[1] = 0; 1524 break; 1525 default: 1526 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1527 } 1528 } 1529 1530 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1531 { 1532 int ret = 0; 1533 unsigned char ch; 1534 switch (run->riscv_sbi.extension_id) { 1535 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1536 ch = run->riscv_sbi.args[0]; 1537 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1538 break; 1539 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1540 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1541 if (ret == sizeof(ch)) { 1542 run->riscv_sbi.ret[0] = ch; 1543 } else { 1544 run->riscv_sbi.ret[0] = -1; 1545 } 1546 ret = 0; 1547 break; 1548 case SBI_EXT_DBCN: 1549 kvm_riscv_handle_sbi_dbcn(cs, run); 1550 break; 1551 default: 1552 qemu_log_mask(LOG_UNIMP, 1553 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1554 __func__, run->riscv_sbi.extension_id); 1555 ret = -1; 1556 break; 1557 } 1558 return ret; 1559 } 1560 1561 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1562 { 1563 target_ulong csr_num = run->riscv_csr.csr_num; 1564 target_ulong new_value = run->riscv_csr.new_value; 1565 target_ulong write_mask = run->riscv_csr.write_mask; 1566 int ret = 0; 1567 1568 switch (csr_num) { 1569 case CSR_SEED: 1570 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1571 break; 1572 default: 1573 qemu_log_mask(LOG_UNIMP, 1574 "%s: un-handled CSR EXIT for CSR %lx\n", 1575 __func__, csr_num); 1576 ret = -1; 1577 break; 1578 } 1579 1580 return ret; 1581 } 1582 1583 static bool kvm_riscv_handle_debug(CPUState *cs) 1584 { 1585 RISCVCPU *cpu = RISCV_CPU(cs); 1586 CPURISCVState *env = &cpu->env; 1587 1588 /* Ensure PC is synchronised */ 1589 kvm_cpu_synchronize_state(cs); 1590 1591 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1592 return true; 1593 } 1594 1595 return false; 1596 } 1597 1598 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1599 { 1600 int ret = 0; 1601 switch (run->exit_reason) { 1602 case KVM_EXIT_RISCV_SBI: 1603 ret = kvm_riscv_handle_sbi(cs, run); 1604 break; 1605 case KVM_EXIT_RISCV_CSR: 1606 ret = kvm_riscv_handle_csr(cs, run); 1607 break; 1608 case KVM_EXIT_DEBUG: 1609 if (kvm_riscv_handle_debug(cs)) { 1610 ret = EXCP_DEBUG; 1611 } 1612 break; 1613 default: 1614 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1615 __func__, run->exit_reason); 1616 ret = -1; 1617 break; 1618 } 1619 return ret; 1620 } 1621 1622 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1623 { 1624 CPURISCVState *env = &cpu->env; 1625 int i; 1626 1627 for (i = 0; i < 32; i++) { 1628 env->gpr[i] = 0; 1629 } 1630 env->pc = cpu->env.kernel_addr; 1631 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1632 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1633 1634 kvm_riscv_reset_regs_csr(env); 1635 } 1636 1637 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1638 { 1639 int ret; 1640 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1641 1642 if (irq != IRQ_S_EXT) { 1643 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1644 abort(); 1645 } 1646 1647 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1648 if (ret < 0) { 1649 perror("Set irq failed"); 1650 abort(); 1651 } 1652 } 1653 1654 static int aia_mode; 1655 1656 static const char *kvm_aia_mode_str(uint64_t mode) 1657 { 1658 switch (mode) { 1659 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1660 return "emul"; 1661 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1662 return "hwaccel"; 1663 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1664 default: 1665 return "auto"; 1666 }; 1667 } 1668 1669 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1670 { 1671 return g_strdup(kvm_aia_mode_str(aia_mode)); 1672 } 1673 1674 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1675 { 1676 if (!strcmp(val, "emul")) { 1677 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1678 } else if (!strcmp(val, "hwaccel")) { 1679 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1680 } else if (!strcmp(val, "auto")) { 1681 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1682 } else { 1683 error_setg(errp, "Invalid KVM AIA mode"); 1684 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1685 } 1686 } 1687 1688 void kvm_arch_accel_class_init(ObjectClass *oc) 1689 { 1690 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1691 riscv_set_kvm_aia); 1692 object_class_property_set_description(oc, "riscv-aia", 1693 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1694 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1695 "if the host supports it"); 1696 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1697 "auto"); 1698 } 1699 1700 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1701 uint64_t aia_irq_num, uint64_t aia_msi_num, 1702 uint64_t aplic_base, uint64_t imsic_base, 1703 uint64_t guest_num) 1704 { 1705 int ret, i; 1706 int aia_fd = -1; 1707 uint64_t default_aia_mode; 1708 uint64_t socket_count = riscv_socket_count(machine); 1709 uint64_t max_hart_per_socket = 0; 1710 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1711 uint64_t socket_bits, hart_bits, guest_bits; 1712 uint64_t max_group_id; 1713 1714 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1715 1716 if (aia_fd < 0) { 1717 error_report("Unable to create in-kernel irqchip"); 1718 exit(1); 1719 } 1720 1721 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1722 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1723 &default_aia_mode, false, NULL); 1724 if (ret < 0) { 1725 error_report("KVM AIA: failed to get current KVM AIA mode"); 1726 exit(1); 1727 } 1728 1729 if (default_aia_mode != aia_mode) { 1730 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1731 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1732 &aia_mode, true, NULL); 1733 if (ret < 0) { 1734 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1735 "default host mode '%s'", 1736 kvm_aia_mode_str(aia_mode), 1737 kvm_aia_mode_str(default_aia_mode)); 1738 1739 /* failed to change AIA mode, use default */ 1740 aia_mode = default_aia_mode; 1741 } 1742 } 1743 1744 /* 1745 * Skip APLIC creation in KVM if we're running split mode. 1746 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1747 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1748 * since KVM won't be using it. 1749 */ 1750 if (!kvm_kernel_irqchip_split()) { 1751 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1752 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1753 &aia_irq_num, true, NULL); 1754 if (ret < 0) { 1755 error_report("KVM AIA: failed to set number of input irq lines"); 1756 exit(1); 1757 } 1758 1759 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1760 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1761 &aplic_base, true, NULL); 1762 if (ret < 0) { 1763 error_report("KVM AIA: failed to set the base address of APLIC"); 1764 exit(1); 1765 } 1766 } 1767 1768 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1769 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1770 &aia_msi_num, true, NULL); 1771 if (ret < 0) { 1772 error_report("KVM AIA: failed to set number of msi"); 1773 exit(1); 1774 } 1775 1776 1777 if (socket_count > 1) { 1778 max_group_id = socket_count - 1; 1779 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1780 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1781 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1782 &socket_bits, true, NULL); 1783 if (ret < 0) { 1784 error_report("KVM AIA: failed to set group_bits"); 1785 exit(1); 1786 } 1787 1788 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1789 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1790 &group_shift, true, NULL); 1791 if (ret < 0) { 1792 error_report("KVM AIA: failed to set group_shift"); 1793 exit(1); 1794 } 1795 } 1796 1797 guest_bits = guest_num == 0 ? 0 : 1798 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1799 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1800 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1801 &guest_bits, true, NULL); 1802 if (ret < 0) { 1803 error_report("KVM AIA: failed to set guest_bits"); 1804 exit(1); 1805 } 1806 1807 for (socket = 0; socket < socket_count; socket++) { 1808 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1809 hart_count = riscv_socket_hart_count(machine, socket); 1810 base_hart = riscv_socket_first_hartid(machine, socket); 1811 1812 if (max_hart_per_socket < hart_count) { 1813 max_hart_per_socket = hart_count; 1814 } 1815 1816 for (i = 0; i < hart_count; i++) { 1817 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1818 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1819 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1820 &imsic_addr, true, NULL); 1821 if (ret < 0) { 1822 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1823 exit(1); 1824 } 1825 } 1826 } 1827 1828 1829 if (max_hart_per_socket > 1) { 1830 max_hart_per_socket--; 1831 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1832 } else { 1833 hart_bits = 0; 1834 } 1835 1836 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1837 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1838 &hart_bits, true, NULL); 1839 if (ret < 0) { 1840 error_report("KVM AIA: failed to set hart_bits"); 1841 exit(1); 1842 } 1843 1844 if (kvm_has_gsi_routing()) { 1845 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1846 /* KVM AIA only has one APLIC instance */ 1847 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1848 } 1849 kvm_gsi_routing_allowed = true; 1850 kvm_irqchip_commit_routes(kvm_state); 1851 } 1852 1853 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1854 KVM_DEV_RISCV_AIA_CTRL_INIT, 1855 NULL, true, NULL); 1856 if (ret < 0) { 1857 error_report("KVM AIA: initialized fail"); 1858 exit(1); 1859 } 1860 1861 kvm_msi_via_irqfd_allowed = true; 1862 } 1863 1864 static void kvm_cpu_instance_init(CPUState *cs) 1865 { 1866 Object *obj = OBJECT(RISCV_CPU(cs)); 1867 1868 riscv_init_kvm_registers(obj); 1869 1870 kvm_riscv_add_cpu_user_properties(obj); 1871 } 1872 1873 /* 1874 * We'll get here via the following path: 1875 * 1876 * riscv_cpu_realize() 1877 * -> cpu_exec_realizefn() 1878 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1879 */ 1880 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1881 { 1882 RISCVCPU *cpu = RISCV_CPU(cs); 1883 int ret; 1884 1885 if (riscv_has_ext(&cpu->env, RVV)) { 1886 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1887 if (ret) { 1888 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1889 strerrorname_np(errno)); 1890 return false; 1891 } 1892 } 1893 1894 return true; 1895 } 1896 1897 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1898 { 1899 CPURISCVState *env = &cpu->env; 1900 KVMScratchCPU kvmcpu; 1901 struct kvm_one_reg reg; 1902 uint64_t val; 1903 int ret; 1904 1905 /* short-circuit without spinning the scratch CPU */ 1906 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1907 !riscv_has_ext(env, RVV)) { 1908 return; 1909 } 1910 1911 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1912 error_setg(errp, "Unable to create scratch KVM cpu"); 1913 return; 1914 } 1915 1916 if (cpu->cfg.ext_zicbom && 1917 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1918 1919 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1920 kvm_cbom_blocksize.kvm_reg_id); 1921 reg.addr = (uint64_t)&val; 1922 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1923 if (ret != 0) { 1924 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1925 return; 1926 } 1927 1928 if (cpu->cfg.cbom_blocksize != val) { 1929 error_setg(errp, "Unable to set cbom_blocksize to a different " 1930 "value than the host (%lu)", val); 1931 return; 1932 } 1933 } 1934 1935 if (cpu->cfg.ext_zicboz && 1936 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1937 1938 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1939 kvm_cboz_blocksize.kvm_reg_id); 1940 reg.addr = (uint64_t)&val; 1941 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1942 if (ret != 0) { 1943 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1944 return; 1945 } 1946 1947 if (cpu->cfg.cboz_blocksize != val) { 1948 error_setg(errp, "Unable to set cboz_blocksize to a different " 1949 "value than the host (%lu)", val); 1950 return; 1951 } 1952 } 1953 1954 /* Users are setting vlen, not vlenb */ 1955 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1956 if (!kvm_v_vlenb.supported) { 1957 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1958 return; 1959 } 1960 1961 reg.id = kvm_v_vlenb.kvm_reg_id; 1962 reg.addr = (uint64_t)&val; 1963 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1964 if (ret != 0) { 1965 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1966 return; 1967 } 1968 1969 if (cpu->cfg.vlenb != val) { 1970 error_setg(errp, "Unable to set 'vlen' to a different " 1971 "value than the host (%lu)", val * 8); 1972 return; 1973 } 1974 } 1975 1976 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1977 } 1978 1979 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1980 { 1981 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1982 1983 acc->cpu_instance_init = kvm_cpu_instance_init; 1984 acc->cpu_target_realize = kvm_cpu_realize; 1985 } 1986 1987 static const TypeInfo kvm_cpu_accel_type_info = { 1988 .name = ACCEL_CPU_NAME("kvm"), 1989 1990 .parent = TYPE_ACCEL_CPU, 1991 .class_init = kvm_cpu_accel_class_init, 1992 .abstract = true, 1993 }; 1994 static void kvm_cpu_accel_register_types(void) 1995 { 1996 type_register_static(&kvm_cpu_accel_type_info); 1997 } 1998 type_init(kvm_cpu_accel_register_types); 1999 2000 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 2001 { 2002 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 2003 2004 #if defined(TARGET_RISCV32) 2005 mcc->misa_mxl_max = MXL_RV32; 2006 #elif defined(TARGET_RISCV64) 2007 mcc->misa_mxl_max = MXL_RV64; 2008 #endif 2009 } 2010 2011 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2012 { 2013 .name = TYPE_RISCV_CPU_HOST, 2014 .parent = TYPE_RISCV_CPU, 2015 .class_init = riscv_host_cpu_class_init, 2016 } 2017 }; 2018 2019 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2020 2021 static const uint32_t ebreak_insn = 0x00100073; 2022 static const uint16_t c_ebreak_insn = 0x9002; 2023 2024 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2025 { 2026 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2027 return -EINVAL; 2028 } 2029 2030 if ((bp->saved_insn & 0x3) == 0x3) { 2031 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2032 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2033 return -EINVAL; 2034 } 2035 } else { 2036 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2037 return -EINVAL; 2038 } 2039 } 2040 2041 return 0; 2042 } 2043 2044 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2045 { 2046 uint32_t ebreak; 2047 uint16_t c_ebreak; 2048 2049 if ((bp->saved_insn & 0x3) == 0x3) { 2050 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2051 ebreak != ebreak_insn || 2052 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2053 return -EINVAL; 2054 } 2055 } else { 2056 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2057 c_ebreak != c_ebreak_insn || 2058 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2059 return -EINVAL; 2060 } 2061 } 2062 2063 return 0; 2064 } 2065 2066 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2067 { 2068 /* TODO; To be implemented later. */ 2069 return -EINVAL; 2070 } 2071 2072 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2073 { 2074 /* TODO; To be implemented later. */ 2075 return -EINVAL; 2076 } 2077 2078 void kvm_arch_remove_all_hw_breakpoints(void) 2079 { 2080 /* TODO; To be implemented later. */ 2081 } 2082 2083 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2084 { 2085 if (kvm_sw_breakpoints_active(cs)) { 2086 dbg->control |= KVM_GUESTDBG_ENABLE; 2087 } 2088 } 2089