1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "accel/accel-cpu-target.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "system/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 278 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 279 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 280 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 281 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 282 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 283 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 284 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 285 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 286 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 287 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 288 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 289 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 290 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 291 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 292 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 293 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 294 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 295 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 296 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 297 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 298 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 299 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 300 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 301 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 302 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 303 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 304 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 305 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 306 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 307 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 308 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 309 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 310 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 311 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 312 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 313 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 314 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 315 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 316 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 317 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 318 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 319 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 320 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 321 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 322 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 323 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 324 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 325 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 326 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 327 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 328 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 329 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 330 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 331 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 332 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 333 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 334 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 335 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 336 }; 337 338 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 339 { 340 return (void *)&cpu->cfg + kvmcfg->offset; 341 } 342 343 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 344 uint32_t val) 345 { 346 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 347 348 *ext_enabled = val; 349 } 350 351 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 352 KVMCPUConfig *multi_ext) 353 { 354 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 355 356 return *ext_enabled; 357 } 358 359 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 360 const char *name, 361 void *opaque, Error **errp) 362 { 363 KVMCPUConfig *multi_ext_cfg = opaque; 364 RISCVCPU *cpu = RISCV_CPU(obj); 365 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 366 367 visit_type_bool(v, name, &value, errp); 368 } 369 370 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 371 const char *name, 372 void *opaque, Error **errp) 373 { 374 KVMCPUConfig *multi_ext_cfg = opaque; 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 bool value, host_val; 377 378 if (!visit_type_bool(v, name, &value, errp)) { 379 return; 380 } 381 382 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 383 384 /* 385 * Ignore if the user is setting the same value 386 * as the host. 387 */ 388 if (value == host_val) { 389 return; 390 } 391 392 if (!multi_ext_cfg->supported) { 393 /* 394 * Error out if the user is trying to enable an 395 * extension that KVM doesn't support. Ignore 396 * option otherwise. 397 */ 398 if (value) { 399 error_setg(errp, "KVM does not support disabling extension %s", 400 multi_ext_cfg->name); 401 } 402 403 return; 404 } 405 406 multi_ext_cfg->user_set = true; 407 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 408 } 409 410 static KVMCPUConfig kvm_cbom_blocksize = { 411 .name = "cbom_blocksize", 412 .offset = CPU_CFG_OFFSET(cbom_blocksize), 413 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 414 }; 415 416 static KVMCPUConfig kvm_cboz_blocksize = { 417 .name = "cboz_blocksize", 418 .offset = CPU_CFG_OFFSET(cboz_blocksize), 419 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 420 }; 421 422 static KVMCPUConfig kvm_v_vlenb = { 423 .name = "vlenb", 424 .offset = CPU_CFG_OFFSET(vlenb), 425 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 426 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 427 }; 428 429 static KVMCPUConfig kvm_sbi_dbcn = { 430 .name = "sbi_dbcn", 431 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 432 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 433 }; 434 435 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 436 { 437 CPURISCVState *env = &cpu->env; 438 uint64_t id, reg; 439 int i, ret; 440 441 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 442 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 443 444 if (!multi_ext_cfg->user_set) { 445 continue; 446 } 447 448 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 449 multi_ext_cfg->kvm_reg_id); 450 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 451 ret = kvm_set_one_reg(cs, id, ®); 452 if (ret != 0) { 453 if (!reg && ret == -EINVAL) { 454 warn_report("KVM cannot disable extension %s", 455 multi_ext_cfg->name); 456 } else { 457 error_report("Unable to enable extension %s in KVM, error %d", 458 multi_ext_cfg->name, ret); 459 exit(EXIT_FAILURE); 460 } 461 } 462 } 463 } 464 465 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 466 const char *name, 467 void *opaque, Error **errp) 468 { 469 bool value = false; 470 471 visit_type_bool(v, name, &value, errp); 472 } 473 474 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 475 const char *name, 476 void *opaque, Error **errp) 477 { 478 const char *propname = opaque; 479 bool value; 480 481 if (!visit_type_bool(v, name, &value, errp)) { 482 return; 483 } 484 485 if (value) { 486 error_setg(errp, "'%s' is not available with KVM", 487 propname); 488 } 489 } 490 491 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 492 { 493 /* Check if KVM created the property already */ 494 if (object_property_find(obj, prop_name)) { 495 return; 496 } 497 498 /* 499 * Set the default to disabled for every extension 500 * unknown to KVM and error out if the user attempts 501 * to enable any of them. 502 */ 503 object_property_add(obj, prop_name, "bool", 504 cpu_get_cfg_unavailable, 505 cpu_set_cfg_unavailable, 506 NULL, (void *)prop_name); 507 } 508 509 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 510 const RISCVCPUMultiExtConfig *array) 511 { 512 const RISCVCPUMultiExtConfig *prop; 513 514 g_assert(array); 515 516 for (prop = array; prop && prop->name; prop++) { 517 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 518 } 519 } 520 521 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 522 { 523 int i; 524 525 riscv_add_satp_mode_properties(cpu_obj); 526 527 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 528 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 529 int bit = misa_cfg->offset; 530 531 misa_cfg->name = riscv_get_misa_ext_name(bit); 532 misa_cfg->description = riscv_get_misa_ext_description(bit); 533 534 object_property_add(cpu_obj, misa_cfg->name, "bool", 535 kvm_cpu_get_misa_ext_cfg, 536 kvm_cpu_set_misa_ext_cfg, 537 NULL, misa_cfg); 538 object_property_set_description(cpu_obj, misa_cfg->name, 539 misa_cfg->description); 540 } 541 542 for (i = 0; misa_bits[i] != 0; i++) { 543 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 544 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 545 } 546 547 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 548 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 549 550 object_property_add(cpu_obj, multi_cfg->name, "bool", 551 kvm_cpu_get_multi_ext_cfg, 552 kvm_cpu_set_multi_ext_cfg, 553 NULL, multi_cfg); 554 } 555 556 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 557 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 558 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 559 560 /* We don't have the needed KVM support for profiles */ 561 for (i = 0; riscv_profiles[i] != NULL; i++) { 562 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 563 } 564 } 565 566 static int kvm_riscv_get_regs_core(CPUState *cs) 567 { 568 int ret = 0; 569 int i; 570 target_ulong reg; 571 CPURISCVState *env = &RISCV_CPU(cs)->env; 572 573 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 574 if (ret) { 575 return ret; 576 } 577 env->pc = reg; 578 579 for (i = 1; i < 32; i++) { 580 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 581 ret = kvm_get_one_reg(cs, id, ®); 582 if (ret) { 583 return ret; 584 } 585 env->gpr[i] = reg; 586 } 587 588 return ret; 589 } 590 591 static int kvm_riscv_put_regs_core(CPUState *cs) 592 { 593 int ret = 0; 594 int i; 595 target_ulong reg; 596 CPURISCVState *env = &RISCV_CPU(cs)->env; 597 598 reg = env->pc; 599 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 600 if (ret) { 601 return ret; 602 } 603 604 for (i = 1; i < 32; i++) { 605 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 606 reg = env->gpr[i]; 607 ret = kvm_set_one_reg(cs, id, ®); 608 if (ret) { 609 return ret; 610 } 611 } 612 613 return ret; 614 } 615 616 static int kvm_riscv_get_regs_csr(CPUState *cs) 617 { 618 CPURISCVState *env = &RISCV_CPU(cs)->env; 619 620 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 621 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 622 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 623 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 624 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 625 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 626 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 627 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 628 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 629 630 return 0; 631 } 632 633 static int kvm_riscv_put_regs_csr(CPUState *cs) 634 { 635 CPURISCVState *env = &RISCV_CPU(cs)->env; 636 637 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 638 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 639 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 640 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 641 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 642 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 643 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 644 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 645 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 646 647 return 0; 648 } 649 650 static void kvm_riscv_reset_regs_csr(CPURISCVState *env) 651 { 652 env->mstatus = 0; 653 env->mie = 0; 654 env->stvec = 0; 655 env->sscratch = 0; 656 env->sepc = 0; 657 env->scause = 0; 658 env->stval = 0; 659 env->mip = 0; 660 env->satp = 0; 661 } 662 663 static int kvm_riscv_get_regs_fp(CPUState *cs) 664 { 665 int ret = 0; 666 int i; 667 CPURISCVState *env = &RISCV_CPU(cs)->env; 668 669 if (riscv_has_ext(env, RVD)) { 670 uint64_t reg; 671 for (i = 0; i < 32; i++) { 672 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 673 if (ret) { 674 return ret; 675 } 676 env->fpr[i] = reg; 677 } 678 return ret; 679 } 680 681 if (riscv_has_ext(env, RVF)) { 682 uint32_t reg; 683 for (i = 0; i < 32; i++) { 684 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 685 if (ret) { 686 return ret; 687 } 688 env->fpr[i] = reg; 689 } 690 return ret; 691 } 692 693 return ret; 694 } 695 696 static int kvm_riscv_put_regs_fp(CPUState *cs) 697 { 698 int ret = 0; 699 int i; 700 CPURISCVState *env = &RISCV_CPU(cs)->env; 701 702 if (riscv_has_ext(env, RVD)) { 703 uint64_t reg; 704 for (i = 0; i < 32; i++) { 705 reg = env->fpr[i]; 706 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 707 if (ret) { 708 return ret; 709 } 710 } 711 return ret; 712 } 713 714 if (riscv_has_ext(env, RVF)) { 715 uint32_t reg; 716 for (i = 0; i < 32; i++) { 717 reg = env->fpr[i]; 718 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 719 if (ret) { 720 return ret; 721 } 722 } 723 return ret; 724 } 725 726 return ret; 727 } 728 729 static void kvm_riscv_get_regs_timer(CPUState *cs) 730 { 731 CPURISCVState *env = &RISCV_CPU(cs)->env; 732 733 if (env->kvm_timer_dirty) { 734 return; 735 } 736 737 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 738 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 739 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 740 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 741 742 env->kvm_timer_dirty = true; 743 } 744 745 static void kvm_riscv_put_regs_timer(CPUState *cs) 746 { 747 uint64_t reg; 748 CPURISCVState *env = &RISCV_CPU(cs)->env; 749 750 if (!env->kvm_timer_dirty) { 751 return; 752 } 753 754 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 755 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 756 757 /* 758 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 759 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 760 * doesn't matter that adaping in QEMU now. 761 * TODO If KVM changes, adapt here. 762 */ 763 if (env->kvm_timer_state) { 764 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 765 } 766 767 /* 768 * For now, migration will not work between Hosts with different timer 769 * frequency. Therefore, we should check whether they are the same here 770 * during the migration. 771 */ 772 if (migration_is_running()) { 773 KVM_RISCV_GET_TIMER(cs, frequency, reg); 774 if (reg != env->kvm_timer_frequency) { 775 error_report("Dst Hosts timer frequency != Src Hosts"); 776 } 777 } 778 779 env->kvm_timer_dirty = false; 780 } 781 782 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 783 { 784 uint64_t reg; 785 786 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 787 788 return reg; 789 } 790 791 static int kvm_riscv_get_regs_vector(CPUState *cs) 792 { 793 RISCVCPU *cpu = RISCV_CPU(cs); 794 CPURISCVState *env = &cpu->env; 795 target_ulong reg; 796 uint64_t vreg_id; 797 int vreg_idx, ret = 0; 798 799 if (!riscv_has_ext(env, RVV)) { 800 return 0; 801 } 802 803 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 804 if (ret) { 805 return ret; 806 } 807 env->vstart = reg; 808 809 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 810 if (ret) { 811 return ret; 812 } 813 env->vl = reg; 814 815 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 816 if (ret) { 817 return ret; 818 } 819 env->vtype = reg; 820 821 if (kvm_v_vlenb.supported) { 822 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 823 if (ret) { 824 return ret; 825 } 826 cpu->cfg.vlenb = reg; 827 828 for (int i = 0; i < 32; i++) { 829 /* 830 * vreg[] is statically allocated using RV_VLEN_MAX. 831 * Use it instead of vlenb to calculate vreg_idx for 832 * simplicity. 833 */ 834 vreg_idx = i * RV_VLEN_MAX / 64; 835 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 836 837 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 838 if (ret) { 839 return ret; 840 } 841 } 842 } 843 844 return 0; 845 } 846 847 static int kvm_riscv_put_regs_vector(CPUState *cs) 848 { 849 RISCVCPU *cpu = RISCV_CPU(cs); 850 CPURISCVState *env = &cpu->env; 851 target_ulong reg; 852 uint64_t vreg_id; 853 int vreg_idx, ret = 0; 854 855 if (!riscv_has_ext(env, RVV)) { 856 return 0; 857 } 858 859 reg = env->vstart; 860 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 861 if (ret) { 862 return ret; 863 } 864 865 reg = env->vl; 866 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 867 if (ret) { 868 return ret; 869 } 870 871 reg = env->vtype; 872 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 873 if (ret) { 874 return ret; 875 } 876 877 if (kvm_v_vlenb.supported) { 878 reg = cpu->cfg.vlenb; 879 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 880 881 for (int i = 0; i < 32; i++) { 882 /* 883 * vreg[] is statically allocated using RV_VLEN_MAX. 884 * Use it instead of vlenb to calculate vreg_idx for 885 * simplicity. 886 */ 887 vreg_idx = i * RV_VLEN_MAX / 64; 888 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 889 890 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 891 if (ret) { 892 return ret; 893 } 894 } 895 } 896 897 return ret; 898 } 899 900 typedef struct KVMScratchCPU { 901 int kvmfd; 902 int vmfd; 903 int cpufd; 904 } KVMScratchCPU; 905 906 /* 907 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 908 * from target/arm/kvm.c. 909 */ 910 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 911 { 912 int kvmfd = -1, vmfd = -1, cpufd = -1; 913 914 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 915 if (kvmfd < 0) { 916 goto err; 917 } 918 do { 919 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 920 } while (vmfd == -1 && errno == EINTR); 921 if (vmfd < 0) { 922 goto err; 923 } 924 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 925 if (cpufd < 0) { 926 goto err; 927 } 928 929 scratch->kvmfd = kvmfd; 930 scratch->vmfd = vmfd; 931 scratch->cpufd = cpufd; 932 933 return true; 934 935 err: 936 if (cpufd >= 0) { 937 close(cpufd); 938 } 939 if (vmfd >= 0) { 940 close(vmfd); 941 } 942 if (kvmfd >= 0) { 943 close(kvmfd); 944 } 945 946 return false; 947 } 948 949 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 950 { 951 close(scratch->cpufd); 952 close(scratch->vmfd); 953 close(scratch->kvmfd); 954 } 955 956 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 957 { 958 CPURISCVState *env = &cpu->env; 959 struct kvm_one_reg reg; 960 int ret; 961 962 reg.id = RISCV_CONFIG_REG(env, mvendorid); 963 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 964 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 965 if (ret != 0) { 966 error_report("Unable to retrieve mvendorid from host, error %d", ret); 967 } 968 969 reg.id = RISCV_CONFIG_REG(env, marchid); 970 reg.addr = (uint64_t)&cpu->cfg.marchid; 971 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 972 if (ret != 0) { 973 error_report("Unable to retrieve marchid from host, error %d", ret); 974 } 975 976 reg.id = RISCV_CONFIG_REG(env, mimpid); 977 reg.addr = (uint64_t)&cpu->cfg.mimpid; 978 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 979 if (ret != 0) { 980 error_report("Unable to retrieve mimpid from host, error %d", ret); 981 } 982 } 983 984 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 985 KVMScratchCPU *kvmcpu) 986 { 987 CPURISCVState *env = &cpu->env; 988 struct kvm_one_reg reg; 989 int ret; 990 991 reg.id = RISCV_CONFIG_REG(env, isa); 992 reg.addr = (uint64_t)&env->misa_ext_mask; 993 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 994 995 if (ret) { 996 error_report("Unable to fetch ISA register from KVM, " 997 "error %d", ret); 998 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 999 exit(EXIT_FAILURE); 1000 } 1001 1002 env->misa_ext = env->misa_ext_mask; 1003 } 1004 1005 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1006 KVMCPUConfig *cbomz_cfg) 1007 { 1008 CPURISCVState *env = &cpu->env; 1009 struct kvm_one_reg reg; 1010 int ret; 1011 1012 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1013 cbomz_cfg->kvm_reg_id); 1014 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 1015 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1016 if (ret != 0) { 1017 error_report("Unable to read KVM reg %s, error %d", 1018 cbomz_cfg->name, ret); 1019 exit(EXIT_FAILURE); 1020 } 1021 } 1022 1023 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1024 KVMScratchCPU *kvmcpu) 1025 { 1026 CPURISCVState *env = &cpu->env; 1027 uint64_t val; 1028 int i, ret; 1029 1030 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1031 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1032 struct kvm_one_reg reg; 1033 1034 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1035 multi_ext_cfg->kvm_reg_id); 1036 reg.addr = (uint64_t)&val; 1037 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1038 if (ret != 0) { 1039 if (errno == EINVAL) { 1040 /* Silently default to 'false' if KVM does not support it. */ 1041 multi_ext_cfg->supported = false; 1042 val = false; 1043 } else { 1044 error_report("Unable to read ISA_EXT KVM register %s: %s", 1045 multi_ext_cfg->name, strerror(errno)); 1046 exit(EXIT_FAILURE); 1047 } 1048 } else { 1049 multi_ext_cfg->supported = true; 1050 } 1051 1052 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1053 } 1054 1055 if (cpu->cfg.ext_zicbom) { 1056 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1057 } 1058 1059 if (cpu->cfg.ext_zicboz) { 1060 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1061 } 1062 } 1063 1064 static int uint64_cmp(const void *a, const void *b) 1065 { 1066 uint64_t val1 = *(const uint64_t *)a; 1067 uint64_t val2 = *(const uint64_t *)b; 1068 1069 if (val1 < val2) { 1070 return -1; 1071 } 1072 1073 if (val1 > val2) { 1074 return 1; 1075 } 1076 1077 return 0; 1078 } 1079 1080 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1081 struct kvm_reg_list *reglist) 1082 { 1083 struct kvm_reg_list *reg_search; 1084 1085 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1086 sizeof(uint64_t), uint64_cmp); 1087 1088 if (reg_search) { 1089 kvm_sbi_dbcn.supported = true; 1090 } 1091 } 1092 1093 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1094 struct kvm_reg_list *reglist) 1095 { 1096 struct kvm_one_reg reg; 1097 struct kvm_reg_list *reg_search; 1098 uint64_t val; 1099 int ret; 1100 1101 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1102 sizeof(uint64_t), uint64_cmp); 1103 1104 if (reg_search) { 1105 reg.id = kvm_v_vlenb.kvm_reg_id; 1106 reg.addr = (uint64_t)&val; 1107 1108 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1109 if (ret != 0) { 1110 error_report("Unable to read vlenb register, error code: %d", 1111 errno); 1112 exit(EXIT_FAILURE); 1113 } 1114 1115 kvm_v_vlenb.supported = true; 1116 cpu->cfg.vlenb = val; 1117 } 1118 } 1119 1120 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1121 { 1122 g_autofree struct kvm_reg_list *reglist = NULL; 1123 KVMCPUConfig *multi_ext_cfg; 1124 struct kvm_one_reg reg; 1125 struct kvm_reg_list rl_struct; 1126 uint64_t val, reg_id, *reg_search; 1127 int i, ret; 1128 1129 rl_struct.n = 0; 1130 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1131 1132 /* 1133 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1134 * (EINVAL). Use read_legacy() in this case. 1135 */ 1136 if (errno == EINVAL) { 1137 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1138 } else if (errno != E2BIG) { 1139 /* 1140 * E2BIG is an expected error message for the API since we 1141 * don't know the number of registers. The right amount will 1142 * be written in rl_struct.n. 1143 * 1144 * Error out if we get any other errno. 1145 */ 1146 error_report("Error when accessing get-reg-list: %s", 1147 strerror(errno)); 1148 exit(EXIT_FAILURE); 1149 } 1150 1151 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1152 rl_struct.n * sizeof(uint64_t)); 1153 reglist->n = rl_struct.n; 1154 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1155 if (ret) { 1156 error_report("Error when reading KVM_GET_REG_LIST: %s", 1157 strerror(errno)); 1158 exit(EXIT_FAILURE); 1159 } 1160 1161 /* sort reglist to use bsearch() */ 1162 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1163 1164 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1165 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1166 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1167 multi_ext_cfg->kvm_reg_id); 1168 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1169 sizeof(uint64_t), uint64_cmp); 1170 if (!reg_search) { 1171 continue; 1172 } 1173 1174 reg.id = reg_id; 1175 reg.addr = (uint64_t)&val; 1176 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1177 if (ret != 0) { 1178 error_report("Unable to read ISA_EXT KVM register %s: %s", 1179 multi_ext_cfg->name, strerror(errno)); 1180 exit(EXIT_FAILURE); 1181 } 1182 1183 multi_ext_cfg->supported = true; 1184 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1185 } 1186 1187 if (cpu->cfg.ext_zicbom) { 1188 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1189 } 1190 1191 if (cpu->cfg.ext_zicboz) { 1192 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1193 } 1194 1195 if (riscv_has_ext(&cpu->env, RVV)) { 1196 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1197 } 1198 1199 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); 1200 } 1201 1202 static void riscv_init_kvm_registers(Object *cpu_obj) 1203 { 1204 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1205 KVMScratchCPU kvmcpu; 1206 1207 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1208 return; 1209 } 1210 1211 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1212 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1213 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1214 1215 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1216 } 1217 1218 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1219 KVM_CAP_LAST_INFO 1220 }; 1221 1222 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1223 { 1224 int ret = 0; 1225 1226 ret = kvm_riscv_get_regs_core(cs); 1227 if (ret) { 1228 return ret; 1229 } 1230 1231 ret = kvm_riscv_get_regs_csr(cs); 1232 if (ret) { 1233 return ret; 1234 } 1235 1236 ret = kvm_riscv_get_regs_fp(cs); 1237 if (ret) { 1238 return ret; 1239 } 1240 1241 ret = kvm_riscv_get_regs_vector(cs); 1242 if (ret) { 1243 return ret; 1244 } 1245 1246 return ret; 1247 } 1248 1249 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1250 { 1251 if (cap_has_mp_state) { 1252 struct kvm_mp_state mp_state = { 1253 .mp_state = state 1254 }; 1255 1256 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1257 if (ret) { 1258 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1259 __func__, ret, strerror(-ret)); 1260 return -1; 1261 } 1262 } 1263 1264 return 0; 1265 } 1266 1267 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1268 { 1269 int ret = 0; 1270 1271 ret = kvm_riscv_put_regs_core(cs); 1272 if (ret) { 1273 return ret; 1274 } 1275 1276 ret = kvm_riscv_put_regs_csr(cs); 1277 if (ret) { 1278 return ret; 1279 } 1280 1281 ret = kvm_riscv_put_regs_fp(cs); 1282 if (ret) { 1283 return ret; 1284 } 1285 1286 ret = kvm_riscv_put_regs_vector(cs); 1287 if (ret) { 1288 return ret; 1289 } 1290 1291 if (KVM_PUT_RESET_STATE == level) { 1292 RISCVCPU *cpu = RISCV_CPU(cs); 1293 if (cs->cpu_index == 0) { 1294 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1295 } else { 1296 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1297 } 1298 if (ret) { 1299 return ret; 1300 } 1301 } 1302 1303 return ret; 1304 } 1305 1306 int kvm_arch_release_virq_post(int virq) 1307 { 1308 return 0; 1309 } 1310 1311 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1312 uint64_t address, uint32_t data, PCIDevice *dev) 1313 { 1314 return 0; 1315 } 1316 1317 int kvm_arch_destroy_vcpu(CPUState *cs) 1318 { 1319 return 0; 1320 } 1321 1322 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1323 { 1324 return cpu->cpu_index; 1325 } 1326 1327 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1328 RunState state) 1329 { 1330 CPUState *cs = opaque; 1331 1332 if (running) { 1333 kvm_riscv_put_regs_timer(cs); 1334 } else { 1335 kvm_riscv_get_regs_timer(cs); 1336 } 1337 } 1338 1339 void kvm_arch_init_irq_routing(KVMState *s) 1340 { 1341 } 1342 1343 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1344 { 1345 CPURISCVState *env = &cpu->env; 1346 target_ulong reg; 1347 uint64_t id; 1348 int ret; 1349 1350 id = RISCV_CONFIG_REG(env, mvendorid); 1351 /* 1352 * cfg.mvendorid is an uint32 but a target_ulong will 1353 * be written. Assign it to a target_ulong var to avoid 1354 * writing pieces of other cpu->cfg fields in the reg. 1355 */ 1356 reg = cpu->cfg.mvendorid; 1357 ret = kvm_set_one_reg(cs, id, ®); 1358 if (ret != 0) { 1359 return ret; 1360 } 1361 1362 id = RISCV_CONFIG_REG(env, marchid); 1363 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1364 if (ret != 0) { 1365 return ret; 1366 } 1367 1368 id = RISCV_CONFIG_REG(env, mimpid); 1369 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1370 1371 return ret; 1372 } 1373 1374 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1375 { 1376 target_ulong reg = 1; 1377 1378 if (!kvm_sbi_dbcn.supported) { 1379 return 0; 1380 } 1381 1382 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1383 } 1384 1385 int kvm_arch_init_vcpu(CPUState *cs) 1386 { 1387 int ret = 0; 1388 RISCVCPU *cpu = RISCV_CPU(cs); 1389 1390 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1391 1392 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1393 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1394 if (ret != 0) { 1395 return ret; 1396 } 1397 } 1398 1399 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1400 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1401 1402 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1403 1404 return ret; 1405 } 1406 1407 int kvm_arch_msi_data_to_gsi(uint32_t data) 1408 { 1409 abort(); 1410 } 1411 1412 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1413 int vector, PCIDevice *dev) 1414 { 1415 return 0; 1416 } 1417 1418 int kvm_arch_get_default_type(MachineState *ms) 1419 { 1420 return 0; 1421 } 1422 1423 int kvm_arch_init(MachineState *ms, KVMState *s) 1424 { 1425 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1426 return 0; 1427 } 1428 1429 int kvm_arch_irqchip_create(KVMState *s) 1430 { 1431 /* 1432 * We can create the VAIA using the newer device control API. 1433 */ 1434 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1435 } 1436 1437 int kvm_arch_process_async_events(CPUState *cs) 1438 { 1439 return 0; 1440 } 1441 1442 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1443 { 1444 } 1445 1446 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1447 { 1448 return MEMTXATTRS_UNSPECIFIED; 1449 } 1450 1451 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1452 { 1453 return true; 1454 } 1455 1456 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1457 { 1458 g_autofree uint8_t *buf = NULL; 1459 RISCVCPU *cpu = RISCV_CPU(cs); 1460 target_ulong num_bytes; 1461 uint64_t addr; 1462 unsigned char ch; 1463 int ret; 1464 1465 switch (run->riscv_sbi.function_id) { 1466 case SBI_EXT_DBCN_CONSOLE_READ: 1467 case SBI_EXT_DBCN_CONSOLE_WRITE: 1468 num_bytes = run->riscv_sbi.args[0]; 1469 1470 if (num_bytes == 0) { 1471 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1472 run->riscv_sbi.ret[1] = 0; 1473 break; 1474 } 1475 1476 addr = run->riscv_sbi.args[1]; 1477 1478 /* 1479 * Handle the case where a 32 bit CPU is running in a 1480 * 64 bit addressing env. 1481 */ 1482 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1483 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1484 } 1485 1486 buf = g_malloc0(num_bytes); 1487 1488 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1489 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1490 if (ret < 0) { 1491 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1492 "reading chardev"); 1493 exit(1); 1494 } 1495 1496 cpu_physical_memory_write(addr, buf, ret); 1497 } else { 1498 cpu_physical_memory_read(addr, buf, num_bytes); 1499 1500 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1501 if (ret < 0) { 1502 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1503 "writing chardev"); 1504 exit(1); 1505 } 1506 } 1507 1508 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1509 run->riscv_sbi.ret[1] = ret; 1510 break; 1511 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1512 ch = run->riscv_sbi.args[0]; 1513 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1514 1515 if (ret < 0) { 1516 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1517 "writing chardev"); 1518 exit(1); 1519 } 1520 1521 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1522 run->riscv_sbi.ret[1] = 0; 1523 break; 1524 default: 1525 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1526 } 1527 } 1528 1529 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1530 { 1531 int ret = 0; 1532 unsigned char ch; 1533 switch (run->riscv_sbi.extension_id) { 1534 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1535 ch = run->riscv_sbi.args[0]; 1536 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1537 break; 1538 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1539 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1540 if (ret == sizeof(ch)) { 1541 run->riscv_sbi.ret[0] = ch; 1542 } else { 1543 run->riscv_sbi.ret[0] = -1; 1544 } 1545 ret = 0; 1546 break; 1547 case SBI_EXT_DBCN: 1548 kvm_riscv_handle_sbi_dbcn(cs, run); 1549 break; 1550 default: 1551 qemu_log_mask(LOG_UNIMP, 1552 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1553 __func__, run->riscv_sbi.extension_id); 1554 ret = -1; 1555 break; 1556 } 1557 return ret; 1558 } 1559 1560 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1561 { 1562 target_ulong csr_num = run->riscv_csr.csr_num; 1563 target_ulong new_value = run->riscv_csr.new_value; 1564 target_ulong write_mask = run->riscv_csr.write_mask; 1565 int ret = 0; 1566 1567 switch (csr_num) { 1568 case CSR_SEED: 1569 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1570 break; 1571 default: 1572 qemu_log_mask(LOG_UNIMP, 1573 "%s: un-handled CSR EXIT for CSR %lx\n", 1574 __func__, csr_num); 1575 ret = -1; 1576 break; 1577 } 1578 1579 return ret; 1580 } 1581 1582 static bool kvm_riscv_handle_debug(CPUState *cs) 1583 { 1584 RISCVCPU *cpu = RISCV_CPU(cs); 1585 CPURISCVState *env = &cpu->env; 1586 1587 /* Ensure PC is synchronised */ 1588 kvm_cpu_synchronize_state(cs); 1589 1590 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1591 return true; 1592 } 1593 1594 return false; 1595 } 1596 1597 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1598 { 1599 int ret = 0; 1600 switch (run->exit_reason) { 1601 case KVM_EXIT_RISCV_SBI: 1602 ret = kvm_riscv_handle_sbi(cs, run); 1603 break; 1604 case KVM_EXIT_RISCV_CSR: 1605 ret = kvm_riscv_handle_csr(cs, run); 1606 break; 1607 case KVM_EXIT_DEBUG: 1608 if (kvm_riscv_handle_debug(cs)) { 1609 ret = EXCP_DEBUG; 1610 } 1611 break; 1612 default: 1613 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1614 __func__, run->exit_reason); 1615 ret = -1; 1616 break; 1617 } 1618 return ret; 1619 } 1620 1621 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1622 { 1623 CPURISCVState *env = &cpu->env; 1624 int i; 1625 1626 for (i = 0; i < 32; i++) { 1627 env->gpr[i] = 0; 1628 } 1629 env->pc = cpu->env.kernel_addr; 1630 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1631 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1632 1633 kvm_riscv_reset_regs_csr(env); 1634 } 1635 1636 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1637 { 1638 int ret; 1639 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1640 1641 if (irq != IRQ_S_EXT) { 1642 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1643 abort(); 1644 } 1645 1646 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1647 if (ret < 0) { 1648 perror("Set irq failed"); 1649 abort(); 1650 } 1651 } 1652 1653 static int aia_mode; 1654 1655 static const char *kvm_aia_mode_str(uint64_t mode) 1656 { 1657 switch (mode) { 1658 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1659 return "emul"; 1660 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1661 return "hwaccel"; 1662 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1663 default: 1664 return "auto"; 1665 }; 1666 } 1667 1668 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1669 { 1670 return g_strdup(kvm_aia_mode_str(aia_mode)); 1671 } 1672 1673 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1674 { 1675 if (!strcmp(val, "emul")) { 1676 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1677 } else if (!strcmp(val, "hwaccel")) { 1678 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1679 } else if (!strcmp(val, "auto")) { 1680 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1681 } else { 1682 error_setg(errp, "Invalid KVM AIA mode"); 1683 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1684 } 1685 } 1686 1687 void kvm_arch_accel_class_init(ObjectClass *oc) 1688 { 1689 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1690 riscv_set_kvm_aia); 1691 object_class_property_set_description(oc, "riscv-aia", 1692 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1693 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1694 "if the host supports it"); 1695 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1696 "auto"); 1697 } 1698 1699 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1700 uint64_t aia_irq_num, uint64_t aia_msi_num, 1701 uint64_t aplic_base, uint64_t imsic_base, 1702 uint64_t guest_num) 1703 { 1704 int ret, i; 1705 int aia_fd = -1; 1706 uint64_t default_aia_mode; 1707 uint64_t socket_count = riscv_socket_count(machine); 1708 uint64_t max_hart_per_socket = 0; 1709 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1710 uint64_t socket_bits, hart_bits, guest_bits; 1711 uint64_t max_group_id; 1712 1713 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1714 1715 if (aia_fd < 0) { 1716 error_report("Unable to create in-kernel irqchip"); 1717 exit(1); 1718 } 1719 1720 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1721 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1722 &default_aia_mode, false, NULL); 1723 if (ret < 0) { 1724 error_report("KVM AIA: failed to get current KVM AIA mode"); 1725 exit(1); 1726 } 1727 1728 if (default_aia_mode != aia_mode) { 1729 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1730 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1731 &aia_mode, true, NULL); 1732 if (ret < 0) { 1733 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1734 "default host mode '%s'", 1735 kvm_aia_mode_str(aia_mode), 1736 kvm_aia_mode_str(default_aia_mode)); 1737 1738 /* failed to change AIA mode, use default */ 1739 aia_mode = default_aia_mode; 1740 } 1741 } 1742 1743 /* 1744 * Skip APLIC creation in KVM if we're running split mode. 1745 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1746 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1747 * since KVM won't be using it. 1748 */ 1749 if (!kvm_kernel_irqchip_split()) { 1750 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1751 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1752 &aia_irq_num, true, NULL); 1753 if (ret < 0) { 1754 error_report("KVM AIA: failed to set number of input irq lines"); 1755 exit(1); 1756 } 1757 1758 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1759 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1760 &aplic_base, true, NULL); 1761 if (ret < 0) { 1762 error_report("KVM AIA: failed to set the base address of APLIC"); 1763 exit(1); 1764 } 1765 } 1766 1767 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1768 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1769 &aia_msi_num, true, NULL); 1770 if (ret < 0) { 1771 error_report("KVM AIA: failed to set number of msi"); 1772 exit(1); 1773 } 1774 1775 1776 if (socket_count > 1) { 1777 max_group_id = socket_count - 1; 1778 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1779 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1780 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1781 &socket_bits, true, NULL); 1782 if (ret < 0) { 1783 error_report("KVM AIA: failed to set group_bits"); 1784 exit(1); 1785 } 1786 1787 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1788 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1789 &group_shift, true, NULL); 1790 if (ret < 0) { 1791 error_report("KVM AIA: failed to set group_shift"); 1792 exit(1); 1793 } 1794 } 1795 1796 guest_bits = guest_num == 0 ? 0 : 1797 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1798 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1799 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1800 &guest_bits, true, NULL); 1801 if (ret < 0) { 1802 error_report("KVM AIA: failed to set guest_bits"); 1803 exit(1); 1804 } 1805 1806 for (socket = 0; socket < socket_count; socket++) { 1807 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1808 hart_count = riscv_socket_hart_count(machine, socket); 1809 base_hart = riscv_socket_first_hartid(machine, socket); 1810 1811 if (max_hart_per_socket < hart_count) { 1812 max_hart_per_socket = hart_count; 1813 } 1814 1815 for (i = 0; i < hart_count; i++) { 1816 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1817 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1818 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1819 &imsic_addr, true, NULL); 1820 if (ret < 0) { 1821 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1822 exit(1); 1823 } 1824 } 1825 } 1826 1827 1828 if (max_hart_per_socket > 1) { 1829 max_hart_per_socket--; 1830 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1831 } else { 1832 hart_bits = 0; 1833 } 1834 1835 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1836 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1837 &hart_bits, true, NULL); 1838 if (ret < 0) { 1839 error_report("KVM AIA: failed to set hart_bits"); 1840 exit(1); 1841 } 1842 1843 if (kvm_has_gsi_routing()) { 1844 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1845 /* KVM AIA only has one APLIC instance */ 1846 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1847 } 1848 kvm_gsi_routing_allowed = true; 1849 kvm_irqchip_commit_routes(kvm_state); 1850 } 1851 1852 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1853 KVM_DEV_RISCV_AIA_CTRL_INIT, 1854 NULL, true, NULL); 1855 if (ret < 0) { 1856 error_report("KVM AIA: initialized fail"); 1857 exit(1); 1858 } 1859 1860 kvm_msi_via_irqfd_allowed = true; 1861 } 1862 1863 static void kvm_cpu_instance_init(CPUState *cs) 1864 { 1865 Object *obj = OBJECT(RISCV_CPU(cs)); 1866 1867 riscv_init_kvm_registers(obj); 1868 1869 kvm_riscv_add_cpu_user_properties(obj); 1870 } 1871 1872 /* 1873 * We'll get here via the following path: 1874 * 1875 * riscv_cpu_realize() 1876 * -> cpu_exec_realizefn() 1877 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1878 */ 1879 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1880 { 1881 RISCVCPU *cpu = RISCV_CPU(cs); 1882 int ret; 1883 1884 if (riscv_has_ext(&cpu->env, RVV)) { 1885 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1886 if (ret) { 1887 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1888 strerrorname_np(errno)); 1889 return false; 1890 } 1891 } 1892 1893 return true; 1894 } 1895 1896 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1897 { 1898 CPURISCVState *env = &cpu->env; 1899 KVMScratchCPU kvmcpu; 1900 struct kvm_one_reg reg; 1901 uint64_t val; 1902 int ret; 1903 1904 /* short-circuit without spinning the scratch CPU */ 1905 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1906 !riscv_has_ext(env, RVV)) { 1907 return; 1908 } 1909 1910 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1911 error_setg(errp, "Unable to create scratch KVM cpu"); 1912 return; 1913 } 1914 1915 if (cpu->cfg.ext_zicbom && 1916 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1917 1918 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1919 kvm_cbom_blocksize.kvm_reg_id); 1920 reg.addr = (uint64_t)&val; 1921 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1922 if (ret != 0) { 1923 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1924 return; 1925 } 1926 1927 if (cpu->cfg.cbom_blocksize != val) { 1928 error_setg(errp, "Unable to set cbom_blocksize to a different " 1929 "value than the host (%lu)", val); 1930 return; 1931 } 1932 } 1933 1934 if (cpu->cfg.ext_zicboz && 1935 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1936 1937 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1938 kvm_cboz_blocksize.kvm_reg_id); 1939 reg.addr = (uint64_t)&val; 1940 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1941 if (ret != 0) { 1942 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1943 return; 1944 } 1945 1946 if (cpu->cfg.cboz_blocksize != val) { 1947 error_setg(errp, "Unable to set cboz_blocksize to a different " 1948 "value than the host (%lu)", val); 1949 return; 1950 } 1951 } 1952 1953 /* Users are setting vlen, not vlenb */ 1954 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1955 if (!kvm_v_vlenb.supported) { 1956 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1957 return; 1958 } 1959 1960 reg.id = kvm_v_vlenb.kvm_reg_id; 1961 reg.addr = (uint64_t)&val; 1962 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1963 if (ret != 0) { 1964 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1965 return; 1966 } 1967 1968 if (cpu->cfg.vlenb != val) { 1969 error_setg(errp, "Unable to set 'vlen' to a different " 1970 "value than the host (%lu)", val * 8); 1971 return; 1972 } 1973 } 1974 1975 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1976 } 1977 1978 static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data) 1979 { 1980 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1981 1982 acc->cpu_instance_init = kvm_cpu_instance_init; 1983 acc->cpu_target_realize = kvm_cpu_realize; 1984 } 1985 1986 static const TypeInfo kvm_cpu_accel_type_info = { 1987 .name = ACCEL_CPU_NAME("kvm"), 1988 1989 .parent = TYPE_ACCEL_CPU, 1990 .class_init = kvm_cpu_accel_class_init, 1991 .abstract = true, 1992 }; 1993 static void kvm_cpu_accel_register_types(void) 1994 { 1995 type_register_static(&kvm_cpu_accel_type_info); 1996 } 1997 type_init(kvm_cpu_accel_register_types); 1998 1999 static void riscv_host_cpu_class_init(ObjectClass *c, const void *data) 2000 { 2001 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 2002 2003 #if defined(TARGET_RISCV32) 2004 mcc->misa_mxl_max = MXL_RV32; 2005 #elif defined(TARGET_RISCV64) 2006 mcc->misa_mxl_max = MXL_RV64; 2007 #endif 2008 } 2009 2010 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2011 { 2012 .name = TYPE_RISCV_CPU_HOST, 2013 .parent = TYPE_RISCV_CPU, 2014 .class_init = riscv_host_cpu_class_init, 2015 } 2016 }; 2017 2018 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2019 2020 static const uint32_t ebreak_insn = 0x00100073; 2021 static const uint16_t c_ebreak_insn = 0x9002; 2022 2023 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2024 { 2025 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2026 return -EINVAL; 2027 } 2028 2029 if ((bp->saved_insn & 0x3) == 0x3) { 2030 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2031 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2032 return -EINVAL; 2033 } 2034 } else { 2035 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2036 return -EINVAL; 2037 } 2038 } 2039 2040 return 0; 2041 } 2042 2043 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2044 { 2045 uint32_t ebreak; 2046 uint16_t c_ebreak; 2047 2048 if ((bp->saved_insn & 0x3) == 0x3) { 2049 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2050 ebreak != ebreak_insn || 2051 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2052 return -EINVAL; 2053 } 2054 } else { 2055 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2056 c_ebreak != c_ebreak_insn || 2057 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2058 return -EINVAL; 2059 } 2060 } 2061 2062 return 0; 2063 } 2064 2065 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2066 { 2067 /* TODO; To be implemented later. */ 2068 return -EINVAL; 2069 } 2070 2071 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2072 { 2073 /* TODO; To be implemented later. */ 2074 return -EINVAL; 2075 } 2076 2077 void kvm_arch_remove_all_hw_breakpoints(void) 2078 { 2079 /* TODO; To be implemented later. */ 2080 } 2081 2082 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2083 { 2084 if (kvm_sw_breakpoints_active(cs)) { 2085 dbg->control |= KVM_GUESTDBG_ENABLE; 2086 } 2087 } 2088