1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "accel/accel-cpu-target.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "system/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 #define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 | \ 62 type | idx) 63 64 #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 | \ 65 type | idx) 66 67 #if defined(TARGET_RISCV64) 68 #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) 69 #else 70 #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) 71 #endif 72 73 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 74 { 75 uint64_t size_ctz = __builtin_ctz(size_b); 76 77 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 78 } 79 80 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 81 uint64_t idx) 82 { 83 uint64_t id; 84 size_t size_b; 85 86 g_assert(idx < 32); 87 88 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 89 size_b = cpu->cfg.vlenb; 90 91 return kvm_encode_reg_size_id(id, size_b); 92 } 93 94 #define RISCV_CORE_REG(name) \ 95 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ 96 KVM_REG_RISCV_CORE_REG(name)) 97 98 #define RISCV_CSR_REG(name) \ 99 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ 100 KVM_REG_RISCV_CSR_REG(name)) 101 102 #define RISCV_CONFIG_REG(name) \ 103 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ 104 KVM_REG_RISCV_CONFIG_REG(name)) 105 106 #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ 107 KVM_REG_RISCV_TIMER_REG(name)) 108 109 #define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) 110 111 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) 112 113 #define RISCV_VECTOR_CSR_REG(name) \ 114 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ 115 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 116 117 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 118 do { \ 119 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 120 if (ret) { \ 121 abort(); \ 122 } \ 123 } while (0) 124 125 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 126 do { \ 127 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 128 if (ret) { \ 129 abort(); \ 130 } \ 131 } while (0) 132 133 typedef struct KVMCPUConfig { 134 const char *name; 135 const char *description; 136 target_ulong offset; 137 uint64_t kvm_reg_id; 138 bool user_set; 139 bool supported; 140 } KVMCPUConfig; 141 142 #define KVM_MISA_CFG(_bit, _reg_id) \ 143 {.offset = _bit, .kvm_reg_id = _reg_id} 144 145 /* KVM ISA extensions */ 146 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 147 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 148 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 149 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 150 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 151 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 152 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 153 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 154 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 155 }; 156 157 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 158 const char *name, 159 void *opaque, Error **errp) 160 { 161 KVMCPUConfig *misa_ext_cfg = opaque; 162 target_ulong misa_bit = misa_ext_cfg->offset; 163 RISCVCPU *cpu = RISCV_CPU(obj); 164 CPURISCVState *env = &cpu->env; 165 bool value = env->misa_ext_mask & misa_bit; 166 167 visit_type_bool(v, name, &value, errp); 168 } 169 170 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 171 const char *name, 172 void *opaque, Error **errp) 173 { 174 KVMCPUConfig *misa_ext_cfg = opaque; 175 target_ulong misa_bit = misa_ext_cfg->offset; 176 RISCVCPU *cpu = RISCV_CPU(obj); 177 CPURISCVState *env = &cpu->env; 178 bool value, host_bit; 179 180 if (!visit_type_bool(v, name, &value, errp)) { 181 return; 182 } 183 184 host_bit = env->misa_ext_mask & misa_bit; 185 186 if (value == host_bit) { 187 return; 188 } 189 190 if (!value) { 191 misa_ext_cfg->user_set = true; 192 return; 193 } 194 195 /* 196 * Forbid users to enable extensions that aren't 197 * available in the hart. 198 */ 199 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 200 "enabled in the host", misa_ext_cfg->name); 201 } 202 203 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 204 { 205 CPURISCVState *env = &cpu->env; 206 uint64_t id, reg; 207 int i, ret; 208 209 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 210 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 211 target_ulong misa_bit = misa_cfg->offset; 212 213 if (!misa_cfg->user_set) { 214 continue; 215 } 216 217 /* If we're here we're going to disable the MISA bit */ 218 reg = 0; 219 id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 220 misa_cfg->kvm_reg_id); 221 ret = kvm_set_one_reg(cs, id, ®); 222 if (ret != 0) { 223 /* 224 * We're not checking for -EINVAL because if the bit is about 225 * to be disabled, it means that it was already enabled by 226 * KVM. We determined that by fetching the 'isa' register 227 * during init() time. Any error at this point is worth 228 * aborting. 229 */ 230 error_report("Unable to set KVM reg %s, error %d", 231 misa_cfg->name, ret); 232 exit(EXIT_FAILURE); 233 } 234 env->misa_ext &= ~misa_bit; 235 } 236 } 237 238 #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ 239 {.name = _name, .offset = ENV_CSR_OFFSET(_env_prop), \ 240 .kvm_reg_id = reg_id} 241 242 static KVMCPUConfig kvm_csr_cfgs[] = { 243 KVM_CSR_CFG("sstatus", mstatus, RISCV_CSR_REG(sstatus)), 244 KVM_CSR_CFG("sie", mie, RISCV_CSR_REG(sie)), 245 KVM_CSR_CFG("stvec", stvec, RISCV_CSR_REG(stvec)), 246 KVM_CSR_CFG("sscratch", sscratch, RISCV_CSR_REG(sscratch)), 247 KVM_CSR_CFG("sepc", sepc, RISCV_CSR_REG(sepc)), 248 KVM_CSR_CFG("scause", scause, RISCV_CSR_REG(scause)), 249 KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), 250 KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), 251 KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), 252 KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), 253 }; 254 255 static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) 256 { 257 return (void *)&cpu->env + csr_cfg->offset; 258 } 259 260 static uint32_t kvm_cpu_csr_get_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) 261 { 262 uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); 263 return *val32; 264 } 265 266 static uint64_t kvm_cpu_csr_get_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) 267 { 268 uint64_t *val64 = kvmconfig_get_env_addr(cpu, csr_cfg); 269 return *val64; 270 } 271 272 static void kvm_cpu_csr_set_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, 273 uint32_t val) 274 { 275 uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); 276 *val32 = val; 277 } 278 279 static void kvm_cpu_csr_set_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, 280 uint64_t val) 281 { 282 uint64_t *val64 = kvmconfig_get_env_addr(cpu, csr_cfg); 283 *val64 = val; 284 } 285 286 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 287 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 288 .kvm_reg_id = _reg_id} 289 290 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 291 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 292 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 293 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 294 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 295 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 296 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 297 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 298 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 299 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 300 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 301 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 302 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 303 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 304 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 305 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 306 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 307 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 308 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 309 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 310 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 311 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 312 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 313 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 314 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 315 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 316 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 317 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 318 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 319 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 320 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 321 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 322 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 323 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 324 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 325 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 326 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 327 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 328 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 329 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 330 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 331 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 332 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 333 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 334 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 335 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 336 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 337 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 338 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 339 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 340 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 341 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 342 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 343 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 344 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 345 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 346 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 347 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 348 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 349 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 350 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 351 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 352 }; 353 354 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 355 { 356 return (void *)&cpu->cfg + kvmcfg->offset; 357 } 358 359 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 360 uint32_t val) 361 { 362 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 363 364 *ext_enabled = val; 365 } 366 367 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 368 KVMCPUConfig *multi_ext) 369 { 370 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 371 372 return *ext_enabled; 373 } 374 375 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 376 const char *name, 377 void *opaque, Error **errp) 378 { 379 KVMCPUConfig *multi_ext_cfg = opaque; 380 RISCVCPU *cpu = RISCV_CPU(obj); 381 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 382 383 visit_type_bool(v, name, &value, errp); 384 } 385 386 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 387 const char *name, 388 void *opaque, Error **errp) 389 { 390 KVMCPUConfig *multi_ext_cfg = opaque; 391 RISCVCPU *cpu = RISCV_CPU(obj); 392 bool value, host_val; 393 394 if (!visit_type_bool(v, name, &value, errp)) { 395 return; 396 } 397 398 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 399 400 /* 401 * Ignore if the user is setting the same value 402 * as the host. 403 */ 404 if (value == host_val) { 405 return; 406 } 407 408 if (!multi_ext_cfg->supported) { 409 /* 410 * Error out if the user is trying to enable an 411 * extension that KVM doesn't support. Ignore 412 * option otherwise. 413 */ 414 if (value) { 415 error_setg(errp, "KVM does not support disabling extension %s", 416 multi_ext_cfg->name); 417 } 418 419 return; 420 } 421 422 multi_ext_cfg->user_set = true; 423 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 424 } 425 426 static KVMCPUConfig kvm_cbom_blocksize = { 427 .name = "cbom_blocksize", 428 .offset = CPU_CFG_OFFSET(cbom_blocksize), 429 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 430 }; 431 432 static KVMCPUConfig kvm_cboz_blocksize = { 433 .name = "cboz_blocksize", 434 .offset = CPU_CFG_OFFSET(cboz_blocksize), 435 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 436 }; 437 438 static KVMCPUConfig kvm_v_vlenb = { 439 .name = "vlenb", 440 .offset = CPU_CFG_OFFSET(vlenb), 441 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 442 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 443 }; 444 445 static KVMCPUConfig kvm_sbi_dbcn = { 446 .name = "sbi_dbcn", 447 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 448 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 449 }; 450 451 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 452 { 453 uint64_t id, reg; 454 int i, ret; 455 456 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 457 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 458 459 if (!multi_ext_cfg->user_set) { 460 continue; 461 } 462 463 id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 464 multi_ext_cfg->kvm_reg_id); 465 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 466 ret = kvm_set_one_reg(cs, id, ®); 467 if (ret != 0) { 468 if (!reg && ret == -EINVAL) { 469 warn_report("KVM cannot disable extension %s", 470 multi_ext_cfg->name); 471 } else { 472 error_report("Unable to enable extension %s in KVM, error %d", 473 multi_ext_cfg->name, ret); 474 exit(EXIT_FAILURE); 475 } 476 } 477 } 478 } 479 480 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 481 const char *name, 482 void *opaque, Error **errp) 483 { 484 bool value = false; 485 486 visit_type_bool(v, name, &value, errp); 487 } 488 489 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 490 const char *name, 491 void *opaque, Error **errp) 492 { 493 const char *propname = opaque; 494 bool value; 495 496 if (!visit_type_bool(v, name, &value, errp)) { 497 return; 498 } 499 500 if (value) { 501 error_setg(errp, "'%s' is not available with KVM", 502 propname); 503 } 504 } 505 506 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 507 { 508 /* Check if KVM created the property already */ 509 if (object_property_find(obj, prop_name)) { 510 return; 511 } 512 513 /* 514 * Set the default to disabled for every extension 515 * unknown to KVM and error out if the user attempts 516 * to enable any of them. 517 */ 518 object_property_add(obj, prop_name, "bool", 519 cpu_get_cfg_unavailable, 520 cpu_set_cfg_unavailable, 521 NULL, (void *)prop_name); 522 } 523 524 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 525 const RISCVCPUMultiExtConfig *array) 526 { 527 const RISCVCPUMultiExtConfig *prop; 528 529 g_assert(array); 530 531 for (prop = array; prop && prop->name; prop++) { 532 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 533 } 534 } 535 536 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 537 { 538 int i; 539 540 riscv_add_satp_mode_properties(cpu_obj); 541 542 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 543 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 544 int bit = misa_cfg->offset; 545 546 misa_cfg->name = riscv_get_misa_ext_name(bit); 547 misa_cfg->description = riscv_get_misa_ext_description(bit); 548 549 object_property_add(cpu_obj, misa_cfg->name, "bool", 550 kvm_cpu_get_misa_ext_cfg, 551 kvm_cpu_set_misa_ext_cfg, 552 NULL, misa_cfg); 553 object_property_set_description(cpu_obj, misa_cfg->name, 554 misa_cfg->description); 555 } 556 557 for (i = 0; misa_bits[i] != 0; i++) { 558 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 559 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 560 } 561 562 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 563 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 564 565 object_property_add(cpu_obj, multi_cfg->name, "bool", 566 kvm_cpu_get_multi_ext_cfg, 567 kvm_cpu_set_multi_ext_cfg, 568 NULL, multi_cfg); 569 } 570 571 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 572 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 573 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 574 575 /* We don't have the needed KVM support for profiles */ 576 for (i = 0; riscv_profiles[i] != NULL; i++) { 577 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 578 } 579 } 580 581 static int kvm_riscv_get_regs_core(CPUState *cs) 582 { 583 int ret = 0; 584 int i; 585 target_ulong reg; 586 CPURISCVState *env = &RISCV_CPU(cs)->env; 587 588 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); 589 if (ret) { 590 return ret; 591 } 592 env->pc = reg; 593 594 for (i = 1; i < 32; i++) { 595 uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); 596 ret = kvm_get_one_reg(cs, id, ®); 597 if (ret) { 598 return ret; 599 } 600 env->gpr[i] = reg; 601 } 602 603 return ret; 604 } 605 606 static int kvm_riscv_put_regs_core(CPUState *cs) 607 { 608 int ret = 0; 609 int i; 610 target_ulong reg; 611 CPURISCVState *env = &RISCV_CPU(cs)->env; 612 613 reg = env->pc; 614 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); 615 if (ret) { 616 return ret; 617 } 618 619 for (i = 1; i < 32; i++) { 620 uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); 621 reg = env->gpr[i]; 622 ret = kvm_set_one_reg(cs, id, ®); 623 if (ret) { 624 return ret; 625 } 626 } 627 628 return ret; 629 } 630 631 static int kvm_riscv_get_regs_csr(CPUState *cs) 632 { 633 RISCVCPU *cpu = RISCV_CPU(cs); 634 uint64_t reg; 635 int i, ret; 636 637 for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { 638 KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; 639 640 if (!csr_cfg->supported) { 641 continue; 642 } 643 644 ret = kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); 645 if (ret) { 646 return ret; 647 } 648 649 if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { 650 kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); 651 } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { 652 kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); 653 } else { 654 g_assert_not_reached(); 655 } 656 } 657 658 return 0; 659 } 660 661 static int kvm_riscv_put_regs_csr(CPUState *cs) 662 { 663 RISCVCPU *cpu = RISCV_CPU(cs); 664 uint64_t reg; 665 int i, ret; 666 667 for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { 668 KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; 669 670 if (!csr_cfg->supported) { 671 continue; 672 } 673 674 if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { 675 reg = kvm_cpu_csr_get_u32(cpu, csr_cfg); 676 } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { 677 reg = kvm_cpu_csr_get_u64(cpu, csr_cfg); 678 } else { 679 g_assert_not_reached(); 680 } 681 682 ret = kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®); 683 if (ret) { 684 return ret; 685 } 686 } 687 688 return 0; 689 } 690 691 static void kvm_riscv_reset_regs_csr(CPURISCVState *env) 692 { 693 env->mstatus = 0; 694 env->mie = 0; 695 env->stvec = 0; 696 env->sscratch = 0; 697 env->sepc = 0; 698 env->scause = 0; 699 env->stval = 0; 700 env->mip = 0; 701 env->satp = 0; 702 env->senvcfg = 0; 703 } 704 705 static int kvm_riscv_get_regs_fp(CPUState *cs) 706 { 707 int ret = 0; 708 int i; 709 CPURISCVState *env = &RISCV_CPU(cs)->env; 710 711 if (riscv_has_ext(env, RVD)) { 712 uint64_t reg; 713 for (i = 0; i < 32; i++) { 714 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 715 if (ret) { 716 return ret; 717 } 718 env->fpr[i] = reg; 719 } 720 return ret; 721 } 722 723 if (riscv_has_ext(env, RVF)) { 724 uint32_t reg; 725 for (i = 0; i < 32; i++) { 726 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 727 if (ret) { 728 return ret; 729 } 730 env->fpr[i] = reg; 731 } 732 return ret; 733 } 734 735 return ret; 736 } 737 738 static int kvm_riscv_put_regs_fp(CPUState *cs) 739 { 740 int ret = 0; 741 int i; 742 CPURISCVState *env = &RISCV_CPU(cs)->env; 743 744 if (riscv_has_ext(env, RVD)) { 745 uint64_t reg; 746 for (i = 0; i < 32; i++) { 747 reg = env->fpr[i]; 748 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 749 if (ret) { 750 return ret; 751 } 752 } 753 return ret; 754 } 755 756 if (riscv_has_ext(env, RVF)) { 757 uint32_t reg; 758 for (i = 0; i < 32; i++) { 759 reg = env->fpr[i]; 760 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 761 if (ret) { 762 return ret; 763 } 764 } 765 return ret; 766 } 767 768 return ret; 769 } 770 771 static void kvm_riscv_get_regs_timer(CPUState *cs) 772 { 773 CPURISCVState *env = &RISCV_CPU(cs)->env; 774 775 if (env->kvm_timer_dirty) { 776 return; 777 } 778 779 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 780 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 781 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 782 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 783 784 env->kvm_timer_dirty = true; 785 } 786 787 static void kvm_riscv_put_regs_timer(CPUState *cs) 788 { 789 uint64_t reg; 790 CPURISCVState *env = &RISCV_CPU(cs)->env; 791 792 if (!env->kvm_timer_dirty) { 793 return; 794 } 795 796 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 797 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 798 799 /* 800 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 801 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 802 * doesn't matter that adaping in QEMU now. 803 * TODO If KVM changes, adapt here. 804 */ 805 if (env->kvm_timer_state) { 806 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 807 } 808 809 /* 810 * For now, migration will not work between Hosts with different timer 811 * frequency. Therefore, we should check whether they are the same here 812 * during the migration. 813 */ 814 if (migration_is_running()) { 815 KVM_RISCV_GET_TIMER(cs, frequency, reg); 816 if (reg != env->kvm_timer_frequency) { 817 error_report("Dst Hosts timer frequency != Src Hosts"); 818 } 819 } 820 821 env->kvm_timer_dirty = false; 822 } 823 824 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 825 { 826 uint64_t reg; 827 828 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 829 830 return reg; 831 } 832 833 static int kvm_riscv_get_regs_vector(CPUState *cs) 834 { 835 RISCVCPU *cpu = RISCV_CPU(cs); 836 CPURISCVState *env = &cpu->env; 837 target_ulong reg; 838 uint64_t vreg_id; 839 int vreg_idx, ret = 0; 840 841 if (!riscv_has_ext(env, RVV)) { 842 return 0; 843 } 844 845 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); 846 if (ret) { 847 return ret; 848 } 849 env->vstart = reg; 850 851 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); 852 if (ret) { 853 return ret; 854 } 855 env->vl = reg; 856 857 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); 858 if (ret) { 859 return ret; 860 } 861 env->vtype = reg; 862 863 if (kvm_v_vlenb.supported) { 864 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); 865 if (ret) { 866 return ret; 867 } 868 cpu->cfg.vlenb = reg; 869 870 for (int i = 0; i < 32; i++) { 871 /* 872 * vreg[] is statically allocated using RV_VLEN_MAX. 873 * Use it instead of vlenb to calculate vreg_idx for 874 * simplicity. 875 */ 876 vreg_idx = i * RV_VLEN_MAX / 64; 877 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 878 879 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 880 if (ret) { 881 return ret; 882 } 883 } 884 } 885 886 return 0; 887 } 888 889 static int kvm_riscv_put_regs_vector(CPUState *cs) 890 { 891 RISCVCPU *cpu = RISCV_CPU(cs); 892 CPURISCVState *env = &cpu->env; 893 target_ulong reg; 894 uint64_t vreg_id; 895 int vreg_idx, ret = 0; 896 897 if (!riscv_has_ext(env, RVV)) { 898 return 0; 899 } 900 901 reg = env->vstart; 902 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); 903 if (ret) { 904 return ret; 905 } 906 907 reg = env->vl; 908 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); 909 if (ret) { 910 return ret; 911 } 912 913 reg = env->vtype; 914 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); 915 if (ret) { 916 return ret; 917 } 918 919 if (kvm_v_vlenb.supported) { 920 reg = cpu->cfg.vlenb; 921 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); 922 923 for (int i = 0; i < 32; i++) { 924 /* 925 * vreg[] is statically allocated using RV_VLEN_MAX. 926 * Use it instead of vlenb to calculate vreg_idx for 927 * simplicity. 928 */ 929 vreg_idx = i * RV_VLEN_MAX / 64; 930 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 931 932 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 933 if (ret) { 934 return ret; 935 } 936 } 937 } 938 939 return ret; 940 } 941 942 typedef struct KVMScratchCPU { 943 int kvmfd; 944 int vmfd; 945 int cpufd; 946 } KVMScratchCPU; 947 948 /* 949 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 950 * from target/arm/kvm.c. 951 */ 952 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 953 { 954 int kvmfd = -1, vmfd = -1, cpufd = -1; 955 956 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 957 if (kvmfd < 0) { 958 goto err; 959 } 960 do { 961 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 962 } while (vmfd == -1 && errno == EINTR); 963 if (vmfd < 0) { 964 goto err; 965 } 966 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 967 if (cpufd < 0) { 968 goto err; 969 } 970 971 scratch->kvmfd = kvmfd; 972 scratch->vmfd = vmfd; 973 scratch->cpufd = cpufd; 974 975 return true; 976 977 err: 978 if (cpufd >= 0) { 979 close(cpufd); 980 } 981 if (vmfd >= 0) { 982 close(vmfd); 983 } 984 if (kvmfd >= 0) { 985 close(kvmfd); 986 } 987 988 return false; 989 } 990 991 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 992 { 993 close(scratch->cpufd); 994 close(scratch->vmfd); 995 close(scratch->kvmfd); 996 } 997 998 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 999 { 1000 struct kvm_one_reg reg; 1001 int ret; 1002 1003 reg.id = RISCV_CONFIG_REG(mvendorid); 1004 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 1005 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1006 if (ret != 0) { 1007 error_report("Unable to retrieve mvendorid from host, error %d", ret); 1008 } 1009 1010 reg.id = RISCV_CONFIG_REG(marchid); 1011 reg.addr = (uint64_t)&cpu->cfg.marchid; 1012 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1013 if (ret != 0) { 1014 error_report("Unable to retrieve marchid from host, error %d", ret); 1015 } 1016 1017 reg.id = RISCV_CONFIG_REG(mimpid); 1018 reg.addr = (uint64_t)&cpu->cfg.mimpid; 1019 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1020 if (ret != 0) { 1021 error_report("Unable to retrieve mimpid from host, error %d", ret); 1022 } 1023 } 1024 1025 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 1026 KVMScratchCPU *kvmcpu) 1027 { 1028 CPURISCVState *env = &cpu->env; 1029 struct kvm_one_reg reg; 1030 int ret; 1031 1032 reg.id = RISCV_CONFIG_REG(isa); 1033 reg.addr = (uint64_t)&env->misa_ext_mask; 1034 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1035 1036 if (ret) { 1037 error_report("Unable to fetch ISA register from KVM, " 1038 "error %d", ret); 1039 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 1040 exit(EXIT_FAILURE); 1041 } 1042 1043 env->misa_ext = env->misa_ext_mask; 1044 } 1045 1046 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1047 KVMCPUConfig *cbomz_cfg) 1048 { 1049 struct kvm_one_reg reg; 1050 int ret; 1051 1052 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 1053 cbomz_cfg->kvm_reg_id); 1054 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 1055 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1056 if (ret != 0) { 1057 error_report("Unable to read KVM reg %s, error %d", 1058 cbomz_cfg->name, ret); 1059 exit(EXIT_FAILURE); 1060 } 1061 } 1062 1063 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1064 KVMScratchCPU *kvmcpu) 1065 { 1066 uint64_t val; 1067 int i, ret; 1068 1069 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1070 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1071 struct kvm_one_reg reg; 1072 1073 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 1074 multi_ext_cfg->kvm_reg_id); 1075 reg.addr = (uint64_t)&val; 1076 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1077 if (ret != 0) { 1078 if (errno == EINVAL) { 1079 /* Silently default to 'false' if KVM does not support it. */ 1080 multi_ext_cfg->supported = false; 1081 val = false; 1082 } else { 1083 error_report("Unable to read ISA_EXT KVM register %s: %s", 1084 multi_ext_cfg->name, strerror(errno)); 1085 exit(EXIT_FAILURE); 1086 } 1087 } else { 1088 multi_ext_cfg->supported = true; 1089 } 1090 1091 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1092 } 1093 1094 if (cpu->cfg.ext_zicbom) { 1095 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1096 } 1097 1098 if (cpu->cfg.ext_zicboz) { 1099 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1100 } 1101 } 1102 1103 static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) 1104 { 1105 uint64_t val; 1106 int i, ret; 1107 1108 for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { 1109 KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; 1110 struct kvm_one_reg reg; 1111 1112 reg.id = csr_cfg->kvm_reg_id; 1113 reg.addr = (uint64_t)&val; 1114 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1115 if (ret != 0) { 1116 if (errno == EINVAL) { 1117 csr_cfg->supported = false; 1118 } else { 1119 error_report("Unable to read KVM CSR %s: %s", 1120 csr_cfg->name, strerror(errno)); 1121 exit(EXIT_FAILURE); 1122 } 1123 } else { 1124 csr_cfg->supported = true; 1125 } 1126 } 1127 } 1128 1129 static int uint64_cmp(const void *a, const void *b) 1130 { 1131 uint64_t val1 = *(const uint64_t *)a; 1132 uint64_t val2 = *(const uint64_t *)b; 1133 1134 if (val1 < val2) { 1135 return -1; 1136 } 1137 1138 if (val1 > val2) { 1139 return 1; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1146 struct kvm_reg_list *reglist) 1147 { 1148 struct kvm_reg_list *reg_search; 1149 1150 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1151 sizeof(uint64_t), uint64_cmp); 1152 1153 if (reg_search) { 1154 kvm_sbi_dbcn.supported = true; 1155 } 1156 } 1157 1158 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1159 struct kvm_reg_list *reglist) 1160 { 1161 struct kvm_one_reg reg; 1162 struct kvm_reg_list *reg_search; 1163 uint64_t val; 1164 int ret; 1165 1166 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1167 sizeof(uint64_t), uint64_cmp); 1168 1169 if (reg_search) { 1170 reg.id = kvm_v_vlenb.kvm_reg_id; 1171 reg.addr = (uint64_t)&val; 1172 1173 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1174 if (ret != 0) { 1175 error_report("Unable to read vlenb register, error code: %d", 1176 errno); 1177 exit(EXIT_FAILURE); 1178 } 1179 1180 kvm_v_vlenb.supported = true; 1181 cpu->cfg.vlenb = val; 1182 } 1183 } 1184 1185 static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) 1186 { 1187 struct kvm_reg_list *reg_search; 1188 uint64_t reg_id; 1189 1190 for (int i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { 1191 KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; 1192 1193 reg_id = csr_cfg->kvm_reg_id; 1194 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1195 sizeof(uint64_t), uint64_cmp); 1196 if (!reg_search) { 1197 continue; 1198 } 1199 1200 csr_cfg->supported = true; 1201 } 1202 } 1203 1204 static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1205 { 1206 g_autofree struct kvm_reg_list *reglist = NULL; 1207 KVMCPUConfig *multi_ext_cfg; 1208 struct kvm_one_reg reg; 1209 struct kvm_reg_list rl_struct; 1210 uint64_t val, reg_id, *reg_search; 1211 int i, ret; 1212 1213 rl_struct.n = 0; 1214 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1215 1216 /* 1217 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1218 * (EINVAL). Use read_legacy() in this case. 1219 */ 1220 if (errno == EINVAL) { 1221 kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1222 kvm_riscv_read_csr_cfg_legacy(kvmcpu); 1223 return; 1224 } else if (errno != E2BIG) { 1225 /* 1226 * E2BIG is an expected error message for the API since we 1227 * don't know the number of registers. The right amount will 1228 * be written in rl_struct.n. 1229 * 1230 * Error out if we get any other errno. 1231 */ 1232 error_report("Error when accessing get-reg-list: %s", 1233 strerror(errno)); 1234 exit(EXIT_FAILURE); 1235 } 1236 1237 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1238 rl_struct.n * sizeof(uint64_t)); 1239 reglist->n = rl_struct.n; 1240 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1241 if (ret) { 1242 error_report("Error when reading KVM_GET_REG_LIST: %s", 1243 strerror(errno)); 1244 exit(EXIT_FAILURE); 1245 } 1246 1247 /* sort reglist to use bsearch() */ 1248 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1249 1250 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1251 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1252 reg_id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 1253 multi_ext_cfg->kvm_reg_id); 1254 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1255 sizeof(uint64_t), uint64_cmp); 1256 if (!reg_search) { 1257 continue; 1258 } 1259 1260 reg.id = reg_id; 1261 reg.addr = (uint64_t)&val; 1262 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1263 if (ret != 0) { 1264 error_report("Unable to read ISA_EXT KVM register %s: %s", 1265 multi_ext_cfg->name, strerror(errno)); 1266 exit(EXIT_FAILURE); 1267 } 1268 1269 multi_ext_cfg->supported = true; 1270 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1271 } 1272 1273 if (cpu->cfg.ext_zicbom) { 1274 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1275 } 1276 1277 if (cpu->cfg.ext_zicboz) { 1278 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1279 } 1280 1281 if (riscv_has_ext(&cpu->env, RVV)) { 1282 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1283 } 1284 1285 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); 1286 kvm_riscv_read_csr_cfg(reglist); 1287 } 1288 1289 static void riscv_init_kvm_registers(Object *cpu_obj) 1290 { 1291 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1292 KVMScratchCPU kvmcpu; 1293 1294 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1295 return; 1296 } 1297 1298 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1299 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1300 kvm_riscv_init_cfg(cpu, &kvmcpu); 1301 1302 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1303 } 1304 1305 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1306 KVM_CAP_LAST_INFO 1307 }; 1308 1309 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1310 { 1311 int ret = 0; 1312 1313 ret = kvm_riscv_get_regs_core(cs); 1314 if (ret) { 1315 return ret; 1316 } 1317 1318 ret = kvm_riscv_get_regs_csr(cs); 1319 if (ret) { 1320 return ret; 1321 } 1322 1323 ret = kvm_riscv_get_regs_fp(cs); 1324 if (ret) { 1325 return ret; 1326 } 1327 1328 ret = kvm_riscv_get_regs_vector(cs); 1329 if (ret) { 1330 return ret; 1331 } 1332 1333 return ret; 1334 } 1335 1336 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1337 { 1338 if (cap_has_mp_state) { 1339 struct kvm_mp_state mp_state = { 1340 .mp_state = state 1341 }; 1342 1343 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1344 if (ret) { 1345 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1346 __func__, ret, strerror(-ret)); 1347 return -1; 1348 } 1349 } 1350 1351 return 0; 1352 } 1353 1354 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1355 { 1356 int ret = 0; 1357 1358 ret = kvm_riscv_put_regs_core(cs); 1359 if (ret) { 1360 return ret; 1361 } 1362 1363 ret = kvm_riscv_put_regs_csr(cs); 1364 if (ret) { 1365 return ret; 1366 } 1367 1368 ret = kvm_riscv_put_regs_fp(cs); 1369 if (ret) { 1370 return ret; 1371 } 1372 1373 ret = kvm_riscv_put_regs_vector(cs); 1374 if (ret) { 1375 return ret; 1376 } 1377 1378 if (KVM_PUT_RESET_STATE == level) { 1379 RISCVCPU *cpu = RISCV_CPU(cs); 1380 if (cs->cpu_index == 0) { 1381 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1382 } else { 1383 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1384 } 1385 if (ret) { 1386 return ret; 1387 } 1388 } 1389 1390 return ret; 1391 } 1392 1393 int kvm_arch_release_virq_post(int virq) 1394 { 1395 return 0; 1396 } 1397 1398 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1399 uint64_t address, uint32_t data, PCIDevice *dev) 1400 { 1401 return 0; 1402 } 1403 1404 int kvm_arch_destroy_vcpu(CPUState *cs) 1405 { 1406 return 0; 1407 } 1408 1409 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1410 { 1411 return cpu->cpu_index; 1412 } 1413 1414 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1415 RunState state) 1416 { 1417 CPUState *cs = opaque; 1418 1419 if (running) { 1420 kvm_riscv_put_regs_timer(cs); 1421 } else { 1422 kvm_riscv_get_regs_timer(cs); 1423 } 1424 } 1425 1426 void kvm_arch_init_irq_routing(KVMState *s) 1427 { 1428 } 1429 1430 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1431 { 1432 target_ulong reg; 1433 uint64_t id; 1434 int ret; 1435 1436 id = RISCV_CONFIG_REG(mvendorid); 1437 /* 1438 * cfg.mvendorid is an uint32 but a target_ulong will 1439 * be written. Assign it to a target_ulong var to avoid 1440 * writing pieces of other cpu->cfg fields in the reg. 1441 */ 1442 reg = cpu->cfg.mvendorid; 1443 ret = kvm_set_one_reg(cs, id, ®); 1444 if (ret != 0) { 1445 return ret; 1446 } 1447 1448 id = RISCV_CONFIG_REG(marchid); 1449 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1450 if (ret != 0) { 1451 return ret; 1452 } 1453 1454 id = RISCV_CONFIG_REG(mimpid); 1455 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1456 1457 return ret; 1458 } 1459 1460 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1461 { 1462 target_ulong reg = 1; 1463 1464 if (!kvm_sbi_dbcn.supported) { 1465 return 0; 1466 } 1467 1468 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1469 } 1470 1471 int kvm_arch_init_vcpu(CPUState *cs) 1472 { 1473 int ret = 0; 1474 RISCVCPU *cpu = RISCV_CPU(cs); 1475 1476 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1477 1478 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1479 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1480 if (ret != 0) { 1481 return ret; 1482 } 1483 } 1484 1485 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1486 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1487 1488 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1489 1490 return ret; 1491 } 1492 1493 int kvm_arch_msi_data_to_gsi(uint32_t data) 1494 { 1495 abort(); 1496 } 1497 1498 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1499 int vector, PCIDevice *dev) 1500 { 1501 return 0; 1502 } 1503 1504 int kvm_arch_get_default_type(MachineState *ms) 1505 { 1506 return 0; 1507 } 1508 1509 int kvm_arch_init(MachineState *ms, KVMState *s) 1510 { 1511 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1512 return 0; 1513 } 1514 1515 int kvm_arch_irqchip_create(KVMState *s) 1516 { 1517 /* 1518 * We can create the VAIA using the newer device control API. 1519 */ 1520 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1521 } 1522 1523 int kvm_arch_process_async_events(CPUState *cs) 1524 { 1525 return 0; 1526 } 1527 1528 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1529 { 1530 } 1531 1532 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1533 { 1534 return MEMTXATTRS_UNSPECIFIED; 1535 } 1536 1537 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1538 { 1539 return true; 1540 } 1541 1542 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1543 { 1544 g_autofree uint8_t *buf = NULL; 1545 RISCVCPU *cpu = RISCV_CPU(cs); 1546 target_ulong num_bytes; 1547 uint64_t addr; 1548 unsigned char ch; 1549 int ret; 1550 1551 switch (run->riscv_sbi.function_id) { 1552 case SBI_EXT_DBCN_CONSOLE_READ: 1553 case SBI_EXT_DBCN_CONSOLE_WRITE: 1554 num_bytes = run->riscv_sbi.args[0]; 1555 1556 if (num_bytes == 0) { 1557 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1558 run->riscv_sbi.ret[1] = 0; 1559 break; 1560 } 1561 1562 addr = run->riscv_sbi.args[1]; 1563 1564 /* 1565 * Handle the case where a 32 bit CPU is running in a 1566 * 64 bit addressing env. 1567 */ 1568 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1569 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1570 } 1571 1572 buf = g_malloc0(num_bytes); 1573 1574 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1575 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1576 if (ret < 0) { 1577 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1578 "reading chardev"); 1579 exit(1); 1580 } 1581 1582 cpu_physical_memory_write(addr, buf, ret); 1583 } else { 1584 cpu_physical_memory_read(addr, buf, num_bytes); 1585 1586 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1587 if (ret < 0) { 1588 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1589 "writing chardev"); 1590 exit(1); 1591 } 1592 } 1593 1594 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1595 run->riscv_sbi.ret[1] = ret; 1596 break; 1597 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1598 ch = run->riscv_sbi.args[0]; 1599 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1600 1601 if (ret < 0) { 1602 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1603 "writing chardev"); 1604 exit(1); 1605 } 1606 1607 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1608 run->riscv_sbi.ret[1] = 0; 1609 break; 1610 default: 1611 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1612 } 1613 } 1614 1615 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1616 { 1617 int ret = 0; 1618 unsigned char ch; 1619 switch (run->riscv_sbi.extension_id) { 1620 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1621 ch = run->riscv_sbi.args[0]; 1622 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1623 break; 1624 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1625 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1626 if (ret == sizeof(ch)) { 1627 run->riscv_sbi.ret[0] = ch; 1628 } else { 1629 run->riscv_sbi.ret[0] = -1; 1630 } 1631 ret = 0; 1632 break; 1633 case SBI_EXT_DBCN: 1634 kvm_riscv_handle_sbi_dbcn(cs, run); 1635 break; 1636 default: 1637 qemu_log_mask(LOG_UNIMP, 1638 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1639 __func__, run->riscv_sbi.extension_id); 1640 ret = -1; 1641 break; 1642 } 1643 return ret; 1644 } 1645 1646 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1647 { 1648 target_ulong csr_num = run->riscv_csr.csr_num; 1649 target_ulong new_value = run->riscv_csr.new_value; 1650 target_ulong write_mask = run->riscv_csr.write_mask; 1651 int ret = 0; 1652 1653 switch (csr_num) { 1654 case CSR_SEED: 1655 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1656 break; 1657 default: 1658 qemu_log_mask(LOG_UNIMP, 1659 "%s: un-handled CSR EXIT for CSR %lx\n", 1660 __func__, csr_num); 1661 ret = -1; 1662 break; 1663 } 1664 1665 return ret; 1666 } 1667 1668 static bool kvm_riscv_handle_debug(CPUState *cs) 1669 { 1670 RISCVCPU *cpu = RISCV_CPU(cs); 1671 CPURISCVState *env = &cpu->env; 1672 1673 /* Ensure PC is synchronised */ 1674 kvm_cpu_synchronize_state(cs); 1675 1676 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1677 return true; 1678 } 1679 1680 return false; 1681 } 1682 1683 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1684 { 1685 int ret = 0; 1686 switch (run->exit_reason) { 1687 case KVM_EXIT_RISCV_SBI: 1688 ret = kvm_riscv_handle_sbi(cs, run); 1689 break; 1690 case KVM_EXIT_RISCV_CSR: 1691 ret = kvm_riscv_handle_csr(cs, run); 1692 break; 1693 case KVM_EXIT_DEBUG: 1694 if (kvm_riscv_handle_debug(cs)) { 1695 ret = EXCP_DEBUG; 1696 } 1697 break; 1698 default: 1699 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1700 __func__, run->exit_reason); 1701 ret = -1; 1702 break; 1703 } 1704 return ret; 1705 } 1706 1707 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1708 { 1709 CPURISCVState *env = &cpu->env; 1710 int i; 1711 1712 for (i = 0; i < 32; i++) { 1713 env->gpr[i] = 0; 1714 } 1715 env->pc = cpu->env.kernel_addr; 1716 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1717 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1718 1719 kvm_riscv_reset_regs_csr(env); 1720 } 1721 1722 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1723 { 1724 int ret; 1725 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1726 1727 if (irq != IRQ_S_EXT) { 1728 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1729 abort(); 1730 } 1731 1732 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1733 if (ret < 0) { 1734 perror("Set irq failed"); 1735 abort(); 1736 } 1737 } 1738 1739 static int aia_mode; 1740 1741 static const char *kvm_aia_mode_str(uint64_t mode) 1742 { 1743 switch (mode) { 1744 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1745 return "emul"; 1746 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1747 return "hwaccel"; 1748 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1749 default: 1750 return "auto"; 1751 }; 1752 } 1753 1754 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1755 { 1756 return g_strdup(kvm_aia_mode_str(aia_mode)); 1757 } 1758 1759 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1760 { 1761 if (!strcmp(val, "emul")) { 1762 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1763 } else if (!strcmp(val, "hwaccel")) { 1764 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1765 } else if (!strcmp(val, "auto")) { 1766 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1767 } else { 1768 error_setg(errp, "Invalid KVM AIA mode"); 1769 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1770 } 1771 } 1772 1773 void kvm_arch_accel_class_init(ObjectClass *oc) 1774 { 1775 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1776 riscv_set_kvm_aia); 1777 object_class_property_set_description(oc, "riscv-aia", 1778 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1779 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1780 "if the host supports it"); 1781 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1782 "auto"); 1783 } 1784 1785 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1786 uint64_t aia_irq_num, uint64_t aia_msi_num, 1787 uint64_t aplic_base, uint64_t imsic_base, 1788 uint64_t guest_num) 1789 { 1790 int ret, i; 1791 int aia_fd = -1; 1792 uint64_t default_aia_mode; 1793 uint64_t socket_count = riscv_socket_count(machine); 1794 uint64_t max_hart_per_socket = 0; 1795 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1796 uint64_t socket_bits, hart_bits, guest_bits; 1797 uint64_t max_group_id; 1798 1799 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1800 1801 if (aia_fd < 0) { 1802 error_report("Unable to create in-kernel irqchip"); 1803 exit(1); 1804 } 1805 1806 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1807 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1808 &default_aia_mode, false, NULL); 1809 if (ret < 0) { 1810 error_report("KVM AIA: failed to get current KVM AIA mode"); 1811 exit(1); 1812 } 1813 1814 if (default_aia_mode != aia_mode) { 1815 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1816 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1817 &aia_mode, true, NULL); 1818 if (ret < 0) { 1819 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1820 "default host mode '%s'", 1821 kvm_aia_mode_str(aia_mode), 1822 kvm_aia_mode_str(default_aia_mode)); 1823 1824 /* failed to change AIA mode, use default */ 1825 aia_mode = default_aia_mode; 1826 } 1827 } 1828 1829 /* 1830 * Skip APLIC creation in KVM if we're running split mode. 1831 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1832 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1833 * since KVM won't be using it. 1834 */ 1835 if (!kvm_kernel_irqchip_split()) { 1836 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1837 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1838 &aia_irq_num, true, NULL); 1839 if (ret < 0) { 1840 error_report("KVM AIA: failed to set number of input irq lines"); 1841 exit(1); 1842 } 1843 1844 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1845 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1846 &aplic_base, true, NULL); 1847 if (ret < 0) { 1848 error_report("KVM AIA: failed to set the base address of APLIC"); 1849 exit(1); 1850 } 1851 } 1852 1853 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1854 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1855 &aia_msi_num, true, NULL); 1856 if (ret < 0) { 1857 error_report("KVM AIA: failed to set number of msi"); 1858 exit(1); 1859 } 1860 1861 1862 if (socket_count > 1) { 1863 max_group_id = socket_count - 1; 1864 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1865 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1866 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1867 &socket_bits, true, NULL); 1868 if (ret < 0) { 1869 error_report("KVM AIA: failed to set group_bits"); 1870 exit(1); 1871 } 1872 1873 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1874 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1875 &group_shift, true, NULL); 1876 if (ret < 0) { 1877 error_report("KVM AIA: failed to set group_shift"); 1878 exit(1); 1879 } 1880 } 1881 1882 guest_bits = guest_num == 0 ? 0 : 1883 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1884 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1885 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1886 &guest_bits, true, NULL); 1887 if (ret < 0) { 1888 error_report("KVM AIA: failed to set guest_bits"); 1889 exit(1); 1890 } 1891 1892 for (socket = 0; socket < socket_count; socket++) { 1893 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1894 hart_count = riscv_socket_hart_count(machine, socket); 1895 base_hart = riscv_socket_first_hartid(machine, socket); 1896 1897 if (max_hart_per_socket < hart_count) { 1898 max_hart_per_socket = hart_count; 1899 } 1900 1901 for (i = 0; i < hart_count; i++) { 1902 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1903 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1904 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1905 &imsic_addr, true, NULL); 1906 if (ret < 0) { 1907 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1908 exit(1); 1909 } 1910 } 1911 } 1912 1913 1914 if (max_hart_per_socket > 1) { 1915 max_hart_per_socket--; 1916 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1917 } else { 1918 hart_bits = 0; 1919 } 1920 1921 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1922 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1923 &hart_bits, true, NULL); 1924 if (ret < 0) { 1925 error_report("KVM AIA: failed to set hart_bits"); 1926 exit(1); 1927 } 1928 1929 if (kvm_has_gsi_routing()) { 1930 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1931 /* KVM AIA only has one APLIC instance */ 1932 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1933 } 1934 kvm_gsi_routing_allowed = true; 1935 kvm_irqchip_commit_routes(kvm_state); 1936 } 1937 1938 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1939 KVM_DEV_RISCV_AIA_CTRL_INIT, 1940 NULL, true, NULL); 1941 if (ret < 0) { 1942 error_report("KVM AIA: initialized fail"); 1943 exit(1); 1944 } 1945 1946 kvm_msi_via_irqfd_allowed = true; 1947 } 1948 1949 static void kvm_cpu_instance_init(CPUState *cs) 1950 { 1951 Object *obj = OBJECT(RISCV_CPU(cs)); 1952 1953 riscv_init_kvm_registers(obj); 1954 1955 kvm_riscv_add_cpu_user_properties(obj); 1956 } 1957 1958 /* 1959 * We'll get here via the following path: 1960 * 1961 * riscv_cpu_realize() 1962 * -> cpu_exec_realizefn() 1963 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1964 */ 1965 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1966 { 1967 RISCVCPU *cpu = RISCV_CPU(cs); 1968 int ret; 1969 1970 if (riscv_has_ext(&cpu->env, RVV)) { 1971 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1972 if (ret) { 1973 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1974 strerrorname_np(errno)); 1975 return false; 1976 } 1977 } 1978 1979 return true; 1980 } 1981 1982 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1983 { 1984 CPURISCVState *env = &cpu->env; 1985 KVMScratchCPU kvmcpu; 1986 struct kvm_one_reg reg; 1987 uint64_t val; 1988 int ret; 1989 1990 /* short-circuit without spinning the scratch CPU */ 1991 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1992 !riscv_has_ext(env, RVV)) { 1993 return; 1994 } 1995 1996 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1997 error_setg(errp, "Unable to create scratch KVM cpu"); 1998 return; 1999 } 2000 2001 if (cpu->cfg.ext_zicbom && 2002 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 2003 2004 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 2005 kvm_cbom_blocksize.kvm_reg_id); 2006 reg.addr = (uint64_t)&val; 2007 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 2008 if (ret != 0) { 2009 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 2010 return; 2011 } 2012 2013 if (cpu->cfg.cbom_blocksize != val) { 2014 error_setg(errp, "Unable to set cbom_blocksize to a different " 2015 "value than the host (%lu)", val); 2016 return; 2017 } 2018 } 2019 2020 if (cpu->cfg.ext_zicboz && 2021 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 2022 2023 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 2024 kvm_cboz_blocksize.kvm_reg_id); 2025 reg.addr = (uint64_t)&val; 2026 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 2027 if (ret != 0) { 2028 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 2029 return; 2030 } 2031 2032 if (cpu->cfg.cboz_blocksize != val) { 2033 error_setg(errp, "Unable to set cboz_blocksize to a different " 2034 "value than the host (%lu)", val); 2035 return; 2036 } 2037 } 2038 2039 /* Users are setting vlen, not vlenb */ 2040 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 2041 if (!kvm_v_vlenb.supported) { 2042 error_setg(errp, "Unable to set 'vlenb': register not supported"); 2043 return; 2044 } 2045 2046 reg.id = kvm_v_vlenb.kvm_reg_id; 2047 reg.addr = (uint64_t)&val; 2048 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 2049 if (ret != 0) { 2050 error_setg(errp, "Unable to read vlenb register, error %d", errno); 2051 return; 2052 } 2053 2054 if (cpu->cfg.vlenb != val) { 2055 error_setg(errp, "Unable to set 'vlen' to a different " 2056 "value than the host (%lu)", val * 8); 2057 return; 2058 } 2059 } 2060 2061 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 2062 } 2063 2064 static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data) 2065 { 2066 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 2067 2068 acc->cpu_instance_init = kvm_cpu_instance_init; 2069 acc->cpu_target_realize = kvm_cpu_realize; 2070 } 2071 2072 static const TypeInfo kvm_cpu_accel_type_info = { 2073 .name = ACCEL_CPU_NAME("kvm"), 2074 2075 .parent = TYPE_ACCEL_CPU, 2076 .class_init = kvm_cpu_accel_class_init, 2077 .abstract = true, 2078 }; 2079 static void kvm_cpu_accel_register_types(void) 2080 { 2081 type_register_static(&kvm_cpu_accel_type_info); 2082 } 2083 type_init(kvm_cpu_accel_register_types); 2084 2085 static void riscv_host_cpu_class_init(ObjectClass *c, const void *data) 2086 { 2087 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 2088 2089 #if defined(TARGET_RISCV32) 2090 mcc->misa_mxl_max = MXL_RV32; 2091 #elif defined(TARGET_RISCV64) 2092 mcc->misa_mxl_max = MXL_RV64; 2093 #endif 2094 } 2095 2096 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2097 { 2098 .name = TYPE_RISCV_CPU_HOST, 2099 .parent = TYPE_RISCV_CPU, 2100 .class_init = riscv_host_cpu_class_init, 2101 } 2102 }; 2103 2104 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2105 2106 static const uint32_t ebreak_insn = 0x00100073; 2107 static const uint16_t c_ebreak_insn = 0x9002; 2108 2109 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2110 { 2111 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2112 return -EINVAL; 2113 } 2114 2115 if ((bp->saved_insn & 0x3) == 0x3) { 2116 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2117 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2118 return -EINVAL; 2119 } 2120 } else { 2121 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2122 return -EINVAL; 2123 } 2124 } 2125 2126 return 0; 2127 } 2128 2129 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2130 { 2131 uint32_t ebreak; 2132 uint16_t c_ebreak; 2133 2134 if ((bp->saved_insn & 0x3) == 0x3) { 2135 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2136 ebreak != ebreak_insn || 2137 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2138 return -EINVAL; 2139 } 2140 } else { 2141 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2142 c_ebreak != c_ebreak_insn || 2143 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2144 return -EINVAL; 2145 } 2146 } 2147 2148 return 0; 2149 } 2150 2151 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2152 { 2153 /* TODO; To be implemented later. */ 2154 return -EINVAL; 2155 } 2156 2157 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2158 { 2159 /* TODO; To be implemented later. */ 2160 return -EINVAL; 2161 } 2162 2163 void kvm_arch_remove_all_hw_breakpoints(void) 2164 { 2165 /* TODO; To be implemented later. */ 2166 } 2167 2168 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2169 { 2170 if (kvm_sw_breakpoints_active(cs)) { 2171 dbg->control |= KVM_GUESTDBG_ENABLE; 2172 } 2173 } 2174