1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "accel/accel-cpu-target.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 278 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 279 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 280 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 281 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 282 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 283 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 284 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 285 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 286 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 287 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 288 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 289 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 290 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 291 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 292 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 293 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 294 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 295 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 296 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 297 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 298 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 299 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 300 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 301 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 302 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 303 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 304 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 305 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 306 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 307 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 308 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 309 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 310 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 311 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 312 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 313 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 314 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 315 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 316 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 317 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 318 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 319 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 320 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 321 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 322 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 323 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 324 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 325 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 326 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 327 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 328 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 329 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 330 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 331 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 332 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 333 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 334 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 335 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 336 }; 337 338 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 339 { 340 return (void *)&cpu->cfg + kvmcfg->offset; 341 } 342 343 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 344 uint32_t val) 345 { 346 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 347 348 *ext_enabled = val; 349 } 350 351 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 352 KVMCPUConfig *multi_ext) 353 { 354 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 355 356 return *ext_enabled; 357 } 358 359 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 360 const char *name, 361 void *opaque, Error **errp) 362 { 363 KVMCPUConfig *multi_ext_cfg = opaque; 364 RISCVCPU *cpu = RISCV_CPU(obj); 365 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 366 367 visit_type_bool(v, name, &value, errp); 368 } 369 370 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 371 const char *name, 372 void *opaque, Error **errp) 373 { 374 KVMCPUConfig *multi_ext_cfg = opaque; 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 bool value, host_val; 377 378 if (!visit_type_bool(v, name, &value, errp)) { 379 return; 380 } 381 382 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 383 384 /* 385 * Ignore if the user is setting the same value 386 * as the host. 387 */ 388 if (value == host_val) { 389 return; 390 } 391 392 if (!multi_ext_cfg->supported) { 393 /* 394 * Error out if the user is trying to enable an 395 * extension that KVM doesn't support. Ignore 396 * option otherwise. 397 */ 398 if (value) { 399 error_setg(errp, "KVM does not support disabling extension %s", 400 multi_ext_cfg->name); 401 } 402 403 return; 404 } 405 406 multi_ext_cfg->user_set = true; 407 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 408 } 409 410 static KVMCPUConfig kvm_cbom_blocksize = { 411 .name = "cbom_blocksize", 412 .offset = CPU_CFG_OFFSET(cbom_blocksize), 413 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 414 }; 415 416 static KVMCPUConfig kvm_cboz_blocksize = { 417 .name = "cboz_blocksize", 418 .offset = CPU_CFG_OFFSET(cboz_blocksize), 419 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 420 }; 421 422 static KVMCPUConfig kvm_v_vlenb = { 423 .name = "vlenb", 424 .offset = CPU_CFG_OFFSET(vlenb), 425 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 426 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 427 }; 428 429 static KVMCPUConfig kvm_sbi_dbcn = { 430 .name = "sbi_dbcn", 431 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 432 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 433 }; 434 435 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 436 { 437 CPURISCVState *env = &cpu->env; 438 uint64_t id, reg; 439 int i, ret; 440 441 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 442 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 443 444 if (!multi_ext_cfg->user_set) { 445 continue; 446 } 447 448 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 449 multi_ext_cfg->kvm_reg_id); 450 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 451 ret = kvm_set_one_reg(cs, id, ®); 452 if (ret != 0) { 453 if (!reg && ret == -EINVAL) { 454 warn_report("KVM cannot disable extension %s", 455 multi_ext_cfg->name); 456 } else { 457 error_report("Unable to enable extension %s in KVM, error %d", 458 multi_ext_cfg->name, ret); 459 exit(EXIT_FAILURE); 460 } 461 } 462 } 463 } 464 465 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 466 const char *name, 467 void *opaque, Error **errp) 468 { 469 bool value = false; 470 471 visit_type_bool(v, name, &value, errp); 472 } 473 474 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 475 const char *name, 476 void *opaque, Error **errp) 477 { 478 const char *propname = opaque; 479 bool value; 480 481 if (!visit_type_bool(v, name, &value, errp)) { 482 return; 483 } 484 485 if (value) { 486 error_setg(errp, "'%s' is not available with KVM", 487 propname); 488 } 489 } 490 491 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 492 { 493 /* Check if KVM created the property already */ 494 if (object_property_find(obj, prop_name)) { 495 return; 496 } 497 498 /* 499 * Set the default to disabled for every extension 500 * unknown to KVM and error out if the user attempts 501 * to enable any of them. 502 */ 503 object_property_add(obj, prop_name, "bool", 504 cpu_get_cfg_unavailable, 505 cpu_set_cfg_unavailable, 506 NULL, (void *)prop_name); 507 } 508 509 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 510 const RISCVCPUMultiExtConfig *array) 511 { 512 const RISCVCPUMultiExtConfig *prop; 513 514 g_assert(array); 515 516 for (prop = array; prop && prop->name; prop++) { 517 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 518 } 519 } 520 521 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 522 { 523 int i; 524 525 riscv_add_satp_mode_properties(cpu_obj); 526 527 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 528 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 529 int bit = misa_cfg->offset; 530 531 misa_cfg->name = riscv_get_misa_ext_name(bit); 532 misa_cfg->description = riscv_get_misa_ext_description(bit); 533 534 object_property_add(cpu_obj, misa_cfg->name, "bool", 535 kvm_cpu_get_misa_ext_cfg, 536 kvm_cpu_set_misa_ext_cfg, 537 NULL, misa_cfg); 538 object_property_set_description(cpu_obj, misa_cfg->name, 539 misa_cfg->description); 540 } 541 542 for (i = 0; misa_bits[i] != 0; i++) { 543 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 544 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 545 } 546 547 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 548 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 549 550 object_property_add(cpu_obj, multi_cfg->name, "bool", 551 kvm_cpu_get_multi_ext_cfg, 552 kvm_cpu_set_multi_ext_cfg, 553 NULL, multi_cfg); 554 } 555 556 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 557 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 558 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 559 560 /* We don't have the needed KVM support for profiles */ 561 for (i = 0; riscv_profiles[i] != NULL; i++) { 562 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 563 } 564 } 565 566 static int kvm_riscv_get_regs_core(CPUState *cs) 567 { 568 int ret = 0; 569 int i; 570 target_ulong reg; 571 CPURISCVState *env = &RISCV_CPU(cs)->env; 572 573 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 574 if (ret) { 575 return ret; 576 } 577 env->pc = reg; 578 579 for (i = 1; i < 32; i++) { 580 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 581 ret = kvm_get_one_reg(cs, id, ®); 582 if (ret) { 583 return ret; 584 } 585 env->gpr[i] = reg; 586 } 587 588 return ret; 589 } 590 591 static int kvm_riscv_put_regs_core(CPUState *cs) 592 { 593 int ret = 0; 594 int i; 595 target_ulong reg; 596 CPURISCVState *env = &RISCV_CPU(cs)->env; 597 598 reg = env->pc; 599 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 600 if (ret) { 601 return ret; 602 } 603 604 for (i = 1; i < 32; i++) { 605 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 606 reg = env->gpr[i]; 607 ret = kvm_set_one_reg(cs, id, ®); 608 if (ret) { 609 return ret; 610 } 611 } 612 613 return ret; 614 } 615 616 static void kvm_riscv_reset_regs_csr(CPURISCVState *env) 617 { 618 env->mstatus = 0; 619 env->mie = 0; 620 env->stvec = 0; 621 env->sscratch = 0; 622 env->sepc = 0; 623 env->scause = 0; 624 env->stval = 0; 625 env->mip = 0; 626 env->satp = 0; 627 env->scounteren = 0; 628 env->senvcfg = 0; 629 } 630 631 static int kvm_riscv_get_regs_csr(CPUState *cs) 632 { 633 CPURISCVState *env = &RISCV_CPU(cs)->env; 634 635 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 636 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 637 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 638 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 639 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 640 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 641 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 642 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 643 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 644 KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren); 645 KVM_RISCV_GET_CSR(cs, env, senvcfg, env->senvcfg); 646 647 return 0; 648 } 649 650 static int kvm_riscv_put_regs_csr(CPUState *cs) 651 { 652 CPURISCVState *env = &RISCV_CPU(cs)->env; 653 654 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 655 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 656 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 657 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 658 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 659 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 660 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 661 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 662 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 663 KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren); 664 KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg); 665 666 return 0; 667 } 668 669 static int kvm_riscv_get_regs_fp(CPUState *cs) 670 { 671 int ret = 0; 672 int i; 673 CPURISCVState *env = &RISCV_CPU(cs)->env; 674 675 if (riscv_has_ext(env, RVD)) { 676 uint64_t reg; 677 for (i = 0; i < 32; i++) { 678 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 679 if (ret) { 680 return ret; 681 } 682 env->fpr[i] = reg; 683 } 684 return ret; 685 } 686 687 if (riscv_has_ext(env, RVF)) { 688 uint32_t reg; 689 for (i = 0; i < 32; i++) { 690 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 691 if (ret) { 692 return ret; 693 } 694 env->fpr[i] = reg; 695 } 696 return ret; 697 } 698 699 return ret; 700 } 701 702 static int kvm_riscv_put_regs_fp(CPUState *cs) 703 { 704 int ret = 0; 705 int i; 706 CPURISCVState *env = &RISCV_CPU(cs)->env; 707 708 if (riscv_has_ext(env, RVD)) { 709 uint64_t reg; 710 for (i = 0; i < 32; i++) { 711 reg = env->fpr[i]; 712 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 713 if (ret) { 714 return ret; 715 } 716 } 717 return ret; 718 } 719 720 if (riscv_has_ext(env, RVF)) { 721 uint32_t reg; 722 for (i = 0; i < 32; i++) { 723 reg = env->fpr[i]; 724 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 725 if (ret) { 726 return ret; 727 } 728 } 729 return ret; 730 } 731 732 return ret; 733 } 734 735 static void kvm_riscv_get_regs_timer(CPUState *cs) 736 { 737 CPURISCVState *env = &RISCV_CPU(cs)->env; 738 739 if (env->kvm_timer_dirty) { 740 return; 741 } 742 743 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 744 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 745 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 746 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 747 748 env->kvm_timer_dirty = true; 749 } 750 751 static void kvm_riscv_put_regs_timer(CPUState *cs) 752 { 753 uint64_t reg; 754 CPURISCVState *env = &RISCV_CPU(cs)->env; 755 756 if (!env->kvm_timer_dirty) { 757 return; 758 } 759 760 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 761 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 762 763 /* 764 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 765 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 766 * doesn't matter that adaping in QEMU now. 767 * TODO If KVM changes, adapt here. 768 */ 769 if (env->kvm_timer_state) { 770 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 771 } 772 773 /* 774 * For now, migration will not work between Hosts with different timer 775 * frequency. Therefore, we should check whether they are the same here 776 * during the migration. 777 */ 778 if (migration_is_running()) { 779 KVM_RISCV_GET_TIMER(cs, frequency, reg); 780 if (reg != env->kvm_timer_frequency) { 781 error_report("Dst Hosts timer frequency != Src Hosts"); 782 } 783 } 784 785 env->kvm_timer_dirty = false; 786 } 787 788 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 789 { 790 uint64_t reg; 791 792 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 793 794 return reg; 795 } 796 797 static int kvm_riscv_get_regs_vector(CPUState *cs) 798 { 799 RISCVCPU *cpu = RISCV_CPU(cs); 800 CPURISCVState *env = &cpu->env; 801 target_ulong reg; 802 uint64_t vreg_id; 803 int vreg_idx, ret = 0; 804 805 if (!riscv_has_ext(env, RVV)) { 806 return 0; 807 } 808 809 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 810 if (ret) { 811 return ret; 812 } 813 env->vstart = reg; 814 815 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 816 if (ret) { 817 return ret; 818 } 819 env->vl = reg; 820 821 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 822 if (ret) { 823 return ret; 824 } 825 env->vtype = reg; 826 827 if (kvm_v_vlenb.supported) { 828 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 829 if (ret) { 830 return ret; 831 } 832 cpu->cfg.vlenb = reg; 833 834 for (int i = 0; i < 32; i++) { 835 /* 836 * vreg[] is statically allocated using RV_VLEN_MAX. 837 * Use it instead of vlenb to calculate vreg_idx for 838 * simplicity. 839 */ 840 vreg_idx = i * RV_VLEN_MAX / 64; 841 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 842 843 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 844 if (ret) { 845 return ret; 846 } 847 } 848 } 849 850 return 0; 851 } 852 853 static int kvm_riscv_put_regs_vector(CPUState *cs) 854 { 855 RISCVCPU *cpu = RISCV_CPU(cs); 856 CPURISCVState *env = &cpu->env; 857 target_ulong reg; 858 uint64_t vreg_id; 859 int vreg_idx, ret = 0; 860 861 if (!riscv_has_ext(env, RVV)) { 862 return 0; 863 } 864 865 reg = env->vstart; 866 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 867 if (ret) { 868 return ret; 869 } 870 871 reg = env->vl; 872 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 873 if (ret) { 874 return ret; 875 } 876 877 reg = env->vtype; 878 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 879 if (ret) { 880 return ret; 881 } 882 883 if (kvm_v_vlenb.supported) { 884 reg = cpu->cfg.vlenb; 885 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 886 887 for (int i = 0; i < 32; i++) { 888 /* 889 * vreg[] is statically allocated using RV_VLEN_MAX. 890 * Use it instead of vlenb to calculate vreg_idx for 891 * simplicity. 892 */ 893 vreg_idx = i * RV_VLEN_MAX / 64; 894 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 895 896 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 897 if (ret) { 898 return ret; 899 } 900 } 901 } 902 903 return ret; 904 } 905 906 typedef struct KVMScratchCPU { 907 int kvmfd; 908 int vmfd; 909 int cpufd; 910 } KVMScratchCPU; 911 912 /* 913 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 914 * from target/arm/kvm.c. 915 */ 916 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 917 { 918 int kvmfd = -1, vmfd = -1, cpufd = -1; 919 920 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 921 if (kvmfd < 0) { 922 goto err; 923 } 924 do { 925 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 926 } while (vmfd == -1 && errno == EINTR); 927 if (vmfd < 0) { 928 goto err; 929 } 930 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 931 if (cpufd < 0) { 932 goto err; 933 } 934 935 scratch->kvmfd = kvmfd; 936 scratch->vmfd = vmfd; 937 scratch->cpufd = cpufd; 938 939 return true; 940 941 err: 942 if (cpufd >= 0) { 943 close(cpufd); 944 } 945 if (vmfd >= 0) { 946 close(vmfd); 947 } 948 if (kvmfd >= 0) { 949 close(kvmfd); 950 } 951 952 return false; 953 } 954 955 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 956 { 957 close(scratch->cpufd); 958 close(scratch->vmfd); 959 close(scratch->kvmfd); 960 } 961 962 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 963 { 964 CPURISCVState *env = &cpu->env; 965 struct kvm_one_reg reg; 966 int ret; 967 968 reg.id = RISCV_CONFIG_REG(env, mvendorid); 969 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 970 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 971 if (ret != 0) { 972 error_report("Unable to retrieve mvendorid from host, error %d", ret); 973 } 974 975 reg.id = RISCV_CONFIG_REG(env, marchid); 976 reg.addr = (uint64_t)&cpu->cfg.marchid; 977 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 978 if (ret != 0) { 979 error_report("Unable to retrieve marchid from host, error %d", ret); 980 } 981 982 reg.id = RISCV_CONFIG_REG(env, mimpid); 983 reg.addr = (uint64_t)&cpu->cfg.mimpid; 984 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 985 if (ret != 0) { 986 error_report("Unable to retrieve mimpid from host, error %d", ret); 987 } 988 } 989 990 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 991 KVMScratchCPU *kvmcpu) 992 { 993 CPURISCVState *env = &cpu->env; 994 struct kvm_one_reg reg; 995 int ret; 996 997 reg.id = RISCV_CONFIG_REG(env, isa); 998 reg.addr = (uint64_t)&env->misa_ext_mask; 999 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1000 1001 if (ret) { 1002 error_report("Unable to fetch ISA register from KVM, " 1003 "error %d", ret); 1004 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 1005 exit(EXIT_FAILURE); 1006 } 1007 1008 env->misa_ext = env->misa_ext_mask; 1009 } 1010 1011 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1012 KVMCPUConfig *cbomz_cfg) 1013 { 1014 CPURISCVState *env = &cpu->env; 1015 struct kvm_one_reg reg; 1016 int ret; 1017 1018 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1019 cbomz_cfg->kvm_reg_id); 1020 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 1021 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1022 if (ret != 0) { 1023 error_report("Unable to read KVM reg %s, error %d", 1024 cbomz_cfg->name, ret); 1025 exit(EXIT_FAILURE); 1026 } 1027 } 1028 1029 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1030 KVMScratchCPU *kvmcpu) 1031 { 1032 CPURISCVState *env = &cpu->env; 1033 uint64_t val; 1034 int i, ret; 1035 1036 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1037 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1038 struct kvm_one_reg reg; 1039 1040 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1041 multi_ext_cfg->kvm_reg_id); 1042 reg.addr = (uint64_t)&val; 1043 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1044 if (ret != 0) { 1045 if (errno == EINVAL) { 1046 /* Silently default to 'false' if KVM does not support it. */ 1047 multi_ext_cfg->supported = false; 1048 val = false; 1049 } else { 1050 error_report("Unable to read ISA_EXT KVM register %s: %s", 1051 multi_ext_cfg->name, strerror(errno)); 1052 exit(EXIT_FAILURE); 1053 } 1054 } else { 1055 multi_ext_cfg->supported = true; 1056 } 1057 1058 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1059 } 1060 1061 if (cpu->cfg.ext_zicbom) { 1062 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1063 } 1064 1065 if (cpu->cfg.ext_zicboz) { 1066 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1067 } 1068 } 1069 1070 static int uint64_cmp(const void *a, const void *b) 1071 { 1072 uint64_t val1 = *(const uint64_t *)a; 1073 uint64_t val2 = *(const uint64_t *)b; 1074 1075 if (val1 < val2) { 1076 return -1; 1077 } 1078 1079 if (val1 > val2) { 1080 return 1; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1087 KVMScratchCPU *kvmcpu, 1088 struct kvm_reg_list *reglist) 1089 { 1090 struct kvm_reg_list *reg_search; 1091 1092 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1093 sizeof(uint64_t), uint64_cmp); 1094 1095 if (reg_search) { 1096 kvm_sbi_dbcn.supported = true; 1097 } 1098 } 1099 1100 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1101 struct kvm_reg_list *reglist) 1102 { 1103 struct kvm_one_reg reg; 1104 struct kvm_reg_list *reg_search; 1105 uint64_t val; 1106 int ret; 1107 1108 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1109 sizeof(uint64_t), uint64_cmp); 1110 1111 if (reg_search) { 1112 reg.id = kvm_v_vlenb.kvm_reg_id; 1113 reg.addr = (uint64_t)&val; 1114 1115 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1116 if (ret != 0) { 1117 error_report("Unable to read vlenb register, error code: %d", 1118 errno); 1119 exit(EXIT_FAILURE); 1120 } 1121 1122 kvm_v_vlenb.supported = true; 1123 cpu->cfg.vlenb = val; 1124 } 1125 } 1126 1127 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1128 { 1129 KVMCPUConfig *multi_ext_cfg; 1130 struct kvm_one_reg reg; 1131 struct kvm_reg_list rl_struct; 1132 struct kvm_reg_list *reglist; 1133 uint64_t val, reg_id, *reg_search; 1134 int i, ret; 1135 1136 rl_struct.n = 0; 1137 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1138 1139 /* 1140 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1141 * (EINVAL). Use read_legacy() in this case. 1142 */ 1143 if (errno == EINVAL) { 1144 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1145 } else if (errno != E2BIG) { 1146 /* 1147 * E2BIG is an expected error message for the API since we 1148 * don't know the number of registers. The right amount will 1149 * be written in rl_struct.n. 1150 * 1151 * Error out if we get any other errno. 1152 */ 1153 error_report("Error when accessing get-reg-list: %s", 1154 strerror(errno)); 1155 exit(EXIT_FAILURE); 1156 } 1157 1158 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1159 rl_struct.n * sizeof(uint64_t)); 1160 reglist->n = rl_struct.n; 1161 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1162 if (ret) { 1163 error_report("Error when reading KVM_GET_REG_LIST: %s", 1164 strerror(errno)); 1165 exit(EXIT_FAILURE); 1166 } 1167 1168 /* sort reglist to use bsearch() */ 1169 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1170 1171 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1172 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1173 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1174 multi_ext_cfg->kvm_reg_id); 1175 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1176 sizeof(uint64_t), uint64_cmp); 1177 if (!reg_search) { 1178 continue; 1179 } 1180 1181 reg.id = reg_id; 1182 reg.addr = (uint64_t)&val; 1183 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1184 if (ret != 0) { 1185 error_report("Unable to read ISA_EXT KVM register %s: %s", 1186 multi_ext_cfg->name, strerror(errno)); 1187 exit(EXIT_FAILURE); 1188 } 1189 1190 multi_ext_cfg->supported = true; 1191 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1192 } 1193 1194 if (cpu->cfg.ext_zicbom) { 1195 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1196 } 1197 1198 if (cpu->cfg.ext_zicboz) { 1199 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1200 } 1201 1202 if (riscv_has_ext(&cpu->env, RVV)) { 1203 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1204 } 1205 1206 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1207 } 1208 1209 static void riscv_init_kvm_registers(Object *cpu_obj) 1210 { 1211 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1212 KVMScratchCPU kvmcpu; 1213 1214 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1215 return; 1216 } 1217 1218 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1219 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1220 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1221 1222 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1223 } 1224 1225 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1226 KVM_CAP_LAST_INFO 1227 }; 1228 1229 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1230 { 1231 int ret = 0; 1232 1233 ret = kvm_riscv_get_regs_core(cs); 1234 if (ret) { 1235 return ret; 1236 } 1237 1238 ret = kvm_riscv_get_regs_csr(cs); 1239 if (ret) { 1240 return ret; 1241 } 1242 1243 ret = kvm_riscv_get_regs_fp(cs); 1244 if (ret) { 1245 return ret; 1246 } 1247 1248 ret = kvm_riscv_get_regs_vector(cs); 1249 if (ret) { 1250 return ret; 1251 } 1252 1253 return ret; 1254 } 1255 1256 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1257 { 1258 if (cap_has_mp_state) { 1259 struct kvm_mp_state mp_state = { 1260 .mp_state = state 1261 }; 1262 1263 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1264 if (ret) { 1265 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1266 __func__, ret, strerror(-ret)); 1267 return -1; 1268 } 1269 } 1270 1271 return 0; 1272 } 1273 1274 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1275 { 1276 int ret = 0; 1277 1278 ret = kvm_riscv_put_regs_core(cs); 1279 if (ret) { 1280 return ret; 1281 } 1282 1283 ret = kvm_riscv_put_regs_csr(cs); 1284 if (ret) { 1285 return ret; 1286 } 1287 1288 ret = kvm_riscv_put_regs_fp(cs); 1289 if (ret) { 1290 return ret; 1291 } 1292 1293 ret = kvm_riscv_put_regs_vector(cs); 1294 if (ret) { 1295 return ret; 1296 } 1297 1298 if (KVM_PUT_RESET_STATE == level) { 1299 RISCVCPU *cpu = RISCV_CPU(cs); 1300 if (cs->cpu_index == 0) { 1301 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1302 } else { 1303 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1304 } 1305 if (ret) { 1306 return ret; 1307 } 1308 } 1309 1310 return ret; 1311 } 1312 1313 int kvm_arch_release_virq_post(int virq) 1314 { 1315 return 0; 1316 } 1317 1318 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1319 uint64_t address, uint32_t data, PCIDevice *dev) 1320 { 1321 return 0; 1322 } 1323 1324 int kvm_arch_destroy_vcpu(CPUState *cs) 1325 { 1326 return 0; 1327 } 1328 1329 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1330 { 1331 return cpu->cpu_index; 1332 } 1333 1334 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1335 RunState state) 1336 { 1337 CPUState *cs = opaque; 1338 1339 if (running) { 1340 kvm_riscv_put_regs_timer(cs); 1341 } else { 1342 kvm_riscv_get_regs_timer(cs); 1343 } 1344 } 1345 1346 void kvm_arch_init_irq_routing(KVMState *s) 1347 { 1348 } 1349 1350 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1351 { 1352 CPURISCVState *env = &cpu->env; 1353 target_ulong reg; 1354 uint64_t id; 1355 int ret; 1356 1357 id = RISCV_CONFIG_REG(env, mvendorid); 1358 /* 1359 * cfg.mvendorid is an uint32 but a target_ulong will 1360 * be written. Assign it to a target_ulong var to avoid 1361 * writing pieces of other cpu->cfg fields in the reg. 1362 */ 1363 reg = cpu->cfg.mvendorid; 1364 ret = kvm_set_one_reg(cs, id, ®); 1365 if (ret != 0) { 1366 return ret; 1367 } 1368 1369 id = RISCV_CONFIG_REG(env, marchid); 1370 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1371 if (ret != 0) { 1372 return ret; 1373 } 1374 1375 id = RISCV_CONFIG_REG(env, mimpid); 1376 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1377 1378 return ret; 1379 } 1380 1381 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1382 { 1383 target_ulong reg = 1; 1384 1385 if (!kvm_sbi_dbcn.supported) { 1386 return 0; 1387 } 1388 1389 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1390 } 1391 1392 int kvm_arch_init_vcpu(CPUState *cs) 1393 { 1394 int ret = 0; 1395 RISCVCPU *cpu = RISCV_CPU(cs); 1396 1397 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1398 1399 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1400 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1401 if (ret != 0) { 1402 return ret; 1403 } 1404 } 1405 1406 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1407 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1408 1409 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1410 1411 return ret; 1412 } 1413 1414 int kvm_arch_msi_data_to_gsi(uint32_t data) 1415 { 1416 abort(); 1417 } 1418 1419 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1420 int vector, PCIDevice *dev) 1421 { 1422 return 0; 1423 } 1424 1425 int kvm_arch_get_default_type(MachineState *ms) 1426 { 1427 return 0; 1428 } 1429 1430 int kvm_arch_init(MachineState *ms, KVMState *s) 1431 { 1432 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1433 return 0; 1434 } 1435 1436 int kvm_arch_irqchip_create(KVMState *s) 1437 { 1438 /* 1439 * We can create the VAIA using the newer device control API. 1440 */ 1441 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1442 } 1443 1444 int kvm_arch_process_async_events(CPUState *cs) 1445 { 1446 return 0; 1447 } 1448 1449 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1450 { 1451 } 1452 1453 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1454 { 1455 return MEMTXATTRS_UNSPECIFIED; 1456 } 1457 1458 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1459 { 1460 return true; 1461 } 1462 1463 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1464 { 1465 g_autofree uint8_t *buf = NULL; 1466 RISCVCPU *cpu = RISCV_CPU(cs); 1467 target_ulong num_bytes; 1468 uint64_t addr; 1469 unsigned char ch; 1470 int ret; 1471 1472 switch (run->riscv_sbi.function_id) { 1473 case SBI_EXT_DBCN_CONSOLE_READ: 1474 case SBI_EXT_DBCN_CONSOLE_WRITE: 1475 num_bytes = run->riscv_sbi.args[0]; 1476 1477 if (num_bytes == 0) { 1478 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1479 run->riscv_sbi.ret[1] = 0; 1480 break; 1481 } 1482 1483 addr = run->riscv_sbi.args[1]; 1484 1485 /* 1486 * Handle the case where a 32 bit CPU is running in a 1487 * 64 bit addressing env. 1488 */ 1489 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1490 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1491 } 1492 1493 buf = g_malloc0(num_bytes); 1494 1495 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1496 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1497 if (ret < 0) { 1498 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1499 "reading chardev"); 1500 exit(1); 1501 } 1502 1503 cpu_physical_memory_write(addr, buf, ret); 1504 } else { 1505 cpu_physical_memory_read(addr, buf, num_bytes); 1506 1507 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1508 if (ret < 0) { 1509 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1510 "writing chardev"); 1511 exit(1); 1512 } 1513 } 1514 1515 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1516 run->riscv_sbi.ret[1] = ret; 1517 break; 1518 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1519 ch = run->riscv_sbi.args[0]; 1520 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1521 1522 if (ret < 0) { 1523 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1524 "writing chardev"); 1525 exit(1); 1526 } 1527 1528 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1529 run->riscv_sbi.ret[1] = 0; 1530 break; 1531 default: 1532 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1533 } 1534 } 1535 1536 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1537 { 1538 int ret = 0; 1539 unsigned char ch; 1540 switch (run->riscv_sbi.extension_id) { 1541 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1542 ch = run->riscv_sbi.args[0]; 1543 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1544 break; 1545 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1546 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1547 if (ret == sizeof(ch)) { 1548 run->riscv_sbi.ret[0] = ch; 1549 } else { 1550 run->riscv_sbi.ret[0] = -1; 1551 } 1552 ret = 0; 1553 break; 1554 case SBI_EXT_DBCN: 1555 kvm_riscv_handle_sbi_dbcn(cs, run); 1556 break; 1557 default: 1558 qemu_log_mask(LOG_UNIMP, 1559 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1560 __func__, run->riscv_sbi.extension_id); 1561 ret = -1; 1562 break; 1563 } 1564 return ret; 1565 } 1566 1567 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1568 { 1569 target_ulong csr_num = run->riscv_csr.csr_num; 1570 target_ulong new_value = run->riscv_csr.new_value; 1571 target_ulong write_mask = run->riscv_csr.write_mask; 1572 int ret = 0; 1573 1574 switch (csr_num) { 1575 case CSR_SEED: 1576 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1577 break; 1578 default: 1579 qemu_log_mask(LOG_UNIMP, 1580 "%s: un-handled CSR EXIT for CSR %lx\n", 1581 __func__, csr_num); 1582 ret = -1; 1583 break; 1584 } 1585 1586 return ret; 1587 } 1588 1589 static bool kvm_riscv_handle_debug(CPUState *cs) 1590 { 1591 RISCVCPU *cpu = RISCV_CPU(cs); 1592 CPURISCVState *env = &cpu->env; 1593 1594 /* Ensure PC is synchronised */ 1595 kvm_cpu_synchronize_state(cs); 1596 1597 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1598 return true; 1599 } 1600 1601 return false; 1602 } 1603 1604 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1605 { 1606 int ret = 0; 1607 switch (run->exit_reason) { 1608 case KVM_EXIT_RISCV_SBI: 1609 ret = kvm_riscv_handle_sbi(cs, run); 1610 break; 1611 case KVM_EXIT_RISCV_CSR: 1612 ret = kvm_riscv_handle_csr(cs, run); 1613 break; 1614 case KVM_EXIT_DEBUG: 1615 if (kvm_riscv_handle_debug(cs)) { 1616 ret = EXCP_DEBUG; 1617 } 1618 break; 1619 default: 1620 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1621 __func__, run->exit_reason); 1622 ret = -1; 1623 break; 1624 } 1625 return ret; 1626 } 1627 1628 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1629 { 1630 CPURISCVState *env = &cpu->env; 1631 int i; 1632 1633 for (i = 0; i < 32; i++) { 1634 env->gpr[i] = 0; 1635 } 1636 env->pc = cpu->env.kernel_addr; 1637 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1638 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1639 1640 kvm_riscv_reset_regs_csr(env); 1641 } 1642 1643 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1644 { 1645 int ret; 1646 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1647 1648 if (irq != IRQ_S_EXT) { 1649 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1650 abort(); 1651 } 1652 1653 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1654 if (ret < 0) { 1655 perror("Set irq failed"); 1656 abort(); 1657 } 1658 } 1659 1660 static int aia_mode; 1661 1662 static const char *kvm_aia_mode_str(uint64_t mode) 1663 { 1664 switch (mode) { 1665 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1666 return "emul"; 1667 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1668 return "hwaccel"; 1669 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1670 default: 1671 return "auto"; 1672 }; 1673 } 1674 1675 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1676 { 1677 return g_strdup(kvm_aia_mode_str(aia_mode)); 1678 } 1679 1680 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1681 { 1682 if (!strcmp(val, "emul")) { 1683 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1684 } else if (!strcmp(val, "hwaccel")) { 1685 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1686 } else if (!strcmp(val, "auto")) { 1687 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1688 } else { 1689 error_setg(errp, "Invalid KVM AIA mode"); 1690 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1691 } 1692 } 1693 1694 void kvm_arch_accel_class_init(ObjectClass *oc) 1695 { 1696 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1697 riscv_set_kvm_aia); 1698 object_class_property_set_description(oc, "riscv-aia", 1699 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1700 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1701 "if the host supports it"); 1702 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1703 "auto"); 1704 } 1705 1706 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1707 uint64_t aia_irq_num, uint64_t aia_msi_num, 1708 uint64_t aplic_base, uint64_t imsic_base, 1709 uint64_t guest_num) 1710 { 1711 int ret, i; 1712 int aia_fd = -1; 1713 uint64_t default_aia_mode; 1714 uint64_t socket_count = riscv_socket_count(machine); 1715 uint64_t max_hart_per_socket = 0; 1716 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1717 uint64_t socket_bits, hart_bits, guest_bits; 1718 uint64_t max_group_id; 1719 1720 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1721 1722 if (aia_fd < 0) { 1723 error_report("Unable to create in-kernel irqchip"); 1724 exit(1); 1725 } 1726 1727 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1728 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1729 &default_aia_mode, false, NULL); 1730 if (ret < 0) { 1731 error_report("KVM AIA: failed to get current KVM AIA mode"); 1732 exit(1); 1733 } 1734 1735 if (default_aia_mode != aia_mode) { 1736 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1737 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1738 &aia_mode, true, NULL); 1739 if (ret < 0) { 1740 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1741 "default host mode '%s'", 1742 kvm_aia_mode_str(aia_mode), 1743 kvm_aia_mode_str(default_aia_mode)); 1744 1745 /* failed to change AIA mode, use default */ 1746 aia_mode = default_aia_mode; 1747 } 1748 } 1749 1750 /* 1751 * Skip APLIC creation in KVM if we're running split mode. 1752 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1753 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1754 * since KVM won't be using it. 1755 */ 1756 if (!kvm_kernel_irqchip_split()) { 1757 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1758 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1759 &aia_irq_num, true, NULL); 1760 if (ret < 0) { 1761 error_report("KVM AIA: failed to set number of input irq lines"); 1762 exit(1); 1763 } 1764 1765 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1766 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1767 &aplic_base, true, NULL); 1768 if (ret < 0) { 1769 error_report("KVM AIA: failed to set the base address of APLIC"); 1770 exit(1); 1771 } 1772 } 1773 1774 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1775 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1776 &aia_msi_num, true, NULL); 1777 if (ret < 0) { 1778 error_report("KVM AIA: failed to set number of msi"); 1779 exit(1); 1780 } 1781 1782 1783 if (socket_count > 1) { 1784 max_group_id = socket_count - 1; 1785 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1786 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1787 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1788 &socket_bits, true, NULL); 1789 if (ret < 0) { 1790 error_report("KVM AIA: failed to set group_bits"); 1791 exit(1); 1792 } 1793 1794 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1795 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1796 &group_shift, true, NULL); 1797 if (ret < 0) { 1798 error_report("KVM AIA: failed to set group_shift"); 1799 exit(1); 1800 } 1801 } 1802 1803 guest_bits = guest_num == 0 ? 0 : 1804 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1805 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1806 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1807 &guest_bits, true, NULL); 1808 if (ret < 0) { 1809 error_report("KVM AIA: failed to set guest_bits"); 1810 exit(1); 1811 } 1812 1813 for (socket = 0; socket < socket_count; socket++) { 1814 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1815 hart_count = riscv_socket_hart_count(machine, socket); 1816 base_hart = riscv_socket_first_hartid(machine, socket); 1817 1818 if (max_hart_per_socket < hart_count) { 1819 max_hart_per_socket = hart_count; 1820 } 1821 1822 for (i = 0; i < hart_count; i++) { 1823 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1824 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1825 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1826 &imsic_addr, true, NULL); 1827 if (ret < 0) { 1828 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1829 exit(1); 1830 } 1831 } 1832 } 1833 1834 1835 if (max_hart_per_socket > 1) { 1836 max_hart_per_socket--; 1837 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1838 } else { 1839 hart_bits = 0; 1840 } 1841 1842 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1843 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1844 &hart_bits, true, NULL); 1845 if (ret < 0) { 1846 error_report("KVM AIA: failed to set hart_bits"); 1847 exit(1); 1848 } 1849 1850 if (kvm_has_gsi_routing()) { 1851 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1852 /* KVM AIA only has one APLIC instance */ 1853 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1854 } 1855 kvm_gsi_routing_allowed = true; 1856 kvm_irqchip_commit_routes(kvm_state); 1857 } 1858 1859 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1860 KVM_DEV_RISCV_AIA_CTRL_INIT, 1861 NULL, true, NULL); 1862 if (ret < 0) { 1863 error_report("KVM AIA: initialized fail"); 1864 exit(1); 1865 } 1866 1867 kvm_msi_via_irqfd_allowed = true; 1868 } 1869 1870 static void kvm_cpu_instance_init(CPUState *cs) 1871 { 1872 Object *obj = OBJECT(RISCV_CPU(cs)); 1873 1874 riscv_init_kvm_registers(obj); 1875 1876 kvm_riscv_add_cpu_user_properties(obj); 1877 } 1878 1879 /* 1880 * We'll get here via the following path: 1881 * 1882 * riscv_cpu_realize() 1883 * -> cpu_exec_realizefn() 1884 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1885 */ 1886 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1887 { 1888 RISCVCPU *cpu = RISCV_CPU(cs); 1889 int ret; 1890 1891 if (riscv_has_ext(&cpu->env, RVV)) { 1892 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1893 if (ret) { 1894 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1895 strerrorname_np(errno)); 1896 return false; 1897 } 1898 } 1899 1900 return true; 1901 } 1902 1903 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1904 { 1905 CPURISCVState *env = &cpu->env; 1906 KVMScratchCPU kvmcpu; 1907 struct kvm_one_reg reg; 1908 uint64_t val; 1909 int ret; 1910 1911 /* short-circuit without spinning the scratch CPU */ 1912 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1913 !riscv_has_ext(env, RVV)) { 1914 return; 1915 } 1916 1917 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1918 error_setg(errp, "Unable to create scratch KVM cpu"); 1919 return; 1920 } 1921 1922 if (cpu->cfg.ext_zicbom && 1923 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1924 1925 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1926 kvm_cbom_blocksize.kvm_reg_id); 1927 reg.addr = (uint64_t)&val; 1928 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1929 if (ret != 0) { 1930 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1931 return; 1932 } 1933 1934 if (cpu->cfg.cbom_blocksize != val) { 1935 error_setg(errp, "Unable to set cbom_blocksize to a different " 1936 "value than the host (%lu)", val); 1937 return; 1938 } 1939 } 1940 1941 if (cpu->cfg.ext_zicboz && 1942 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1943 1944 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1945 kvm_cboz_blocksize.kvm_reg_id); 1946 reg.addr = (uint64_t)&val; 1947 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1948 if (ret != 0) { 1949 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1950 return; 1951 } 1952 1953 if (cpu->cfg.cboz_blocksize != val) { 1954 error_setg(errp, "Unable to set cboz_blocksize to a different " 1955 "value than the host (%lu)", val); 1956 return; 1957 } 1958 } 1959 1960 /* Users are setting vlen, not vlenb */ 1961 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1962 if (!kvm_v_vlenb.supported) { 1963 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1964 return; 1965 } 1966 1967 reg.id = kvm_v_vlenb.kvm_reg_id; 1968 reg.addr = (uint64_t)&val; 1969 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1970 if (ret != 0) { 1971 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1972 return; 1973 } 1974 1975 if (cpu->cfg.vlenb != val) { 1976 error_setg(errp, "Unable to set 'vlen' to a different " 1977 "value than the host (%lu)", val * 8); 1978 return; 1979 } 1980 } 1981 1982 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1983 } 1984 1985 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1986 { 1987 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1988 1989 acc->cpu_instance_init = kvm_cpu_instance_init; 1990 acc->cpu_target_realize = kvm_cpu_realize; 1991 } 1992 1993 static const TypeInfo kvm_cpu_accel_type_info = { 1994 .name = ACCEL_CPU_NAME("kvm"), 1995 1996 .parent = TYPE_ACCEL_CPU, 1997 .class_init = kvm_cpu_accel_class_init, 1998 .abstract = true, 1999 }; 2000 static void kvm_cpu_accel_register_types(void) 2001 { 2002 type_register_static(&kvm_cpu_accel_type_info); 2003 } 2004 type_init(kvm_cpu_accel_register_types); 2005 2006 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 2007 { 2008 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 2009 2010 #if defined(TARGET_RISCV32) 2011 mcc->misa_mxl_max = MXL_RV32; 2012 #elif defined(TARGET_RISCV64) 2013 mcc->misa_mxl_max = MXL_RV64; 2014 #endif 2015 } 2016 2017 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2018 { 2019 .name = TYPE_RISCV_CPU_HOST, 2020 .parent = TYPE_RISCV_CPU, 2021 .class_init = riscv_host_cpu_class_init, 2022 } 2023 }; 2024 2025 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2026 2027 static const uint32_t ebreak_insn = 0x00100073; 2028 static const uint16_t c_ebreak_insn = 0x9002; 2029 2030 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2031 { 2032 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2033 return -EINVAL; 2034 } 2035 2036 if ((bp->saved_insn & 0x3) == 0x3) { 2037 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2038 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2039 return -EINVAL; 2040 } 2041 } else { 2042 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2043 return -EINVAL; 2044 } 2045 } 2046 2047 return 0; 2048 } 2049 2050 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2051 { 2052 uint32_t ebreak; 2053 uint16_t c_ebreak; 2054 2055 if ((bp->saved_insn & 0x3) == 0x3) { 2056 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2057 ebreak != ebreak_insn || 2058 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2059 return -EINVAL; 2060 } 2061 } else { 2062 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2063 c_ebreak != c_ebreak_insn || 2064 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2065 return -EINVAL; 2066 } 2067 } 2068 2069 return 0; 2070 } 2071 2072 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2073 { 2074 /* TODO; To be implemented later. */ 2075 return -EINVAL; 2076 } 2077 2078 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2079 { 2080 /* TODO; To be implemented later. */ 2081 return -EINVAL; 2082 } 2083 2084 void kvm_arch_remove_all_hw_breakpoints(void) 2085 { 2086 /* TODO; To be implemented later. */ 2087 } 2088 2089 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2090 { 2091 if (kvm_sw_breakpoints_active(cs)) { 2092 dbg->control |= KVM_GUESTDBG_ENABLE; 2093 } 2094 } 2095