1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 76 { 77 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 78 } 79 80 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 81 KVM_REG_RISCV_CORE_REG(name)) 82 83 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 84 KVM_REG_RISCV_CSR_REG(name)) 85 86 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 87 KVM_REG_RISCV_TIMER_REG(name)) 88 89 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 90 91 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 92 93 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 94 do { \ 95 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 96 if (_ret) { \ 97 return _ret; \ 98 } \ 99 } while (0) 100 101 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 102 do { \ 103 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 104 if (_ret) { \ 105 return _ret; \ 106 } \ 107 } while (0) 108 109 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 110 do { \ 111 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 112 if (ret) { \ 113 abort(); \ 114 } \ 115 } while (0) 116 117 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 118 do { \ 119 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 120 if (ret) { \ 121 abort(); \ 122 } \ 123 } while (0) 124 125 typedef struct KVMCPUConfig { 126 const char *name; 127 const char *description; 128 target_ulong offset; 129 int kvm_reg_id; 130 bool user_set; 131 bool supported; 132 } KVMCPUConfig; 133 134 #define KVM_MISA_CFG(_bit, _reg_id) \ 135 {.offset = _bit, .kvm_reg_id = _reg_id} 136 137 /* KVM ISA extensions */ 138 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 139 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 140 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 141 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 142 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 143 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 144 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 145 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 146 }; 147 148 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 149 const char *name, 150 void *opaque, Error **errp) 151 { 152 KVMCPUConfig *misa_ext_cfg = opaque; 153 target_ulong misa_bit = misa_ext_cfg->offset; 154 RISCVCPU *cpu = RISCV_CPU(obj); 155 CPURISCVState *env = &cpu->env; 156 bool value = env->misa_ext_mask & misa_bit; 157 158 visit_type_bool(v, name, &value, errp); 159 } 160 161 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 162 const char *name, 163 void *opaque, Error **errp) 164 { 165 KVMCPUConfig *misa_ext_cfg = opaque; 166 target_ulong misa_bit = misa_ext_cfg->offset; 167 RISCVCPU *cpu = RISCV_CPU(obj); 168 CPURISCVState *env = &cpu->env; 169 bool value, host_bit; 170 171 if (!visit_type_bool(v, name, &value, errp)) { 172 return; 173 } 174 175 host_bit = env->misa_ext_mask & misa_bit; 176 177 if (value == host_bit) { 178 return; 179 } 180 181 if (!value) { 182 misa_ext_cfg->user_set = true; 183 return; 184 } 185 186 /* 187 * Forbid users to enable extensions that aren't 188 * available in the hart. 189 */ 190 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 191 "enabled in the host", misa_ext_cfg->name); 192 } 193 194 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 195 { 196 CPURISCVState *env = &cpu->env; 197 uint64_t id, reg; 198 int i, ret; 199 200 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 201 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 202 target_ulong misa_bit = misa_cfg->offset; 203 204 if (!misa_cfg->user_set) { 205 continue; 206 } 207 208 /* If we're here we're going to disable the MISA bit */ 209 reg = 0; 210 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 211 misa_cfg->kvm_reg_id); 212 ret = kvm_set_one_reg(cs, id, ®); 213 if (ret != 0) { 214 /* 215 * We're not checking for -EINVAL because if the bit is about 216 * to be disabled, it means that it was already enabled by 217 * KVM. We determined that by fetching the 'isa' register 218 * during init() time. Any error at this point is worth 219 * aborting. 220 */ 221 error_report("Unable to set KVM reg %s, error %d", 222 misa_cfg->name, ret); 223 exit(EXIT_FAILURE); 224 } 225 env->misa_ext &= ~misa_bit; 226 } 227 } 228 229 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 230 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 231 .kvm_reg_id = _reg_id} 232 233 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 234 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 235 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 236 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 237 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 238 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 239 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 240 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 241 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 242 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 243 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 244 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 245 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 246 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 247 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 248 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 249 }; 250 251 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 252 { 253 return (void *)&cpu->cfg + kvmcfg->offset; 254 } 255 256 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 257 uint32_t val) 258 { 259 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 260 261 *ext_enabled = val; 262 } 263 264 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 265 KVMCPUConfig *multi_ext) 266 { 267 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 268 269 return *ext_enabled; 270 } 271 272 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 273 const char *name, 274 void *opaque, Error **errp) 275 { 276 KVMCPUConfig *multi_ext_cfg = opaque; 277 RISCVCPU *cpu = RISCV_CPU(obj); 278 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 279 280 visit_type_bool(v, name, &value, errp); 281 } 282 283 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 284 const char *name, 285 void *opaque, Error **errp) 286 { 287 KVMCPUConfig *multi_ext_cfg = opaque; 288 RISCVCPU *cpu = RISCV_CPU(obj); 289 bool value, host_val; 290 291 if (!visit_type_bool(v, name, &value, errp)) { 292 return; 293 } 294 295 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 296 297 /* 298 * Ignore if the user is setting the same value 299 * as the host. 300 */ 301 if (value == host_val) { 302 return; 303 } 304 305 if (!multi_ext_cfg->supported) { 306 /* 307 * Error out if the user is trying to enable an 308 * extension that KVM doesn't support. Ignore 309 * option otherwise. 310 */ 311 if (value) { 312 error_setg(errp, "KVM does not support disabling extension %s", 313 multi_ext_cfg->name); 314 } 315 316 return; 317 } 318 319 multi_ext_cfg->user_set = true; 320 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 321 } 322 323 static KVMCPUConfig kvm_cbom_blocksize = { 324 .name = "cbom_blocksize", 325 .offset = CPU_CFG_OFFSET(cbom_blocksize), 326 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 327 }; 328 329 static KVMCPUConfig kvm_cboz_blocksize = { 330 .name = "cboz_blocksize", 331 .offset = CPU_CFG_OFFSET(cboz_blocksize), 332 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 333 }; 334 335 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 336 const char *name, 337 void *opaque, Error **errp) 338 { 339 KVMCPUConfig *cbomz_cfg = opaque; 340 RISCVCPU *cpu = RISCV_CPU(obj); 341 uint16_t value, *host_val; 342 343 if (!visit_type_uint16(v, name, &value, errp)) { 344 return; 345 } 346 347 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 348 349 if (value != *host_val) { 350 error_report("Unable to set %s to a different value than " 351 "the host (%u)", 352 cbomz_cfg->name, *host_val); 353 exit(EXIT_FAILURE); 354 } 355 356 cbomz_cfg->user_set = true; 357 } 358 359 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 360 { 361 CPURISCVState *env = &cpu->env; 362 uint64_t id, reg; 363 int i, ret; 364 365 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 366 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 367 368 if (!multi_ext_cfg->user_set) { 369 continue; 370 } 371 372 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 373 multi_ext_cfg->kvm_reg_id); 374 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 375 ret = kvm_set_one_reg(cs, id, ®); 376 if (ret != 0) { 377 error_report("Unable to %s extension %s in KVM, error %d", 378 reg ? "enable" : "disable", 379 multi_ext_cfg->name, ret); 380 exit(EXIT_FAILURE); 381 } 382 } 383 } 384 385 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 386 const char *name, 387 void *opaque, Error **errp) 388 { 389 bool value = false; 390 391 visit_type_bool(v, name, &value, errp); 392 } 393 394 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 395 const char *name, 396 void *opaque, Error **errp) 397 { 398 const char *propname = opaque; 399 bool value; 400 401 if (!visit_type_bool(v, name, &value, errp)) { 402 return; 403 } 404 405 if (value) { 406 error_setg(errp, "extension %s is not available with KVM", 407 propname); 408 } 409 } 410 411 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 412 { 413 /* Check if KVM created the property already */ 414 if (object_property_find(obj, prop_name)) { 415 return; 416 } 417 418 /* 419 * Set the default to disabled for every extension 420 * unknown to KVM and error out if the user attempts 421 * to enable any of them. 422 */ 423 object_property_add(obj, prop_name, "bool", 424 cpu_get_cfg_unavailable, 425 cpu_set_cfg_unavailable, 426 NULL, (void *)prop_name); 427 } 428 429 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 430 const RISCVCPUMultiExtConfig *array) 431 { 432 const RISCVCPUMultiExtConfig *prop; 433 434 g_assert(array); 435 436 for (prop = array; prop && prop->name; prop++) { 437 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 438 } 439 } 440 441 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 442 { 443 int i; 444 445 riscv_add_satp_mode_properties(cpu_obj); 446 447 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 448 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 449 int bit = misa_cfg->offset; 450 451 misa_cfg->name = riscv_get_misa_ext_name(bit); 452 misa_cfg->description = riscv_get_misa_ext_description(bit); 453 454 object_property_add(cpu_obj, misa_cfg->name, "bool", 455 kvm_cpu_get_misa_ext_cfg, 456 kvm_cpu_set_misa_ext_cfg, 457 NULL, misa_cfg); 458 object_property_set_description(cpu_obj, misa_cfg->name, 459 misa_cfg->description); 460 } 461 462 for (i = 0; misa_bits[i] != 0; i++) { 463 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 464 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 465 } 466 467 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 468 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 469 470 object_property_add(cpu_obj, multi_cfg->name, "bool", 471 kvm_cpu_get_multi_ext_cfg, 472 kvm_cpu_set_multi_ext_cfg, 473 NULL, multi_cfg); 474 } 475 476 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 477 NULL, kvm_cpu_set_cbomz_blksize, 478 NULL, &kvm_cbom_blocksize); 479 480 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 481 NULL, kvm_cpu_set_cbomz_blksize, 482 NULL, &kvm_cboz_blocksize); 483 484 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 485 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 486 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 487 } 488 489 static int kvm_riscv_get_regs_core(CPUState *cs) 490 { 491 int ret = 0; 492 int i; 493 target_ulong reg; 494 CPURISCVState *env = &RISCV_CPU(cs)->env; 495 496 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 497 if (ret) { 498 return ret; 499 } 500 env->pc = reg; 501 502 for (i = 1; i < 32; i++) { 503 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 504 ret = kvm_get_one_reg(cs, id, ®); 505 if (ret) { 506 return ret; 507 } 508 env->gpr[i] = reg; 509 } 510 511 return ret; 512 } 513 514 static int kvm_riscv_put_regs_core(CPUState *cs) 515 { 516 int ret = 0; 517 int i; 518 target_ulong reg; 519 CPURISCVState *env = &RISCV_CPU(cs)->env; 520 521 reg = env->pc; 522 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 523 if (ret) { 524 return ret; 525 } 526 527 for (i = 1; i < 32; i++) { 528 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 529 reg = env->gpr[i]; 530 ret = kvm_set_one_reg(cs, id, ®); 531 if (ret) { 532 return ret; 533 } 534 } 535 536 return ret; 537 } 538 539 static int kvm_riscv_get_regs_csr(CPUState *cs) 540 { 541 CPURISCVState *env = &RISCV_CPU(cs)->env; 542 543 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 544 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 545 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 546 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 547 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 548 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 549 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 550 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 551 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 552 553 return 0; 554 } 555 556 static int kvm_riscv_put_regs_csr(CPUState *cs) 557 { 558 CPURISCVState *env = &RISCV_CPU(cs)->env; 559 560 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 561 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 562 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 563 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 564 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 565 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 566 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 567 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 568 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 569 570 return 0; 571 } 572 573 static int kvm_riscv_get_regs_fp(CPUState *cs) 574 { 575 int ret = 0; 576 int i; 577 CPURISCVState *env = &RISCV_CPU(cs)->env; 578 579 if (riscv_has_ext(env, RVD)) { 580 uint64_t reg; 581 for (i = 0; i < 32; i++) { 582 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 583 if (ret) { 584 return ret; 585 } 586 env->fpr[i] = reg; 587 } 588 return ret; 589 } 590 591 if (riscv_has_ext(env, RVF)) { 592 uint32_t reg; 593 for (i = 0; i < 32; i++) { 594 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 595 if (ret) { 596 return ret; 597 } 598 env->fpr[i] = reg; 599 } 600 return ret; 601 } 602 603 return ret; 604 } 605 606 static int kvm_riscv_put_regs_fp(CPUState *cs) 607 { 608 int ret = 0; 609 int i; 610 CPURISCVState *env = &RISCV_CPU(cs)->env; 611 612 if (riscv_has_ext(env, RVD)) { 613 uint64_t reg; 614 for (i = 0; i < 32; i++) { 615 reg = env->fpr[i]; 616 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 617 if (ret) { 618 return ret; 619 } 620 } 621 return ret; 622 } 623 624 if (riscv_has_ext(env, RVF)) { 625 uint32_t reg; 626 for (i = 0; i < 32; i++) { 627 reg = env->fpr[i]; 628 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 629 if (ret) { 630 return ret; 631 } 632 } 633 return ret; 634 } 635 636 return ret; 637 } 638 639 static void kvm_riscv_get_regs_timer(CPUState *cs) 640 { 641 CPURISCVState *env = &RISCV_CPU(cs)->env; 642 643 if (env->kvm_timer_dirty) { 644 return; 645 } 646 647 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 648 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 649 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 650 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 651 652 env->kvm_timer_dirty = true; 653 } 654 655 static void kvm_riscv_put_regs_timer(CPUState *cs) 656 { 657 uint64_t reg; 658 CPURISCVState *env = &RISCV_CPU(cs)->env; 659 660 if (!env->kvm_timer_dirty) { 661 return; 662 } 663 664 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 665 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 666 667 /* 668 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 669 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 670 * doesn't matter that adaping in QEMU now. 671 * TODO If KVM changes, adapt here. 672 */ 673 if (env->kvm_timer_state) { 674 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 675 } 676 677 /* 678 * For now, migration will not work between Hosts with different timer 679 * frequency. Therefore, we should check whether they are the same here 680 * during the migration. 681 */ 682 if (migration_is_running(migrate_get_current()->state)) { 683 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 684 if (reg != env->kvm_timer_frequency) { 685 error_report("Dst Hosts timer frequency != Src Hosts"); 686 } 687 } 688 689 env->kvm_timer_dirty = false; 690 } 691 692 typedef struct KVMScratchCPU { 693 int kvmfd; 694 int vmfd; 695 int cpufd; 696 } KVMScratchCPU; 697 698 /* 699 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 700 * from target/arm/kvm.c. 701 */ 702 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 703 { 704 int kvmfd = -1, vmfd = -1, cpufd = -1; 705 706 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 707 if (kvmfd < 0) { 708 goto err; 709 } 710 do { 711 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 712 } while (vmfd == -1 && errno == EINTR); 713 if (vmfd < 0) { 714 goto err; 715 } 716 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 717 if (cpufd < 0) { 718 goto err; 719 } 720 721 scratch->kvmfd = kvmfd; 722 scratch->vmfd = vmfd; 723 scratch->cpufd = cpufd; 724 725 return true; 726 727 err: 728 if (cpufd >= 0) { 729 close(cpufd); 730 } 731 if (vmfd >= 0) { 732 close(vmfd); 733 } 734 if (kvmfd >= 0) { 735 close(kvmfd); 736 } 737 738 return false; 739 } 740 741 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 742 { 743 close(scratch->cpufd); 744 close(scratch->vmfd); 745 close(scratch->kvmfd); 746 } 747 748 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 749 { 750 CPURISCVState *env = &cpu->env; 751 struct kvm_one_reg reg; 752 int ret; 753 754 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 755 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 756 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 757 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 758 if (ret != 0) { 759 error_report("Unable to retrieve mvendorid from host, error %d", ret); 760 } 761 762 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 763 KVM_REG_RISCV_CONFIG_REG(marchid)); 764 reg.addr = (uint64_t)&cpu->cfg.marchid; 765 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 766 if (ret != 0) { 767 error_report("Unable to retrieve marchid from host, error %d", ret); 768 } 769 770 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 771 KVM_REG_RISCV_CONFIG_REG(mimpid)); 772 reg.addr = (uint64_t)&cpu->cfg.mimpid; 773 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 774 if (ret != 0) { 775 error_report("Unable to retrieve mimpid from host, error %d", ret); 776 } 777 } 778 779 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 780 KVMScratchCPU *kvmcpu) 781 { 782 CPURISCVState *env = &cpu->env; 783 struct kvm_one_reg reg; 784 int ret; 785 786 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 787 KVM_REG_RISCV_CONFIG_REG(isa)); 788 reg.addr = (uint64_t)&env->misa_ext_mask; 789 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 790 791 if (ret) { 792 error_report("Unable to fetch ISA register from KVM, " 793 "error %d", ret); 794 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 795 exit(EXIT_FAILURE); 796 } 797 798 env->misa_ext = env->misa_ext_mask; 799 } 800 801 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 802 KVMCPUConfig *cbomz_cfg) 803 { 804 CPURISCVState *env = &cpu->env; 805 struct kvm_one_reg reg; 806 int ret; 807 808 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 809 cbomz_cfg->kvm_reg_id); 810 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 811 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 812 if (ret != 0) { 813 error_report("Unable to read KVM reg %s, error %d", 814 cbomz_cfg->name, ret); 815 exit(EXIT_FAILURE); 816 } 817 } 818 819 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 820 KVMScratchCPU *kvmcpu) 821 { 822 CPURISCVState *env = &cpu->env; 823 uint64_t val; 824 int i, ret; 825 826 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 827 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 828 struct kvm_one_reg reg; 829 830 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 831 multi_ext_cfg->kvm_reg_id); 832 reg.addr = (uint64_t)&val; 833 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 834 if (ret != 0) { 835 if (errno == EINVAL) { 836 /* Silently default to 'false' if KVM does not support it. */ 837 multi_ext_cfg->supported = false; 838 val = false; 839 } else { 840 error_report("Unable to read ISA_EXT KVM register %s: %s", 841 multi_ext_cfg->name, strerror(errno)); 842 exit(EXIT_FAILURE); 843 } 844 } else { 845 multi_ext_cfg->supported = true; 846 } 847 848 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 849 } 850 851 if (cpu->cfg.ext_zicbom) { 852 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 853 } 854 855 if (cpu->cfg.ext_zicboz) { 856 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 857 } 858 } 859 860 static int uint64_cmp(const void *a, const void *b) 861 { 862 uint64_t val1 = *(const uint64_t *)a; 863 uint64_t val2 = *(const uint64_t *)b; 864 865 if (val1 < val2) { 866 return -1; 867 } 868 869 if (val1 > val2) { 870 return 1; 871 } 872 873 return 0; 874 } 875 876 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 877 { 878 KVMCPUConfig *multi_ext_cfg; 879 struct kvm_one_reg reg; 880 struct kvm_reg_list rl_struct; 881 struct kvm_reg_list *reglist; 882 uint64_t val, reg_id, *reg_search; 883 int i, ret; 884 885 rl_struct.n = 0; 886 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 887 888 /* 889 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 890 * (EINVAL). Use read_legacy() in this case. 891 */ 892 if (errno == EINVAL) { 893 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 894 } else if (errno != E2BIG) { 895 /* 896 * E2BIG is an expected error message for the API since we 897 * don't know the number of registers. The right amount will 898 * be written in rl_struct.n. 899 * 900 * Error out if we get any other errno. 901 */ 902 error_report("Error when accessing get-reg-list: %s", 903 strerror(errno)); 904 exit(EXIT_FAILURE); 905 } 906 907 reglist = g_malloc(sizeof(struct kvm_reg_list) + 908 rl_struct.n * sizeof(uint64_t)); 909 reglist->n = rl_struct.n; 910 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 911 if (ret) { 912 error_report("Error when reading KVM_GET_REG_LIST: %s", 913 strerror(errno)); 914 exit(EXIT_FAILURE); 915 } 916 917 /* sort reglist to use bsearch() */ 918 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 919 920 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 921 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 922 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 923 multi_ext_cfg->kvm_reg_id); 924 reg_search = bsearch(®_id, reglist->reg, reglist->n, 925 sizeof(uint64_t), uint64_cmp); 926 if (!reg_search) { 927 continue; 928 } 929 930 reg.id = reg_id; 931 reg.addr = (uint64_t)&val; 932 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 933 if (ret != 0) { 934 error_report("Unable to read ISA_EXT KVM register %s: %s", 935 multi_ext_cfg->name, strerror(errno)); 936 exit(EXIT_FAILURE); 937 } 938 939 multi_ext_cfg->supported = true; 940 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 941 } 942 943 if (cpu->cfg.ext_zicbom) { 944 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 945 } 946 947 if (cpu->cfg.ext_zicboz) { 948 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 949 } 950 } 951 952 static void riscv_init_kvm_registers(Object *cpu_obj) 953 { 954 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 955 KVMScratchCPU kvmcpu; 956 957 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 958 return; 959 } 960 961 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 962 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 963 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 964 965 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 966 } 967 968 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 969 KVM_CAP_LAST_INFO 970 }; 971 972 int kvm_arch_get_registers(CPUState *cs) 973 { 974 int ret = 0; 975 976 ret = kvm_riscv_get_regs_core(cs); 977 if (ret) { 978 return ret; 979 } 980 981 ret = kvm_riscv_get_regs_csr(cs); 982 if (ret) { 983 return ret; 984 } 985 986 ret = kvm_riscv_get_regs_fp(cs); 987 if (ret) { 988 return ret; 989 } 990 991 return ret; 992 } 993 994 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 995 { 996 if (cap_has_mp_state) { 997 struct kvm_mp_state mp_state = { 998 .mp_state = state 999 }; 1000 1001 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1002 if (ret) { 1003 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1004 __func__, ret, strerror(-ret)); 1005 return -1; 1006 } 1007 } 1008 1009 return 0; 1010 } 1011 1012 int kvm_arch_put_registers(CPUState *cs, int level) 1013 { 1014 int ret = 0; 1015 1016 ret = kvm_riscv_put_regs_core(cs); 1017 if (ret) { 1018 return ret; 1019 } 1020 1021 ret = kvm_riscv_put_regs_csr(cs); 1022 if (ret) { 1023 return ret; 1024 } 1025 1026 ret = kvm_riscv_put_regs_fp(cs); 1027 if (ret) { 1028 return ret; 1029 } 1030 1031 if (KVM_PUT_RESET_STATE == level) { 1032 RISCVCPU *cpu = RISCV_CPU(cs); 1033 if (cs->cpu_index == 0) { 1034 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1035 } else { 1036 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1037 } 1038 if (ret) { 1039 return ret; 1040 } 1041 } 1042 1043 return ret; 1044 } 1045 1046 int kvm_arch_release_virq_post(int virq) 1047 { 1048 return 0; 1049 } 1050 1051 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1052 uint64_t address, uint32_t data, PCIDevice *dev) 1053 { 1054 return 0; 1055 } 1056 1057 int kvm_arch_destroy_vcpu(CPUState *cs) 1058 { 1059 return 0; 1060 } 1061 1062 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1063 { 1064 return cpu->cpu_index; 1065 } 1066 1067 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1068 RunState state) 1069 { 1070 CPUState *cs = opaque; 1071 1072 if (running) { 1073 kvm_riscv_put_regs_timer(cs); 1074 } else { 1075 kvm_riscv_get_regs_timer(cs); 1076 } 1077 } 1078 1079 void kvm_arch_init_irq_routing(KVMState *s) 1080 { 1081 } 1082 1083 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1084 { 1085 CPURISCVState *env = &cpu->env; 1086 target_ulong reg; 1087 uint64_t id; 1088 int ret; 1089 1090 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1091 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1092 /* 1093 * cfg.mvendorid is an uint32 but a target_ulong will 1094 * be written. Assign it to a target_ulong var to avoid 1095 * writing pieces of other cpu->cfg fields in the reg. 1096 */ 1097 reg = cpu->cfg.mvendorid; 1098 ret = kvm_set_one_reg(cs, id, ®); 1099 if (ret != 0) { 1100 return ret; 1101 } 1102 1103 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1104 KVM_REG_RISCV_CONFIG_REG(marchid)); 1105 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1106 if (ret != 0) { 1107 return ret; 1108 } 1109 1110 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1111 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1112 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1113 1114 return ret; 1115 } 1116 1117 int kvm_arch_init_vcpu(CPUState *cs) 1118 { 1119 int ret = 0; 1120 RISCVCPU *cpu = RISCV_CPU(cs); 1121 1122 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1123 1124 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1125 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1126 if (ret != 0) { 1127 return ret; 1128 } 1129 } 1130 1131 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1132 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1133 1134 return ret; 1135 } 1136 1137 int kvm_arch_msi_data_to_gsi(uint32_t data) 1138 { 1139 abort(); 1140 } 1141 1142 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1143 int vector, PCIDevice *dev) 1144 { 1145 return 0; 1146 } 1147 1148 int kvm_arch_get_default_type(MachineState *ms) 1149 { 1150 return 0; 1151 } 1152 1153 int kvm_arch_init(MachineState *ms, KVMState *s) 1154 { 1155 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1156 return 0; 1157 } 1158 1159 int kvm_arch_irqchip_create(KVMState *s) 1160 { 1161 if (kvm_kernel_irqchip_split()) { 1162 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1163 exit(1); 1164 } 1165 1166 /* 1167 * We can create the VAIA using the newer device control API. 1168 */ 1169 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1170 } 1171 1172 int kvm_arch_process_async_events(CPUState *cs) 1173 { 1174 return 0; 1175 } 1176 1177 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1178 { 1179 } 1180 1181 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1182 { 1183 return MEMTXATTRS_UNSPECIFIED; 1184 } 1185 1186 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1187 { 1188 return true; 1189 } 1190 1191 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1192 { 1193 int ret = 0; 1194 unsigned char ch; 1195 switch (run->riscv_sbi.extension_id) { 1196 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1197 ch = run->riscv_sbi.args[0]; 1198 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1199 break; 1200 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1201 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1202 if (ret == sizeof(ch)) { 1203 run->riscv_sbi.ret[0] = ch; 1204 } else { 1205 run->riscv_sbi.ret[0] = -1; 1206 } 1207 ret = 0; 1208 break; 1209 default: 1210 qemu_log_mask(LOG_UNIMP, 1211 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1212 __func__, run->riscv_sbi.extension_id); 1213 ret = -1; 1214 break; 1215 } 1216 return ret; 1217 } 1218 1219 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1220 { 1221 int ret = 0; 1222 switch (run->exit_reason) { 1223 case KVM_EXIT_RISCV_SBI: 1224 ret = kvm_riscv_handle_sbi(cs, run); 1225 break; 1226 default: 1227 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1228 __func__, run->exit_reason); 1229 ret = -1; 1230 break; 1231 } 1232 return ret; 1233 } 1234 1235 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1236 { 1237 CPURISCVState *env = &cpu->env; 1238 int i; 1239 1240 if (!kvm_enabled()) { 1241 return; 1242 } 1243 for (i = 0; i < 32; i++) { 1244 env->gpr[i] = 0; 1245 } 1246 env->pc = cpu->env.kernel_addr; 1247 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1248 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1249 env->satp = 0; 1250 env->mie = 0; 1251 env->stvec = 0; 1252 env->sscratch = 0; 1253 env->sepc = 0; 1254 env->scause = 0; 1255 env->stval = 0; 1256 env->mip = 0; 1257 } 1258 1259 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1260 { 1261 int ret; 1262 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1263 1264 if (irq != IRQ_S_EXT) { 1265 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1266 abort(); 1267 } 1268 1269 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1270 if (ret < 0) { 1271 perror("Set irq failed"); 1272 abort(); 1273 } 1274 } 1275 1276 bool kvm_arch_cpu_check_are_resettable(void) 1277 { 1278 return true; 1279 } 1280 1281 static int aia_mode; 1282 1283 static const char *kvm_aia_mode_str(uint64_t mode) 1284 { 1285 switch (mode) { 1286 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1287 return "emul"; 1288 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1289 return "hwaccel"; 1290 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1291 default: 1292 return "auto"; 1293 }; 1294 } 1295 1296 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1297 { 1298 return g_strdup(kvm_aia_mode_str(aia_mode)); 1299 } 1300 1301 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1302 { 1303 if (!strcmp(val, "emul")) { 1304 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1305 } else if (!strcmp(val, "hwaccel")) { 1306 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1307 } else if (!strcmp(val, "auto")) { 1308 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1309 } else { 1310 error_setg(errp, "Invalid KVM AIA mode"); 1311 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1312 } 1313 } 1314 1315 void kvm_arch_accel_class_init(ObjectClass *oc) 1316 { 1317 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1318 riscv_set_kvm_aia); 1319 object_class_property_set_description(oc, "riscv-aia", 1320 "Set KVM AIA mode. Valid values are " 1321 "emul, hwaccel, and auto. Default " 1322 "is auto."); 1323 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1324 "auto"); 1325 } 1326 1327 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1328 uint64_t aia_irq_num, uint64_t aia_msi_num, 1329 uint64_t aplic_base, uint64_t imsic_base, 1330 uint64_t guest_num) 1331 { 1332 int ret, i; 1333 int aia_fd = -1; 1334 uint64_t default_aia_mode; 1335 uint64_t socket_count = riscv_socket_count(machine); 1336 uint64_t max_hart_per_socket = 0; 1337 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1338 uint64_t socket_bits, hart_bits, guest_bits; 1339 1340 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1341 1342 if (aia_fd < 0) { 1343 error_report("Unable to create in-kernel irqchip"); 1344 exit(1); 1345 } 1346 1347 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1348 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1349 &default_aia_mode, false, NULL); 1350 if (ret < 0) { 1351 error_report("KVM AIA: failed to get current KVM AIA mode"); 1352 exit(1); 1353 } 1354 qemu_log("KVM AIA: default mode is %s\n", 1355 kvm_aia_mode_str(default_aia_mode)); 1356 1357 if (default_aia_mode != aia_mode) { 1358 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1359 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1360 &aia_mode, true, NULL); 1361 if (ret < 0) 1362 warn_report("KVM AIA: failed to set KVM AIA mode"); 1363 else 1364 qemu_log("KVM AIA: set current mode to %s\n", 1365 kvm_aia_mode_str(aia_mode)); 1366 } 1367 1368 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1369 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1370 &aia_irq_num, true, NULL); 1371 if (ret < 0) { 1372 error_report("KVM AIA: failed to set number of input irq lines"); 1373 exit(1); 1374 } 1375 1376 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1377 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1378 &aia_msi_num, true, NULL); 1379 if (ret < 0) { 1380 error_report("KVM AIA: failed to set number of msi"); 1381 exit(1); 1382 } 1383 1384 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1385 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1386 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1387 &socket_bits, true, NULL); 1388 if (ret < 0) { 1389 error_report("KVM AIA: failed to set group_bits"); 1390 exit(1); 1391 } 1392 1393 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1394 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1395 &group_shift, true, NULL); 1396 if (ret < 0) { 1397 error_report("KVM AIA: failed to set group_shift"); 1398 exit(1); 1399 } 1400 1401 guest_bits = guest_num == 0 ? 0 : 1402 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1403 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1404 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1405 &guest_bits, true, NULL); 1406 if (ret < 0) { 1407 error_report("KVM AIA: failed to set guest_bits"); 1408 exit(1); 1409 } 1410 1411 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1412 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1413 &aplic_base, true, NULL); 1414 if (ret < 0) { 1415 error_report("KVM AIA: failed to set the base address of APLIC"); 1416 exit(1); 1417 } 1418 1419 for (socket = 0; socket < socket_count; socket++) { 1420 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1421 hart_count = riscv_socket_hart_count(machine, socket); 1422 base_hart = riscv_socket_first_hartid(machine, socket); 1423 1424 if (max_hart_per_socket < hart_count) { 1425 max_hart_per_socket = hart_count; 1426 } 1427 1428 for (i = 0; i < hart_count; i++) { 1429 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1430 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1431 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1432 &imsic_addr, true, NULL); 1433 if (ret < 0) { 1434 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1435 exit(1); 1436 } 1437 } 1438 } 1439 1440 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1441 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1442 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1443 &hart_bits, true, NULL); 1444 if (ret < 0) { 1445 error_report("KVM AIA: failed to set hart_bits"); 1446 exit(1); 1447 } 1448 1449 if (kvm_has_gsi_routing()) { 1450 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1451 /* KVM AIA only has one APLIC instance */ 1452 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1453 } 1454 kvm_gsi_routing_allowed = true; 1455 kvm_irqchip_commit_routes(kvm_state); 1456 } 1457 1458 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1459 KVM_DEV_RISCV_AIA_CTRL_INIT, 1460 NULL, true, NULL); 1461 if (ret < 0) { 1462 error_report("KVM AIA: initialized fail"); 1463 exit(1); 1464 } 1465 1466 kvm_msi_via_irqfd_allowed = true; 1467 } 1468 1469 static void kvm_cpu_instance_init(CPUState *cs) 1470 { 1471 Object *obj = OBJECT(RISCV_CPU(cs)); 1472 DeviceState *dev = DEVICE(obj); 1473 1474 riscv_init_kvm_registers(obj); 1475 1476 kvm_riscv_add_cpu_user_properties(obj); 1477 1478 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1479 /* Check if we have a specific KVM handler for the option */ 1480 if (object_property_find(obj, prop->name)) { 1481 continue; 1482 } 1483 qdev_property_add_static(dev, prop); 1484 } 1485 } 1486 1487 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1488 { 1489 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1490 1491 acc->cpu_instance_init = kvm_cpu_instance_init; 1492 } 1493 1494 static const TypeInfo kvm_cpu_accel_type_info = { 1495 .name = ACCEL_CPU_NAME("kvm"), 1496 1497 .parent = TYPE_ACCEL_CPU, 1498 .class_init = kvm_cpu_accel_class_init, 1499 .abstract = true, 1500 }; 1501 static void kvm_cpu_accel_register_types(void) 1502 { 1503 type_register_static(&kvm_cpu_accel_type_info); 1504 } 1505 type_init(kvm_cpu_accel_register_types); 1506 1507 static void riscv_host_cpu_init(Object *obj) 1508 { 1509 CPURISCVState *env = &RISCV_CPU(obj)->env; 1510 1511 #if defined(TARGET_RISCV32) 1512 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1513 #elif defined(TARGET_RISCV64) 1514 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1515 #endif 1516 } 1517 1518 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1519 { 1520 .name = TYPE_RISCV_CPU_HOST, 1521 .parent = TYPE_RISCV_CPU, 1522 .instance_init = riscv_host_cpu_init, 1523 } 1524 }; 1525 1526 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1527