1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value = env->misa_ext_mask & misa_bit; 152 153 visit_type_bool(v, name, &value, errp); 154 } 155 156 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 157 const char *name, 158 void *opaque, Error **errp) 159 { 160 KVMCPUConfig *misa_ext_cfg = opaque; 161 target_ulong misa_bit = misa_ext_cfg->offset; 162 RISCVCPU *cpu = RISCV_CPU(obj); 163 CPURISCVState *env = &cpu->env; 164 bool value, host_bit; 165 166 if (!visit_type_bool(v, name, &value, errp)) { 167 return; 168 } 169 170 host_bit = env->misa_ext_mask & misa_bit; 171 172 if (value == host_bit) { 173 return; 174 } 175 176 if (!value) { 177 misa_ext_cfg->user_set = true; 178 return; 179 } 180 181 /* 182 * Forbid users to enable extensions that aren't 183 * available in the hart. 184 */ 185 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 186 "enabled in the host", misa_ext_cfg->name); 187 } 188 189 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 190 { 191 CPURISCVState *env = &cpu->env; 192 uint64_t id, reg; 193 int i, ret; 194 195 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 196 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 197 target_ulong misa_bit = misa_cfg->offset; 198 199 if (!misa_cfg->user_set) { 200 continue; 201 } 202 203 /* If we're here we're going to disable the MISA bit */ 204 reg = 0; 205 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 206 misa_cfg->kvm_reg_id); 207 ret = kvm_set_one_reg(cs, id, ®); 208 if (ret != 0) { 209 /* 210 * We're not checking for -EINVAL because if the bit is about 211 * to be disabled, it means that it was already enabled by 212 * KVM. We determined that by fetching the 'isa' register 213 * during init() time. Any error at this point is worth 214 * aborting. 215 */ 216 error_report("Unable to set KVM reg %s, error %d", 217 misa_cfg->name, ret); 218 exit(EXIT_FAILURE); 219 } 220 env->misa_ext &= ~misa_bit; 221 } 222 } 223 224 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 225 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 226 .kvm_reg_id = _reg_id} 227 228 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 229 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 230 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 231 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 232 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 233 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 234 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 235 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 236 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 237 }; 238 239 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 240 { 241 return (void *)&cpu->cfg + kvmcfg->offset; 242 } 243 244 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 245 uint32_t val) 246 { 247 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 248 249 *ext_enabled = val; 250 } 251 252 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 253 KVMCPUConfig *multi_ext) 254 { 255 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 256 257 return *ext_enabled; 258 } 259 260 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 261 const char *name, 262 void *opaque, Error **errp) 263 { 264 KVMCPUConfig *multi_ext_cfg = opaque; 265 RISCVCPU *cpu = RISCV_CPU(obj); 266 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 267 268 visit_type_bool(v, name, &value, errp); 269 } 270 271 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 272 const char *name, 273 void *opaque, Error **errp) 274 { 275 KVMCPUConfig *multi_ext_cfg = opaque; 276 RISCVCPU *cpu = RISCV_CPU(obj); 277 bool value, host_val; 278 279 if (!visit_type_bool(v, name, &value, errp)) { 280 return; 281 } 282 283 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 284 285 /* 286 * Ignore if the user is setting the same value 287 * as the host. 288 */ 289 if (value == host_val) { 290 return; 291 } 292 293 if (!multi_ext_cfg->supported) { 294 /* 295 * Error out if the user is trying to enable an 296 * extension that KVM doesn't support. Ignore 297 * option otherwise. 298 */ 299 if (value) { 300 error_setg(errp, "KVM does not support disabling extension %s", 301 multi_ext_cfg->name); 302 } 303 304 return; 305 } 306 307 multi_ext_cfg->user_set = true; 308 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 309 } 310 311 static KVMCPUConfig kvm_cbom_blocksize = { 312 .name = "cbom_blocksize", 313 .offset = CPU_CFG_OFFSET(cbom_blocksize), 314 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 315 }; 316 317 static KVMCPUConfig kvm_cboz_blocksize = { 318 .name = "cboz_blocksize", 319 .offset = CPU_CFG_OFFSET(cboz_blocksize), 320 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 321 }; 322 323 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 324 const char *name, 325 void *opaque, Error **errp) 326 { 327 KVMCPUConfig *cbomz_cfg = opaque; 328 RISCVCPU *cpu = RISCV_CPU(obj); 329 uint16_t value, *host_val; 330 331 if (!visit_type_uint16(v, name, &value, errp)) { 332 return; 333 } 334 335 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 336 337 if (value != *host_val) { 338 error_report("Unable to set %s to a different value than " 339 "the host (%u)", 340 cbomz_cfg->name, *host_val); 341 exit(EXIT_FAILURE); 342 } 343 344 cbomz_cfg->user_set = true; 345 } 346 347 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 348 { 349 CPURISCVState *env = &cpu->env; 350 uint64_t id, reg; 351 int i, ret; 352 353 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 354 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 355 356 if (!multi_ext_cfg->user_set) { 357 continue; 358 } 359 360 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 361 multi_ext_cfg->kvm_reg_id); 362 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 363 ret = kvm_set_one_reg(cs, id, ®); 364 if (ret != 0) { 365 error_report("Unable to %s extension %s in KVM, error %d", 366 reg ? "enable" : "disable", 367 multi_ext_cfg->name, ret); 368 exit(EXIT_FAILURE); 369 } 370 } 371 } 372 373 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 374 const char *name, 375 void *opaque, Error **errp) 376 { 377 bool value = false; 378 379 visit_type_bool(v, name, &value, errp); 380 } 381 382 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 383 const char *name, 384 void *opaque, Error **errp) 385 { 386 const char *propname = opaque; 387 bool value; 388 389 if (!visit_type_bool(v, name, &value, errp)) { 390 return; 391 } 392 393 if (value) { 394 error_setg(errp, "extension %s is not available with KVM", 395 propname); 396 } 397 } 398 399 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 400 { 401 /* Check if KVM created the property already */ 402 if (object_property_find(obj, prop_name)) { 403 return; 404 } 405 406 /* 407 * Set the default to disabled for every extension 408 * unknown to KVM and error out if the user attempts 409 * to enable any of them. 410 */ 411 object_property_add(obj, prop_name, "bool", 412 cpu_get_cfg_unavailable, 413 cpu_set_cfg_unavailable, 414 NULL, (void *)prop_name); 415 } 416 417 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 418 const RISCVCPUMultiExtConfig *array) 419 { 420 const RISCVCPUMultiExtConfig *prop; 421 422 g_assert(array); 423 424 for (prop = array; prop && prop->name; prop++) { 425 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 426 } 427 } 428 429 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 430 { 431 int i; 432 433 riscv_add_satp_mode_properties(cpu_obj); 434 435 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 436 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 437 int bit = misa_cfg->offset; 438 439 misa_cfg->name = riscv_get_misa_ext_name(bit); 440 misa_cfg->description = riscv_get_misa_ext_description(bit); 441 442 object_property_add(cpu_obj, misa_cfg->name, "bool", 443 kvm_cpu_get_misa_ext_cfg, 444 kvm_cpu_set_misa_ext_cfg, 445 NULL, misa_cfg); 446 object_property_set_description(cpu_obj, misa_cfg->name, 447 misa_cfg->description); 448 } 449 450 for (i = 0; misa_bits[i] != 0; i++) { 451 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 452 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 453 } 454 455 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 456 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 457 458 object_property_add(cpu_obj, multi_cfg->name, "bool", 459 kvm_cpu_get_multi_ext_cfg, 460 kvm_cpu_set_multi_ext_cfg, 461 NULL, multi_cfg); 462 } 463 464 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 465 NULL, kvm_cpu_set_cbomz_blksize, 466 NULL, &kvm_cbom_blocksize); 467 468 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 469 NULL, kvm_cpu_set_cbomz_blksize, 470 NULL, &kvm_cboz_blocksize); 471 472 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 473 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 474 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 475 } 476 477 static int kvm_riscv_get_regs_core(CPUState *cs) 478 { 479 int ret = 0; 480 int i; 481 target_ulong reg; 482 CPURISCVState *env = &RISCV_CPU(cs)->env; 483 484 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 485 if (ret) { 486 return ret; 487 } 488 env->pc = reg; 489 490 for (i = 1; i < 32; i++) { 491 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 492 ret = kvm_get_one_reg(cs, id, ®); 493 if (ret) { 494 return ret; 495 } 496 env->gpr[i] = reg; 497 } 498 499 return ret; 500 } 501 502 static int kvm_riscv_put_regs_core(CPUState *cs) 503 { 504 int ret = 0; 505 int i; 506 target_ulong reg; 507 CPURISCVState *env = &RISCV_CPU(cs)->env; 508 509 reg = env->pc; 510 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 511 if (ret) { 512 return ret; 513 } 514 515 for (i = 1; i < 32; i++) { 516 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 517 reg = env->gpr[i]; 518 ret = kvm_set_one_reg(cs, id, ®); 519 if (ret) { 520 return ret; 521 } 522 } 523 524 return ret; 525 } 526 527 static int kvm_riscv_get_regs_csr(CPUState *cs) 528 { 529 int ret = 0; 530 CPURISCVState *env = &RISCV_CPU(cs)->env; 531 532 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 533 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 534 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 535 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 536 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 537 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 538 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 539 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 540 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 541 return ret; 542 } 543 544 static int kvm_riscv_put_regs_csr(CPUState *cs) 545 { 546 int ret = 0; 547 CPURISCVState *env = &RISCV_CPU(cs)->env; 548 549 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 550 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 551 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 552 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 553 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 554 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 555 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 556 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 557 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 558 559 return ret; 560 } 561 562 static int kvm_riscv_get_regs_fp(CPUState *cs) 563 { 564 int ret = 0; 565 int i; 566 CPURISCVState *env = &RISCV_CPU(cs)->env; 567 568 if (riscv_has_ext(env, RVD)) { 569 uint64_t reg; 570 for (i = 0; i < 32; i++) { 571 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 572 if (ret) { 573 return ret; 574 } 575 env->fpr[i] = reg; 576 } 577 return ret; 578 } 579 580 if (riscv_has_ext(env, RVF)) { 581 uint32_t reg; 582 for (i = 0; i < 32; i++) { 583 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 584 if (ret) { 585 return ret; 586 } 587 env->fpr[i] = reg; 588 } 589 return ret; 590 } 591 592 return ret; 593 } 594 595 static int kvm_riscv_put_regs_fp(CPUState *cs) 596 { 597 int ret = 0; 598 int i; 599 CPURISCVState *env = &RISCV_CPU(cs)->env; 600 601 if (riscv_has_ext(env, RVD)) { 602 uint64_t reg; 603 for (i = 0; i < 32; i++) { 604 reg = env->fpr[i]; 605 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 606 if (ret) { 607 return ret; 608 } 609 } 610 return ret; 611 } 612 613 if (riscv_has_ext(env, RVF)) { 614 uint32_t reg; 615 for (i = 0; i < 32; i++) { 616 reg = env->fpr[i]; 617 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 618 if (ret) { 619 return ret; 620 } 621 } 622 return ret; 623 } 624 625 return ret; 626 } 627 628 static void kvm_riscv_get_regs_timer(CPUState *cs) 629 { 630 CPURISCVState *env = &RISCV_CPU(cs)->env; 631 632 if (env->kvm_timer_dirty) { 633 return; 634 } 635 636 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 637 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 638 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 639 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 640 641 env->kvm_timer_dirty = true; 642 } 643 644 static void kvm_riscv_put_regs_timer(CPUState *cs) 645 { 646 uint64_t reg; 647 CPURISCVState *env = &RISCV_CPU(cs)->env; 648 649 if (!env->kvm_timer_dirty) { 650 return; 651 } 652 653 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 654 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 655 656 /* 657 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 658 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 659 * doesn't matter that adaping in QEMU now. 660 * TODO If KVM changes, adapt here. 661 */ 662 if (env->kvm_timer_state) { 663 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 664 } 665 666 /* 667 * For now, migration will not work between Hosts with different timer 668 * frequency. Therefore, we should check whether they are the same here 669 * during the migration. 670 */ 671 if (migration_is_running(migrate_get_current()->state)) { 672 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 673 if (reg != env->kvm_timer_frequency) { 674 error_report("Dst Hosts timer frequency != Src Hosts"); 675 } 676 } 677 678 env->kvm_timer_dirty = false; 679 } 680 681 typedef struct KVMScratchCPU { 682 int kvmfd; 683 int vmfd; 684 int cpufd; 685 } KVMScratchCPU; 686 687 /* 688 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 689 * from target/arm/kvm.c. 690 */ 691 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 692 { 693 int kvmfd = -1, vmfd = -1, cpufd = -1; 694 695 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 696 if (kvmfd < 0) { 697 goto err; 698 } 699 do { 700 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 701 } while (vmfd == -1 && errno == EINTR); 702 if (vmfd < 0) { 703 goto err; 704 } 705 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 706 if (cpufd < 0) { 707 goto err; 708 } 709 710 scratch->kvmfd = kvmfd; 711 scratch->vmfd = vmfd; 712 scratch->cpufd = cpufd; 713 714 return true; 715 716 err: 717 if (cpufd >= 0) { 718 close(cpufd); 719 } 720 if (vmfd >= 0) { 721 close(vmfd); 722 } 723 if (kvmfd >= 0) { 724 close(kvmfd); 725 } 726 727 return false; 728 } 729 730 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 731 { 732 close(scratch->cpufd); 733 close(scratch->vmfd); 734 close(scratch->kvmfd); 735 } 736 737 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 738 { 739 CPURISCVState *env = &cpu->env; 740 struct kvm_one_reg reg; 741 int ret; 742 743 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 744 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 745 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 746 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 747 if (ret != 0) { 748 error_report("Unable to retrieve mvendorid from host, error %d", ret); 749 } 750 751 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 752 KVM_REG_RISCV_CONFIG_REG(marchid)); 753 reg.addr = (uint64_t)&cpu->cfg.marchid; 754 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 755 if (ret != 0) { 756 error_report("Unable to retrieve marchid from host, error %d", ret); 757 } 758 759 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 760 KVM_REG_RISCV_CONFIG_REG(mimpid)); 761 reg.addr = (uint64_t)&cpu->cfg.mimpid; 762 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 763 if (ret != 0) { 764 error_report("Unable to retrieve mimpid from host, error %d", ret); 765 } 766 } 767 768 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 769 KVMScratchCPU *kvmcpu) 770 { 771 CPURISCVState *env = &cpu->env; 772 struct kvm_one_reg reg; 773 int ret; 774 775 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 776 KVM_REG_RISCV_CONFIG_REG(isa)); 777 reg.addr = (uint64_t)&env->misa_ext_mask; 778 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 779 780 if (ret) { 781 error_report("Unable to fetch ISA register from KVM, " 782 "error %d", ret); 783 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 784 exit(EXIT_FAILURE); 785 } 786 787 env->misa_ext = env->misa_ext_mask; 788 } 789 790 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 791 KVMCPUConfig *cbomz_cfg) 792 { 793 CPURISCVState *env = &cpu->env; 794 struct kvm_one_reg reg; 795 int ret; 796 797 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 798 cbomz_cfg->kvm_reg_id); 799 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 800 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 801 if (ret != 0) { 802 error_report("Unable to read KVM reg %s, error %d", 803 cbomz_cfg->name, ret); 804 exit(EXIT_FAILURE); 805 } 806 } 807 808 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 809 KVMScratchCPU *kvmcpu) 810 { 811 CPURISCVState *env = &cpu->env; 812 uint64_t val; 813 int i, ret; 814 815 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 816 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 817 struct kvm_one_reg reg; 818 819 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 820 multi_ext_cfg->kvm_reg_id); 821 reg.addr = (uint64_t)&val; 822 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 823 if (ret != 0) { 824 if (errno == EINVAL) { 825 /* Silently default to 'false' if KVM does not support it. */ 826 multi_ext_cfg->supported = false; 827 val = false; 828 } else { 829 error_report("Unable to read ISA_EXT KVM register %s, " 830 "error code: %s", multi_ext_cfg->name, 831 strerrorname_np(errno)); 832 exit(EXIT_FAILURE); 833 } 834 } else { 835 multi_ext_cfg->supported = true; 836 } 837 838 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 839 } 840 841 if (cpu->cfg.ext_zicbom) { 842 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 843 } 844 845 if (cpu->cfg.ext_zicboz) { 846 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 847 } 848 } 849 850 static int uint64_cmp(const void *a, const void *b) 851 { 852 uint64_t val1 = *(const uint64_t *)a; 853 uint64_t val2 = *(const uint64_t *)b; 854 855 if (val1 < val2) { 856 return -1; 857 } 858 859 if (val1 > val2) { 860 return 1; 861 } 862 863 return 0; 864 } 865 866 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 867 { 868 KVMCPUConfig *multi_ext_cfg; 869 struct kvm_one_reg reg; 870 struct kvm_reg_list rl_struct; 871 struct kvm_reg_list *reglist; 872 uint64_t val, reg_id, *reg_search; 873 int i, ret; 874 875 rl_struct.n = 0; 876 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 877 878 /* 879 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 880 * (EINVAL). Use read_legacy() in this case. 881 */ 882 if (errno == EINVAL) { 883 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 884 } else if (errno != E2BIG) { 885 /* 886 * E2BIG is an expected error message for the API since we 887 * don't know the number of registers. The right amount will 888 * be written in rl_struct.n. 889 * 890 * Error out if we get any other errno. 891 */ 892 error_report("Error when accessing get-reg-list, code: %s", 893 strerrorname_np(errno)); 894 exit(EXIT_FAILURE); 895 } 896 897 reglist = g_malloc(sizeof(struct kvm_reg_list) + 898 rl_struct.n * sizeof(uint64_t)); 899 reglist->n = rl_struct.n; 900 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 901 if (ret) { 902 error_report("Error when reading KVM_GET_REG_LIST, code %s ", 903 strerrorname_np(errno)); 904 exit(EXIT_FAILURE); 905 } 906 907 /* sort reglist to use bsearch() */ 908 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 909 910 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 911 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 912 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 913 multi_ext_cfg->kvm_reg_id); 914 reg_search = bsearch(®_id, reglist->reg, reglist->n, 915 sizeof(uint64_t), uint64_cmp); 916 if (!reg_search) { 917 continue; 918 } 919 920 reg.id = reg_id; 921 reg.addr = (uint64_t)&val; 922 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 923 if (ret != 0) { 924 error_report("Unable to read ISA_EXT KVM register %s, " 925 "error code: %s", multi_ext_cfg->name, 926 strerrorname_np(errno)); 927 exit(EXIT_FAILURE); 928 } 929 930 multi_ext_cfg->supported = true; 931 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 932 } 933 934 if (cpu->cfg.ext_zicbom) { 935 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 936 } 937 938 if (cpu->cfg.ext_zicboz) { 939 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 940 } 941 } 942 943 static void riscv_init_kvm_registers(Object *cpu_obj) 944 { 945 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 946 KVMScratchCPU kvmcpu; 947 948 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 949 return; 950 } 951 952 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 953 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 954 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 955 956 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 957 } 958 959 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 960 KVM_CAP_LAST_INFO 961 }; 962 963 int kvm_arch_get_registers(CPUState *cs) 964 { 965 int ret = 0; 966 967 ret = kvm_riscv_get_regs_core(cs); 968 if (ret) { 969 return ret; 970 } 971 972 ret = kvm_riscv_get_regs_csr(cs); 973 if (ret) { 974 return ret; 975 } 976 977 ret = kvm_riscv_get_regs_fp(cs); 978 if (ret) { 979 return ret; 980 } 981 982 return ret; 983 } 984 985 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 986 { 987 if (cap_has_mp_state) { 988 struct kvm_mp_state mp_state = { 989 .mp_state = state 990 }; 991 992 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 993 if (ret) { 994 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 995 __func__, ret, strerror(-ret)); 996 return -1; 997 } 998 } 999 1000 return 0; 1001 } 1002 1003 int kvm_arch_put_registers(CPUState *cs, int level) 1004 { 1005 int ret = 0; 1006 1007 ret = kvm_riscv_put_regs_core(cs); 1008 if (ret) { 1009 return ret; 1010 } 1011 1012 ret = kvm_riscv_put_regs_csr(cs); 1013 if (ret) { 1014 return ret; 1015 } 1016 1017 ret = kvm_riscv_put_regs_fp(cs); 1018 if (ret) { 1019 return ret; 1020 } 1021 1022 if (KVM_PUT_RESET_STATE == level) { 1023 RISCVCPU *cpu = RISCV_CPU(cs); 1024 if (cs->cpu_index == 0) { 1025 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1026 } else { 1027 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1028 } 1029 if (ret) { 1030 return ret; 1031 } 1032 } 1033 1034 return ret; 1035 } 1036 1037 int kvm_arch_release_virq_post(int virq) 1038 { 1039 return 0; 1040 } 1041 1042 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1043 uint64_t address, uint32_t data, PCIDevice *dev) 1044 { 1045 return 0; 1046 } 1047 1048 int kvm_arch_destroy_vcpu(CPUState *cs) 1049 { 1050 return 0; 1051 } 1052 1053 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1054 { 1055 return cpu->cpu_index; 1056 } 1057 1058 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1059 RunState state) 1060 { 1061 CPUState *cs = opaque; 1062 1063 if (running) { 1064 kvm_riscv_put_regs_timer(cs); 1065 } else { 1066 kvm_riscv_get_regs_timer(cs); 1067 } 1068 } 1069 1070 void kvm_arch_init_irq_routing(KVMState *s) 1071 { 1072 } 1073 1074 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1075 { 1076 CPURISCVState *env = &cpu->env; 1077 target_ulong reg; 1078 uint64_t id; 1079 int ret; 1080 1081 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1082 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1083 /* 1084 * cfg.mvendorid is an uint32 but a target_ulong will 1085 * be written. Assign it to a target_ulong var to avoid 1086 * writing pieces of other cpu->cfg fields in the reg. 1087 */ 1088 reg = cpu->cfg.mvendorid; 1089 ret = kvm_set_one_reg(cs, id, ®); 1090 if (ret != 0) { 1091 return ret; 1092 } 1093 1094 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1095 KVM_REG_RISCV_CONFIG_REG(marchid)); 1096 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1097 if (ret != 0) { 1098 return ret; 1099 } 1100 1101 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1102 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1103 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1104 1105 return ret; 1106 } 1107 1108 int kvm_arch_init_vcpu(CPUState *cs) 1109 { 1110 int ret = 0; 1111 RISCVCPU *cpu = RISCV_CPU(cs); 1112 1113 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1114 1115 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1116 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1117 if (ret != 0) { 1118 return ret; 1119 } 1120 } 1121 1122 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1123 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1124 1125 return ret; 1126 } 1127 1128 int kvm_arch_msi_data_to_gsi(uint32_t data) 1129 { 1130 abort(); 1131 } 1132 1133 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1134 int vector, PCIDevice *dev) 1135 { 1136 return 0; 1137 } 1138 1139 int kvm_arch_get_default_type(MachineState *ms) 1140 { 1141 return 0; 1142 } 1143 1144 int kvm_arch_init(MachineState *ms, KVMState *s) 1145 { 1146 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1147 return 0; 1148 } 1149 1150 int kvm_arch_irqchip_create(KVMState *s) 1151 { 1152 if (kvm_kernel_irqchip_split()) { 1153 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1154 exit(1); 1155 } 1156 1157 /* 1158 * We can create the VAIA using the newer device control API. 1159 */ 1160 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1161 } 1162 1163 int kvm_arch_process_async_events(CPUState *cs) 1164 { 1165 return 0; 1166 } 1167 1168 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1169 { 1170 } 1171 1172 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1173 { 1174 return MEMTXATTRS_UNSPECIFIED; 1175 } 1176 1177 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1178 { 1179 return true; 1180 } 1181 1182 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1183 { 1184 int ret = 0; 1185 unsigned char ch; 1186 switch (run->riscv_sbi.extension_id) { 1187 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1188 ch = run->riscv_sbi.args[0]; 1189 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1190 break; 1191 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1192 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1193 if (ret == sizeof(ch)) { 1194 run->riscv_sbi.ret[0] = ch; 1195 } else { 1196 run->riscv_sbi.ret[0] = -1; 1197 } 1198 ret = 0; 1199 break; 1200 default: 1201 qemu_log_mask(LOG_UNIMP, 1202 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1203 __func__, run->riscv_sbi.extension_id); 1204 ret = -1; 1205 break; 1206 } 1207 return ret; 1208 } 1209 1210 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1211 { 1212 int ret = 0; 1213 switch (run->exit_reason) { 1214 case KVM_EXIT_RISCV_SBI: 1215 ret = kvm_riscv_handle_sbi(cs, run); 1216 break; 1217 default: 1218 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1219 __func__, run->exit_reason); 1220 ret = -1; 1221 break; 1222 } 1223 return ret; 1224 } 1225 1226 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1227 { 1228 CPURISCVState *env = &cpu->env; 1229 int i; 1230 1231 if (!kvm_enabled()) { 1232 return; 1233 } 1234 for (i = 0; i < 32; i++) { 1235 env->gpr[i] = 0; 1236 } 1237 env->pc = cpu->env.kernel_addr; 1238 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1239 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1240 env->satp = 0; 1241 env->mie = 0; 1242 env->stvec = 0; 1243 env->sscratch = 0; 1244 env->sepc = 0; 1245 env->scause = 0; 1246 env->stval = 0; 1247 env->mip = 0; 1248 } 1249 1250 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1251 { 1252 int ret; 1253 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1254 1255 if (irq != IRQ_S_EXT) { 1256 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1257 abort(); 1258 } 1259 1260 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1261 if (ret < 0) { 1262 perror("Set irq failed"); 1263 abort(); 1264 } 1265 } 1266 1267 bool kvm_arch_cpu_check_are_resettable(void) 1268 { 1269 return true; 1270 } 1271 1272 static int aia_mode; 1273 1274 static const char *kvm_aia_mode_str(uint64_t mode) 1275 { 1276 switch (mode) { 1277 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1278 return "emul"; 1279 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1280 return "hwaccel"; 1281 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1282 default: 1283 return "auto"; 1284 }; 1285 } 1286 1287 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1288 { 1289 return g_strdup(kvm_aia_mode_str(aia_mode)); 1290 } 1291 1292 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1293 { 1294 if (!strcmp(val, "emul")) { 1295 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1296 } else if (!strcmp(val, "hwaccel")) { 1297 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1298 } else if (!strcmp(val, "auto")) { 1299 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1300 } else { 1301 error_setg(errp, "Invalid KVM AIA mode"); 1302 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1303 } 1304 } 1305 1306 void kvm_arch_accel_class_init(ObjectClass *oc) 1307 { 1308 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1309 riscv_set_kvm_aia); 1310 object_class_property_set_description(oc, "riscv-aia", 1311 "Set KVM AIA mode. Valid values are " 1312 "emul, hwaccel, and auto. Default " 1313 "is auto."); 1314 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1315 "auto"); 1316 } 1317 1318 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1319 uint64_t aia_irq_num, uint64_t aia_msi_num, 1320 uint64_t aplic_base, uint64_t imsic_base, 1321 uint64_t guest_num) 1322 { 1323 int ret, i; 1324 int aia_fd = -1; 1325 uint64_t default_aia_mode; 1326 uint64_t socket_count = riscv_socket_count(machine); 1327 uint64_t max_hart_per_socket = 0; 1328 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1329 uint64_t socket_bits, hart_bits, guest_bits; 1330 1331 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1332 1333 if (aia_fd < 0) { 1334 error_report("Unable to create in-kernel irqchip"); 1335 exit(1); 1336 } 1337 1338 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1339 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1340 &default_aia_mode, false, NULL); 1341 if (ret < 0) { 1342 error_report("KVM AIA: failed to get current KVM AIA mode"); 1343 exit(1); 1344 } 1345 qemu_log("KVM AIA: default mode is %s\n", 1346 kvm_aia_mode_str(default_aia_mode)); 1347 1348 if (default_aia_mode != aia_mode) { 1349 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1350 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1351 &aia_mode, true, NULL); 1352 if (ret < 0) 1353 warn_report("KVM AIA: failed to set KVM AIA mode"); 1354 else 1355 qemu_log("KVM AIA: set current mode to %s\n", 1356 kvm_aia_mode_str(aia_mode)); 1357 } 1358 1359 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1360 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1361 &aia_irq_num, true, NULL); 1362 if (ret < 0) { 1363 error_report("KVM AIA: failed to set number of input irq lines"); 1364 exit(1); 1365 } 1366 1367 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1368 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1369 &aia_msi_num, true, NULL); 1370 if (ret < 0) { 1371 error_report("KVM AIA: failed to set number of msi"); 1372 exit(1); 1373 } 1374 1375 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1376 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1377 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1378 &socket_bits, true, NULL); 1379 if (ret < 0) { 1380 error_report("KVM AIA: failed to set group_bits"); 1381 exit(1); 1382 } 1383 1384 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1385 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1386 &group_shift, true, NULL); 1387 if (ret < 0) { 1388 error_report("KVM AIA: failed to set group_shift"); 1389 exit(1); 1390 } 1391 1392 guest_bits = guest_num == 0 ? 0 : 1393 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1394 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1395 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1396 &guest_bits, true, NULL); 1397 if (ret < 0) { 1398 error_report("KVM AIA: failed to set guest_bits"); 1399 exit(1); 1400 } 1401 1402 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1403 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1404 &aplic_base, true, NULL); 1405 if (ret < 0) { 1406 error_report("KVM AIA: failed to set the base address of APLIC"); 1407 exit(1); 1408 } 1409 1410 for (socket = 0; socket < socket_count; socket++) { 1411 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1412 hart_count = riscv_socket_hart_count(machine, socket); 1413 base_hart = riscv_socket_first_hartid(machine, socket); 1414 1415 if (max_hart_per_socket < hart_count) { 1416 max_hart_per_socket = hart_count; 1417 } 1418 1419 for (i = 0; i < hart_count; i++) { 1420 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1421 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1422 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1423 &imsic_addr, true, NULL); 1424 if (ret < 0) { 1425 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1426 exit(1); 1427 } 1428 } 1429 } 1430 1431 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1432 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1433 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1434 &hart_bits, true, NULL); 1435 if (ret < 0) { 1436 error_report("KVM AIA: failed to set hart_bits"); 1437 exit(1); 1438 } 1439 1440 if (kvm_has_gsi_routing()) { 1441 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1442 /* KVM AIA only has one APLIC instance */ 1443 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1444 } 1445 kvm_gsi_routing_allowed = true; 1446 kvm_irqchip_commit_routes(kvm_state); 1447 } 1448 1449 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1450 KVM_DEV_RISCV_AIA_CTRL_INIT, 1451 NULL, true, NULL); 1452 if (ret < 0) { 1453 error_report("KVM AIA: initialized fail"); 1454 exit(1); 1455 } 1456 1457 kvm_msi_via_irqfd_allowed = true; 1458 } 1459 1460 static void kvm_cpu_instance_init(CPUState *cs) 1461 { 1462 Object *obj = OBJECT(RISCV_CPU(cs)); 1463 DeviceState *dev = DEVICE(obj); 1464 1465 riscv_init_kvm_registers(obj); 1466 1467 kvm_riscv_add_cpu_user_properties(obj); 1468 1469 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1470 /* Check if we have a specific KVM handler for the option */ 1471 if (object_property_find(obj, prop->name)) { 1472 continue; 1473 } 1474 qdev_property_add_static(dev, prop); 1475 } 1476 } 1477 1478 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1479 { 1480 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1481 1482 acc->cpu_instance_init = kvm_cpu_instance_init; 1483 } 1484 1485 static const TypeInfo kvm_cpu_accel_type_info = { 1486 .name = ACCEL_CPU_NAME("kvm"), 1487 1488 .parent = TYPE_ACCEL_CPU, 1489 .class_init = kvm_cpu_accel_class_init, 1490 .abstract = true, 1491 }; 1492 static void kvm_cpu_accel_register_types(void) 1493 { 1494 type_register_static(&kvm_cpu_accel_type_info); 1495 } 1496 type_init(kvm_cpu_accel_register_types); 1497 1498 static void riscv_host_cpu_init(Object *obj) 1499 { 1500 CPURISCVState *env = &RISCV_CPU(obj)->env; 1501 1502 #if defined(TARGET_RISCV32) 1503 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1504 #elif defined(TARGET_RISCV64) 1505 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1506 #endif 1507 } 1508 1509 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1510 { 1511 .name = TYPE_RISCV_CPU_HOST, 1512 .parent = TYPE_RISCV_CPU, 1513 .instance_init = riscv_host_cpu_init, 1514 } 1515 }; 1516 1517 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1518