1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 76 { 77 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 78 } 79 80 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 81 { 82 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 83 } 84 85 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 86 KVM_REG_RISCV_CORE_REG(name)) 87 88 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 89 KVM_REG_RISCV_CSR_REG(name)) 90 91 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 92 KVM_REG_RISCV_TIMER_REG(name)) 93 94 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 95 96 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 97 98 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 99 do { \ 100 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 101 if (_ret) { \ 102 return _ret; \ 103 } \ 104 } while (0) 105 106 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 107 do { \ 108 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 109 if (_ret) { \ 110 return _ret; \ 111 } \ 112 } while (0) 113 114 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 115 do { \ 116 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 117 if (ret) { \ 118 abort(); \ 119 } \ 120 } while (0) 121 122 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 123 do { \ 124 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 125 if (ret) { \ 126 abort(); \ 127 } \ 128 } while (0) 129 130 typedef struct KVMCPUConfig { 131 const char *name; 132 const char *description; 133 target_ulong offset; 134 int kvm_reg_id; 135 bool user_set; 136 bool supported; 137 } KVMCPUConfig; 138 139 #define KVM_MISA_CFG(_bit, _reg_id) \ 140 {.offset = _bit, .kvm_reg_id = _reg_id} 141 142 /* KVM ISA extensions */ 143 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 144 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 145 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 146 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 147 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 148 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 149 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 150 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 151 }; 152 153 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 154 const char *name, 155 void *opaque, Error **errp) 156 { 157 KVMCPUConfig *misa_ext_cfg = opaque; 158 target_ulong misa_bit = misa_ext_cfg->offset; 159 RISCVCPU *cpu = RISCV_CPU(obj); 160 CPURISCVState *env = &cpu->env; 161 bool value = env->misa_ext_mask & misa_bit; 162 163 visit_type_bool(v, name, &value, errp); 164 } 165 166 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 167 const char *name, 168 void *opaque, Error **errp) 169 { 170 KVMCPUConfig *misa_ext_cfg = opaque; 171 target_ulong misa_bit = misa_ext_cfg->offset; 172 RISCVCPU *cpu = RISCV_CPU(obj); 173 CPURISCVState *env = &cpu->env; 174 bool value, host_bit; 175 176 if (!visit_type_bool(v, name, &value, errp)) { 177 return; 178 } 179 180 host_bit = env->misa_ext_mask & misa_bit; 181 182 if (value == host_bit) { 183 return; 184 } 185 186 if (!value) { 187 misa_ext_cfg->user_set = true; 188 return; 189 } 190 191 /* 192 * Forbid users to enable extensions that aren't 193 * available in the hart. 194 */ 195 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 196 "enabled in the host", misa_ext_cfg->name); 197 } 198 199 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 200 { 201 CPURISCVState *env = &cpu->env; 202 uint64_t id, reg; 203 int i, ret; 204 205 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 206 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 207 target_ulong misa_bit = misa_cfg->offset; 208 209 if (!misa_cfg->user_set) { 210 continue; 211 } 212 213 /* If we're here we're going to disable the MISA bit */ 214 reg = 0; 215 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 216 misa_cfg->kvm_reg_id); 217 ret = kvm_set_one_reg(cs, id, ®); 218 if (ret != 0) { 219 /* 220 * We're not checking for -EINVAL because if the bit is about 221 * to be disabled, it means that it was already enabled by 222 * KVM. We determined that by fetching the 'isa' register 223 * during init() time. Any error at this point is worth 224 * aborting. 225 */ 226 error_report("Unable to set KVM reg %s, error %d", 227 misa_cfg->name, ret); 228 exit(EXIT_FAILURE); 229 } 230 env->misa_ext &= ~misa_bit; 231 } 232 } 233 234 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 235 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 236 .kvm_reg_id = _reg_id} 237 238 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 239 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 240 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 241 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 242 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 243 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 244 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 245 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 246 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 247 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 248 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 249 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 250 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 251 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 252 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 253 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 254 }; 255 256 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 257 { 258 return (void *)&cpu->cfg + kvmcfg->offset; 259 } 260 261 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 262 uint32_t val) 263 { 264 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 265 266 *ext_enabled = val; 267 } 268 269 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 270 KVMCPUConfig *multi_ext) 271 { 272 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 273 274 return *ext_enabled; 275 } 276 277 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 278 const char *name, 279 void *opaque, Error **errp) 280 { 281 KVMCPUConfig *multi_ext_cfg = opaque; 282 RISCVCPU *cpu = RISCV_CPU(obj); 283 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 284 285 visit_type_bool(v, name, &value, errp); 286 } 287 288 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 289 const char *name, 290 void *opaque, Error **errp) 291 { 292 KVMCPUConfig *multi_ext_cfg = opaque; 293 RISCVCPU *cpu = RISCV_CPU(obj); 294 bool value, host_val; 295 296 if (!visit_type_bool(v, name, &value, errp)) { 297 return; 298 } 299 300 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 301 302 /* 303 * Ignore if the user is setting the same value 304 * as the host. 305 */ 306 if (value == host_val) { 307 return; 308 } 309 310 if (!multi_ext_cfg->supported) { 311 /* 312 * Error out if the user is trying to enable an 313 * extension that KVM doesn't support. Ignore 314 * option otherwise. 315 */ 316 if (value) { 317 error_setg(errp, "KVM does not support disabling extension %s", 318 multi_ext_cfg->name); 319 } 320 321 return; 322 } 323 324 multi_ext_cfg->user_set = true; 325 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 326 } 327 328 static KVMCPUConfig kvm_cbom_blocksize = { 329 .name = "cbom_blocksize", 330 .offset = CPU_CFG_OFFSET(cbom_blocksize), 331 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 332 }; 333 334 static KVMCPUConfig kvm_cboz_blocksize = { 335 .name = "cboz_blocksize", 336 .offset = CPU_CFG_OFFSET(cboz_blocksize), 337 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 338 }; 339 340 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 341 const char *name, 342 void *opaque, Error **errp) 343 { 344 KVMCPUConfig *cbomz_cfg = opaque; 345 RISCVCPU *cpu = RISCV_CPU(obj); 346 uint16_t value, *host_val; 347 348 if (!visit_type_uint16(v, name, &value, errp)) { 349 return; 350 } 351 352 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 353 354 if (value != *host_val) { 355 error_report("Unable to set %s to a different value than " 356 "the host (%u)", 357 cbomz_cfg->name, *host_val); 358 exit(EXIT_FAILURE); 359 } 360 361 cbomz_cfg->user_set = true; 362 } 363 364 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 365 { 366 CPURISCVState *env = &cpu->env; 367 uint64_t id, reg; 368 int i, ret; 369 370 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 371 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 372 373 if (!multi_ext_cfg->user_set) { 374 continue; 375 } 376 377 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 378 multi_ext_cfg->kvm_reg_id); 379 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 380 ret = kvm_set_one_reg(cs, id, ®); 381 if (ret != 0) { 382 error_report("Unable to %s extension %s in KVM, error %d", 383 reg ? "enable" : "disable", 384 multi_ext_cfg->name, ret); 385 exit(EXIT_FAILURE); 386 } 387 } 388 } 389 390 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 391 const char *name, 392 void *opaque, Error **errp) 393 { 394 bool value = false; 395 396 visit_type_bool(v, name, &value, errp); 397 } 398 399 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 400 const char *name, 401 void *opaque, Error **errp) 402 { 403 const char *propname = opaque; 404 bool value; 405 406 if (!visit_type_bool(v, name, &value, errp)) { 407 return; 408 } 409 410 if (value) { 411 error_setg(errp, "extension %s is not available with KVM", 412 propname); 413 } 414 } 415 416 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 417 { 418 /* Check if KVM created the property already */ 419 if (object_property_find(obj, prop_name)) { 420 return; 421 } 422 423 /* 424 * Set the default to disabled for every extension 425 * unknown to KVM and error out if the user attempts 426 * to enable any of them. 427 */ 428 object_property_add(obj, prop_name, "bool", 429 cpu_get_cfg_unavailable, 430 cpu_set_cfg_unavailable, 431 NULL, (void *)prop_name); 432 } 433 434 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 435 const RISCVCPUMultiExtConfig *array) 436 { 437 const RISCVCPUMultiExtConfig *prop; 438 439 g_assert(array); 440 441 for (prop = array; prop && prop->name; prop++) { 442 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 443 } 444 } 445 446 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 447 { 448 int i; 449 450 riscv_add_satp_mode_properties(cpu_obj); 451 452 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 453 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 454 int bit = misa_cfg->offset; 455 456 misa_cfg->name = riscv_get_misa_ext_name(bit); 457 misa_cfg->description = riscv_get_misa_ext_description(bit); 458 459 object_property_add(cpu_obj, misa_cfg->name, "bool", 460 kvm_cpu_get_misa_ext_cfg, 461 kvm_cpu_set_misa_ext_cfg, 462 NULL, misa_cfg); 463 object_property_set_description(cpu_obj, misa_cfg->name, 464 misa_cfg->description); 465 } 466 467 for (i = 0; misa_bits[i] != 0; i++) { 468 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 469 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 470 } 471 472 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 473 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 474 475 object_property_add(cpu_obj, multi_cfg->name, "bool", 476 kvm_cpu_get_multi_ext_cfg, 477 kvm_cpu_set_multi_ext_cfg, 478 NULL, multi_cfg); 479 } 480 481 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 482 NULL, kvm_cpu_set_cbomz_blksize, 483 NULL, &kvm_cbom_blocksize); 484 485 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 486 NULL, kvm_cpu_set_cbomz_blksize, 487 NULL, &kvm_cboz_blocksize); 488 489 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 490 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 491 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 492 } 493 494 static int kvm_riscv_get_regs_core(CPUState *cs) 495 { 496 int ret = 0; 497 int i; 498 target_ulong reg; 499 CPURISCVState *env = &RISCV_CPU(cs)->env; 500 501 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 502 if (ret) { 503 return ret; 504 } 505 env->pc = reg; 506 507 for (i = 1; i < 32; i++) { 508 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 509 ret = kvm_get_one_reg(cs, id, ®); 510 if (ret) { 511 return ret; 512 } 513 env->gpr[i] = reg; 514 } 515 516 return ret; 517 } 518 519 static int kvm_riscv_put_regs_core(CPUState *cs) 520 { 521 int ret = 0; 522 int i; 523 target_ulong reg; 524 CPURISCVState *env = &RISCV_CPU(cs)->env; 525 526 reg = env->pc; 527 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 528 if (ret) { 529 return ret; 530 } 531 532 for (i = 1; i < 32; i++) { 533 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 534 reg = env->gpr[i]; 535 ret = kvm_set_one_reg(cs, id, ®); 536 if (ret) { 537 return ret; 538 } 539 } 540 541 return ret; 542 } 543 544 static int kvm_riscv_get_regs_csr(CPUState *cs) 545 { 546 CPURISCVState *env = &RISCV_CPU(cs)->env; 547 548 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 549 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 550 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 551 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 552 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 553 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 554 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 555 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 556 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 557 558 return 0; 559 } 560 561 static int kvm_riscv_put_regs_csr(CPUState *cs) 562 { 563 CPURISCVState *env = &RISCV_CPU(cs)->env; 564 565 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 566 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 567 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 568 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 569 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 570 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 571 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 572 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 573 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 574 575 return 0; 576 } 577 578 static int kvm_riscv_get_regs_fp(CPUState *cs) 579 { 580 int ret = 0; 581 int i; 582 CPURISCVState *env = &RISCV_CPU(cs)->env; 583 584 if (riscv_has_ext(env, RVD)) { 585 uint64_t reg; 586 for (i = 0; i < 32; i++) { 587 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 588 if (ret) { 589 return ret; 590 } 591 env->fpr[i] = reg; 592 } 593 return ret; 594 } 595 596 if (riscv_has_ext(env, RVF)) { 597 uint32_t reg; 598 for (i = 0; i < 32; i++) { 599 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 600 if (ret) { 601 return ret; 602 } 603 env->fpr[i] = reg; 604 } 605 return ret; 606 } 607 608 return ret; 609 } 610 611 static int kvm_riscv_put_regs_fp(CPUState *cs) 612 { 613 int ret = 0; 614 int i; 615 CPURISCVState *env = &RISCV_CPU(cs)->env; 616 617 if (riscv_has_ext(env, RVD)) { 618 uint64_t reg; 619 for (i = 0; i < 32; i++) { 620 reg = env->fpr[i]; 621 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 622 if (ret) { 623 return ret; 624 } 625 } 626 return ret; 627 } 628 629 if (riscv_has_ext(env, RVF)) { 630 uint32_t reg; 631 for (i = 0; i < 32; i++) { 632 reg = env->fpr[i]; 633 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 634 if (ret) { 635 return ret; 636 } 637 } 638 return ret; 639 } 640 641 return ret; 642 } 643 644 static void kvm_riscv_get_regs_timer(CPUState *cs) 645 { 646 CPURISCVState *env = &RISCV_CPU(cs)->env; 647 648 if (env->kvm_timer_dirty) { 649 return; 650 } 651 652 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 653 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 654 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 655 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 656 657 env->kvm_timer_dirty = true; 658 } 659 660 static void kvm_riscv_put_regs_timer(CPUState *cs) 661 { 662 uint64_t reg; 663 CPURISCVState *env = &RISCV_CPU(cs)->env; 664 665 if (!env->kvm_timer_dirty) { 666 return; 667 } 668 669 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 670 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 671 672 /* 673 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 674 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 675 * doesn't matter that adaping in QEMU now. 676 * TODO If KVM changes, adapt here. 677 */ 678 if (env->kvm_timer_state) { 679 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 680 } 681 682 /* 683 * For now, migration will not work between Hosts with different timer 684 * frequency. Therefore, we should check whether they are the same here 685 * during the migration. 686 */ 687 if (migration_is_running(migrate_get_current()->state)) { 688 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 689 if (reg != env->kvm_timer_frequency) { 690 error_report("Dst Hosts timer frequency != Src Hosts"); 691 } 692 } 693 694 env->kvm_timer_dirty = false; 695 } 696 697 typedef struct KVMScratchCPU { 698 int kvmfd; 699 int vmfd; 700 int cpufd; 701 } KVMScratchCPU; 702 703 /* 704 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 705 * from target/arm/kvm.c. 706 */ 707 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 708 { 709 int kvmfd = -1, vmfd = -1, cpufd = -1; 710 711 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 712 if (kvmfd < 0) { 713 goto err; 714 } 715 do { 716 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 717 } while (vmfd == -1 && errno == EINTR); 718 if (vmfd < 0) { 719 goto err; 720 } 721 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 722 if (cpufd < 0) { 723 goto err; 724 } 725 726 scratch->kvmfd = kvmfd; 727 scratch->vmfd = vmfd; 728 scratch->cpufd = cpufd; 729 730 return true; 731 732 err: 733 if (cpufd >= 0) { 734 close(cpufd); 735 } 736 if (vmfd >= 0) { 737 close(vmfd); 738 } 739 if (kvmfd >= 0) { 740 close(kvmfd); 741 } 742 743 return false; 744 } 745 746 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 747 { 748 close(scratch->cpufd); 749 close(scratch->vmfd); 750 close(scratch->kvmfd); 751 } 752 753 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 754 { 755 CPURISCVState *env = &cpu->env; 756 struct kvm_one_reg reg; 757 int ret; 758 759 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 760 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 761 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 762 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 763 if (ret != 0) { 764 error_report("Unable to retrieve mvendorid from host, error %d", ret); 765 } 766 767 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 768 KVM_REG_RISCV_CONFIG_REG(marchid)); 769 reg.addr = (uint64_t)&cpu->cfg.marchid; 770 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 771 if (ret != 0) { 772 error_report("Unable to retrieve marchid from host, error %d", ret); 773 } 774 775 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 776 KVM_REG_RISCV_CONFIG_REG(mimpid)); 777 reg.addr = (uint64_t)&cpu->cfg.mimpid; 778 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 779 if (ret != 0) { 780 error_report("Unable to retrieve mimpid from host, error %d", ret); 781 } 782 } 783 784 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 785 KVMScratchCPU *kvmcpu) 786 { 787 CPURISCVState *env = &cpu->env; 788 struct kvm_one_reg reg; 789 int ret; 790 791 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 792 KVM_REG_RISCV_CONFIG_REG(isa)); 793 reg.addr = (uint64_t)&env->misa_ext_mask; 794 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 795 796 if (ret) { 797 error_report("Unable to fetch ISA register from KVM, " 798 "error %d", ret); 799 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 800 exit(EXIT_FAILURE); 801 } 802 803 env->misa_ext = env->misa_ext_mask; 804 } 805 806 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 807 KVMCPUConfig *cbomz_cfg) 808 { 809 CPURISCVState *env = &cpu->env; 810 struct kvm_one_reg reg; 811 int ret; 812 813 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 814 cbomz_cfg->kvm_reg_id); 815 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 816 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 817 if (ret != 0) { 818 error_report("Unable to read KVM reg %s, error %d", 819 cbomz_cfg->name, ret); 820 exit(EXIT_FAILURE); 821 } 822 } 823 824 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 825 KVMScratchCPU *kvmcpu) 826 { 827 CPURISCVState *env = &cpu->env; 828 uint64_t val; 829 int i, ret; 830 831 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 832 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 833 struct kvm_one_reg reg; 834 835 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 836 multi_ext_cfg->kvm_reg_id); 837 reg.addr = (uint64_t)&val; 838 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 839 if (ret != 0) { 840 if (errno == EINVAL) { 841 /* Silently default to 'false' if KVM does not support it. */ 842 multi_ext_cfg->supported = false; 843 val = false; 844 } else { 845 error_report("Unable to read ISA_EXT KVM register %s: %s", 846 multi_ext_cfg->name, strerror(errno)); 847 exit(EXIT_FAILURE); 848 } 849 } else { 850 multi_ext_cfg->supported = true; 851 } 852 853 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 854 } 855 856 if (cpu->cfg.ext_zicbom) { 857 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 858 } 859 860 if (cpu->cfg.ext_zicboz) { 861 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 862 } 863 } 864 865 static int uint64_cmp(const void *a, const void *b) 866 { 867 uint64_t val1 = *(const uint64_t *)a; 868 uint64_t val2 = *(const uint64_t *)b; 869 870 if (val1 < val2) { 871 return -1; 872 } 873 874 if (val1 > val2) { 875 return 1; 876 } 877 878 return 0; 879 } 880 881 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 882 { 883 KVMCPUConfig *multi_ext_cfg; 884 struct kvm_one_reg reg; 885 struct kvm_reg_list rl_struct; 886 struct kvm_reg_list *reglist; 887 uint64_t val, reg_id, *reg_search; 888 int i, ret; 889 890 rl_struct.n = 0; 891 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 892 893 /* 894 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 895 * (EINVAL). Use read_legacy() in this case. 896 */ 897 if (errno == EINVAL) { 898 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 899 } else if (errno != E2BIG) { 900 /* 901 * E2BIG is an expected error message for the API since we 902 * don't know the number of registers. The right amount will 903 * be written in rl_struct.n. 904 * 905 * Error out if we get any other errno. 906 */ 907 error_report("Error when accessing get-reg-list: %s", 908 strerror(errno)); 909 exit(EXIT_FAILURE); 910 } 911 912 reglist = g_malloc(sizeof(struct kvm_reg_list) + 913 rl_struct.n * sizeof(uint64_t)); 914 reglist->n = rl_struct.n; 915 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 916 if (ret) { 917 error_report("Error when reading KVM_GET_REG_LIST: %s", 918 strerror(errno)); 919 exit(EXIT_FAILURE); 920 } 921 922 /* sort reglist to use bsearch() */ 923 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 924 925 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 926 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 927 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 928 multi_ext_cfg->kvm_reg_id); 929 reg_search = bsearch(®_id, reglist->reg, reglist->n, 930 sizeof(uint64_t), uint64_cmp); 931 if (!reg_search) { 932 continue; 933 } 934 935 reg.id = reg_id; 936 reg.addr = (uint64_t)&val; 937 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 938 if (ret != 0) { 939 error_report("Unable to read ISA_EXT KVM register %s: %s", 940 multi_ext_cfg->name, strerror(errno)); 941 exit(EXIT_FAILURE); 942 } 943 944 multi_ext_cfg->supported = true; 945 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 946 } 947 948 if (cpu->cfg.ext_zicbom) { 949 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 950 } 951 952 if (cpu->cfg.ext_zicboz) { 953 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 954 } 955 } 956 957 static void riscv_init_kvm_registers(Object *cpu_obj) 958 { 959 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 960 KVMScratchCPU kvmcpu; 961 962 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 963 return; 964 } 965 966 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 967 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 968 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 969 970 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 971 } 972 973 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 974 KVM_CAP_LAST_INFO 975 }; 976 977 int kvm_arch_get_registers(CPUState *cs) 978 { 979 int ret = 0; 980 981 ret = kvm_riscv_get_regs_core(cs); 982 if (ret) { 983 return ret; 984 } 985 986 ret = kvm_riscv_get_regs_csr(cs); 987 if (ret) { 988 return ret; 989 } 990 991 ret = kvm_riscv_get_regs_fp(cs); 992 if (ret) { 993 return ret; 994 } 995 996 return ret; 997 } 998 999 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1000 { 1001 if (cap_has_mp_state) { 1002 struct kvm_mp_state mp_state = { 1003 .mp_state = state 1004 }; 1005 1006 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1007 if (ret) { 1008 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1009 __func__, ret, strerror(-ret)); 1010 return -1; 1011 } 1012 } 1013 1014 return 0; 1015 } 1016 1017 int kvm_arch_put_registers(CPUState *cs, int level) 1018 { 1019 int ret = 0; 1020 1021 ret = kvm_riscv_put_regs_core(cs); 1022 if (ret) { 1023 return ret; 1024 } 1025 1026 ret = kvm_riscv_put_regs_csr(cs); 1027 if (ret) { 1028 return ret; 1029 } 1030 1031 ret = kvm_riscv_put_regs_fp(cs); 1032 if (ret) { 1033 return ret; 1034 } 1035 1036 if (KVM_PUT_RESET_STATE == level) { 1037 RISCVCPU *cpu = RISCV_CPU(cs); 1038 if (cs->cpu_index == 0) { 1039 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1040 } else { 1041 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1042 } 1043 if (ret) { 1044 return ret; 1045 } 1046 } 1047 1048 return ret; 1049 } 1050 1051 int kvm_arch_release_virq_post(int virq) 1052 { 1053 return 0; 1054 } 1055 1056 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1057 uint64_t address, uint32_t data, PCIDevice *dev) 1058 { 1059 return 0; 1060 } 1061 1062 int kvm_arch_destroy_vcpu(CPUState *cs) 1063 { 1064 return 0; 1065 } 1066 1067 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1068 { 1069 return cpu->cpu_index; 1070 } 1071 1072 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1073 RunState state) 1074 { 1075 CPUState *cs = opaque; 1076 1077 if (running) { 1078 kvm_riscv_put_regs_timer(cs); 1079 } else { 1080 kvm_riscv_get_regs_timer(cs); 1081 } 1082 } 1083 1084 void kvm_arch_init_irq_routing(KVMState *s) 1085 { 1086 } 1087 1088 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1089 { 1090 CPURISCVState *env = &cpu->env; 1091 target_ulong reg; 1092 uint64_t id; 1093 int ret; 1094 1095 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1096 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1097 /* 1098 * cfg.mvendorid is an uint32 but a target_ulong will 1099 * be written. Assign it to a target_ulong var to avoid 1100 * writing pieces of other cpu->cfg fields in the reg. 1101 */ 1102 reg = cpu->cfg.mvendorid; 1103 ret = kvm_set_one_reg(cs, id, ®); 1104 if (ret != 0) { 1105 return ret; 1106 } 1107 1108 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1109 KVM_REG_RISCV_CONFIG_REG(marchid)); 1110 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1111 if (ret != 0) { 1112 return ret; 1113 } 1114 1115 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1116 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1117 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1118 1119 return ret; 1120 } 1121 1122 int kvm_arch_init_vcpu(CPUState *cs) 1123 { 1124 int ret = 0; 1125 RISCVCPU *cpu = RISCV_CPU(cs); 1126 1127 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1128 1129 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1130 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1131 if (ret != 0) { 1132 return ret; 1133 } 1134 } 1135 1136 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1137 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1138 1139 return ret; 1140 } 1141 1142 int kvm_arch_msi_data_to_gsi(uint32_t data) 1143 { 1144 abort(); 1145 } 1146 1147 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1148 int vector, PCIDevice *dev) 1149 { 1150 return 0; 1151 } 1152 1153 int kvm_arch_get_default_type(MachineState *ms) 1154 { 1155 return 0; 1156 } 1157 1158 int kvm_arch_init(MachineState *ms, KVMState *s) 1159 { 1160 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1161 return 0; 1162 } 1163 1164 int kvm_arch_irqchip_create(KVMState *s) 1165 { 1166 if (kvm_kernel_irqchip_split()) { 1167 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1168 exit(1); 1169 } 1170 1171 /* 1172 * We can create the VAIA using the newer device control API. 1173 */ 1174 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1175 } 1176 1177 int kvm_arch_process_async_events(CPUState *cs) 1178 { 1179 return 0; 1180 } 1181 1182 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1183 { 1184 } 1185 1186 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1187 { 1188 return MEMTXATTRS_UNSPECIFIED; 1189 } 1190 1191 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1192 { 1193 return true; 1194 } 1195 1196 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1197 { 1198 int ret = 0; 1199 unsigned char ch; 1200 switch (run->riscv_sbi.extension_id) { 1201 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1202 ch = run->riscv_sbi.args[0]; 1203 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1204 break; 1205 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1206 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1207 if (ret == sizeof(ch)) { 1208 run->riscv_sbi.ret[0] = ch; 1209 } else { 1210 run->riscv_sbi.ret[0] = -1; 1211 } 1212 ret = 0; 1213 break; 1214 default: 1215 qemu_log_mask(LOG_UNIMP, 1216 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1217 __func__, run->riscv_sbi.extension_id); 1218 ret = -1; 1219 break; 1220 } 1221 return ret; 1222 } 1223 1224 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1225 { 1226 int ret = 0; 1227 switch (run->exit_reason) { 1228 case KVM_EXIT_RISCV_SBI: 1229 ret = kvm_riscv_handle_sbi(cs, run); 1230 break; 1231 default: 1232 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1233 __func__, run->exit_reason); 1234 ret = -1; 1235 break; 1236 } 1237 return ret; 1238 } 1239 1240 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1241 { 1242 CPURISCVState *env = &cpu->env; 1243 int i; 1244 1245 if (!kvm_enabled()) { 1246 return; 1247 } 1248 for (i = 0; i < 32; i++) { 1249 env->gpr[i] = 0; 1250 } 1251 env->pc = cpu->env.kernel_addr; 1252 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1253 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1254 env->satp = 0; 1255 env->mie = 0; 1256 env->stvec = 0; 1257 env->sscratch = 0; 1258 env->sepc = 0; 1259 env->scause = 0; 1260 env->stval = 0; 1261 env->mip = 0; 1262 } 1263 1264 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1265 { 1266 int ret; 1267 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1268 1269 if (irq != IRQ_S_EXT) { 1270 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1271 abort(); 1272 } 1273 1274 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1275 if (ret < 0) { 1276 perror("Set irq failed"); 1277 abort(); 1278 } 1279 } 1280 1281 bool kvm_arch_cpu_check_are_resettable(void) 1282 { 1283 return true; 1284 } 1285 1286 static int aia_mode; 1287 1288 static const char *kvm_aia_mode_str(uint64_t mode) 1289 { 1290 switch (mode) { 1291 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1292 return "emul"; 1293 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1294 return "hwaccel"; 1295 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1296 default: 1297 return "auto"; 1298 }; 1299 } 1300 1301 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1302 { 1303 return g_strdup(kvm_aia_mode_str(aia_mode)); 1304 } 1305 1306 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1307 { 1308 if (!strcmp(val, "emul")) { 1309 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1310 } else if (!strcmp(val, "hwaccel")) { 1311 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1312 } else if (!strcmp(val, "auto")) { 1313 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1314 } else { 1315 error_setg(errp, "Invalid KVM AIA mode"); 1316 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1317 } 1318 } 1319 1320 void kvm_arch_accel_class_init(ObjectClass *oc) 1321 { 1322 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1323 riscv_set_kvm_aia); 1324 object_class_property_set_description(oc, "riscv-aia", 1325 "Set KVM AIA mode. Valid values are " 1326 "emul, hwaccel, and auto. Default " 1327 "is auto."); 1328 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1329 "auto"); 1330 } 1331 1332 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1333 uint64_t aia_irq_num, uint64_t aia_msi_num, 1334 uint64_t aplic_base, uint64_t imsic_base, 1335 uint64_t guest_num) 1336 { 1337 int ret, i; 1338 int aia_fd = -1; 1339 uint64_t default_aia_mode; 1340 uint64_t socket_count = riscv_socket_count(machine); 1341 uint64_t max_hart_per_socket = 0; 1342 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1343 uint64_t socket_bits, hart_bits, guest_bits; 1344 1345 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1346 1347 if (aia_fd < 0) { 1348 error_report("Unable to create in-kernel irqchip"); 1349 exit(1); 1350 } 1351 1352 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1353 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1354 &default_aia_mode, false, NULL); 1355 if (ret < 0) { 1356 error_report("KVM AIA: failed to get current KVM AIA mode"); 1357 exit(1); 1358 } 1359 qemu_log("KVM AIA: default mode is %s\n", 1360 kvm_aia_mode_str(default_aia_mode)); 1361 1362 if (default_aia_mode != aia_mode) { 1363 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1364 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1365 &aia_mode, true, NULL); 1366 if (ret < 0) 1367 warn_report("KVM AIA: failed to set KVM AIA mode"); 1368 else 1369 qemu_log("KVM AIA: set current mode to %s\n", 1370 kvm_aia_mode_str(aia_mode)); 1371 } 1372 1373 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1374 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1375 &aia_irq_num, true, NULL); 1376 if (ret < 0) { 1377 error_report("KVM AIA: failed to set number of input irq lines"); 1378 exit(1); 1379 } 1380 1381 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1382 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1383 &aia_msi_num, true, NULL); 1384 if (ret < 0) { 1385 error_report("KVM AIA: failed to set number of msi"); 1386 exit(1); 1387 } 1388 1389 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1390 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1391 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1392 &socket_bits, true, NULL); 1393 if (ret < 0) { 1394 error_report("KVM AIA: failed to set group_bits"); 1395 exit(1); 1396 } 1397 1398 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1399 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1400 &group_shift, true, NULL); 1401 if (ret < 0) { 1402 error_report("KVM AIA: failed to set group_shift"); 1403 exit(1); 1404 } 1405 1406 guest_bits = guest_num == 0 ? 0 : 1407 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1408 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1409 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1410 &guest_bits, true, NULL); 1411 if (ret < 0) { 1412 error_report("KVM AIA: failed to set guest_bits"); 1413 exit(1); 1414 } 1415 1416 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1417 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1418 &aplic_base, true, NULL); 1419 if (ret < 0) { 1420 error_report("KVM AIA: failed to set the base address of APLIC"); 1421 exit(1); 1422 } 1423 1424 for (socket = 0; socket < socket_count; socket++) { 1425 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1426 hart_count = riscv_socket_hart_count(machine, socket); 1427 base_hart = riscv_socket_first_hartid(machine, socket); 1428 1429 if (max_hart_per_socket < hart_count) { 1430 max_hart_per_socket = hart_count; 1431 } 1432 1433 for (i = 0; i < hart_count; i++) { 1434 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1435 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1436 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1437 &imsic_addr, true, NULL); 1438 if (ret < 0) { 1439 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1440 exit(1); 1441 } 1442 } 1443 } 1444 1445 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1446 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1447 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1448 &hart_bits, true, NULL); 1449 if (ret < 0) { 1450 error_report("KVM AIA: failed to set hart_bits"); 1451 exit(1); 1452 } 1453 1454 if (kvm_has_gsi_routing()) { 1455 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1456 /* KVM AIA only has one APLIC instance */ 1457 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1458 } 1459 kvm_gsi_routing_allowed = true; 1460 kvm_irqchip_commit_routes(kvm_state); 1461 } 1462 1463 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1464 KVM_DEV_RISCV_AIA_CTRL_INIT, 1465 NULL, true, NULL); 1466 if (ret < 0) { 1467 error_report("KVM AIA: initialized fail"); 1468 exit(1); 1469 } 1470 1471 kvm_msi_via_irqfd_allowed = true; 1472 } 1473 1474 static void kvm_cpu_instance_init(CPUState *cs) 1475 { 1476 Object *obj = OBJECT(RISCV_CPU(cs)); 1477 DeviceState *dev = DEVICE(obj); 1478 1479 riscv_init_kvm_registers(obj); 1480 1481 kvm_riscv_add_cpu_user_properties(obj); 1482 1483 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1484 /* Check if we have a specific KVM handler for the option */ 1485 if (object_property_find(obj, prop->name)) { 1486 continue; 1487 } 1488 qdev_property_add_static(dev, prop); 1489 } 1490 } 1491 1492 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1493 { 1494 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1495 1496 acc->cpu_instance_init = kvm_cpu_instance_init; 1497 } 1498 1499 static const TypeInfo kvm_cpu_accel_type_info = { 1500 .name = ACCEL_CPU_NAME("kvm"), 1501 1502 .parent = TYPE_ACCEL_CPU, 1503 .class_init = kvm_cpu_accel_class_init, 1504 .abstract = true, 1505 }; 1506 static void kvm_cpu_accel_register_types(void) 1507 { 1508 type_register_static(&kvm_cpu_accel_type_info); 1509 } 1510 type_init(kvm_cpu_accel_register_types); 1511 1512 static void riscv_host_cpu_init(Object *obj) 1513 { 1514 CPURISCVState *env = &RISCV_CPU(obj)->env; 1515 1516 #if defined(TARGET_RISCV32) 1517 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1518 #elif defined(TARGET_RISCV64) 1519 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1520 #endif 1521 } 1522 1523 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1524 { 1525 .name = TYPE_RISCV_CPU_HOST, 1526 .parent = TYPE_RISCV_CPU, 1527 .instance_init = riscv_host_cpu_init, 1528 } 1529 }; 1530 1531 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1532