1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 278 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 279 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 280 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 281 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 282 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 283 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 284 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 285 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 286 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 287 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 288 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 289 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 290 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 291 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 292 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 293 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 294 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 295 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 296 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 297 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 298 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 299 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 300 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 301 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 302 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 303 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 304 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 305 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 306 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 307 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 308 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 309 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 310 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 311 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 312 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 313 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 314 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 315 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 316 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 317 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 318 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 319 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 320 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 321 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 322 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 323 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 324 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 325 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 326 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 327 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 328 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 329 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 330 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 331 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 332 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 333 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 334 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 335 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 336 }; 337 338 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 339 { 340 return (void *)&cpu->cfg + kvmcfg->offset; 341 } 342 343 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 344 uint32_t val) 345 { 346 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 347 348 *ext_enabled = val; 349 } 350 351 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 352 KVMCPUConfig *multi_ext) 353 { 354 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 355 356 return *ext_enabled; 357 } 358 359 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 360 const char *name, 361 void *opaque, Error **errp) 362 { 363 KVMCPUConfig *multi_ext_cfg = opaque; 364 RISCVCPU *cpu = RISCV_CPU(obj); 365 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 366 367 visit_type_bool(v, name, &value, errp); 368 } 369 370 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 371 const char *name, 372 void *opaque, Error **errp) 373 { 374 KVMCPUConfig *multi_ext_cfg = opaque; 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 bool value, host_val; 377 378 if (!visit_type_bool(v, name, &value, errp)) { 379 return; 380 } 381 382 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 383 384 /* 385 * Ignore if the user is setting the same value 386 * as the host. 387 */ 388 if (value == host_val) { 389 return; 390 } 391 392 if (!multi_ext_cfg->supported) { 393 /* 394 * Error out if the user is trying to enable an 395 * extension that KVM doesn't support. Ignore 396 * option otherwise. 397 */ 398 if (value) { 399 error_setg(errp, "KVM does not support disabling extension %s", 400 multi_ext_cfg->name); 401 } 402 403 return; 404 } 405 406 multi_ext_cfg->user_set = true; 407 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 408 } 409 410 static KVMCPUConfig kvm_cbom_blocksize = { 411 .name = "cbom_blocksize", 412 .offset = CPU_CFG_OFFSET(cbom_blocksize), 413 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 414 }; 415 416 static KVMCPUConfig kvm_cboz_blocksize = { 417 .name = "cboz_blocksize", 418 .offset = CPU_CFG_OFFSET(cboz_blocksize), 419 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 420 }; 421 422 static KVMCPUConfig kvm_v_vlenb = { 423 .name = "vlenb", 424 .offset = CPU_CFG_OFFSET(vlenb), 425 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 426 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 427 }; 428 429 static KVMCPUConfig kvm_sbi_dbcn = { 430 .name = "sbi_dbcn", 431 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 432 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 433 }; 434 435 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 436 { 437 CPURISCVState *env = &cpu->env; 438 uint64_t id, reg; 439 int i, ret; 440 441 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 442 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 443 444 if (!multi_ext_cfg->user_set) { 445 continue; 446 } 447 448 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 449 multi_ext_cfg->kvm_reg_id); 450 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 451 ret = kvm_set_one_reg(cs, id, ®); 452 if (ret != 0) { 453 if (!reg && ret == -EINVAL) { 454 warn_report("KVM cannot disable extension %s", 455 multi_ext_cfg->name); 456 } else { 457 error_report("Unable to enable extension %s in KVM, error %d", 458 multi_ext_cfg->name, ret); 459 exit(EXIT_FAILURE); 460 } 461 } 462 } 463 } 464 465 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 466 const char *name, 467 void *opaque, Error **errp) 468 { 469 bool value = false; 470 471 visit_type_bool(v, name, &value, errp); 472 } 473 474 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 475 const char *name, 476 void *opaque, Error **errp) 477 { 478 const char *propname = opaque; 479 bool value; 480 481 if (!visit_type_bool(v, name, &value, errp)) { 482 return; 483 } 484 485 if (value) { 486 error_setg(errp, "'%s' is not available with KVM", 487 propname); 488 } 489 } 490 491 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 492 { 493 /* Check if KVM created the property already */ 494 if (object_property_find(obj, prop_name)) { 495 return; 496 } 497 498 /* 499 * Set the default to disabled for every extension 500 * unknown to KVM and error out if the user attempts 501 * to enable any of them. 502 */ 503 object_property_add(obj, prop_name, "bool", 504 cpu_get_cfg_unavailable, 505 cpu_set_cfg_unavailable, 506 NULL, (void *)prop_name); 507 } 508 509 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 510 const RISCVCPUMultiExtConfig *array) 511 { 512 const RISCVCPUMultiExtConfig *prop; 513 514 g_assert(array); 515 516 for (prop = array; prop && prop->name; prop++) { 517 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 518 } 519 } 520 521 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 522 { 523 int i; 524 525 riscv_add_satp_mode_properties(cpu_obj); 526 527 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 528 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 529 int bit = misa_cfg->offset; 530 531 misa_cfg->name = riscv_get_misa_ext_name(bit); 532 misa_cfg->description = riscv_get_misa_ext_description(bit); 533 534 object_property_add(cpu_obj, misa_cfg->name, "bool", 535 kvm_cpu_get_misa_ext_cfg, 536 kvm_cpu_set_misa_ext_cfg, 537 NULL, misa_cfg); 538 object_property_set_description(cpu_obj, misa_cfg->name, 539 misa_cfg->description); 540 } 541 542 for (i = 0; misa_bits[i] != 0; i++) { 543 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 544 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 545 } 546 547 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 548 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 549 550 object_property_add(cpu_obj, multi_cfg->name, "bool", 551 kvm_cpu_get_multi_ext_cfg, 552 kvm_cpu_set_multi_ext_cfg, 553 NULL, multi_cfg); 554 } 555 556 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 557 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 558 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 559 560 /* We don't have the needed KVM support for profiles */ 561 for (i = 0; riscv_profiles[i] != NULL; i++) { 562 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 563 } 564 } 565 566 static int kvm_riscv_get_regs_core(CPUState *cs) 567 { 568 int ret = 0; 569 int i; 570 target_ulong reg; 571 CPURISCVState *env = &RISCV_CPU(cs)->env; 572 573 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 574 if (ret) { 575 return ret; 576 } 577 env->pc = reg; 578 579 for (i = 1; i < 32; i++) { 580 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 581 ret = kvm_get_one_reg(cs, id, ®); 582 if (ret) { 583 return ret; 584 } 585 env->gpr[i] = reg; 586 } 587 588 return ret; 589 } 590 591 static int kvm_riscv_put_regs_core(CPUState *cs) 592 { 593 int ret = 0; 594 int i; 595 target_ulong reg; 596 CPURISCVState *env = &RISCV_CPU(cs)->env; 597 598 reg = env->pc; 599 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 600 if (ret) { 601 return ret; 602 } 603 604 for (i = 1; i < 32; i++) { 605 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 606 reg = env->gpr[i]; 607 ret = kvm_set_one_reg(cs, id, ®); 608 if (ret) { 609 return ret; 610 } 611 } 612 613 return ret; 614 } 615 616 static int kvm_riscv_get_regs_csr(CPUState *cs) 617 { 618 CPURISCVState *env = &RISCV_CPU(cs)->env; 619 620 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 621 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 622 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 623 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 624 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 625 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 626 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 627 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 628 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 629 630 return 0; 631 } 632 633 static int kvm_riscv_put_regs_csr(CPUState *cs) 634 { 635 CPURISCVState *env = &RISCV_CPU(cs)->env; 636 637 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 638 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 639 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 640 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 641 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 642 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 643 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 644 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 645 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 646 647 return 0; 648 } 649 650 static int kvm_riscv_get_regs_fp(CPUState *cs) 651 { 652 int ret = 0; 653 int i; 654 CPURISCVState *env = &RISCV_CPU(cs)->env; 655 656 if (riscv_has_ext(env, RVD)) { 657 uint64_t reg; 658 for (i = 0; i < 32; i++) { 659 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 660 if (ret) { 661 return ret; 662 } 663 env->fpr[i] = reg; 664 } 665 return ret; 666 } 667 668 if (riscv_has_ext(env, RVF)) { 669 uint32_t reg; 670 for (i = 0; i < 32; i++) { 671 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 672 if (ret) { 673 return ret; 674 } 675 env->fpr[i] = reg; 676 } 677 return ret; 678 } 679 680 return ret; 681 } 682 683 static int kvm_riscv_put_regs_fp(CPUState *cs) 684 { 685 int ret = 0; 686 int i; 687 CPURISCVState *env = &RISCV_CPU(cs)->env; 688 689 if (riscv_has_ext(env, RVD)) { 690 uint64_t reg; 691 for (i = 0; i < 32; i++) { 692 reg = env->fpr[i]; 693 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 694 if (ret) { 695 return ret; 696 } 697 } 698 return ret; 699 } 700 701 if (riscv_has_ext(env, RVF)) { 702 uint32_t reg; 703 for (i = 0; i < 32; i++) { 704 reg = env->fpr[i]; 705 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 706 if (ret) { 707 return ret; 708 } 709 } 710 return ret; 711 } 712 713 return ret; 714 } 715 716 static void kvm_riscv_get_regs_timer(CPUState *cs) 717 { 718 CPURISCVState *env = &RISCV_CPU(cs)->env; 719 720 if (env->kvm_timer_dirty) { 721 return; 722 } 723 724 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 725 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 726 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 727 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 728 729 env->kvm_timer_dirty = true; 730 } 731 732 static void kvm_riscv_put_regs_timer(CPUState *cs) 733 { 734 uint64_t reg; 735 CPURISCVState *env = &RISCV_CPU(cs)->env; 736 737 if (!env->kvm_timer_dirty) { 738 return; 739 } 740 741 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 742 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 743 744 /* 745 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 746 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 747 * doesn't matter that adaping in QEMU now. 748 * TODO If KVM changes, adapt here. 749 */ 750 if (env->kvm_timer_state) { 751 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 752 } 753 754 /* 755 * For now, migration will not work between Hosts with different timer 756 * frequency. Therefore, we should check whether they are the same here 757 * during the migration. 758 */ 759 if (migration_is_running()) { 760 KVM_RISCV_GET_TIMER(cs, frequency, reg); 761 if (reg != env->kvm_timer_frequency) { 762 error_report("Dst Hosts timer frequency != Src Hosts"); 763 } 764 } 765 766 env->kvm_timer_dirty = false; 767 } 768 769 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 770 { 771 uint64_t reg; 772 773 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 774 775 return reg; 776 } 777 778 static int kvm_riscv_get_regs_vector(CPUState *cs) 779 { 780 RISCVCPU *cpu = RISCV_CPU(cs); 781 CPURISCVState *env = &cpu->env; 782 target_ulong reg; 783 uint64_t vreg_id; 784 int vreg_idx, ret = 0; 785 786 if (!riscv_has_ext(env, RVV)) { 787 return 0; 788 } 789 790 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 791 if (ret) { 792 return ret; 793 } 794 env->vstart = reg; 795 796 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 797 if (ret) { 798 return ret; 799 } 800 env->vl = reg; 801 802 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 803 if (ret) { 804 return ret; 805 } 806 env->vtype = reg; 807 808 if (kvm_v_vlenb.supported) { 809 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 810 if (ret) { 811 return ret; 812 } 813 cpu->cfg.vlenb = reg; 814 815 for (int i = 0; i < 32; i++) { 816 /* 817 * vreg[] is statically allocated using RV_VLEN_MAX. 818 * Use it instead of vlenb to calculate vreg_idx for 819 * simplicity. 820 */ 821 vreg_idx = i * RV_VLEN_MAX / 64; 822 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 823 824 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 825 if (ret) { 826 return ret; 827 } 828 } 829 } 830 831 return 0; 832 } 833 834 static int kvm_riscv_put_regs_vector(CPUState *cs) 835 { 836 RISCVCPU *cpu = RISCV_CPU(cs); 837 CPURISCVState *env = &cpu->env; 838 target_ulong reg; 839 uint64_t vreg_id; 840 int vreg_idx, ret = 0; 841 842 if (!riscv_has_ext(env, RVV)) { 843 return 0; 844 } 845 846 reg = env->vstart; 847 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 848 if (ret) { 849 return ret; 850 } 851 852 reg = env->vl; 853 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 854 if (ret) { 855 return ret; 856 } 857 858 reg = env->vtype; 859 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 860 if (ret) { 861 return ret; 862 } 863 864 if (kvm_v_vlenb.supported) { 865 reg = cpu->cfg.vlenb; 866 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 867 868 for (int i = 0; i < 32; i++) { 869 /* 870 * vreg[] is statically allocated using RV_VLEN_MAX. 871 * Use it instead of vlenb to calculate vreg_idx for 872 * simplicity. 873 */ 874 vreg_idx = i * RV_VLEN_MAX / 64; 875 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 876 877 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 878 if (ret) { 879 return ret; 880 } 881 } 882 } 883 884 return ret; 885 } 886 887 typedef struct KVMScratchCPU { 888 int kvmfd; 889 int vmfd; 890 int cpufd; 891 } KVMScratchCPU; 892 893 /* 894 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 895 * from target/arm/kvm.c. 896 */ 897 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 898 { 899 int kvmfd = -1, vmfd = -1, cpufd = -1; 900 901 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 902 if (kvmfd < 0) { 903 goto err; 904 } 905 do { 906 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 907 } while (vmfd == -1 && errno == EINTR); 908 if (vmfd < 0) { 909 goto err; 910 } 911 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 912 if (cpufd < 0) { 913 goto err; 914 } 915 916 scratch->kvmfd = kvmfd; 917 scratch->vmfd = vmfd; 918 scratch->cpufd = cpufd; 919 920 return true; 921 922 err: 923 if (cpufd >= 0) { 924 close(cpufd); 925 } 926 if (vmfd >= 0) { 927 close(vmfd); 928 } 929 if (kvmfd >= 0) { 930 close(kvmfd); 931 } 932 933 return false; 934 } 935 936 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 937 { 938 close(scratch->cpufd); 939 close(scratch->vmfd); 940 close(scratch->kvmfd); 941 } 942 943 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 944 { 945 CPURISCVState *env = &cpu->env; 946 struct kvm_one_reg reg; 947 int ret; 948 949 reg.id = RISCV_CONFIG_REG(env, mvendorid); 950 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 951 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 952 if (ret != 0) { 953 error_report("Unable to retrieve mvendorid from host, error %d", ret); 954 } 955 956 reg.id = RISCV_CONFIG_REG(env, marchid); 957 reg.addr = (uint64_t)&cpu->cfg.marchid; 958 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 959 if (ret != 0) { 960 error_report("Unable to retrieve marchid from host, error %d", ret); 961 } 962 963 reg.id = RISCV_CONFIG_REG(env, mimpid); 964 reg.addr = (uint64_t)&cpu->cfg.mimpid; 965 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 966 if (ret != 0) { 967 error_report("Unable to retrieve mimpid from host, error %d", ret); 968 } 969 } 970 971 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 972 KVMScratchCPU *kvmcpu) 973 { 974 CPURISCVState *env = &cpu->env; 975 struct kvm_one_reg reg; 976 int ret; 977 978 reg.id = RISCV_CONFIG_REG(env, isa); 979 reg.addr = (uint64_t)&env->misa_ext_mask; 980 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 981 982 if (ret) { 983 error_report("Unable to fetch ISA register from KVM, " 984 "error %d", ret); 985 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 986 exit(EXIT_FAILURE); 987 } 988 989 env->misa_ext = env->misa_ext_mask; 990 } 991 992 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 993 KVMCPUConfig *cbomz_cfg) 994 { 995 CPURISCVState *env = &cpu->env; 996 struct kvm_one_reg reg; 997 int ret; 998 999 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1000 cbomz_cfg->kvm_reg_id); 1001 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 1002 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1003 if (ret != 0) { 1004 error_report("Unable to read KVM reg %s, error %d", 1005 cbomz_cfg->name, ret); 1006 exit(EXIT_FAILURE); 1007 } 1008 } 1009 1010 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1011 KVMScratchCPU *kvmcpu) 1012 { 1013 CPURISCVState *env = &cpu->env; 1014 uint64_t val; 1015 int i, ret; 1016 1017 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1018 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1019 struct kvm_one_reg reg; 1020 1021 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1022 multi_ext_cfg->kvm_reg_id); 1023 reg.addr = (uint64_t)&val; 1024 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1025 if (ret != 0) { 1026 if (errno == EINVAL) { 1027 /* Silently default to 'false' if KVM does not support it. */ 1028 multi_ext_cfg->supported = false; 1029 val = false; 1030 } else { 1031 error_report("Unable to read ISA_EXT KVM register %s: %s", 1032 multi_ext_cfg->name, strerror(errno)); 1033 exit(EXIT_FAILURE); 1034 } 1035 } else { 1036 multi_ext_cfg->supported = true; 1037 } 1038 1039 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1040 } 1041 1042 if (cpu->cfg.ext_zicbom) { 1043 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1044 } 1045 1046 if (cpu->cfg.ext_zicboz) { 1047 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1048 } 1049 } 1050 1051 static int uint64_cmp(const void *a, const void *b) 1052 { 1053 uint64_t val1 = *(const uint64_t *)a; 1054 uint64_t val2 = *(const uint64_t *)b; 1055 1056 if (val1 < val2) { 1057 return -1; 1058 } 1059 1060 if (val1 > val2) { 1061 return 1; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1068 KVMScratchCPU *kvmcpu, 1069 struct kvm_reg_list *reglist) 1070 { 1071 struct kvm_reg_list *reg_search; 1072 1073 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1074 sizeof(uint64_t), uint64_cmp); 1075 1076 if (reg_search) { 1077 kvm_sbi_dbcn.supported = true; 1078 } 1079 } 1080 1081 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1082 struct kvm_reg_list *reglist) 1083 { 1084 struct kvm_one_reg reg; 1085 struct kvm_reg_list *reg_search; 1086 uint64_t val; 1087 int ret; 1088 1089 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1090 sizeof(uint64_t), uint64_cmp); 1091 1092 if (reg_search) { 1093 reg.id = kvm_v_vlenb.kvm_reg_id; 1094 reg.addr = (uint64_t)&val; 1095 1096 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1097 if (ret != 0) { 1098 error_report("Unable to read vlenb register, error code: %d", 1099 errno); 1100 exit(EXIT_FAILURE); 1101 } 1102 1103 kvm_v_vlenb.supported = true; 1104 cpu->cfg.vlenb = val; 1105 } 1106 } 1107 1108 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1109 { 1110 KVMCPUConfig *multi_ext_cfg; 1111 struct kvm_one_reg reg; 1112 struct kvm_reg_list rl_struct; 1113 struct kvm_reg_list *reglist; 1114 uint64_t val, reg_id, *reg_search; 1115 int i, ret; 1116 1117 rl_struct.n = 0; 1118 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1119 1120 /* 1121 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1122 * (EINVAL). Use read_legacy() in this case. 1123 */ 1124 if (errno == EINVAL) { 1125 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1126 } else if (errno != E2BIG) { 1127 /* 1128 * E2BIG is an expected error message for the API since we 1129 * don't know the number of registers. The right amount will 1130 * be written in rl_struct.n. 1131 * 1132 * Error out if we get any other errno. 1133 */ 1134 error_report("Error when accessing get-reg-list: %s", 1135 strerror(errno)); 1136 exit(EXIT_FAILURE); 1137 } 1138 1139 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1140 rl_struct.n * sizeof(uint64_t)); 1141 reglist->n = rl_struct.n; 1142 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1143 if (ret) { 1144 error_report("Error when reading KVM_GET_REG_LIST: %s", 1145 strerror(errno)); 1146 exit(EXIT_FAILURE); 1147 } 1148 1149 /* sort reglist to use bsearch() */ 1150 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1151 1152 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1153 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1154 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1155 multi_ext_cfg->kvm_reg_id); 1156 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1157 sizeof(uint64_t), uint64_cmp); 1158 if (!reg_search) { 1159 continue; 1160 } 1161 1162 reg.id = reg_id; 1163 reg.addr = (uint64_t)&val; 1164 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1165 if (ret != 0) { 1166 error_report("Unable to read ISA_EXT KVM register %s: %s", 1167 multi_ext_cfg->name, strerror(errno)); 1168 exit(EXIT_FAILURE); 1169 } 1170 1171 multi_ext_cfg->supported = true; 1172 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1173 } 1174 1175 if (cpu->cfg.ext_zicbom) { 1176 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1177 } 1178 1179 if (cpu->cfg.ext_zicboz) { 1180 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1181 } 1182 1183 if (riscv_has_ext(&cpu->env, RVV)) { 1184 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1185 } 1186 1187 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1188 } 1189 1190 static void riscv_init_kvm_registers(Object *cpu_obj) 1191 { 1192 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1193 KVMScratchCPU kvmcpu; 1194 1195 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1196 return; 1197 } 1198 1199 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1200 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1201 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1202 1203 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1204 } 1205 1206 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1207 KVM_CAP_LAST_INFO 1208 }; 1209 1210 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1211 { 1212 int ret = 0; 1213 1214 ret = kvm_riscv_get_regs_core(cs); 1215 if (ret) { 1216 return ret; 1217 } 1218 1219 ret = kvm_riscv_get_regs_csr(cs); 1220 if (ret) { 1221 return ret; 1222 } 1223 1224 ret = kvm_riscv_get_regs_fp(cs); 1225 if (ret) { 1226 return ret; 1227 } 1228 1229 ret = kvm_riscv_get_regs_vector(cs); 1230 if (ret) { 1231 return ret; 1232 } 1233 1234 return ret; 1235 } 1236 1237 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1238 { 1239 if (cap_has_mp_state) { 1240 struct kvm_mp_state mp_state = { 1241 .mp_state = state 1242 }; 1243 1244 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1245 if (ret) { 1246 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1247 __func__, ret, strerror(-ret)); 1248 return -1; 1249 } 1250 } 1251 1252 return 0; 1253 } 1254 1255 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1256 { 1257 int ret = 0; 1258 1259 ret = kvm_riscv_put_regs_core(cs); 1260 if (ret) { 1261 return ret; 1262 } 1263 1264 ret = kvm_riscv_put_regs_csr(cs); 1265 if (ret) { 1266 return ret; 1267 } 1268 1269 ret = kvm_riscv_put_regs_fp(cs); 1270 if (ret) { 1271 return ret; 1272 } 1273 1274 ret = kvm_riscv_put_regs_vector(cs); 1275 if (ret) { 1276 return ret; 1277 } 1278 1279 if (KVM_PUT_RESET_STATE == level) { 1280 RISCVCPU *cpu = RISCV_CPU(cs); 1281 if (cs->cpu_index == 0) { 1282 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1283 } else { 1284 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1285 } 1286 if (ret) { 1287 return ret; 1288 } 1289 } 1290 1291 return ret; 1292 } 1293 1294 int kvm_arch_release_virq_post(int virq) 1295 { 1296 return 0; 1297 } 1298 1299 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1300 uint64_t address, uint32_t data, PCIDevice *dev) 1301 { 1302 return 0; 1303 } 1304 1305 int kvm_arch_destroy_vcpu(CPUState *cs) 1306 { 1307 return 0; 1308 } 1309 1310 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1311 { 1312 return cpu->cpu_index; 1313 } 1314 1315 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1316 RunState state) 1317 { 1318 CPUState *cs = opaque; 1319 1320 if (running) { 1321 kvm_riscv_put_regs_timer(cs); 1322 } else { 1323 kvm_riscv_get_regs_timer(cs); 1324 } 1325 } 1326 1327 void kvm_arch_init_irq_routing(KVMState *s) 1328 { 1329 } 1330 1331 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1332 { 1333 CPURISCVState *env = &cpu->env; 1334 target_ulong reg; 1335 uint64_t id; 1336 int ret; 1337 1338 id = RISCV_CONFIG_REG(env, mvendorid); 1339 /* 1340 * cfg.mvendorid is an uint32 but a target_ulong will 1341 * be written. Assign it to a target_ulong var to avoid 1342 * writing pieces of other cpu->cfg fields in the reg. 1343 */ 1344 reg = cpu->cfg.mvendorid; 1345 ret = kvm_set_one_reg(cs, id, ®); 1346 if (ret != 0) { 1347 return ret; 1348 } 1349 1350 id = RISCV_CONFIG_REG(env, marchid); 1351 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1352 if (ret != 0) { 1353 return ret; 1354 } 1355 1356 id = RISCV_CONFIG_REG(env, mimpid); 1357 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1358 1359 return ret; 1360 } 1361 1362 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1363 { 1364 target_ulong reg = 1; 1365 1366 if (!kvm_sbi_dbcn.supported) { 1367 return 0; 1368 } 1369 1370 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1371 } 1372 1373 int kvm_arch_init_vcpu(CPUState *cs) 1374 { 1375 int ret = 0; 1376 RISCVCPU *cpu = RISCV_CPU(cs); 1377 1378 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1379 1380 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1381 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1382 if (ret != 0) { 1383 return ret; 1384 } 1385 } 1386 1387 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1388 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1389 1390 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1391 1392 return ret; 1393 } 1394 1395 int kvm_arch_msi_data_to_gsi(uint32_t data) 1396 { 1397 abort(); 1398 } 1399 1400 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1401 int vector, PCIDevice *dev) 1402 { 1403 return 0; 1404 } 1405 1406 int kvm_arch_get_default_type(MachineState *ms) 1407 { 1408 return 0; 1409 } 1410 1411 int kvm_arch_init(MachineState *ms, KVMState *s) 1412 { 1413 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1414 return 0; 1415 } 1416 1417 int kvm_arch_irqchip_create(KVMState *s) 1418 { 1419 /* 1420 * We can create the VAIA using the newer device control API. 1421 */ 1422 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1423 } 1424 1425 int kvm_arch_process_async_events(CPUState *cs) 1426 { 1427 return 0; 1428 } 1429 1430 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1431 { 1432 } 1433 1434 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1435 { 1436 return MEMTXATTRS_UNSPECIFIED; 1437 } 1438 1439 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1440 { 1441 return true; 1442 } 1443 1444 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1445 { 1446 g_autofree uint8_t *buf = NULL; 1447 RISCVCPU *cpu = RISCV_CPU(cs); 1448 target_ulong num_bytes; 1449 uint64_t addr; 1450 unsigned char ch; 1451 int ret; 1452 1453 switch (run->riscv_sbi.function_id) { 1454 case SBI_EXT_DBCN_CONSOLE_READ: 1455 case SBI_EXT_DBCN_CONSOLE_WRITE: 1456 num_bytes = run->riscv_sbi.args[0]; 1457 1458 if (num_bytes == 0) { 1459 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1460 run->riscv_sbi.ret[1] = 0; 1461 break; 1462 } 1463 1464 addr = run->riscv_sbi.args[1]; 1465 1466 /* 1467 * Handle the case where a 32 bit CPU is running in a 1468 * 64 bit addressing env. 1469 */ 1470 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1471 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1472 } 1473 1474 buf = g_malloc0(num_bytes); 1475 1476 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1477 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1478 if (ret < 0) { 1479 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1480 "reading chardev"); 1481 exit(1); 1482 } 1483 1484 cpu_physical_memory_write(addr, buf, ret); 1485 } else { 1486 cpu_physical_memory_read(addr, buf, num_bytes); 1487 1488 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1489 if (ret < 0) { 1490 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1491 "writing chardev"); 1492 exit(1); 1493 } 1494 } 1495 1496 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1497 run->riscv_sbi.ret[1] = ret; 1498 break; 1499 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1500 ch = run->riscv_sbi.args[0]; 1501 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1502 1503 if (ret < 0) { 1504 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1505 "writing chardev"); 1506 exit(1); 1507 } 1508 1509 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1510 run->riscv_sbi.ret[1] = 0; 1511 break; 1512 default: 1513 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1514 } 1515 } 1516 1517 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1518 { 1519 int ret = 0; 1520 unsigned char ch; 1521 switch (run->riscv_sbi.extension_id) { 1522 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1523 ch = run->riscv_sbi.args[0]; 1524 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1525 break; 1526 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1527 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1528 if (ret == sizeof(ch)) { 1529 run->riscv_sbi.ret[0] = ch; 1530 } else { 1531 run->riscv_sbi.ret[0] = -1; 1532 } 1533 ret = 0; 1534 break; 1535 case SBI_EXT_DBCN: 1536 kvm_riscv_handle_sbi_dbcn(cs, run); 1537 break; 1538 default: 1539 qemu_log_mask(LOG_UNIMP, 1540 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1541 __func__, run->riscv_sbi.extension_id); 1542 ret = -1; 1543 break; 1544 } 1545 return ret; 1546 } 1547 1548 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1549 { 1550 target_ulong csr_num = run->riscv_csr.csr_num; 1551 target_ulong new_value = run->riscv_csr.new_value; 1552 target_ulong write_mask = run->riscv_csr.write_mask; 1553 int ret = 0; 1554 1555 switch (csr_num) { 1556 case CSR_SEED: 1557 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1558 break; 1559 default: 1560 qemu_log_mask(LOG_UNIMP, 1561 "%s: un-handled CSR EXIT for CSR %lx\n", 1562 __func__, csr_num); 1563 ret = -1; 1564 break; 1565 } 1566 1567 return ret; 1568 } 1569 1570 static bool kvm_riscv_handle_debug(CPUState *cs) 1571 { 1572 RISCVCPU *cpu = RISCV_CPU(cs); 1573 CPURISCVState *env = &cpu->env; 1574 1575 /* Ensure PC is synchronised */ 1576 kvm_cpu_synchronize_state(cs); 1577 1578 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1579 return true; 1580 } 1581 1582 return false; 1583 } 1584 1585 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1586 { 1587 int ret = 0; 1588 switch (run->exit_reason) { 1589 case KVM_EXIT_RISCV_SBI: 1590 ret = kvm_riscv_handle_sbi(cs, run); 1591 break; 1592 case KVM_EXIT_RISCV_CSR: 1593 ret = kvm_riscv_handle_csr(cs, run); 1594 break; 1595 case KVM_EXIT_DEBUG: 1596 if (kvm_riscv_handle_debug(cs)) { 1597 ret = EXCP_DEBUG; 1598 } 1599 break; 1600 default: 1601 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1602 __func__, run->exit_reason); 1603 ret = -1; 1604 break; 1605 } 1606 return ret; 1607 } 1608 1609 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1610 { 1611 CPURISCVState *env = &cpu->env; 1612 int i; 1613 1614 if (!kvm_enabled()) { 1615 return; 1616 } 1617 for (i = 0; i < 32; i++) { 1618 env->gpr[i] = 0; 1619 } 1620 env->pc = cpu->env.kernel_addr; 1621 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1622 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1623 env->satp = 0; 1624 env->mie = 0; 1625 env->stvec = 0; 1626 env->sscratch = 0; 1627 env->sepc = 0; 1628 env->scause = 0; 1629 env->stval = 0; 1630 env->mip = 0; 1631 } 1632 1633 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1634 { 1635 int ret; 1636 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1637 1638 if (irq != IRQ_S_EXT) { 1639 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1640 abort(); 1641 } 1642 1643 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1644 if (ret < 0) { 1645 perror("Set irq failed"); 1646 abort(); 1647 } 1648 } 1649 1650 static int aia_mode; 1651 1652 static const char *kvm_aia_mode_str(uint64_t mode) 1653 { 1654 switch (mode) { 1655 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1656 return "emul"; 1657 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1658 return "hwaccel"; 1659 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1660 default: 1661 return "auto"; 1662 }; 1663 } 1664 1665 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1666 { 1667 return g_strdup(kvm_aia_mode_str(aia_mode)); 1668 } 1669 1670 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1671 { 1672 if (!strcmp(val, "emul")) { 1673 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1674 } else if (!strcmp(val, "hwaccel")) { 1675 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1676 } else if (!strcmp(val, "auto")) { 1677 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1678 } else { 1679 error_setg(errp, "Invalid KVM AIA mode"); 1680 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1681 } 1682 } 1683 1684 void kvm_arch_accel_class_init(ObjectClass *oc) 1685 { 1686 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1687 riscv_set_kvm_aia); 1688 object_class_property_set_description(oc, "riscv-aia", 1689 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1690 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1691 "if the host supports it"); 1692 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1693 "auto"); 1694 } 1695 1696 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1697 uint64_t aia_irq_num, uint64_t aia_msi_num, 1698 uint64_t aplic_base, uint64_t imsic_base, 1699 uint64_t guest_num) 1700 { 1701 int ret, i; 1702 int aia_fd = -1; 1703 uint64_t default_aia_mode; 1704 uint64_t socket_count = riscv_socket_count(machine); 1705 uint64_t max_hart_per_socket = 0; 1706 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1707 uint64_t socket_bits, hart_bits, guest_bits; 1708 uint64_t max_group_id; 1709 1710 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1711 1712 if (aia_fd < 0) { 1713 error_report("Unable to create in-kernel irqchip"); 1714 exit(1); 1715 } 1716 1717 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1718 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1719 &default_aia_mode, false, NULL); 1720 if (ret < 0) { 1721 error_report("KVM AIA: failed to get current KVM AIA mode"); 1722 exit(1); 1723 } 1724 1725 if (default_aia_mode != aia_mode) { 1726 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1727 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1728 &aia_mode, true, NULL); 1729 if (ret < 0) { 1730 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1731 "default host mode '%s'", 1732 kvm_aia_mode_str(aia_mode), 1733 kvm_aia_mode_str(default_aia_mode)); 1734 1735 /* failed to change AIA mode, use default */ 1736 aia_mode = default_aia_mode; 1737 } 1738 } 1739 1740 /* 1741 * Skip APLIC creation in KVM if we're running split mode. 1742 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1743 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1744 * since KVM won't be using it. 1745 */ 1746 if (!kvm_kernel_irqchip_split()) { 1747 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1748 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1749 &aia_irq_num, true, NULL); 1750 if (ret < 0) { 1751 error_report("KVM AIA: failed to set number of input irq lines"); 1752 exit(1); 1753 } 1754 1755 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1756 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1757 &aplic_base, true, NULL); 1758 if (ret < 0) { 1759 error_report("KVM AIA: failed to set the base address of APLIC"); 1760 exit(1); 1761 } 1762 } 1763 1764 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1765 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1766 &aia_msi_num, true, NULL); 1767 if (ret < 0) { 1768 error_report("KVM AIA: failed to set number of msi"); 1769 exit(1); 1770 } 1771 1772 1773 if (socket_count > 1) { 1774 max_group_id = socket_count - 1; 1775 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1776 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1777 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1778 &socket_bits, true, NULL); 1779 if (ret < 0) { 1780 error_report("KVM AIA: failed to set group_bits"); 1781 exit(1); 1782 } 1783 1784 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1785 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1786 &group_shift, true, NULL); 1787 if (ret < 0) { 1788 error_report("KVM AIA: failed to set group_shift"); 1789 exit(1); 1790 } 1791 } 1792 1793 guest_bits = guest_num == 0 ? 0 : 1794 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1795 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1796 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1797 &guest_bits, true, NULL); 1798 if (ret < 0) { 1799 error_report("KVM AIA: failed to set guest_bits"); 1800 exit(1); 1801 } 1802 1803 for (socket = 0; socket < socket_count; socket++) { 1804 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1805 hart_count = riscv_socket_hart_count(machine, socket); 1806 base_hart = riscv_socket_first_hartid(machine, socket); 1807 1808 if (max_hart_per_socket < hart_count) { 1809 max_hart_per_socket = hart_count; 1810 } 1811 1812 for (i = 0; i < hart_count; i++) { 1813 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1814 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1815 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1816 &imsic_addr, true, NULL); 1817 if (ret < 0) { 1818 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1819 exit(1); 1820 } 1821 } 1822 } 1823 1824 1825 if (max_hart_per_socket > 1) { 1826 max_hart_per_socket--; 1827 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1828 } else { 1829 hart_bits = 0; 1830 } 1831 1832 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1833 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1834 &hart_bits, true, NULL); 1835 if (ret < 0) { 1836 error_report("KVM AIA: failed to set hart_bits"); 1837 exit(1); 1838 } 1839 1840 if (kvm_has_gsi_routing()) { 1841 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1842 /* KVM AIA only has one APLIC instance */ 1843 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1844 } 1845 kvm_gsi_routing_allowed = true; 1846 kvm_irqchip_commit_routes(kvm_state); 1847 } 1848 1849 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1850 KVM_DEV_RISCV_AIA_CTRL_INIT, 1851 NULL, true, NULL); 1852 if (ret < 0) { 1853 error_report("KVM AIA: initialized fail"); 1854 exit(1); 1855 } 1856 1857 kvm_msi_via_irqfd_allowed = true; 1858 } 1859 1860 static void kvm_cpu_instance_init(CPUState *cs) 1861 { 1862 Object *obj = OBJECT(RISCV_CPU(cs)); 1863 1864 riscv_init_kvm_registers(obj); 1865 1866 kvm_riscv_add_cpu_user_properties(obj); 1867 } 1868 1869 /* 1870 * We'll get here via the following path: 1871 * 1872 * riscv_cpu_realize() 1873 * -> cpu_exec_realizefn() 1874 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1875 */ 1876 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1877 { 1878 RISCVCPU *cpu = RISCV_CPU(cs); 1879 int ret; 1880 1881 if (riscv_has_ext(&cpu->env, RVV)) { 1882 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1883 if (ret) { 1884 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1885 strerrorname_np(errno)); 1886 return false; 1887 } 1888 } 1889 1890 return true; 1891 } 1892 1893 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1894 { 1895 CPURISCVState *env = &cpu->env; 1896 KVMScratchCPU kvmcpu; 1897 struct kvm_one_reg reg; 1898 uint64_t val; 1899 int ret; 1900 1901 /* short-circuit without spinning the scratch CPU */ 1902 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1903 !riscv_has_ext(env, RVV)) { 1904 return; 1905 } 1906 1907 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1908 error_setg(errp, "Unable to create scratch KVM cpu"); 1909 return; 1910 } 1911 1912 if (cpu->cfg.ext_zicbom && 1913 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1914 1915 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1916 kvm_cbom_blocksize.kvm_reg_id); 1917 reg.addr = (uint64_t)&val; 1918 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1919 if (ret != 0) { 1920 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1921 return; 1922 } 1923 1924 if (cpu->cfg.cbom_blocksize != val) { 1925 error_setg(errp, "Unable to set cbom_blocksize to a different " 1926 "value than the host (%lu)", val); 1927 return; 1928 } 1929 } 1930 1931 if (cpu->cfg.ext_zicboz && 1932 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1933 1934 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1935 kvm_cboz_blocksize.kvm_reg_id); 1936 reg.addr = (uint64_t)&val; 1937 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1938 if (ret != 0) { 1939 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1940 return; 1941 } 1942 1943 if (cpu->cfg.cboz_blocksize != val) { 1944 error_setg(errp, "Unable to set cboz_blocksize to a different " 1945 "value than the host (%lu)", val); 1946 return; 1947 } 1948 } 1949 1950 /* Users are setting vlen, not vlenb */ 1951 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1952 if (!kvm_v_vlenb.supported) { 1953 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1954 return; 1955 } 1956 1957 reg.id = kvm_v_vlenb.kvm_reg_id; 1958 reg.addr = (uint64_t)&val; 1959 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1960 if (ret != 0) { 1961 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1962 return; 1963 } 1964 1965 if (cpu->cfg.vlenb != val) { 1966 error_setg(errp, "Unable to set 'vlen' to a different " 1967 "value than the host (%lu)", val * 8); 1968 return; 1969 } 1970 } 1971 1972 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1973 } 1974 1975 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1976 { 1977 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1978 1979 acc->cpu_instance_init = kvm_cpu_instance_init; 1980 acc->cpu_target_realize = kvm_cpu_realize; 1981 } 1982 1983 static const TypeInfo kvm_cpu_accel_type_info = { 1984 .name = ACCEL_CPU_NAME("kvm"), 1985 1986 .parent = TYPE_ACCEL_CPU, 1987 .class_init = kvm_cpu_accel_class_init, 1988 .abstract = true, 1989 }; 1990 static void kvm_cpu_accel_register_types(void) 1991 { 1992 type_register_static(&kvm_cpu_accel_type_info); 1993 } 1994 type_init(kvm_cpu_accel_register_types); 1995 1996 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 1997 { 1998 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1999 2000 #if defined(TARGET_RISCV32) 2001 mcc->misa_mxl_max = MXL_RV32; 2002 #elif defined(TARGET_RISCV64) 2003 mcc->misa_mxl_max = MXL_RV64; 2004 #endif 2005 } 2006 2007 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 2008 { 2009 .name = TYPE_RISCV_CPU_HOST, 2010 .parent = TYPE_RISCV_CPU, 2011 .class_init = riscv_host_cpu_class_init, 2012 } 2013 }; 2014 2015 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2016 2017 static const uint32_t ebreak_insn = 0x00100073; 2018 static const uint16_t c_ebreak_insn = 0x9002; 2019 2020 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2021 { 2022 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2023 return -EINVAL; 2024 } 2025 2026 if ((bp->saved_insn & 0x3) == 0x3) { 2027 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2028 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2029 return -EINVAL; 2030 } 2031 } else { 2032 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2033 return -EINVAL; 2034 } 2035 } 2036 2037 return 0; 2038 } 2039 2040 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2041 { 2042 uint32_t ebreak; 2043 uint16_t c_ebreak; 2044 2045 if ((bp->saved_insn & 0x3) == 0x3) { 2046 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2047 ebreak != ebreak_insn || 2048 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2049 return -EINVAL; 2050 } 2051 } else { 2052 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2053 c_ebreak != c_ebreak_insn || 2054 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2055 return -EINVAL; 2056 } 2057 } 2058 2059 return 0; 2060 } 2061 2062 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2063 { 2064 /* TODO; To be implemented later. */ 2065 return -EINVAL; 2066 } 2067 2068 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2069 { 2070 /* TODO; To be implemented later. */ 2071 return -EINVAL; 2072 } 2073 2074 void kvm_arch_remove_all_hw_breakpoints(void) 2075 { 2076 /* TODO; To be implemented later. */ 2077 } 2078 2079 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2080 { 2081 if (kvm_sw_breakpoints_active(cs)) { 2082 dbg->control |= KVM_GUESTDBG_ENABLE; 2083 } 2084 } 2085