1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "system/system.h" 31 #include "system/kvm.h" 32 #include "system/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "accel/accel-cpu-target.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "system/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "system/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 #define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 | \ 62 type | idx) 63 64 #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 | \ 65 type | idx) 66 67 #if defined(TARGET_RISCV64) 68 #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) 69 #else 70 #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) 71 #endif 72 73 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 74 { 75 uint64_t size_ctz = __builtin_ctz(size_b); 76 77 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 78 } 79 80 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 81 uint64_t idx) 82 { 83 uint64_t id; 84 size_t size_b; 85 86 g_assert(idx < 32); 87 88 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 89 size_b = cpu->cfg.vlenb; 90 91 return kvm_encode_reg_size_id(id, size_b); 92 } 93 94 #define RISCV_CORE_REG(name) \ 95 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ 96 KVM_REG_RISCV_CORE_REG(name)) 97 98 #define RISCV_CSR_REG(name) \ 99 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ 100 KVM_REG_RISCV_CSR_REG(name)) 101 102 #define RISCV_CONFIG_REG(name) \ 103 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ 104 KVM_REG_RISCV_CONFIG_REG(name)) 105 106 #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ 107 KVM_REG_RISCV_TIMER_REG(name)) 108 109 #define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) 110 111 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) 112 113 #define RISCV_VECTOR_CSR_REG(name) \ 114 KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ 115 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 116 117 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 118 do { \ 119 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ 120 if (_ret) { \ 121 return _ret; \ 122 } \ 123 } while (0) 124 125 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 126 do { \ 127 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ 128 if (_ret) { \ 129 return _ret; \ 130 } \ 131 } while (0) 132 133 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 134 do { \ 135 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 136 if (ret) { \ 137 abort(); \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 142 do { \ 143 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 144 if (ret) { \ 145 abort(); \ 146 } \ 147 } while (0) 148 149 typedef struct KVMCPUConfig { 150 const char *name; 151 const char *description; 152 target_ulong offset; 153 uint64_t kvm_reg_id; 154 bool user_set; 155 bool supported; 156 } KVMCPUConfig; 157 158 #define KVM_MISA_CFG(_bit, _reg_id) \ 159 {.offset = _bit, .kvm_reg_id = _reg_id} 160 161 /* KVM ISA extensions */ 162 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 163 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 164 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 165 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 166 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 167 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 168 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 169 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 170 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 171 }; 172 173 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 174 const char *name, 175 void *opaque, Error **errp) 176 { 177 KVMCPUConfig *misa_ext_cfg = opaque; 178 target_ulong misa_bit = misa_ext_cfg->offset; 179 RISCVCPU *cpu = RISCV_CPU(obj); 180 CPURISCVState *env = &cpu->env; 181 bool value = env->misa_ext_mask & misa_bit; 182 183 visit_type_bool(v, name, &value, errp); 184 } 185 186 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 187 const char *name, 188 void *opaque, Error **errp) 189 { 190 KVMCPUConfig *misa_ext_cfg = opaque; 191 target_ulong misa_bit = misa_ext_cfg->offset; 192 RISCVCPU *cpu = RISCV_CPU(obj); 193 CPURISCVState *env = &cpu->env; 194 bool value, host_bit; 195 196 if (!visit_type_bool(v, name, &value, errp)) { 197 return; 198 } 199 200 host_bit = env->misa_ext_mask & misa_bit; 201 202 if (value == host_bit) { 203 return; 204 } 205 206 if (!value) { 207 misa_ext_cfg->user_set = true; 208 return; 209 } 210 211 /* 212 * Forbid users to enable extensions that aren't 213 * available in the hart. 214 */ 215 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 216 "enabled in the host", misa_ext_cfg->name); 217 } 218 219 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 220 { 221 CPURISCVState *env = &cpu->env; 222 uint64_t id, reg; 223 int i, ret; 224 225 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 226 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 227 target_ulong misa_bit = misa_cfg->offset; 228 229 if (!misa_cfg->user_set) { 230 continue; 231 } 232 233 /* If we're here we're going to disable the MISA bit */ 234 reg = 0; 235 id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 236 misa_cfg->kvm_reg_id); 237 ret = kvm_set_one_reg(cs, id, ®); 238 if (ret != 0) { 239 /* 240 * We're not checking for -EINVAL because if the bit is about 241 * to be disabled, it means that it was already enabled by 242 * KVM. We determined that by fetching the 'isa' register 243 * during init() time. Any error at this point is worth 244 * aborting. 245 */ 246 error_report("Unable to set KVM reg %s, error %d", 247 misa_cfg->name, ret); 248 exit(EXIT_FAILURE); 249 } 250 env->misa_ext &= ~misa_bit; 251 } 252 } 253 254 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 255 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 256 .kvm_reg_id = _reg_id} 257 258 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 259 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 260 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 261 KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), 262 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 263 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 264 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 265 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 266 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 267 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 268 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 269 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 270 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 271 KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), 272 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 273 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 274 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 275 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 276 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 277 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 278 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 279 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 280 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 281 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 282 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 283 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 284 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 285 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 286 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 287 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 288 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 289 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 290 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 291 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 292 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 293 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 294 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 295 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 296 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 297 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 298 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 299 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 300 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 301 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 302 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 303 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 304 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 305 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 306 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 307 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 308 KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), 309 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 310 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 311 KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), 312 KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), 313 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 314 KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), 315 KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), 316 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 317 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 318 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 319 KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), 320 }; 321 322 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 323 { 324 return (void *)&cpu->cfg + kvmcfg->offset; 325 } 326 327 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 328 uint32_t val) 329 { 330 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 331 332 *ext_enabled = val; 333 } 334 335 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 336 KVMCPUConfig *multi_ext) 337 { 338 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 339 340 return *ext_enabled; 341 } 342 343 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 344 const char *name, 345 void *opaque, Error **errp) 346 { 347 KVMCPUConfig *multi_ext_cfg = opaque; 348 RISCVCPU *cpu = RISCV_CPU(obj); 349 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 350 351 visit_type_bool(v, name, &value, errp); 352 } 353 354 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 355 const char *name, 356 void *opaque, Error **errp) 357 { 358 KVMCPUConfig *multi_ext_cfg = opaque; 359 RISCVCPU *cpu = RISCV_CPU(obj); 360 bool value, host_val; 361 362 if (!visit_type_bool(v, name, &value, errp)) { 363 return; 364 } 365 366 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 367 368 /* 369 * Ignore if the user is setting the same value 370 * as the host. 371 */ 372 if (value == host_val) { 373 return; 374 } 375 376 if (!multi_ext_cfg->supported) { 377 /* 378 * Error out if the user is trying to enable an 379 * extension that KVM doesn't support. Ignore 380 * option otherwise. 381 */ 382 if (value) { 383 error_setg(errp, "KVM does not support disabling extension %s", 384 multi_ext_cfg->name); 385 } 386 387 return; 388 } 389 390 multi_ext_cfg->user_set = true; 391 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 392 } 393 394 static KVMCPUConfig kvm_cbom_blocksize = { 395 .name = "cbom_blocksize", 396 .offset = CPU_CFG_OFFSET(cbom_blocksize), 397 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 398 }; 399 400 static KVMCPUConfig kvm_cboz_blocksize = { 401 .name = "cboz_blocksize", 402 .offset = CPU_CFG_OFFSET(cboz_blocksize), 403 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 404 }; 405 406 static KVMCPUConfig kvm_v_vlenb = { 407 .name = "vlenb", 408 .offset = CPU_CFG_OFFSET(vlenb), 409 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 410 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 411 }; 412 413 static KVMCPUConfig kvm_sbi_dbcn = { 414 .name = "sbi_dbcn", 415 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 416 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 417 }; 418 419 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 420 { 421 uint64_t id, reg; 422 int i, ret; 423 424 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 425 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 426 427 if (!multi_ext_cfg->user_set) { 428 continue; 429 } 430 431 id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 432 multi_ext_cfg->kvm_reg_id); 433 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 434 ret = kvm_set_one_reg(cs, id, ®); 435 if (ret != 0) { 436 if (!reg && ret == -EINVAL) { 437 warn_report("KVM cannot disable extension %s", 438 multi_ext_cfg->name); 439 } else { 440 error_report("Unable to enable extension %s in KVM, error %d", 441 multi_ext_cfg->name, ret); 442 exit(EXIT_FAILURE); 443 } 444 } 445 } 446 } 447 448 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 449 const char *name, 450 void *opaque, Error **errp) 451 { 452 bool value = false; 453 454 visit_type_bool(v, name, &value, errp); 455 } 456 457 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 458 const char *name, 459 void *opaque, Error **errp) 460 { 461 const char *propname = opaque; 462 bool value; 463 464 if (!visit_type_bool(v, name, &value, errp)) { 465 return; 466 } 467 468 if (value) { 469 error_setg(errp, "'%s' is not available with KVM", 470 propname); 471 } 472 } 473 474 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 475 { 476 /* Check if KVM created the property already */ 477 if (object_property_find(obj, prop_name)) { 478 return; 479 } 480 481 /* 482 * Set the default to disabled for every extension 483 * unknown to KVM and error out if the user attempts 484 * to enable any of them. 485 */ 486 object_property_add(obj, prop_name, "bool", 487 cpu_get_cfg_unavailable, 488 cpu_set_cfg_unavailable, 489 NULL, (void *)prop_name); 490 } 491 492 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 493 const RISCVCPUMultiExtConfig *array) 494 { 495 const RISCVCPUMultiExtConfig *prop; 496 497 g_assert(array); 498 499 for (prop = array; prop && prop->name; prop++) { 500 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 501 } 502 } 503 504 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 505 { 506 int i; 507 508 riscv_add_satp_mode_properties(cpu_obj); 509 510 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 511 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 512 int bit = misa_cfg->offset; 513 514 misa_cfg->name = riscv_get_misa_ext_name(bit); 515 misa_cfg->description = riscv_get_misa_ext_description(bit); 516 517 object_property_add(cpu_obj, misa_cfg->name, "bool", 518 kvm_cpu_get_misa_ext_cfg, 519 kvm_cpu_set_misa_ext_cfg, 520 NULL, misa_cfg); 521 object_property_set_description(cpu_obj, misa_cfg->name, 522 misa_cfg->description); 523 } 524 525 for (i = 0; misa_bits[i] != 0; i++) { 526 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 527 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 528 } 529 530 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 531 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 532 533 object_property_add(cpu_obj, multi_cfg->name, "bool", 534 kvm_cpu_get_multi_ext_cfg, 535 kvm_cpu_set_multi_ext_cfg, 536 NULL, multi_cfg); 537 } 538 539 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 540 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 541 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 542 543 /* We don't have the needed KVM support for profiles */ 544 for (i = 0; riscv_profiles[i] != NULL; i++) { 545 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 546 } 547 } 548 549 static int kvm_riscv_get_regs_core(CPUState *cs) 550 { 551 int ret = 0; 552 int i; 553 target_ulong reg; 554 CPURISCVState *env = &RISCV_CPU(cs)->env; 555 556 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); 557 if (ret) { 558 return ret; 559 } 560 env->pc = reg; 561 562 for (i = 1; i < 32; i++) { 563 uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); 564 ret = kvm_get_one_reg(cs, id, ®); 565 if (ret) { 566 return ret; 567 } 568 env->gpr[i] = reg; 569 } 570 571 return ret; 572 } 573 574 static int kvm_riscv_put_regs_core(CPUState *cs) 575 { 576 int ret = 0; 577 int i; 578 target_ulong reg; 579 CPURISCVState *env = &RISCV_CPU(cs)->env; 580 581 reg = env->pc; 582 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); 583 if (ret) { 584 return ret; 585 } 586 587 for (i = 1; i < 32; i++) { 588 uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); 589 reg = env->gpr[i]; 590 ret = kvm_set_one_reg(cs, id, ®); 591 if (ret) { 592 return ret; 593 } 594 } 595 596 return ret; 597 } 598 599 static int kvm_riscv_get_regs_csr(CPUState *cs) 600 { 601 CPURISCVState *env = &RISCV_CPU(cs)->env; 602 603 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 604 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 605 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 606 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 607 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 608 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 609 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 610 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 611 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 612 613 return 0; 614 } 615 616 static int kvm_riscv_put_regs_csr(CPUState *cs) 617 { 618 CPURISCVState *env = &RISCV_CPU(cs)->env; 619 620 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 621 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 622 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 623 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 624 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 625 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 626 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 627 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 628 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 629 630 return 0; 631 } 632 633 static void kvm_riscv_reset_regs_csr(CPURISCVState *env) 634 { 635 env->mstatus = 0; 636 env->mie = 0; 637 env->stvec = 0; 638 env->sscratch = 0; 639 env->sepc = 0; 640 env->scause = 0; 641 env->stval = 0; 642 env->mip = 0; 643 env->satp = 0; 644 } 645 646 static int kvm_riscv_get_regs_fp(CPUState *cs) 647 { 648 int ret = 0; 649 int i; 650 CPURISCVState *env = &RISCV_CPU(cs)->env; 651 652 if (riscv_has_ext(env, RVD)) { 653 uint64_t reg; 654 for (i = 0; i < 32; i++) { 655 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 656 if (ret) { 657 return ret; 658 } 659 env->fpr[i] = reg; 660 } 661 return ret; 662 } 663 664 if (riscv_has_ext(env, RVF)) { 665 uint32_t reg; 666 for (i = 0; i < 32; i++) { 667 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 668 if (ret) { 669 return ret; 670 } 671 env->fpr[i] = reg; 672 } 673 return ret; 674 } 675 676 return ret; 677 } 678 679 static int kvm_riscv_put_regs_fp(CPUState *cs) 680 { 681 int ret = 0; 682 int i; 683 CPURISCVState *env = &RISCV_CPU(cs)->env; 684 685 if (riscv_has_ext(env, RVD)) { 686 uint64_t reg; 687 for (i = 0; i < 32; i++) { 688 reg = env->fpr[i]; 689 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 690 if (ret) { 691 return ret; 692 } 693 } 694 return ret; 695 } 696 697 if (riscv_has_ext(env, RVF)) { 698 uint32_t reg; 699 for (i = 0; i < 32; i++) { 700 reg = env->fpr[i]; 701 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 702 if (ret) { 703 return ret; 704 } 705 } 706 return ret; 707 } 708 709 return ret; 710 } 711 712 static void kvm_riscv_get_regs_timer(CPUState *cs) 713 { 714 CPURISCVState *env = &RISCV_CPU(cs)->env; 715 716 if (env->kvm_timer_dirty) { 717 return; 718 } 719 720 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 721 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 722 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 723 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 724 725 env->kvm_timer_dirty = true; 726 } 727 728 static void kvm_riscv_put_regs_timer(CPUState *cs) 729 { 730 uint64_t reg; 731 CPURISCVState *env = &RISCV_CPU(cs)->env; 732 733 if (!env->kvm_timer_dirty) { 734 return; 735 } 736 737 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 738 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 739 740 /* 741 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 742 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 743 * doesn't matter that adaping in QEMU now. 744 * TODO If KVM changes, adapt here. 745 */ 746 if (env->kvm_timer_state) { 747 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 748 } 749 750 /* 751 * For now, migration will not work between Hosts with different timer 752 * frequency. Therefore, we should check whether they are the same here 753 * during the migration. 754 */ 755 if (migration_is_running()) { 756 KVM_RISCV_GET_TIMER(cs, frequency, reg); 757 if (reg != env->kvm_timer_frequency) { 758 error_report("Dst Hosts timer frequency != Src Hosts"); 759 } 760 } 761 762 env->kvm_timer_dirty = false; 763 } 764 765 uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) 766 { 767 uint64_t reg; 768 769 KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); 770 771 return reg; 772 } 773 774 static int kvm_riscv_get_regs_vector(CPUState *cs) 775 { 776 RISCVCPU *cpu = RISCV_CPU(cs); 777 CPURISCVState *env = &cpu->env; 778 target_ulong reg; 779 uint64_t vreg_id; 780 int vreg_idx, ret = 0; 781 782 if (!riscv_has_ext(env, RVV)) { 783 return 0; 784 } 785 786 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); 787 if (ret) { 788 return ret; 789 } 790 env->vstart = reg; 791 792 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); 793 if (ret) { 794 return ret; 795 } 796 env->vl = reg; 797 798 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); 799 if (ret) { 800 return ret; 801 } 802 env->vtype = reg; 803 804 if (kvm_v_vlenb.supported) { 805 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); 806 if (ret) { 807 return ret; 808 } 809 cpu->cfg.vlenb = reg; 810 811 for (int i = 0; i < 32; i++) { 812 /* 813 * vreg[] is statically allocated using RV_VLEN_MAX. 814 * Use it instead of vlenb to calculate vreg_idx for 815 * simplicity. 816 */ 817 vreg_idx = i * RV_VLEN_MAX / 64; 818 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 819 820 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 821 if (ret) { 822 return ret; 823 } 824 } 825 } 826 827 return 0; 828 } 829 830 static int kvm_riscv_put_regs_vector(CPUState *cs) 831 { 832 RISCVCPU *cpu = RISCV_CPU(cs); 833 CPURISCVState *env = &cpu->env; 834 target_ulong reg; 835 uint64_t vreg_id; 836 int vreg_idx, ret = 0; 837 838 if (!riscv_has_ext(env, RVV)) { 839 return 0; 840 } 841 842 reg = env->vstart; 843 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); 844 if (ret) { 845 return ret; 846 } 847 848 reg = env->vl; 849 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); 850 if (ret) { 851 return ret; 852 } 853 854 reg = env->vtype; 855 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); 856 if (ret) { 857 return ret; 858 } 859 860 if (kvm_v_vlenb.supported) { 861 reg = cpu->cfg.vlenb; 862 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); 863 864 for (int i = 0; i < 32; i++) { 865 /* 866 * vreg[] is statically allocated using RV_VLEN_MAX. 867 * Use it instead of vlenb to calculate vreg_idx for 868 * simplicity. 869 */ 870 vreg_idx = i * RV_VLEN_MAX / 64; 871 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 872 873 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 874 if (ret) { 875 return ret; 876 } 877 } 878 } 879 880 return ret; 881 } 882 883 typedef struct KVMScratchCPU { 884 int kvmfd; 885 int vmfd; 886 int cpufd; 887 } KVMScratchCPU; 888 889 /* 890 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 891 * from target/arm/kvm.c. 892 */ 893 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 894 { 895 int kvmfd = -1, vmfd = -1, cpufd = -1; 896 897 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 898 if (kvmfd < 0) { 899 goto err; 900 } 901 do { 902 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 903 } while (vmfd == -1 && errno == EINTR); 904 if (vmfd < 0) { 905 goto err; 906 } 907 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 908 if (cpufd < 0) { 909 goto err; 910 } 911 912 scratch->kvmfd = kvmfd; 913 scratch->vmfd = vmfd; 914 scratch->cpufd = cpufd; 915 916 return true; 917 918 err: 919 if (cpufd >= 0) { 920 close(cpufd); 921 } 922 if (vmfd >= 0) { 923 close(vmfd); 924 } 925 if (kvmfd >= 0) { 926 close(kvmfd); 927 } 928 929 return false; 930 } 931 932 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 933 { 934 close(scratch->cpufd); 935 close(scratch->vmfd); 936 close(scratch->kvmfd); 937 } 938 939 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 940 { 941 struct kvm_one_reg reg; 942 int ret; 943 944 reg.id = RISCV_CONFIG_REG(mvendorid); 945 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 946 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 947 if (ret != 0) { 948 error_report("Unable to retrieve mvendorid from host, error %d", ret); 949 } 950 951 reg.id = RISCV_CONFIG_REG(marchid); 952 reg.addr = (uint64_t)&cpu->cfg.marchid; 953 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 954 if (ret != 0) { 955 error_report("Unable to retrieve marchid from host, error %d", ret); 956 } 957 958 reg.id = RISCV_CONFIG_REG(mimpid); 959 reg.addr = (uint64_t)&cpu->cfg.mimpid; 960 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 961 if (ret != 0) { 962 error_report("Unable to retrieve mimpid from host, error %d", ret); 963 } 964 } 965 966 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 967 KVMScratchCPU *kvmcpu) 968 { 969 CPURISCVState *env = &cpu->env; 970 struct kvm_one_reg reg; 971 int ret; 972 973 reg.id = RISCV_CONFIG_REG(isa); 974 reg.addr = (uint64_t)&env->misa_ext_mask; 975 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 976 977 if (ret) { 978 error_report("Unable to fetch ISA register from KVM, " 979 "error %d", ret); 980 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 981 exit(EXIT_FAILURE); 982 } 983 984 env->misa_ext = env->misa_ext_mask; 985 } 986 987 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 988 KVMCPUConfig *cbomz_cfg) 989 { 990 struct kvm_one_reg reg; 991 int ret; 992 993 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 994 cbomz_cfg->kvm_reg_id); 995 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 996 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 997 if (ret != 0) { 998 error_report("Unable to read KVM reg %s, error %d", 999 cbomz_cfg->name, ret); 1000 exit(EXIT_FAILURE); 1001 } 1002 } 1003 1004 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1005 KVMScratchCPU *kvmcpu) 1006 { 1007 uint64_t val; 1008 int i, ret; 1009 1010 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1011 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1012 struct kvm_one_reg reg; 1013 1014 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 1015 multi_ext_cfg->kvm_reg_id); 1016 reg.addr = (uint64_t)&val; 1017 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1018 if (ret != 0) { 1019 if (errno == EINVAL) { 1020 /* Silently default to 'false' if KVM does not support it. */ 1021 multi_ext_cfg->supported = false; 1022 val = false; 1023 } else { 1024 error_report("Unable to read ISA_EXT KVM register %s: %s", 1025 multi_ext_cfg->name, strerror(errno)); 1026 exit(EXIT_FAILURE); 1027 } 1028 } else { 1029 multi_ext_cfg->supported = true; 1030 } 1031 1032 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1033 } 1034 1035 if (cpu->cfg.ext_zicbom) { 1036 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1037 } 1038 1039 if (cpu->cfg.ext_zicboz) { 1040 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1041 } 1042 } 1043 1044 static int uint64_cmp(const void *a, const void *b) 1045 { 1046 uint64_t val1 = *(const uint64_t *)a; 1047 uint64_t val2 = *(const uint64_t *)b; 1048 1049 if (val1 < val2) { 1050 return -1; 1051 } 1052 1053 if (val1 > val2) { 1054 return 1; 1055 } 1056 1057 return 0; 1058 } 1059 1060 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1061 struct kvm_reg_list *reglist) 1062 { 1063 struct kvm_reg_list *reg_search; 1064 1065 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1066 sizeof(uint64_t), uint64_cmp); 1067 1068 if (reg_search) { 1069 kvm_sbi_dbcn.supported = true; 1070 } 1071 } 1072 1073 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1074 struct kvm_reg_list *reglist) 1075 { 1076 struct kvm_one_reg reg; 1077 struct kvm_reg_list *reg_search; 1078 uint64_t val; 1079 int ret; 1080 1081 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1082 sizeof(uint64_t), uint64_cmp); 1083 1084 if (reg_search) { 1085 reg.id = kvm_v_vlenb.kvm_reg_id; 1086 reg.addr = (uint64_t)&val; 1087 1088 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1089 if (ret != 0) { 1090 error_report("Unable to read vlenb register, error code: %d", 1091 errno); 1092 exit(EXIT_FAILURE); 1093 } 1094 1095 kvm_v_vlenb.supported = true; 1096 cpu->cfg.vlenb = val; 1097 } 1098 } 1099 1100 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1101 { 1102 g_autofree struct kvm_reg_list *reglist = NULL; 1103 KVMCPUConfig *multi_ext_cfg; 1104 struct kvm_one_reg reg; 1105 struct kvm_reg_list rl_struct; 1106 uint64_t val, reg_id, *reg_search; 1107 int i, ret; 1108 1109 rl_struct.n = 0; 1110 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1111 1112 /* 1113 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1114 * (EINVAL). Use read_legacy() in this case. 1115 */ 1116 if (errno == EINVAL) { 1117 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1118 } else if (errno != E2BIG) { 1119 /* 1120 * E2BIG is an expected error message for the API since we 1121 * don't know the number of registers. The right amount will 1122 * be written in rl_struct.n. 1123 * 1124 * Error out if we get any other errno. 1125 */ 1126 error_report("Error when accessing get-reg-list: %s", 1127 strerror(errno)); 1128 exit(EXIT_FAILURE); 1129 } 1130 1131 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1132 rl_struct.n * sizeof(uint64_t)); 1133 reglist->n = rl_struct.n; 1134 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1135 if (ret) { 1136 error_report("Error when reading KVM_GET_REG_LIST: %s", 1137 strerror(errno)); 1138 exit(EXIT_FAILURE); 1139 } 1140 1141 /* sort reglist to use bsearch() */ 1142 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1143 1144 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1145 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1146 reg_id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, 1147 multi_ext_cfg->kvm_reg_id); 1148 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1149 sizeof(uint64_t), uint64_cmp); 1150 if (!reg_search) { 1151 continue; 1152 } 1153 1154 reg.id = reg_id; 1155 reg.addr = (uint64_t)&val; 1156 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1157 if (ret != 0) { 1158 error_report("Unable to read ISA_EXT KVM register %s: %s", 1159 multi_ext_cfg->name, strerror(errno)); 1160 exit(EXIT_FAILURE); 1161 } 1162 1163 multi_ext_cfg->supported = true; 1164 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1165 } 1166 1167 if (cpu->cfg.ext_zicbom) { 1168 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1169 } 1170 1171 if (cpu->cfg.ext_zicboz) { 1172 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1173 } 1174 1175 if (riscv_has_ext(&cpu->env, RVV)) { 1176 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1177 } 1178 1179 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); 1180 } 1181 1182 static void riscv_init_kvm_registers(Object *cpu_obj) 1183 { 1184 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1185 KVMScratchCPU kvmcpu; 1186 1187 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1188 return; 1189 } 1190 1191 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1192 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1193 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1194 1195 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1196 } 1197 1198 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1199 KVM_CAP_LAST_INFO 1200 }; 1201 1202 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1203 { 1204 int ret = 0; 1205 1206 ret = kvm_riscv_get_regs_core(cs); 1207 if (ret) { 1208 return ret; 1209 } 1210 1211 ret = kvm_riscv_get_regs_csr(cs); 1212 if (ret) { 1213 return ret; 1214 } 1215 1216 ret = kvm_riscv_get_regs_fp(cs); 1217 if (ret) { 1218 return ret; 1219 } 1220 1221 ret = kvm_riscv_get_regs_vector(cs); 1222 if (ret) { 1223 return ret; 1224 } 1225 1226 return ret; 1227 } 1228 1229 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1230 { 1231 if (cap_has_mp_state) { 1232 struct kvm_mp_state mp_state = { 1233 .mp_state = state 1234 }; 1235 1236 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1237 if (ret) { 1238 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1239 __func__, ret, strerror(-ret)); 1240 return -1; 1241 } 1242 } 1243 1244 return 0; 1245 } 1246 1247 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1248 { 1249 int ret = 0; 1250 1251 ret = kvm_riscv_put_regs_core(cs); 1252 if (ret) { 1253 return ret; 1254 } 1255 1256 ret = kvm_riscv_put_regs_csr(cs); 1257 if (ret) { 1258 return ret; 1259 } 1260 1261 ret = kvm_riscv_put_regs_fp(cs); 1262 if (ret) { 1263 return ret; 1264 } 1265 1266 ret = kvm_riscv_put_regs_vector(cs); 1267 if (ret) { 1268 return ret; 1269 } 1270 1271 if (KVM_PUT_RESET_STATE == level) { 1272 RISCVCPU *cpu = RISCV_CPU(cs); 1273 if (cs->cpu_index == 0) { 1274 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1275 } else { 1276 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1277 } 1278 if (ret) { 1279 return ret; 1280 } 1281 } 1282 1283 return ret; 1284 } 1285 1286 int kvm_arch_release_virq_post(int virq) 1287 { 1288 return 0; 1289 } 1290 1291 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1292 uint64_t address, uint32_t data, PCIDevice *dev) 1293 { 1294 return 0; 1295 } 1296 1297 int kvm_arch_destroy_vcpu(CPUState *cs) 1298 { 1299 return 0; 1300 } 1301 1302 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1303 { 1304 return cpu->cpu_index; 1305 } 1306 1307 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1308 RunState state) 1309 { 1310 CPUState *cs = opaque; 1311 1312 if (running) { 1313 kvm_riscv_put_regs_timer(cs); 1314 } else { 1315 kvm_riscv_get_regs_timer(cs); 1316 } 1317 } 1318 1319 void kvm_arch_init_irq_routing(KVMState *s) 1320 { 1321 } 1322 1323 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1324 { 1325 target_ulong reg; 1326 uint64_t id; 1327 int ret; 1328 1329 id = RISCV_CONFIG_REG(mvendorid); 1330 /* 1331 * cfg.mvendorid is an uint32 but a target_ulong will 1332 * be written. Assign it to a target_ulong var to avoid 1333 * writing pieces of other cpu->cfg fields in the reg. 1334 */ 1335 reg = cpu->cfg.mvendorid; 1336 ret = kvm_set_one_reg(cs, id, ®); 1337 if (ret != 0) { 1338 return ret; 1339 } 1340 1341 id = RISCV_CONFIG_REG(marchid); 1342 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1343 if (ret != 0) { 1344 return ret; 1345 } 1346 1347 id = RISCV_CONFIG_REG(mimpid); 1348 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1349 1350 return ret; 1351 } 1352 1353 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1354 { 1355 target_ulong reg = 1; 1356 1357 if (!kvm_sbi_dbcn.supported) { 1358 return 0; 1359 } 1360 1361 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1362 } 1363 1364 int kvm_arch_init_vcpu(CPUState *cs) 1365 { 1366 int ret = 0; 1367 RISCVCPU *cpu = RISCV_CPU(cs); 1368 1369 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1370 1371 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1372 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1373 if (ret != 0) { 1374 return ret; 1375 } 1376 } 1377 1378 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1379 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1380 1381 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1382 1383 return ret; 1384 } 1385 1386 int kvm_arch_msi_data_to_gsi(uint32_t data) 1387 { 1388 abort(); 1389 } 1390 1391 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1392 int vector, PCIDevice *dev) 1393 { 1394 return 0; 1395 } 1396 1397 int kvm_arch_get_default_type(MachineState *ms) 1398 { 1399 return 0; 1400 } 1401 1402 int kvm_arch_init(MachineState *ms, KVMState *s) 1403 { 1404 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1405 return 0; 1406 } 1407 1408 int kvm_arch_irqchip_create(KVMState *s) 1409 { 1410 /* 1411 * We can create the VAIA using the newer device control API. 1412 */ 1413 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1414 } 1415 1416 int kvm_arch_process_async_events(CPUState *cs) 1417 { 1418 return 0; 1419 } 1420 1421 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1422 { 1423 } 1424 1425 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1426 { 1427 return MEMTXATTRS_UNSPECIFIED; 1428 } 1429 1430 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1431 { 1432 return true; 1433 } 1434 1435 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1436 { 1437 g_autofree uint8_t *buf = NULL; 1438 RISCVCPU *cpu = RISCV_CPU(cs); 1439 target_ulong num_bytes; 1440 uint64_t addr; 1441 unsigned char ch; 1442 int ret; 1443 1444 switch (run->riscv_sbi.function_id) { 1445 case SBI_EXT_DBCN_CONSOLE_READ: 1446 case SBI_EXT_DBCN_CONSOLE_WRITE: 1447 num_bytes = run->riscv_sbi.args[0]; 1448 1449 if (num_bytes == 0) { 1450 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1451 run->riscv_sbi.ret[1] = 0; 1452 break; 1453 } 1454 1455 addr = run->riscv_sbi.args[1]; 1456 1457 /* 1458 * Handle the case where a 32 bit CPU is running in a 1459 * 64 bit addressing env. 1460 */ 1461 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1462 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1463 } 1464 1465 buf = g_malloc0(num_bytes); 1466 1467 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1468 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1469 if (ret < 0) { 1470 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1471 "reading chardev"); 1472 exit(1); 1473 } 1474 1475 cpu_physical_memory_write(addr, buf, ret); 1476 } else { 1477 cpu_physical_memory_read(addr, buf, num_bytes); 1478 1479 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1480 if (ret < 0) { 1481 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1482 "writing chardev"); 1483 exit(1); 1484 } 1485 } 1486 1487 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1488 run->riscv_sbi.ret[1] = ret; 1489 break; 1490 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1491 ch = run->riscv_sbi.args[0]; 1492 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1493 1494 if (ret < 0) { 1495 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1496 "writing chardev"); 1497 exit(1); 1498 } 1499 1500 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1501 run->riscv_sbi.ret[1] = 0; 1502 break; 1503 default: 1504 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1505 } 1506 } 1507 1508 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1509 { 1510 int ret = 0; 1511 unsigned char ch; 1512 switch (run->riscv_sbi.extension_id) { 1513 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1514 ch = run->riscv_sbi.args[0]; 1515 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1516 break; 1517 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1518 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1519 if (ret == sizeof(ch)) { 1520 run->riscv_sbi.ret[0] = ch; 1521 } else { 1522 run->riscv_sbi.ret[0] = -1; 1523 } 1524 ret = 0; 1525 break; 1526 case SBI_EXT_DBCN: 1527 kvm_riscv_handle_sbi_dbcn(cs, run); 1528 break; 1529 default: 1530 qemu_log_mask(LOG_UNIMP, 1531 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1532 __func__, run->riscv_sbi.extension_id); 1533 ret = -1; 1534 break; 1535 } 1536 return ret; 1537 } 1538 1539 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1540 { 1541 target_ulong csr_num = run->riscv_csr.csr_num; 1542 target_ulong new_value = run->riscv_csr.new_value; 1543 target_ulong write_mask = run->riscv_csr.write_mask; 1544 int ret = 0; 1545 1546 switch (csr_num) { 1547 case CSR_SEED: 1548 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1549 break; 1550 default: 1551 qemu_log_mask(LOG_UNIMP, 1552 "%s: un-handled CSR EXIT for CSR %lx\n", 1553 __func__, csr_num); 1554 ret = -1; 1555 break; 1556 } 1557 1558 return ret; 1559 } 1560 1561 static bool kvm_riscv_handle_debug(CPUState *cs) 1562 { 1563 RISCVCPU *cpu = RISCV_CPU(cs); 1564 CPURISCVState *env = &cpu->env; 1565 1566 /* Ensure PC is synchronised */ 1567 kvm_cpu_synchronize_state(cs); 1568 1569 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1570 return true; 1571 } 1572 1573 return false; 1574 } 1575 1576 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1577 { 1578 int ret = 0; 1579 switch (run->exit_reason) { 1580 case KVM_EXIT_RISCV_SBI: 1581 ret = kvm_riscv_handle_sbi(cs, run); 1582 break; 1583 case KVM_EXIT_RISCV_CSR: 1584 ret = kvm_riscv_handle_csr(cs, run); 1585 break; 1586 case KVM_EXIT_DEBUG: 1587 if (kvm_riscv_handle_debug(cs)) { 1588 ret = EXCP_DEBUG; 1589 } 1590 break; 1591 default: 1592 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1593 __func__, run->exit_reason); 1594 ret = -1; 1595 break; 1596 } 1597 return ret; 1598 } 1599 1600 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1601 { 1602 CPURISCVState *env = &cpu->env; 1603 int i; 1604 1605 for (i = 0; i < 32; i++) { 1606 env->gpr[i] = 0; 1607 } 1608 env->pc = cpu->env.kernel_addr; 1609 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1610 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1611 1612 kvm_riscv_reset_regs_csr(env); 1613 } 1614 1615 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1616 { 1617 int ret; 1618 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1619 1620 if (irq != IRQ_S_EXT) { 1621 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1622 abort(); 1623 } 1624 1625 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1626 if (ret < 0) { 1627 perror("Set irq failed"); 1628 abort(); 1629 } 1630 } 1631 1632 static int aia_mode; 1633 1634 static const char *kvm_aia_mode_str(uint64_t mode) 1635 { 1636 switch (mode) { 1637 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1638 return "emul"; 1639 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1640 return "hwaccel"; 1641 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1642 default: 1643 return "auto"; 1644 }; 1645 } 1646 1647 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1648 { 1649 return g_strdup(kvm_aia_mode_str(aia_mode)); 1650 } 1651 1652 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1653 { 1654 if (!strcmp(val, "emul")) { 1655 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1656 } else if (!strcmp(val, "hwaccel")) { 1657 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1658 } else if (!strcmp(val, "auto")) { 1659 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1660 } else { 1661 error_setg(errp, "Invalid KVM AIA mode"); 1662 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1663 } 1664 } 1665 1666 void kvm_arch_accel_class_init(ObjectClass *oc) 1667 { 1668 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1669 riscv_set_kvm_aia); 1670 object_class_property_set_description(oc, "riscv-aia", 1671 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1672 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1673 "if the host supports it"); 1674 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1675 "auto"); 1676 } 1677 1678 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1679 uint64_t aia_irq_num, uint64_t aia_msi_num, 1680 uint64_t aplic_base, uint64_t imsic_base, 1681 uint64_t guest_num) 1682 { 1683 int ret, i; 1684 int aia_fd = -1; 1685 uint64_t default_aia_mode; 1686 uint64_t socket_count = riscv_socket_count(machine); 1687 uint64_t max_hart_per_socket = 0; 1688 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1689 uint64_t socket_bits, hart_bits, guest_bits; 1690 uint64_t max_group_id; 1691 1692 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1693 1694 if (aia_fd < 0) { 1695 error_report("Unable to create in-kernel irqchip"); 1696 exit(1); 1697 } 1698 1699 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1700 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1701 &default_aia_mode, false, NULL); 1702 if (ret < 0) { 1703 error_report("KVM AIA: failed to get current KVM AIA mode"); 1704 exit(1); 1705 } 1706 1707 if (default_aia_mode != aia_mode) { 1708 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1709 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1710 &aia_mode, true, NULL); 1711 if (ret < 0) { 1712 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1713 "default host mode '%s'", 1714 kvm_aia_mode_str(aia_mode), 1715 kvm_aia_mode_str(default_aia_mode)); 1716 1717 /* failed to change AIA mode, use default */ 1718 aia_mode = default_aia_mode; 1719 } 1720 } 1721 1722 /* 1723 * Skip APLIC creation in KVM if we're running split mode. 1724 * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS 1725 * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC 1726 * since KVM won't be using it. 1727 */ 1728 if (!kvm_kernel_irqchip_split()) { 1729 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1730 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1731 &aia_irq_num, true, NULL); 1732 if (ret < 0) { 1733 error_report("KVM AIA: failed to set number of input irq lines"); 1734 exit(1); 1735 } 1736 1737 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1738 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1739 &aplic_base, true, NULL); 1740 if (ret < 0) { 1741 error_report("KVM AIA: failed to set the base address of APLIC"); 1742 exit(1); 1743 } 1744 } 1745 1746 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1747 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1748 &aia_msi_num, true, NULL); 1749 if (ret < 0) { 1750 error_report("KVM AIA: failed to set number of msi"); 1751 exit(1); 1752 } 1753 1754 1755 if (socket_count > 1) { 1756 max_group_id = socket_count - 1; 1757 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1758 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1759 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1760 &socket_bits, true, NULL); 1761 if (ret < 0) { 1762 error_report("KVM AIA: failed to set group_bits"); 1763 exit(1); 1764 } 1765 1766 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1767 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1768 &group_shift, true, NULL); 1769 if (ret < 0) { 1770 error_report("KVM AIA: failed to set group_shift"); 1771 exit(1); 1772 } 1773 } 1774 1775 guest_bits = guest_num == 0 ? 0 : 1776 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1777 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1778 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1779 &guest_bits, true, NULL); 1780 if (ret < 0) { 1781 error_report("KVM AIA: failed to set guest_bits"); 1782 exit(1); 1783 } 1784 1785 for (socket = 0; socket < socket_count; socket++) { 1786 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1787 hart_count = riscv_socket_hart_count(machine, socket); 1788 base_hart = riscv_socket_first_hartid(machine, socket); 1789 1790 if (max_hart_per_socket < hart_count) { 1791 max_hart_per_socket = hart_count; 1792 } 1793 1794 for (i = 0; i < hart_count; i++) { 1795 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1796 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1797 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1798 &imsic_addr, true, NULL); 1799 if (ret < 0) { 1800 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1801 exit(1); 1802 } 1803 } 1804 } 1805 1806 1807 if (max_hart_per_socket > 1) { 1808 max_hart_per_socket--; 1809 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1810 } else { 1811 hart_bits = 0; 1812 } 1813 1814 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1815 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1816 &hart_bits, true, NULL); 1817 if (ret < 0) { 1818 error_report("KVM AIA: failed to set hart_bits"); 1819 exit(1); 1820 } 1821 1822 if (kvm_has_gsi_routing()) { 1823 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1824 /* KVM AIA only has one APLIC instance */ 1825 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1826 } 1827 kvm_gsi_routing_allowed = true; 1828 kvm_irqchip_commit_routes(kvm_state); 1829 } 1830 1831 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1832 KVM_DEV_RISCV_AIA_CTRL_INIT, 1833 NULL, true, NULL); 1834 if (ret < 0) { 1835 error_report("KVM AIA: initialized fail"); 1836 exit(1); 1837 } 1838 1839 kvm_msi_via_irqfd_allowed = true; 1840 } 1841 1842 static void kvm_cpu_instance_init(CPUState *cs) 1843 { 1844 Object *obj = OBJECT(RISCV_CPU(cs)); 1845 1846 riscv_init_kvm_registers(obj); 1847 1848 kvm_riscv_add_cpu_user_properties(obj); 1849 } 1850 1851 /* 1852 * We'll get here via the following path: 1853 * 1854 * riscv_cpu_realize() 1855 * -> cpu_exec_realizefn() 1856 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1857 */ 1858 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1859 { 1860 RISCVCPU *cpu = RISCV_CPU(cs); 1861 int ret; 1862 1863 if (riscv_has_ext(&cpu->env, RVV)) { 1864 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1865 if (ret) { 1866 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1867 strerrorname_np(errno)); 1868 return false; 1869 } 1870 } 1871 1872 return true; 1873 } 1874 1875 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1876 { 1877 CPURISCVState *env = &cpu->env; 1878 KVMScratchCPU kvmcpu; 1879 struct kvm_one_reg reg; 1880 uint64_t val; 1881 int ret; 1882 1883 /* short-circuit without spinning the scratch CPU */ 1884 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1885 !riscv_has_ext(env, RVV)) { 1886 return; 1887 } 1888 1889 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1890 error_setg(errp, "Unable to create scratch KVM cpu"); 1891 return; 1892 } 1893 1894 if (cpu->cfg.ext_zicbom && 1895 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1896 1897 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 1898 kvm_cbom_blocksize.kvm_reg_id); 1899 reg.addr = (uint64_t)&val; 1900 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1901 if (ret != 0) { 1902 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1903 return; 1904 } 1905 1906 if (cpu->cfg.cbom_blocksize != val) { 1907 error_setg(errp, "Unable to set cbom_blocksize to a different " 1908 "value than the host (%lu)", val); 1909 return; 1910 } 1911 } 1912 1913 if (cpu->cfg.ext_zicboz && 1914 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1915 1916 reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, 1917 kvm_cboz_blocksize.kvm_reg_id); 1918 reg.addr = (uint64_t)&val; 1919 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1920 if (ret != 0) { 1921 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1922 return; 1923 } 1924 1925 if (cpu->cfg.cboz_blocksize != val) { 1926 error_setg(errp, "Unable to set cboz_blocksize to a different " 1927 "value than the host (%lu)", val); 1928 return; 1929 } 1930 } 1931 1932 /* Users are setting vlen, not vlenb */ 1933 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1934 if (!kvm_v_vlenb.supported) { 1935 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1936 return; 1937 } 1938 1939 reg.id = kvm_v_vlenb.kvm_reg_id; 1940 reg.addr = (uint64_t)&val; 1941 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1942 if (ret != 0) { 1943 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1944 return; 1945 } 1946 1947 if (cpu->cfg.vlenb != val) { 1948 error_setg(errp, "Unable to set 'vlen' to a different " 1949 "value than the host (%lu)", val * 8); 1950 return; 1951 } 1952 } 1953 1954 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1955 } 1956 1957 static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data) 1958 { 1959 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1960 1961 acc->cpu_instance_init = kvm_cpu_instance_init; 1962 acc->cpu_target_realize = kvm_cpu_realize; 1963 } 1964 1965 static const TypeInfo kvm_cpu_accel_type_info = { 1966 .name = ACCEL_CPU_NAME("kvm"), 1967 1968 .parent = TYPE_ACCEL_CPU, 1969 .class_init = kvm_cpu_accel_class_init, 1970 .abstract = true, 1971 }; 1972 static void kvm_cpu_accel_register_types(void) 1973 { 1974 type_register_static(&kvm_cpu_accel_type_info); 1975 } 1976 type_init(kvm_cpu_accel_register_types); 1977 1978 static void riscv_host_cpu_class_init(ObjectClass *c, const void *data) 1979 { 1980 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1981 1982 #if defined(TARGET_RISCV32) 1983 mcc->misa_mxl_max = MXL_RV32; 1984 #elif defined(TARGET_RISCV64) 1985 mcc->misa_mxl_max = MXL_RV64; 1986 #endif 1987 } 1988 1989 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1990 { 1991 .name = TYPE_RISCV_CPU_HOST, 1992 .parent = TYPE_RISCV_CPU, 1993 .class_init = riscv_host_cpu_class_init, 1994 } 1995 }; 1996 1997 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1998 1999 static const uint32_t ebreak_insn = 0x00100073; 2000 static const uint16_t c_ebreak_insn = 0x9002; 2001 2002 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2003 { 2004 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2005 return -EINVAL; 2006 } 2007 2008 if ((bp->saved_insn & 0x3) == 0x3) { 2009 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2010 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2011 return -EINVAL; 2012 } 2013 } else { 2014 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2015 return -EINVAL; 2016 } 2017 } 2018 2019 return 0; 2020 } 2021 2022 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2023 { 2024 uint32_t ebreak; 2025 uint16_t c_ebreak; 2026 2027 if ((bp->saved_insn & 0x3) == 0x3) { 2028 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2029 ebreak != ebreak_insn || 2030 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2031 return -EINVAL; 2032 } 2033 } else { 2034 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2035 c_ebreak != c_ebreak_insn || 2036 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2037 return -EINVAL; 2038 } 2039 } 2040 2041 return 0; 2042 } 2043 2044 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2045 { 2046 /* TODO; To be implemented later. */ 2047 return -EINVAL; 2048 } 2049 2050 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2051 { 2052 /* TODO; To be implemented later. */ 2053 return -EINVAL; 2054 } 2055 2056 void kvm_arch_remove_all_hw_breakpoints(void) 2057 { 2058 /* TODO; To be implemented later. */ 2059 } 2060 2061 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2062 { 2063 if (kvm_sw_breakpoints_active(cs)) { 2064 dbg->control |= KVM_GUESTDBG_ENABLE; 2065 } 2066 } 2067