1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/migration.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 #define RISCV_CORE_REG(env, name) \ 90 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 91 KVM_REG_RISCV_CORE_REG(name)) 92 93 #define RISCV_CSR_REG(env, name) \ 94 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 95 KVM_REG_RISCV_CSR_REG(name)) 96 97 #define RISCV_CONFIG_REG(env, name) \ 98 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 99 KVM_REG_RISCV_CONFIG_REG(name)) 100 101 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 102 KVM_REG_RISCV_TIMER_REG(name)) 103 104 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 105 106 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 107 108 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 109 do { \ 110 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 111 if (_ret) { \ 112 return _ret; \ 113 } \ 114 } while (0) 115 116 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 117 do { \ 118 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 119 if (_ret) { \ 120 return _ret; \ 121 } \ 122 } while (0) 123 124 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 125 do { \ 126 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 127 if (ret) { \ 128 abort(); \ 129 } \ 130 } while (0) 131 132 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 133 do { \ 134 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 135 if (ret) { \ 136 abort(); \ 137 } \ 138 } while (0) 139 140 typedef struct KVMCPUConfig { 141 const char *name; 142 const char *description; 143 target_ulong offset; 144 int kvm_reg_id; 145 bool user_set; 146 bool supported; 147 } KVMCPUConfig; 148 149 #define KVM_MISA_CFG(_bit, _reg_id) \ 150 {.offset = _bit, .kvm_reg_id = _reg_id} 151 152 /* KVM ISA extensions */ 153 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 154 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 155 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 156 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 157 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 158 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 159 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 160 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 161 }; 162 163 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 164 const char *name, 165 void *opaque, Error **errp) 166 { 167 KVMCPUConfig *misa_ext_cfg = opaque; 168 target_ulong misa_bit = misa_ext_cfg->offset; 169 RISCVCPU *cpu = RISCV_CPU(obj); 170 CPURISCVState *env = &cpu->env; 171 bool value = env->misa_ext_mask & misa_bit; 172 173 visit_type_bool(v, name, &value, errp); 174 } 175 176 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 177 const char *name, 178 void *opaque, Error **errp) 179 { 180 KVMCPUConfig *misa_ext_cfg = opaque; 181 target_ulong misa_bit = misa_ext_cfg->offset; 182 RISCVCPU *cpu = RISCV_CPU(obj); 183 CPURISCVState *env = &cpu->env; 184 bool value, host_bit; 185 186 if (!visit_type_bool(v, name, &value, errp)) { 187 return; 188 } 189 190 host_bit = env->misa_ext_mask & misa_bit; 191 192 if (value == host_bit) { 193 return; 194 } 195 196 if (!value) { 197 misa_ext_cfg->user_set = true; 198 return; 199 } 200 201 /* 202 * Forbid users to enable extensions that aren't 203 * available in the hart. 204 */ 205 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 206 "enabled in the host", misa_ext_cfg->name); 207 } 208 209 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 210 { 211 CPURISCVState *env = &cpu->env; 212 uint64_t id, reg; 213 int i, ret; 214 215 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 216 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 217 target_ulong misa_bit = misa_cfg->offset; 218 219 if (!misa_cfg->user_set) { 220 continue; 221 } 222 223 /* If we're here we're going to disable the MISA bit */ 224 reg = 0; 225 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 226 misa_cfg->kvm_reg_id); 227 ret = kvm_set_one_reg(cs, id, ®); 228 if (ret != 0) { 229 /* 230 * We're not checking for -EINVAL because if the bit is about 231 * to be disabled, it means that it was already enabled by 232 * KVM. We determined that by fetching the 'isa' register 233 * during init() time. Any error at this point is worth 234 * aborting. 235 */ 236 error_report("Unable to set KVM reg %s, error %d", 237 misa_cfg->name, ret); 238 exit(EXIT_FAILURE); 239 } 240 env->misa_ext &= ~misa_bit; 241 } 242 } 243 244 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 245 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 246 .kvm_reg_id = _reg_id} 247 248 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 249 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 250 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 251 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 252 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 253 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 254 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 255 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 256 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 257 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 258 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 259 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 260 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 261 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 262 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 263 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 264 }; 265 266 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 267 { 268 return (void *)&cpu->cfg + kvmcfg->offset; 269 } 270 271 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 272 uint32_t val) 273 { 274 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 275 276 *ext_enabled = val; 277 } 278 279 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 280 KVMCPUConfig *multi_ext) 281 { 282 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 283 284 return *ext_enabled; 285 } 286 287 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 288 const char *name, 289 void *opaque, Error **errp) 290 { 291 KVMCPUConfig *multi_ext_cfg = opaque; 292 RISCVCPU *cpu = RISCV_CPU(obj); 293 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 294 295 visit_type_bool(v, name, &value, errp); 296 } 297 298 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 299 const char *name, 300 void *opaque, Error **errp) 301 { 302 KVMCPUConfig *multi_ext_cfg = opaque; 303 RISCVCPU *cpu = RISCV_CPU(obj); 304 bool value, host_val; 305 306 if (!visit_type_bool(v, name, &value, errp)) { 307 return; 308 } 309 310 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 311 312 /* 313 * Ignore if the user is setting the same value 314 * as the host. 315 */ 316 if (value == host_val) { 317 return; 318 } 319 320 if (!multi_ext_cfg->supported) { 321 /* 322 * Error out if the user is trying to enable an 323 * extension that KVM doesn't support. Ignore 324 * option otherwise. 325 */ 326 if (value) { 327 error_setg(errp, "KVM does not support disabling extension %s", 328 multi_ext_cfg->name); 329 } 330 331 return; 332 } 333 334 multi_ext_cfg->user_set = true; 335 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 336 } 337 338 static KVMCPUConfig kvm_cbom_blocksize = { 339 .name = "cbom_blocksize", 340 .offset = CPU_CFG_OFFSET(cbom_blocksize), 341 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 342 }; 343 344 static KVMCPUConfig kvm_cboz_blocksize = { 345 .name = "cboz_blocksize", 346 .offset = CPU_CFG_OFFSET(cboz_blocksize), 347 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 348 }; 349 350 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 351 const char *name, 352 void *opaque, Error **errp) 353 { 354 KVMCPUConfig *cbomz_cfg = opaque; 355 RISCVCPU *cpu = RISCV_CPU(obj); 356 uint16_t value, *host_val; 357 358 if (!visit_type_uint16(v, name, &value, errp)) { 359 return; 360 } 361 362 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 363 364 if (value != *host_val) { 365 error_report("Unable to set %s to a different value than " 366 "the host (%u)", 367 cbomz_cfg->name, *host_val); 368 exit(EXIT_FAILURE); 369 } 370 371 cbomz_cfg->user_set = true; 372 } 373 374 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 375 { 376 CPURISCVState *env = &cpu->env; 377 uint64_t id, reg; 378 int i, ret; 379 380 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 381 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 382 383 if (!multi_ext_cfg->user_set) { 384 continue; 385 } 386 387 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 388 multi_ext_cfg->kvm_reg_id); 389 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 390 ret = kvm_set_one_reg(cs, id, ®); 391 if (ret != 0) { 392 error_report("Unable to %s extension %s in KVM, error %d", 393 reg ? "enable" : "disable", 394 multi_ext_cfg->name, ret); 395 exit(EXIT_FAILURE); 396 } 397 } 398 } 399 400 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 401 const char *name, 402 void *opaque, Error **errp) 403 { 404 bool value = false; 405 406 visit_type_bool(v, name, &value, errp); 407 } 408 409 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 410 const char *name, 411 void *opaque, Error **errp) 412 { 413 const char *propname = opaque; 414 bool value; 415 416 if (!visit_type_bool(v, name, &value, errp)) { 417 return; 418 } 419 420 if (value) { 421 error_setg(errp, "'%s' is not available with KVM", 422 propname); 423 } 424 } 425 426 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 427 { 428 /* Check if KVM created the property already */ 429 if (object_property_find(obj, prop_name)) { 430 return; 431 } 432 433 /* 434 * Set the default to disabled for every extension 435 * unknown to KVM and error out if the user attempts 436 * to enable any of them. 437 */ 438 object_property_add(obj, prop_name, "bool", 439 cpu_get_cfg_unavailable, 440 cpu_set_cfg_unavailable, 441 NULL, (void *)prop_name); 442 } 443 444 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 445 const RISCVCPUMultiExtConfig *array) 446 { 447 const RISCVCPUMultiExtConfig *prop; 448 449 g_assert(array); 450 451 for (prop = array; prop && prop->name; prop++) { 452 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 453 } 454 } 455 456 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 457 { 458 int i; 459 460 riscv_add_satp_mode_properties(cpu_obj); 461 462 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 463 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 464 int bit = misa_cfg->offset; 465 466 misa_cfg->name = riscv_get_misa_ext_name(bit); 467 misa_cfg->description = riscv_get_misa_ext_description(bit); 468 469 object_property_add(cpu_obj, misa_cfg->name, "bool", 470 kvm_cpu_get_misa_ext_cfg, 471 kvm_cpu_set_misa_ext_cfg, 472 NULL, misa_cfg); 473 object_property_set_description(cpu_obj, misa_cfg->name, 474 misa_cfg->description); 475 } 476 477 for (i = 0; misa_bits[i] != 0; i++) { 478 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 479 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 480 } 481 482 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 483 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 484 485 object_property_add(cpu_obj, multi_cfg->name, "bool", 486 kvm_cpu_get_multi_ext_cfg, 487 kvm_cpu_set_multi_ext_cfg, 488 NULL, multi_cfg); 489 } 490 491 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 492 NULL, kvm_cpu_set_cbomz_blksize, 493 NULL, &kvm_cbom_blocksize); 494 495 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 496 NULL, kvm_cpu_set_cbomz_blksize, 497 NULL, &kvm_cboz_blocksize); 498 499 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 500 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 501 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 502 503 /* We don't have the needed KVM support for profiles */ 504 for (i = 0; riscv_profiles[i] != NULL; i++) { 505 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 506 } 507 } 508 509 static int kvm_riscv_get_regs_core(CPUState *cs) 510 { 511 int ret = 0; 512 int i; 513 target_ulong reg; 514 CPURISCVState *env = &RISCV_CPU(cs)->env; 515 516 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 517 if (ret) { 518 return ret; 519 } 520 env->pc = reg; 521 522 for (i = 1; i < 32; i++) { 523 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 524 ret = kvm_get_one_reg(cs, id, ®); 525 if (ret) { 526 return ret; 527 } 528 env->gpr[i] = reg; 529 } 530 531 return ret; 532 } 533 534 static int kvm_riscv_put_regs_core(CPUState *cs) 535 { 536 int ret = 0; 537 int i; 538 target_ulong reg; 539 CPURISCVState *env = &RISCV_CPU(cs)->env; 540 541 reg = env->pc; 542 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 543 if (ret) { 544 return ret; 545 } 546 547 for (i = 1; i < 32; i++) { 548 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 549 reg = env->gpr[i]; 550 ret = kvm_set_one_reg(cs, id, ®); 551 if (ret) { 552 return ret; 553 } 554 } 555 556 return ret; 557 } 558 559 static int kvm_riscv_get_regs_csr(CPUState *cs) 560 { 561 CPURISCVState *env = &RISCV_CPU(cs)->env; 562 563 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 564 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 565 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 566 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 567 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 568 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 569 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 570 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 571 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 572 573 return 0; 574 } 575 576 static int kvm_riscv_put_regs_csr(CPUState *cs) 577 { 578 CPURISCVState *env = &RISCV_CPU(cs)->env; 579 580 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 581 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 582 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 583 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 584 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 585 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 586 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 587 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 588 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 589 590 return 0; 591 } 592 593 static int kvm_riscv_get_regs_fp(CPUState *cs) 594 { 595 int ret = 0; 596 int i; 597 CPURISCVState *env = &RISCV_CPU(cs)->env; 598 599 if (riscv_has_ext(env, RVD)) { 600 uint64_t reg; 601 for (i = 0; i < 32; i++) { 602 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 603 if (ret) { 604 return ret; 605 } 606 env->fpr[i] = reg; 607 } 608 return ret; 609 } 610 611 if (riscv_has_ext(env, RVF)) { 612 uint32_t reg; 613 for (i = 0; i < 32; i++) { 614 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 615 if (ret) { 616 return ret; 617 } 618 env->fpr[i] = reg; 619 } 620 return ret; 621 } 622 623 return ret; 624 } 625 626 static int kvm_riscv_put_regs_fp(CPUState *cs) 627 { 628 int ret = 0; 629 int i; 630 CPURISCVState *env = &RISCV_CPU(cs)->env; 631 632 if (riscv_has_ext(env, RVD)) { 633 uint64_t reg; 634 for (i = 0; i < 32; i++) { 635 reg = env->fpr[i]; 636 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 637 if (ret) { 638 return ret; 639 } 640 } 641 return ret; 642 } 643 644 if (riscv_has_ext(env, RVF)) { 645 uint32_t reg; 646 for (i = 0; i < 32; i++) { 647 reg = env->fpr[i]; 648 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 649 if (ret) { 650 return ret; 651 } 652 } 653 return ret; 654 } 655 656 return ret; 657 } 658 659 static void kvm_riscv_get_regs_timer(CPUState *cs) 660 { 661 CPURISCVState *env = &RISCV_CPU(cs)->env; 662 663 if (env->kvm_timer_dirty) { 664 return; 665 } 666 667 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 668 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 669 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 670 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 671 672 env->kvm_timer_dirty = true; 673 } 674 675 static void kvm_riscv_put_regs_timer(CPUState *cs) 676 { 677 uint64_t reg; 678 CPURISCVState *env = &RISCV_CPU(cs)->env; 679 680 if (!env->kvm_timer_dirty) { 681 return; 682 } 683 684 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 685 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 686 687 /* 688 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 689 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 690 * doesn't matter that adaping in QEMU now. 691 * TODO If KVM changes, adapt here. 692 */ 693 if (env->kvm_timer_state) { 694 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 695 } 696 697 /* 698 * For now, migration will not work between Hosts with different timer 699 * frequency. Therefore, we should check whether they are the same here 700 * during the migration. 701 */ 702 if (migration_is_running(migrate_get_current()->state)) { 703 KVM_RISCV_GET_TIMER(cs, frequency, reg); 704 if (reg != env->kvm_timer_frequency) { 705 error_report("Dst Hosts timer frequency != Src Hosts"); 706 } 707 } 708 709 env->kvm_timer_dirty = false; 710 } 711 712 typedef struct KVMScratchCPU { 713 int kvmfd; 714 int vmfd; 715 int cpufd; 716 } KVMScratchCPU; 717 718 /* 719 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 720 * from target/arm/kvm.c. 721 */ 722 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 723 { 724 int kvmfd = -1, vmfd = -1, cpufd = -1; 725 726 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 727 if (kvmfd < 0) { 728 goto err; 729 } 730 do { 731 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 732 } while (vmfd == -1 && errno == EINTR); 733 if (vmfd < 0) { 734 goto err; 735 } 736 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 737 if (cpufd < 0) { 738 goto err; 739 } 740 741 scratch->kvmfd = kvmfd; 742 scratch->vmfd = vmfd; 743 scratch->cpufd = cpufd; 744 745 return true; 746 747 err: 748 if (cpufd >= 0) { 749 close(cpufd); 750 } 751 if (vmfd >= 0) { 752 close(vmfd); 753 } 754 if (kvmfd >= 0) { 755 close(kvmfd); 756 } 757 758 return false; 759 } 760 761 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 762 { 763 close(scratch->cpufd); 764 close(scratch->vmfd); 765 close(scratch->kvmfd); 766 } 767 768 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 769 { 770 CPURISCVState *env = &cpu->env; 771 struct kvm_one_reg reg; 772 int ret; 773 774 reg.id = RISCV_CONFIG_REG(env, mvendorid); 775 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 776 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 777 if (ret != 0) { 778 error_report("Unable to retrieve mvendorid from host, error %d", ret); 779 } 780 781 reg.id = RISCV_CONFIG_REG(env, marchid); 782 reg.addr = (uint64_t)&cpu->cfg.marchid; 783 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 784 if (ret != 0) { 785 error_report("Unable to retrieve marchid from host, error %d", ret); 786 } 787 788 reg.id = RISCV_CONFIG_REG(env, mimpid); 789 reg.addr = (uint64_t)&cpu->cfg.mimpid; 790 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 791 if (ret != 0) { 792 error_report("Unable to retrieve mimpid from host, error %d", ret); 793 } 794 } 795 796 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 797 KVMScratchCPU *kvmcpu) 798 { 799 CPURISCVState *env = &cpu->env; 800 struct kvm_one_reg reg; 801 int ret; 802 803 reg.id = RISCV_CONFIG_REG(env, isa); 804 reg.addr = (uint64_t)&env->misa_ext_mask; 805 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 806 807 if (ret) { 808 error_report("Unable to fetch ISA register from KVM, " 809 "error %d", ret); 810 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 811 exit(EXIT_FAILURE); 812 } 813 814 env->misa_ext = env->misa_ext_mask; 815 } 816 817 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 818 KVMCPUConfig *cbomz_cfg) 819 { 820 CPURISCVState *env = &cpu->env; 821 struct kvm_one_reg reg; 822 int ret; 823 824 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 825 cbomz_cfg->kvm_reg_id); 826 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 827 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 828 if (ret != 0) { 829 error_report("Unable to read KVM reg %s, error %d", 830 cbomz_cfg->name, ret); 831 exit(EXIT_FAILURE); 832 } 833 } 834 835 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 836 KVMScratchCPU *kvmcpu) 837 { 838 CPURISCVState *env = &cpu->env; 839 uint64_t val; 840 int i, ret; 841 842 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 843 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 844 struct kvm_one_reg reg; 845 846 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 847 multi_ext_cfg->kvm_reg_id); 848 reg.addr = (uint64_t)&val; 849 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 850 if (ret != 0) { 851 if (errno == EINVAL) { 852 /* Silently default to 'false' if KVM does not support it. */ 853 multi_ext_cfg->supported = false; 854 val = false; 855 } else { 856 error_report("Unable to read ISA_EXT KVM register %s: %s", 857 multi_ext_cfg->name, strerror(errno)); 858 exit(EXIT_FAILURE); 859 } 860 } else { 861 multi_ext_cfg->supported = true; 862 } 863 864 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 865 } 866 867 if (cpu->cfg.ext_zicbom) { 868 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 869 } 870 871 if (cpu->cfg.ext_zicboz) { 872 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 873 } 874 } 875 876 static int uint64_cmp(const void *a, const void *b) 877 { 878 uint64_t val1 = *(const uint64_t *)a; 879 uint64_t val2 = *(const uint64_t *)b; 880 881 if (val1 < val2) { 882 return -1; 883 } 884 885 if (val1 > val2) { 886 return 1; 887 } 888 889 return 0; 890 } 891 892 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 893 { 894 KVMCPUConfig *multi_ext_cfg; 895 struct kvm_one_reg reg; 896 struct kvm_reg_list rl_struct; 897 struct kvm_reg_list *reglist; 898 uint64_t val, reg_id, *reg_search; 899 int i, ret; 900 901 rl_struct.n = 0; 902 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 903 904 /* 905 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 906 * (EINVAL). Use read_legacy() in this case. 907 */ 908 if (errno == EINVAL) { 909 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 910 } else if (errno != E2BIG) { 911 /* 912 * E2BIG is an expected error message for the API since we 913 * don't know the number of registers. The right amount will 914 * be written in rl_struct.n. 915 * 916 * Error out if we get any other errno. 917 */ 918 error_report("Error when accessing get-reg-list: %s", 919 strerror(errno)); 920 exit(EXIT_FAILURE); 921 } 922 923 reglist = g_malloc(sizeof(struct kvm_reg_list) + 924 rl_struct.n * sizeof(uint64_t)); 925 reglist->n = rl_struct.n; 926 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 927 if (ret) { 928 error_report("Error when reading KVM_GET_REG_LIST: %s", 929 strerror(errno)); 930 exit(EXIT_FAILURE); 931 } 932 933 /* sort reglist to use bsearch() */ 934 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 935 936 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 937 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 938 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 939 multi_ext_cfg->kvm_reg_id); 940 reg_search = bsearch(®_id, reglist->reg, reglist->n, 941 sizeof(uint64_t), uint64_cmp); 942 if (!reg_search) { 943 continue; 944 } 945 946 reg.id = reg_id; 947 reg.addr = (uint64_t)&val; 948 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 949 if (ret != 0) { 950 error_report("Unable to read ISA_EXT KVM register %s: %s", 951 multi_ext_cfg->name, strerror(errno)); 952 exit(EXIT_FAILURE); 953 } 954 955 multi_ext_cfg->supported = true; 956 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 957 } 958 959 if (cpu->cfg.ext_zicbom) { 960 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 961 } 962 963 if (cpu->cfg.ext_zicboz) { 964 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 965 } 966 } 967 968 static void riscv_init_kvm_registers(Object *cpu_obj) 969 { 970 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 971 KVMScratchCPU kvmcpu; 972 973 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 974 return; 975 } 976 977 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 978 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 979 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 980 981 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 982 } 983 984 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 985 KVM_CAP_LAST_INFO 986 }; 987 988 int kvm_arch_get_registers(CPUState *cs) 989 { 990 int ret = 0; 991 992 ret = kvm_riscv_get_regs_core(cs); 993 if (ret) { 994 return ret; 995 } 996 997 ret = kvm_riscv_get_regs_csr(cs); 998 if (ret) { 999 return ret; 1000 } 1001 1002 ret = kvm_riscv_get_regs_fp(cs); 1003 if (ret) { 1004 return ret; 1005 } 1006 1007 return ret; 1008 } 1009 1010 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1011 { 1012 if (cap_has_mp_state) { 1013 struct kvm_mp_state mp_state = { 1014 .mp_state = state 1015 }; 1016 1017 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1018 if (ret) { 1019 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1020 __func__, ret, strerror(-ret)); 1021 return -1; 1022 } 1023 } 1024 1025 return 0; 1026 } 1027 1028 int kvm_arch_put_registers(CPUState *cs, int level) 1029 { 1030 int ret = 0; 1031 1032 ret = kvm_riscv_put_regs_core(cs); 1033 if (ret) { 1034 return ret; 1035 } 1036 1037 ret = kvm_riscv_put_regs_csr(cs); 1038 if (ret) { 1039 return ret; 1040 } 1041 1042 ret = kvm_riscv_put_regs_fp(cs); 1043 if (ret) { 1044 return ret; 1045 } 1046 1047 if (KVM_PUT_RESET_STATE == level) { 1048 RISCVCPU *cpu = RISCV_CPU(cs); 1049 if (cs->cpu_index == 0) { 1050 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1051 } else { 1052 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1053 } 1054 if (ret) { 1055 return ret; 1056 } 1057 } 1058 1059 return ret; 1060 } 1061 1062 int kvm_arch_release_virq_post(int virq) 1063 { 1064 return 0; 1065 } 1066 1067 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1068 uint64_t address, uint32_t data, PCIDevice *dev) 1069 { 1070 return 0; 1071 } 1072 1073 int kvm_arch_destroy_vcpu(CPUState *cs) 1074 { 1075 return 0; 1076 } 1077 1078 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1079 { 1080 return cpu->cpu_index; 1081 } 1082 1083 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1084 RunState state) 1085 { 1086 CPUState *cs = opaque; 1087 1088 if (running) { 1089 kvm_riscv_put_regs_timer(cs); 1090 } else { 1091 kvm_riscv_get_regs_timer(cs); 1092 } 1093 } 1094 1095 void kvm_arch_init_irq_routing(KVMState *s) 1096 { 1097 } 1098 1099 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1100 { 1101 CPURISCVState *env = &cpu->env; 1102 target_ulong reg; 1103 uint64_t id; 1104 int ret; 1105 1106 id = RISCV_CONFIG_REG(env, mvendorid); 1107 /* 1108 * cfg.mvendorid is an uint32 but a target_ulong will 1109 * be written. Assign it to a target_ulong var to avoid 1110 * writing pieces of other cpu->cfg fields in the reg. 1111 */ 1112 reg = cpu->cfg.mvendorid; 1113 ret = kvm_set_one_reg(cs, id, ®); 1114 if (ret != 0) { 1115 return ret; 1116 } 1117 1118 id = RISCV_CONFIG_REG(env, marchid); 1119 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1120 if (ret != 0) { 1121 return ret; 1122 } 1123 1124 id = RISCV_CONFIG_REG(env, mimpid); 1125 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1126 1127 return ret; 1128 } 1129 1130 int kvm_arch_init_vcpu(CPUState *cs) 1131 { 1132 int ret = 0; 1133 RISCVCPU *cpu = RISCV_CPU(cs); 1134 1135 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1136 1137 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1138 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1139 if (ret != 0) { 1140 return ret; 1141 } 1142 } 1143 1144 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1145 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1146 1147 return ret; 1148 } 1149 1150 int kvm_arch_msi_data_to_gsi(uint32_t data) 1151 { 1152 abort(); 1153 } 1154 1155 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1156 int vector, PCIDevice *dev) 1157 { 1158 return 0; 1159 } 1160 1161 int kvm_arch_get_default_type(MachineState *ms) 1162 { 1163 return 0; 1164 } 1165 1166 int kvm_arch_init(MachineState *ms, KVMState *s) 1167 { 1168 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1169 return 0; 1170 } 1171 1172 int kvm_arch_irqchip_create(KVMState *s) 1173 { 1174 if (kvm_kernel_irqchip_split()) { 1175 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1176 exit(1); 1177 } 1178 1179 /* 1180 * We can create the VAIA using the newer device control API. 1181 */ 1182 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1183 } 1184 1185 int kvm_arch_process_async_events(CPUState *cs) 1186 { 1187 return 0; 1188 } 1189 1190 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1191 { 1192 } 1193 1194 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1195 { 1196 return MEMTXATTRS_UNSPECIFIED; 1197 } 1198 1199 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1200 { 1201 return true; 1202 } 1203 1204 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1205 { 1206 int ret = 0; 1207 unsigned char ch; 1208 switch (run->riscv_sbi.extension_id) { 1209 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1210 ch = run->riscv_sbi.args[0]; 1211 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1212 break; 1213 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1214 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1215 if (ret == sizeof(ch)) { 1216 run->riscv_sbi.ret[0] = ch; 1217 } else { 1218 run->riscv_sbi.ret[0] = -1; 1219 } 1220 ret = 0; 1221 break; 1222 default: 1223 qemu_log_mask(LOG_UNIMP, 1224 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1225 __func__, run->riscv_sbi.extension_id); 1226 ret = -1; 1227 break; 1228 } 1229 return ret; 1230 } 1231 1232 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1233 { 1234 int ret = 0; 1235 switch (run->exit_reason) { 1236 case KVM_EXIT_RISCV_SBI: 1237 ret = kvm_riscv_handle_sbi(cs, run); 1238 break; 1239 default: 1240 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1241 __func__, run->exit_reason); 1242 ret = -1; 1243 break; 1244 } 1245 return ret; 1246 } 1247 1248 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1249 { 1250 CPURISCVState *env = &cpu->env; 1251 int i; 1252 1253 if (!kvm_enabled()) { 1254 return; 1255 } 1256 for (i = 0; i < 32; i++) { 1257 env->gpr[i] = 0; 1258 } 1259 env->pc = cpu->env.kernel_addr; 1260 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1261 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1262 env->satp = 0; 1263 env->mie = 0; 1264 env->stvec = 0; 1265 env->sscratch = 0; 1266 env->sepc = 0; 1267 env->scause = 0; 1268 env->stval = 0; 1269 env->mip = 0; 1270 } 1271 1272 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1273 { 1274 int ret; 1275 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1276 1277 if (irq != IRQ_S_EXT) { 1278 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1279 abort(); 1280 } 1281 1282 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1283 if (ret < 0) { 1284 perror("Set irq failed"); 1285 abort(); 1286 } 1287 } 1288 1289 bool kvm_arch_cpu_check_are_resettable(void) 1290 { 1291 return true; 1292 } 1293 1294 static int aia_mode; 1295 1296 static const char *kvm_aia_mode_str(uint64_t mode) 1297 { 1298 switch (mode) { 1299 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1300 return "emul"; 1301 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1302 return "hwaccel"; 1303 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1304 default: 1305 return "auto"; 1306 }; 1307 } 1308 1309 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1310 { 1311 return g_strdup(kvm_aia_mode_str(aia_mode)); 1312 } 1313 1314 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1315 { 1316 if (!strcmp(val, "emul")) { 1317 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1318 } else if (!strcmp(val, "hwaccel")) { 1319 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1320 } else if (!strcmp(val, "auto")) { 1321 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1322 } else { 1323 error_setg(errp, "Invalid KVM AIA mode"); 1324 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1325 } 1326 } 1327 1328 void kvm_arch_accel_class_init(ObjectClass *oc) 1329 { 1330 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1331 riscv_set_kvm_aia); 1332 object_class_property_set_description(oc, "riscv-aia", 1333 "Set KVM AIA mode. Valid values are " 1334 "emul, hwaccel, and auto. Default " 1335 "is auto."); 1336 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1337 "auto"); 1338 } 1339 1340 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1341 uint64_t aia_irq_num, uint64_t aia_msi_num, 1342 uint64_t aplic_base, uint64_t imsic_base, 1343 uint64_t guest_num) 1344 { 1345 int ret, i; 1346 int aia_fd = -1; 1347 uint64_t default_aia_mode; 1348 uint64_t socket_count = riscv_socket_count(machine); 1349 uint64_t max_hart_per_socket = 0; 1350 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1351 uint64_t socket_bits, hart_bits, guest_bits; 1352 1353 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1354 1355 if (aia_fd < 0) { 1356 error_report("Unable to create in-kernel irqchip"); 1357 exit(1); 1358 } 1359 1360 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1361 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1362 &default_aia_mode, false, NULL); 1363 if (ret < 0) { 1364 error_report("KVM AIA: failed to get current KVM AIA mode"); 1365 exit(1); 1366 } 1367 qemu_log("KVM AIA: default mode is %s\n", 1368 kvm_aia_mode_str(default_aia_mode)); 1369 1370 if (default_aia_mode != aia_mode) { 1371 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1372 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1373 &aia_mode, true, NULL); 1374 if (ret < 0) 1375 warn_report("KVM AIA: failed to set KVM AIA mode"); 1376 else 1377 qemu_log("KVM AIA: set current mode to %s\n", 1378 kvm_aia_mode_str(aia_mode)); 1379 } 1380 1381 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1382 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1383 &aia_irq_num, true, NULL); 1384 if (ret < 0) { 1385 error_report("KVM AIA: failed to set number of input irq lines"); 1386 exit(1); 1387 } 1388 1389 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1390 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1391 &aia_msi_num, true, NULL); 1392 if (ret < 0) { 1393 error_report("KVM AIA: failed to set number of msi"); 1394 exit(1); 1395 } 1396 1397 1398 if (socket_count > 1) { 1399 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1400 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1401 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1402 &socket_bits, true, NULL); 1403 if (ret < 0) { 1404 error_report("KVM AIA: failed to set group_bits"); 1405 exit(1); 1406 } 1407 1408 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1409 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1410 &group_shift, true, NULL); 1411 if (ret < 0) { 1412 error_report("KVM AIA: failed to set group_shift"); 1413 exit(1); 1414 } 1415 } 1416 1417 guest_bits = guest_num == 0 ? 0 : 1418 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1419 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1420 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1421 &guest_bits, true, NULL); 1422 if (ret < 0) { 1423 error_report("KVM AIA: failed to set guest_bits"); 1424 exit(1); 1425 } 1426 1427 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1428 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1429 &aplic_base, true, NULL); 1430 if (ret < 0) { 1431 error_report("KVM AIA: failed to set the base address of APLIC"); 1432 exit(1); 1433 } 1434 1435 for (socket = 0; socket < socket_count; socket++) { 1436 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1437 hart_count = riscv_socket_hart_count(machine, socket); 1438 base_hart = riscv_socket_first_hartid(machine, socket); 1439 1440 if (max_hart_per_socket < hart_count) { 1441 max_hart_per_socket = hart_count; 1442 } 1443 1444 for (i = 0; i < hart_count; i++) { 1445 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1446 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1447 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1448 &imsic_addr, true, NULL); 1449 if (ret < 0) { 1450 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1451 exit(1); 1452 } 1453 } 1454 } 1455 1456 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1457 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1458 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1459 &hart_bits, true, NULL); 1460 if (ret < 0) { 1461 error_report("KVM AIA: failed to set hart_bits"); 1462 exit(1); 1463 } 1464 1465 if (kvm_has_gsi_routing()) { 1466 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1467 /* KVM AIA only has one APLIC instance */ 1468 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1469 } 1470 kvm_gsi_routing_allowed = true; 1471 kvm_irqchip_commit_routes(kvm_state); 1472 } 1473 1474 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1475 KVM_DEV_RISCV_AIA_CTRL_INIT, 1476 NULL, true, NULL); 1477 if (ret < 0) { 1478 error_report("KVM AIA: initialized fail"); 1479 exit(1); 1480 } 1481 1482 kvm_msi_via_irqfd_allowed = true; 1483 } 1484 1485 static void kvm_cpu_instance_init(CPUState *cs) 1486 { 1487 Object *obj = OBJECT(RISCV_CPU(cs)); 1488 DeviceState *dev = DEVICE(obj); 1489 1490 riscv_init_kvm_registers(obj); 1491 1492 kvm_riscv_add_cpu_user_properties(obj); 1493 1494 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1495 /* Check if we have a specific KVM handler for the option */ 1496 if (object_property_find(obj, prop->name)) { 1497 continue; 1498 } 1499 qdev_property_add_static(dev, prop); 1500 } 1501 } 1502 1503 /* 1504 * We'll get here via the following path: 1505 * 1506 * riscv_cpu_realize() 1507 * -> cpu_exec_realizefn() 1508 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1509 */ 1510 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1511 { 1512 RISCVCPU *cpu = RISCV_CPU(cs); 1513 int ret; 1514 1515 if (riscv_has_ext(&cpu->env, RVV)) { 1516 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1517 if (ret) { 1518 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1519 strerrorname_np(errno)); 1520 return false; 1521 } 1522 } 1523 1524 return true; 1525 } 1526 1527 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1528 { 1529 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1530 1531 acc->cpu_instance_init = kvm_cpu_instance_init; 1532 acc->cpu_target_realize = kvm_cpu_realize; 1533 } 1534 1535 static const TypeInfo kvm_cpu_accel_type_info = { 1536 .name = ACCEL_CPU_NAME("kvm"), 1537 1538 .parent = TYPE_ACCEL_CPU, 1539 .class_init = kvm_cpu_accel_class_init, 1540 .abstract = true, 1541 }; 1542 static void kvm_cpu_accel_register_types(void) 1543 { 1544 type_register_static(&kvm_cpu_accel_type_info); 1545 } 1546 type_init(kvm_cpu_accel_register_types); 1547 1548 static void riscv_host_cpu_init(Object *obj) 1549 { 1550 CPURISCVState *env = &RISCV_CPU(obj)->env; 1551 1552 #if defined(TARGET_RISCV32) 1553 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1554 #elif defined(TARGET_RISCV64) 1555 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1556 #endif 1557 } 1558 1559 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1560 { 1561 .name = TYPE_RISCV_CPU_HOST, 1562 .parent = TYPE_RISCV_CPU, 1563 .instance_init = riscv_host_cpu_init, 1564 } 1565 }; 1566 1567 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1568