1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu-common.h" 25 #include "qemu/timer.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/kvm_int.h" 31 #include "cpu.h" 32 #include "trace.h" 33 #include "hw/pci/pci.h" 34 #include "exec/memattrs.h" 35 #include "exec/address-spaces.h" 36 #include "hw/boards.h" 37 #include "hw/irq.h" 38 #include "qemu/log.h" 39 #include "hw/loader.h" 40 41 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 42 uint64_t idx) 43 { 44 uint64_t id = KVM_REG_RISCV | type | idx; 45 46 switch (riscv_cpu_mxl(env)) { 47 case MXL_RV32: 48 id |= KVM_REG_SIZE_U32; 49 break; 50 case MXL_RV64: 51 id |= KVM_REG_SIZE_U64; 52 break; 53 default: 54 g_assert_not_reached(); 55 } 56 return id; 57 } 58 59 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 60 KVM_CAP_LAST_INFO 61 }; 62 63 int kvm_arch_get_registers(CPUState *cs) 64 { 65 return 0; 66 } 67 68 int kvm_arch_put_registers(CPUState *cs, int level) 69 { 70 return 0; 71 } 72 73 int kvm_arch_release_virq_post(int virq) 74 { 75 return 0; 76 } 77 78 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 79 uint64_t address, uint32_t data, PCIDevice *dev) 80 { 81 return 0; 82 } 83 84 int kvm_arch_destroy_vcpu(CPUState *cs) 85 { 86 return 0; 87 } 88 89 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 90 { 91 return cpu->cpu_index; 92 } 93 94 void kvm_arch_init_irq_routing(KVMState *s) 95 { 96 } 97 98 int kvm_arch_init_vcpu(CPUState *cs) 99 { 100 int ret = 0; 101 target_ulong isa; 102 RISCVCPU *cpu = RISCV_CPU(cs); 103 CPURISCVState *env = &cpu->env; 104 uint64_t id; 105 106 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 107 KVM_REG_RISCV_CONFIG_REG(isa)); 108 ret = kvm_get_one_reg(cs, id, &isa); 109 if (ret) { 110 return ret; 111 } 112 env->misa_ext = isa; 113 114 return ret; 115 } 116 117 int kvm_arch_msi_data_to_gsi(uint32_t data) 118 { 119 abort(); 120 } 121 122 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 123 int vector, PCIDevice *dev) 124 { 125 return 0; 126 } 127 128 int kvm_arch_init(MachineState *ms, KVMState *s) 129 { 130 return 0; 131 } 132 133 int kvm_arch_irqchip_create(KVMState *s) 134 { 135 return 0; 136 } 137 138 int kvm_arch_process_async_events(CPUState *cs) 139 { 140 return 0; 141 } 142 143 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 144 { 145 } 146 147 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 148 { 149 return MEMTXATTRS_UNSPECIFIED; 150 } 151 152 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 153 { 154 return true; 155 } 156 157 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 158 { 159 return 0; 160 } 161 162 bool kvm_arch_cpu_check_are_resettable(void) 163 { 164 return true; 165 } 166