xref: /qemu/target/riscv/internals.h (revision 751538d5da557e5c10e5045c2d27639580ea54a7)
1f476f177SLIU Zhiwei /*
2f476f177SLIU Zhiwei  * QEMU RISC-V CPU -- internal functions and types
3f476f177SLIU Zhiwei  *
4f476f177SLIU Zhiwei  * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5f476f177SLIU Zhiwei  *
6f476f177SLIU Zhiwei  * This program is free software; you can redistribute it and/or modify it
7f476f177SLIU Zhiwei  * under the terms and conditions of the GNU General Public License,
8f476f177SLIU Zhiwei  * version 2 or later, as published by the Free Software Foundation.
9f476f177SLIU Zhiwei  *
10f476f177SLIU Zhiwei  * This program is distributed in the hope it will be useful, but WITHOUT
11f476f177SLIU Zhiwei  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12f476f177SLIU Zhiwei  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13f476f177SLIU Zhiwei  * more details.
14f476f177SLIU Zhiwei  *
15f476f177SLIU Zhiwei  * You should have received a copy of the GNU General Public License along with
16f476f177SLIU Zhiwei  * this program.  If not, see <http://www.gnu.org/licenses/>.
17f476f177SLIU Zhiwei  */
18f476f177SLIU Zhiwei 
19f476f177SLIU Zhiwei #ifndef RISCV_CPU_INTERNALS_H
20f476f177SLIU Zhiwei #define RISCV_CPU_INTERNALS_H
21f476f177SLIU Zhiwei 
22f476f177SLIU Zhiwei #include "hw/registerfields.h"
23f476f177SLIU Zhiwei 
24*751538d5SLIU Zhiwei /* share data between vector helpers and decode code */
25*751538d5SLIU Zhiwei FIELD(VDATA, MLEN, 0, 8)
26*751538d5SLIU Zhiwei FIELD(VDATA, VM, 8, 1)
27*751538d5SLIU Zhiwei FIELD(VDATA, LMUL, 9, 2)
28*751538d5SLIU Zhiwei FIELD(VDATA, NF, 11, 4)
29f476f177SLIU Zhiwei #endif
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