1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24%sh5 20:5 25%sh6 20:6 26 27%sh7 20:7 28%csr 20:12 29%rm 12:3 30%nf 29:3 !function=ex_plus_1 31 32# immediates: 33%imm_i 20:s12 34%imm_s 25:s7 7:5 35%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 36%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 37%imm_u 12:s20 !function=ex_shift_12 38%imm_bs 30:2 !function=ex_shift_3 39%imm_rnum 20:4 40%imm_z6 26:1 15:5 41%imm_mop5 30:1 26:2 20:2 42%imm_mop3 30:1 26:2 43 44# Argument sets: 45&empty 46&b imm rs2 rs1 47&i imm rs1 rd 48&j imm rd 49&r rd rs1 rs2 50&r2 rd rs1 51&r2_s rs1 rs2 52&s imm rs1 rs2 53&u imm rd 54&shift shamt rs1 rd 55&atomic aq rl rs2 rs1 rd 56&rmrr vm rd rs1 rs2 57&rmr vm rd rs2 58&r2nfvm vm rd rs1 nf 59&rnfvm vm rd rs1 rs2 nf 60&k_aes shamt rs2 rs1 rd 61&mop5 imm rd rs1 62&mop3 imm rd rs1 rs2 63 64# Formats 32: 65@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 66@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 67@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 68@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 69@u .................... ..... ....... &u imm=%imm_u %rd 70@j .................... ..... ....... &j imm=%imm_j %rd 71 72@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd 73@csr ............ ..... ... ..... ....... %csr %rs1 %rd 74 75@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 76@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 77 78@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 79@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 80@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 81@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 82@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd 83@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 84@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd 85@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd 86@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 87@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd 88@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 89@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 90@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 91@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd 92@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd 93@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd 94@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 95 96@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 97@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 98 99@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 100@sfence_vm ....... ..... ..... ... ..... ....... %rs1 101 102@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd 103@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd 104 105@mop5 . . .. .. .... .. ..... ... ..... ....... &mop5 imm=%imm_mop5 %rd %rs1 106@mop3 . . .. .. . ..... ..... ... ..... ....... &mop3 imm=%imm_mop3 %rd %rs1 %rs2 107 108# Formats 64: 109@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 110 111# Formats 128: 112@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd 113 114# *** Privileged Instructions *** 115ecall 000000000000 00000 000 00000 1110011 116ebreak 000000000001 00000 000 00000 1110011 117uret 0000000 00010 00000 000 00000 1110011 118sret 0001000 00010 00000 000 00000 1110011 119mret 0011000 00010 00000 000 00000 1110011 120wfi 0001000 00101 00000 000 00000 1110011 121sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 122sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 123 124# *** NMI *** 125mnret 0111000 00010 00000 000 00000 1110011 126 127# *** RV32I Base Instruction Set *** 128lui .................... ..... 0110111 @u 129{ 130 lpad label:20 00000 0010111 131 auipc .................... ..... 0010111 @u 132} 133jal .................... ..... 1101111 @j 134jalr ............ ..... 000 ..... 1100111 @i 135beq ....... ..... ..... 000 ..... 1100011 @b 136bne ....... ..... ..... 001 ..... 1100011 @b 137blt ....... ..... ..... 100 ..... 1100011 @b 138bge ....... ..... ..... 101 ..... 1100011 @b 139bltu ....... ..... ..... 110 ..... 1100011 @b 140bgeu ....... ..... ..... 111 ..... 1100011 @b 141lb ............ ..... 000 ..... 0000011 @i 142lh ............ ..... 001 ..... 0000011 @i 143lw ............ ..... 010 ..... 0000011 @i 144lbu ............ ..... 100 ..... 0000011 @i 145lhu ............ ..... 101 ..... 0000011 @i 146sb ....... ..... ..... 000 ..... 0100011 @s 147sh ....... ..... ..... 001 ..... 0100011 @s 148sw ....... ..... ..... 010 ..... 0100011 @s 149addi ............ ..... 000 ..... 0010011 @i 150slti ............ ..... 010 ..... 0010011 @i 151sltiu ............ ..... 011 ..... 0010011 @i 152xori ............ ..... 100 ..... 0010011 @i 153# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. 154ori ............ ..... 110 ..... 0010011 @i 155andi ............ ..... 111 ..... 0010011 @i 156slli 00000. ...... ..... 001 ..... 0010011 @sh 157srli 00000. ...... ..... 101 ..... 0010011 @sh 158srai 01000. ...... ..... 101 ..... 0010011 @sh 159add 0000000 ..... ..... 000 ..... 0110011 @r 160sub 0100000 ..... ..... 000 ..... 0110011 @r 161sll 0000000 ..... ..... 001 ..... 0110011 @r 162slt 0000000 ..... ..... 010 ..... 0110011 @r 163sltu 0000000 ..... ..... 011 ..... 0110011 @r 164xor 0000000 ..... ..... 100 ..... 0110011 @r 165srl 0000000 ..... ..... 101 ..... 0110011 @r 166sra 0100000 ..... ..... 101 ..... 0110011 @r 167or 0000000 ..... ..... 110 ..... 0110011 @r 168and 0000000 ..... ..... 111 ..... 0110011 @r 169 170{ 171 pause 0000 0001 0000 00000 000 00000 0001111 172 fence ---- pred:4 succ:4 ----- 000 ----- 0001111 173} 174 175fence_i ---- ---- ---- ----- 001 ----- 0001111 176csrrw ............ ..... 001 ..... 1110011 @csr 177csrrs ............ ..... 010 ..... 1110011 @csr 178csrrc ............ ..... 011 ..... 1110011 @csr 179csrrwi ............ ..... 101 ..... 1110011 @csr 180csrrsi ............ ..... 110 ..... 1110011 @csr 181csrrci ............ ..... 111 ..... 1110011 @csr 182 183# *** RV64I Base Instruction Set (in addition to RV32I) *** 184lwu ............ ..... 110 ..... 0000011 @i 185ld ............ ..... 011 ..... 0000011 @i 186sd ....... ..... ..... 011 ..... 0100011 @s 187addiw ............ ..... 000 ..... 0011011 @i 188slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 189srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 190sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 191addw 0000000 ..... ..... 000 ..... 0111011 @r 192subw 0100000 ..... ..... 000 ..... 0111011 @r 193sllw 0000000 ..... ..... 001 ..... 0111011 @r 194srlw 0000000 ..... ..... 101 ..... 0111011 @r 195sraw 0100000 ..... ..... 101 ..... 0111011 @r 196 197# *** RV128I Base Instruction Set (in addition to RV64I) *** 198ldu ............ ..... 111 ..... 0000011 @i 199{ 200 [ 201 # *** RV32 Zicbom Standard Extension *** 202 cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm 203 cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm 204 cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm 205 206 # *** RV32 Zicboz Standard Extension *** 207 cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm 208 ] 209 210 # *** RVI128 lq *** 211 lq ............ ..... 010 ..... 0001111 @i 212} 213sq ............ ..... 100 ..... 0100011 @s 214addid ............ ..... 000 ..... 1011011 @i 215sllid 000000 ...... ..... 001 ..... 1011011 @sh6 216srlid 000000 ...... ..... 101 ..... 1011011 @sh6 217sraid 010000 ...... ..... 101 ..... 1011011 @sh6 218addd 0000000 ..... ..... 000 ..... 1111011 @r 219subd 0100000 ..... ..... 000 ..... 1111011 @r 220slld 0000000 ..... ..... 001 ..... 1111011 @r 221srld 0000000 ..... ..... 101 ..... 1111011 @r 222srad 0100000 ..... ..... 101 ..... 1111011 @r 223 224# *** RV32M Standard Extension *** 225mul 0000001 ..... ..... 000 ..... 0110011 @r 226mulh 0000001 ..... ..... 001 ..... 0110011 @r 227mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 228mulhu 0000001 ..... ..... 011 ..... 0110011 @r 229div 0000001 ..... ..... 100 ..... 0110011 @r 230divu 0000001 ..... ..... 101 ..... 0110011 @r 231rem 0000001 ..... ..... 110 ..... 0110011 @r 232remu 0000001 ..... ..... 111 ..... 0110011 @r 233 234# *** RV64M Standard Extension (in addition to RV32M) *** 235mulw 0000001 ..... ..... 000 ..... 0111011 @r 236divw 0000001 ..... ..... 100 ..... 0111011 @r 237divuw 0000001 ..... ..... 101 ..... 0111011 @r 238remw 0000001 ..... ..... 110 ..... 0111011 @r 239remuw 0000001 ..... ..... 111 ..... 0111011 @r 240 241# *** RV128M Standard Extension (in addition to RV64M) *** 242muld 0000001 ..... ..... 000 ..... 1111011 @r 243divd 0000001 ..... ..... 100 ..... 1111011 @r 244divud 0000001 ..... ..... 101 ..... 1111011 @r 245remd 0000001 ..... ..... 110 ..... 1111011 @r 246remud 0000001 ..... ..... 111 ..... 1111011 @r 247 248# *** RV32A Standard Extension *** 249lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 250sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 251amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 252ssamoswap_w 01001 . . ..... ..... 010 ..... 0101111 @atom_st 253amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 254amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 255amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 256amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 257amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 258amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 259amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 260amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 261 262# *** RV64A Standard Extension (in addition to RV32A) *** 263lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld 264sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st 265amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st 266ssamoswap_d 01001 . . ..... ..... 011 ..... 0101111 @atom_st 267amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st 268amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st 269amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st 270amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st 271amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st 272amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st 273amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st 274amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st 275 276# *** RV32F Standard Extension *** 277flw ............ ..... 010 ..... 0000111 @i 278fsw ....... ..... ..... 010 ..... 0100111 @s 279fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 280fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 281fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 282fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 283fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 284fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 285fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 286fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 287fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 288fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 289fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 290fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 291fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 292fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 293fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 294fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 295fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 296feq_s 1010000 ..... ..... 010 ..... 1010011 @r 297flt_s 1010000 ..... ..... 001 ..... 1010011 @r 298fle_s 1010000 ..... ..... 000 ..... 1010011 @r 299fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 300fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 301fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 302fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 303 304# *** RV64F Standard Extension (in addition to RV32F) *** 305fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm 306fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm 307fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm 308fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm 309 310# *** RV32D Standard Extension *** 311fld ............ ..... 011 ..... 0000111 @i 312fsd ....... ..... ..... 011 ..... 0100111 @s 313fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 314fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 315fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 316fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 317fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 318fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 319fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 320fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 321fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 322fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 323fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 324fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 325fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 326fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 327fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 328fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 329feq_d 1010001 ..... ..... 010 ..... 1010011 @r 330flt_d 1010001 ..... ..... 001 ..... 1010011 @r 331fle_d 1010001 ..... ..... 000 ..... 1010011 @r 332fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 333fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 334fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 335fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 336fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 337 338# *** RV64D Standard Extension (in addition to RV32D) *** 339fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm 340fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm 341fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 342fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm 343fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm 344fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 345 346# *** RV32H Base Instruction Set *** 347hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 348hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 349hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 350hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 351hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 352hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 353hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 354hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s 355hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s 356hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s 357hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 358hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 359 360# *** RV64H Base Instruction Set *** 361hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 362hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 363hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s 364 365# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 366# Vector unit-stride load/store insns. 367vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 368vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 369vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 370vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 371vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 372vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 373vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 374vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 375 376# Vector unit-stride mask load/store insns. 377vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 378vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 379 380# Vector strided insns. 381vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 382vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 383vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 384vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 385vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 386vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 387vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 388vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 389 390# Vector ordered-indexed and unordered-indexed load insns. 391vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm 392vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm 393vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm 394vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm 395 396# Vector ordered-indexed and unordered-indexed store insns. 397vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm 398vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm 399vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm 400vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm 401 402# Vector unit-stride fault-only-first load insns. 403vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 404vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 405vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 406vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 407 408# Vector whole register insns 409vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 410vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 411vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 412vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 413vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 414vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 415vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 416vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 417vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 418vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 419vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 420vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 421vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 422vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 423vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 424vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 425vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 426vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 427vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 428vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 429 430# *** new major opcode OP-V *** 431vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 432vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 433vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 434vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 435vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 436vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 437vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 438vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 439vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 440vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 441vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 442vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 443vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 444vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 445vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 446vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 447vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 448vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 449vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 450vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 451vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 452vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 453vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 454vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 455vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 456vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 457vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm 458vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm 459vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm 460vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 461vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 462vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm 463vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm 464vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 465vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 466vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 467vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 468vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 469vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 470vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 471vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 472vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 473vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 474vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 475vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 476vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 477vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 478vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 479vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 480vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 481vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 482vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm 483vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm 484vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm 485vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm 486vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm 487vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm 488vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 489vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 490vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 491vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 492vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 493vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 494vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 495vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 496vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 497vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 498vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 499vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 500vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 501vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 502vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 503vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 504vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 505vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 506vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 507vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 508vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 509vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 510vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 511vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 512vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 513vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 514vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 515vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 516vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 517vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 518vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 519vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 520vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 521vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 522vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 523vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 524vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 525vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 526vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 527vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 528vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 529vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 530vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 531vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 532vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 533vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 534vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 535vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 536vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 537vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 538vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 539vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 540vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 541vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 542vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 543vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 544vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 545vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 546vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 547vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 548vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 549vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 550vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm 551vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 552vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 553vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 554vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 555vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 556vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 557vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 558vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 559vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 560vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 561vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 562vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 563vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 564vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 565vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 566vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 567vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 568vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 569vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm 570vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm 571vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm 572vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm 573vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm 574vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm 575vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm 576vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm 577vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 578vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 579vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm 580vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm 581vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm 582vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm 583vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm 584vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm 585vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm 586vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm 587vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm 588vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm 589vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm 590vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm 591vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm 592vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm 593vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm 594vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm 595vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm 596vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm 597vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm 598vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm 599vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm 600vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm 601vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm 602vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm 603vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm 604vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm 605vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm 606vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm 607vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm 608vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm 609vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm 610vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm 611vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm 612vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm 613vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm 614vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm 615vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm 616vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm 617vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm 618vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm 619vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm 620vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm 621vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm 622vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm 623vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm 624vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm 625vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm 626vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm 627vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm 628vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm 629vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm 630vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm 631vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm 632vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm 633vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm 634vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm 635vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm 636vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm 637vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm 638vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm 639vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm 640vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm 641vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm 642vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm 643vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm 644vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm 645vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 646vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 647vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 648vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm 649vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm 650vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 651vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 652vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 653vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 654vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 655vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 656vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 657vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 658vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 659vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 660vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm 661vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 662vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 663 664vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm 665vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm 666vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm 667vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm 668vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm 669vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm 670 671vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm 672vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm 673vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm 674vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm 675vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm 676vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm 677vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm 678 679vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm 680vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm 681vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm 682vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm 683vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm 684vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm 685vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm 686vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm 687 688vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm 689vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm 690vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm 691vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm 692vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm 693vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm 694vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm 695vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm 696vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm 697vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm 698# Vector ordered and unordered reduction sum 699vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm 700vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm 701vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm 702vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm 703# Vector widening ordered and unordered float reduction sum 704vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm 705vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm 706vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r 707vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r 708vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r 709vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r 710vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r 711vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r 712vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r 713vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r 714vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm 715vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm 716vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm 717vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm 718vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm 719viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm 720vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm 721vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd 722vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 723vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd 724vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 725vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm 726vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm 727vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm 728vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm 729vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm 730vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 731vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 732vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm 733vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 734vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 735vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 736vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd 737vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd 738vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd 739vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd 740 741# Vector Integer Extension 742vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm 743vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm 744vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm 745vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm 746vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm 747vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm 748 749vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 750vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 751vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 752 753# *** Zawrs Standard Extension *** 754wrs_nto 000000001101 00000 000 00000 1110011 755wrs_sto 000000011101 00000 000 00000 1110011 756 757# *** RV32 Zba Standard Extension *** 758sh1add 0010000 .......... 010 ..... 0110011 @r 759sh2add 0010000 .......... 100 ..... 0110011 @r 760sh3add 0010000 .......... 110 ..... 0110011 @r 761 762# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** 763add_uw 0000100 .......... 000 ..... 0111011 @r 764sh1add_uw 0010000 .......... 010 ..... 0111011 @r 765sh2add_uw 0010000 .......... 100 ..... 0111011 @r 766sh3add_uw 0010000 .......... 110 ..... 0111011 @r 767slli_uw 00001 ............ 001 ..... 0011011 @sh 768 769# *** RV32 Zbb/Zbkb Standard Extension *** 770andn 0100000 .......... 111 ..... 0110011 @r 771rol 0110000 .......... 001 ..... 0110011 @r 772ror 0110000 .......... 101 ..... 0110011 @r 773rori 01100 ............ 101 ..... 0010011 @sh 774# The encoding for rev8 differs between RV32 and RV64. 775# rev8_32 denotes the RV32 variant. 776rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 777# The encoding for zext.h differs between RV32 and RV64. 778# zext_h_32 denotes the RV32 variant. 779{ 780 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 781 pack 0000100 ..... ..... 100 ..... 0110011 @r 782} 783xnor 0100000 .......... 100 ..... 0110011 @r 784# *** RV32 extra Zbb Standard Extension *** 785clz 011000 000000 ..... 001 ..... 0010011 @r2 786cpop 011000 000010 ..... 001 ..... 0010011 @r2 787ctz 011000 000001 ..... 001 ..... 0010011 @r2 788max 0000101 .......... 110 ..... 0110011 @r 789maxu 0000101 .......... 111 ..... 0110011 @r 790min 0000101 .......... 100 ..... 0110011 @r 791minu 0000101 .......... 101 ..... 0110011 @r 792orc_b 001010 000111 ..... 101 ..... 0010011 @r2 793orn 0100000 .......... 110 ..... 0110011 @r 794sext_b 011000 000100 ..... 001 ..... 0010011 @r2 795sext_h 011000 000101 ..... 001 ..... 0010011 @r2 796# *** RV32 extra Zbkb Standard Extension *** 797brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi 798packh 0000100 .......... 111 ..... 0110011 @r 799unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl 800zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl 801 802# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) *** 803# The encoding for rev8 differs between RV32 and RV64. 804# When executing on RV64, the encoding used in RV32 is an illegal 805# instruction, so we use different handler functions to differentiate. 806rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 807rolw 0110000 .......... 001 ..... 0111011 @r 808roriw 0110000 .......... 101 ..... 0011011 @sh5 809rorw 0110000 .......... 101 ..... 0111011 @r 810# The encoding for zext.h differs between RV32 and RV64. 811# When executing on RV64, the encoding used in RV32 is an illegal 812# instruction, so we use different handler functions to differentiate. 813{ 814 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 815 packw 0000100 ..... ..... 100 ..... 0111011 @r 816} 817# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) *** 818clzw 0110000 00000 ..... 001 ..... 0011011 @r2 819ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 820cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 821 822# *** RV32 Zbc/Zbkc Standard Extension *** 823clmul 0000101 .......... 001 ..... 0110011 @r 824clmulh 0000101 .......... 011 ..... 0110011 @r 825# *** RV32 extra Zbc Standard Extension *** 826clmulr 0000101 .......... 010 ..... 0110011 @r 827 828# *** RV32 Zbkx Standard Extension *** 829xperm4 0010100 .......... 010 ..... 0110011 @r 830xperm8 0010100 .......... 100 ..... 0110011 @r 831 832# *** RV32 Zbs Standard Extension *** 833bclr 0100100 .......... 001 ..... 0110011 @r 834bclri 01001. ........... 001 ..... 0010011 @sh 835bext 0100100 .......... 101 ..... 0110011 @r 836bexti 01001. ........... 101 ..... 0010011 @sh 837binv 0110100 .......... 001 ..... 0110011 @r 838binvi 01101. ........... 001 ..... 0010011 @sh 839bset 0010100 .......... 001 ..... 0110011 @r 840bseti 00101. ........... 001 ..... 0010011 @sh 841 842# *** Zfa Standard Extension *** 843fli_s 1111000 00001 ..... 000 ..... 1010011 @r2 844fli_d 1111001 00001 ..... 000 ..... 1010011 @r2 845fli_h 1111010 00001 ..... 000 ..... 1010011 @r2 846fminm_s 0010100 ..... ..... 010 ..... 1010011 @r 847fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r 848fminm_d 0010101 ..... ..... 010 ..... 1010011 @r 849fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r 850fminm_h 0010110 ..... ..... 010 ..... 1010011 @r 851fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r 852fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm 853froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm 854fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm 855froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm 856fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm 857froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm 858fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2 859fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2 860fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r 861fleq_s 1010000 ..... ..... 100 ..... 1010011 @r 862fltq_s 1010000 ..... ..... 101 ..... 1010011 @r 863fleq_d 1010001 ..... ..... 100 ..... 1010011 @r 864fltq_d 1010001 ..... ..... 101 ..... 1010011 @r 865fleq_h 1010010 ..... ..... 100 ..... 1010011 @r 866fltq_h 1010010 ..... ..... 101 ..... 1010011 @r 867 868# *** RV32 Zfh Extension *** 869flh ............ ..... 001 ..... 0000111 @i 870fsh ....... ..... ..... 001 ..... 0100111 @s 871fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm 872fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm 873fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm 874fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm 875fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm 876fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm 877fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm 878fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm 879fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm 880fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r 881fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r 882fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r 883fmin_h 0010110 ..... ..... 000 ..... 1010011 @r 884fmax_h 0010110 ..... ..... 001 ..... 1010011 @r 885fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm 886fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm 887fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm 888fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm 889fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm 890fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm 891fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 892feq_h 1010010 ..... ..... 010 ..... 1010011 @r 893flt_h 1010010 ..... ..... 001 ..... 1010011 @r 894fle_h 1010010 ..... ..... 000 ..... 1010011 @r 895fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 896fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm 897fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm 898fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 899 900# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** 901fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm 902fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm 903fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm 904fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm 905 906# *** Svinval Standard Extension *** 907sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma 908sfence_w_inval 0001100 00000 00000 000 00000 1110011 909sfence_inval_ir 0001100 00001 00000 000 00000 1110011 910hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma 911hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma 912 913# *** RV32 Zknd Standard Extension *** 914aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes 915aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes 916# *** RV64 Zknd Standard Extension *** 917aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r 918aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r 919aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2 920# *** RV32 Zkne Standard Extension *** 921aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes 922aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes 923# *** RV64 Zkne Standard Extension *** 924aes64es 00 11001 ..... ..... 000 ..... 0110011 @r 925aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r 926# *** RV64 Zkne/zknd Standard Extension *** 927aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r 928aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes 929# *** RV32 Zknh Standard Extension *** 930sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 931sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 932sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 933sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 934sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r 935sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r 936sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r 937sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r 938sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r 939sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r 940# *** RV64 Zknh Standard Extension *** 941sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2 942sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2 943sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2 944sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2 945# *** RV32 Zksh Standard Extension *** 946sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2 947sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2 948# *** RV32 Zksed Standard Extension *** 949sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes 950sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes 951 952# *** RV32 Zicond Standard Extension *** 953czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r 954czero_nez 0000111 ..... ..... 111 ..... 0110011 @r 955 956# *** Zfbfmin Standard Extension *** 957fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm 958fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm 959 960# *** Zvfbfmin Standard Extension *** 961vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm 962vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm 963 964# *** Zvfbfwma Standard Extension *** 965vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm 966vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm 967 968# *** Zvbc vector crypto extension *** 969vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm 970vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm 971vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm 972vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm 973 974# *** Zvbb vector crypto extension *** 975vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm 976vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm 977vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm 978vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm 979vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 980vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm 981vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm 982vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm 983vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm 984vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm 985vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm 986vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm 987vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm 988vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm 989vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm 990vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm 991 992# *** Zvkned vector crypto extension *** 993vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 994vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 995vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 996vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 997vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 998vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 999vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 1000vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 1001vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 1002vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 1003vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 1004 1005# *** Zvknh vector crypto extension *** 1006vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 1007vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 1008vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 1009 1010# *** Zvksh vector crypto extension *** 1011vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 1012vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 1013 1014# *** Zvkg vector crypto extension *** 1015vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 1016vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 1017 1018# *** Zvksed vector crypto extension *** 1019vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 1020vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 1021vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 1022 1023# *** RV32 Zacas Standard Extension *** 1024amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st 1025amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st 1026# *** RV64 Zacas Standard Extension *** 1027amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st 1028 1029# *** Zimop may-be-operation extension *** 1030{ 1031 # zicfiss instructions carved out of mop.r 1032 [ 1033 ssrdp 1100110 11100 00000 100 rd:5 1110011 1034 sspopchk 1100110 11100 00001 100 00000 1110011 &r2 rs1=1 rd=0 1035 sspopchk 1100110 11100 00101 100 00000 1110011 &r2 rs1=5 rd=0 1036 ] 1037 mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 1110011 @mop5 1038} 1039{ 1040 # zicfiss instruction carved out of mop.rr 1041 [ 1042 sspush 1100111 00001 00000 100 00000 1110011 &r2_s rs2=1 rs1=0 1043 sspush 1100111 00101 00000 100 00000 1110011 &r2_s rs2=5 rs1=0 1044 ] 1045 mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 1110011 @mop3 1046} 1047 1048# *** Zabhb Standard Extension *** 1049amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st 1050amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st 1051amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st 1052amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st 1053amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st 1054amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st 1055amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st 1056amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st 1057amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st 1058amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st 1059amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st 1060amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st 1061amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st 1062amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st 1063amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st 1064amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st 1065amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st 1066amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st 1067amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st 1068amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st 1069