1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 75 get_field(env->mcounteren, HCOUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 81 get_field(env->mcounteren, HCOUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 87 get_field(env->mcounteren, HCOUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_is_32bit(env)) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 102 get_field(env->mcounteren, HCOUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 108 get_field(env->mcounteren, HCOUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 114 get_field(env->mcounteren, HCOUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (!riscv_cpu_is_32bit(env)) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (!riscv_cpu_is_32bit(env)) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (!riscv_cpu_is_32bit(env)) { 184 if (riscv_cpu_virt_enabled(env)) { 185 return RISCV_EXCP_ILLEGAL_INST; 186 } else { 187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 188 } 189 } 190 191 return hmode(env, csrno); 192 193 } 194 195 static RISCVException pmp(CPURISCVState *env, int csrno) 196 { 197 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 198 return RISCV_EXCP_NONE; 199 } 200 201 return RISCV_EXCP_ILLEGAL_INST; 202 } 203 204 static RISCVException epmp(CPURISCVState *env, int csrno) 205 { 206 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 207 return RISCV_EXCP_NONE; 208 } 209 210 return RISCV_EXCP_ILLEGAL_INST; 211 } 212 #endif 213 214 /* User Floating-Point CSRs */ 215 static RISCVException read_fflags(CPURISCVState *env, int csrno, 216 target_ulong *val) 217 { 218 *val = riscv_cpu_get_fflags(env); 219 return RISCV_EXCP_NONE; 220 } 221 222 static RISCVException write_fflags(CPURISCVState *env, int csrno, 223 target_ulong val) 224 { 225 #if !defined(CONFIG_USER_ONLY) 226 env->mstatus |= MSTATUS_FS; 227 #endif 228 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 229 return RISCV_EXCP_NONE; 230 } 231 232 static RISCVException read_frm(CPURISCVState *env, int csrno, 233 target_ulong *val) 234 { 235 *val = env->frm; 236 return RISCV_EXCP_NONE; 237 } 238 239 static RISCVException write_frm(CPURISCVState *env, int csrno, 240 target_ulong val) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 env->mstatus |= MSTATUS_FS; 244 #endif 245 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 246 return RISCV_EXCP_NONE; 247 } 248 249 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 250 target_ulong *val) 251 { 252 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 253 | (env->frm << FSR_RD_SHIFT); 254 if (vs(env, csrno) >= 0) { 255 *val |= (env->vxrm << FSR_VXRM_SHIFT) 256 | (env->vxsat << FSR_VXSAT_SHIFT); 257 } 258 return RISCV_EXCP_NONE; 259 } 260 261 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 262 target_ulong val) 263 { 264 #if !defined(CONFIG_USER_ONLY) 265 env->mstatus |= MSTATUS_FS; 266 #endif 267 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 268 if (vs(env, csrno) >= 0) { 269 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 270 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 271 } 272 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 273 return RISCV_EXCP_NONE; 274 } 275 276 static RISCVException read_vtype(CPURISCVState *env, int csrno, 277 target_ulong *val) 278 { 279 *val = env->vtype; 280 return RISCV_EXCP_NONE; 281 } 282 283 static RISCVException read_vl(CPURISCVState *env, int csrno, 284 target_ulong *val) 285 { 286 *val = env->vl; 287 return RISCV_EXCP_NONE; 288 } 289 290 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 291 target_ulong *val) 292 { 293 *val = env->vxrm; 294 return RISCV_EXCP_NONE; 295 } 296 297 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 298 target_ulong val) 299 { 300 env->vxrm = val; 301 return RISCV_EXCP_NONE; 302 } 303 304 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 305 target_ulong *val) 306 { 307 *val = env->vxsat; 308 return RISCV_EXCP_NONE; 309 } 310 311 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 312 target_ulong val) 313 { 314 env->vxsat = val; 315 return RISCV_EXCP_NONE; 316 } 317 318 static RISCVException read_vstart(CPURISCVState *env, int csrno, 319 target_ulong *val) 320 { 321 *val = env->vstart; 322 return RISCV_EXCP_NONE; 323 } 324 325 static RISCVException write_vstart(CPURISCVState *env, int csrno, 326 target_ulong val) 327 { 328 env->vstart = val; 329 return RISCV_EXCP_NONE; 330 } 331 332 /* User Timers and Counters */ 333 static RISCVException read_instret(CPURISCVState *env, int csrno, 334 target_ulong *val) 335 { 336 #if !defined(CONFIG_USER_ONLY) 337 if (icount_enabled()) { 338 *val = icount_get(); 339 } else { 340 *val = cpu_get_host_ticks(); 341 } 342 #else 343 *val = cpu_get_host_ticks(); 344 #endif 345 return RISCV_EXCP_NONE; 346 } 347 348 static RISCVException read_instreth(CPURISCVState *env, int csrno, 349 target_ulong *val) 350 { 351 #if !defined(CONFIG_USER_ONLY) 352 if (icount_enabled()) { 353 *val = icount_get() >> 32; 354 } else { 355 *val = cpu_get_host_ticks() >> 32; 356 } 357 #else 358 *val = cpu_get_host_ticks() >> 32; 359 #endif 360 return RISCV_EXCP_NONE; 361 } 362 363 #if defined(CONFIG_USER_ONLY) 364 static RISCVException read_time(CPURISCVState *env, int csrno, 365 target_ulong *val) 366 { 367 *val = cpu_get_host_ticks(); 368 return RISCV_EXCP_NONE; 369 } 370 371 static RISCVException read_timeh(CPURISCVState *env, int csrno, 372 target_ulong *val) 373 { 374 *val = cpu_get_host_ticks() >> 32; 375 return RISCV_EXCP_NONE; 376 } 377 378 #else /* CONFIG_USER_ONLY */ 379 380 static RISCVException read_time(CPURISCVState *env, int csrno, 381 target_ulong *val) 382 { 383 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 384 385 if (!env->rdtime_fn) { 386 return RISCV_EXCP_ILLEGAL_INST; 387 } 388 389 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 390 return RISCV_EXCP_NONE; 391 } 392 393 static RISCVException read_timeh(CPURISCVState *env, int csrno, 394 target_ulong *val) 395 { 396 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 397 398 if (!env->rdtime_fn) { 399 return RISCV_EXCP_ILLEGAL_INST; 400 } 401 402 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 403 return RISCV_EXCP_NONE; 404 } 405 406 /* Machine constants */ 407 408 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 409 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 410 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 411 412 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 413 VS_MODE_INTERRUPTS; 414 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 415 VS_MODE_INTERRUPTS; 416 static const target_ulong delegable_excps = 417 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 418 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 419 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 420 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 421 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 422 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 423 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 424 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 425 (1ULL << (RISCV_EXCP_U_ECALL)) | 426 (1ULL << (RISCV_EXCP_S_ECALL)) | 427 (1ULL << (RISCV_EXCP_VS_ECALL)) | 428 (1ULL << (RISCV_EXCP_M_ECALL)) | 429 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 430 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 431 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 432 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 433 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 434 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 435 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 436 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 437 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 438 SSTATUS_SUM | SSTATUS_MXR; 439 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 440 static const target_ulong hip_writable_mask = MIP_VSSIP; 441 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 442 static const target_ulong vsip_writable_mask = MIP_VSSIP; 443 444 static const char valid_vm_1_10_32[16] = { 445 [VM_1_10_MBARE] = 1, 446 [VM_1_10_SV32] = 1 447 }; 448 449 static const char valid_vm_1_10_64[16] = { 450 [VM_1_10_MBARE] = 1, 451 [VM_1_10_SV39] = 1, 452 [VM_1_10_SV48] = 1, 453 [VM_1_10_SV57] = 1 454 }; 455 456 /* Machine Information Registers */ 457 static RISCVException read_zero(CPURISCVState *env, int csrno, 458 target_ulong *val) 459 { 460 *val = 0; 461 return RISCV_EXCP_NONE; 462 } 463 464 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 465 target_ulong *val) 466 { 467 *val = env->mhartid; 468 return RISCV_EXCP_NONE; 469 } 470 471 /* Machine Trap Setup */ 472 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 473 target_ulong *val) 474 { 475 *val = env->mstatus; 476 return RISCV_EXCP_NONE; 477 } 478 479 static int validate_vm(CPURISCVState *env, target_ulong vm) 480 { 481 if (riscv_cpu_is_32bit(env)) { 482 return valid_vm_1_10_32[vm & 0xf]; 483 } else { 484 return valid_vm_1_10_64[vm & 0xf]; 485 } 486 } 487 488 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 489 target_ulong val) 490 { 491 uint64_t mstatus = env->mstatus; 492 uint64_t mask = 0; 493 int dirty; 494 495 /* flush tlb on mstatus fields that affect VM */ 496 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 497 MSTATUS_MPRV | MSTATUS_SUM)) { 498 tlb_flush(env_cpu(env)); 499 } 500 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 501 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 502 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 503 MSTATUS_TW; 504 505 if (!riscv_cpu_is_32bit(env)) { 506 /* 507 * RV32: MPV and GVA are not in mstatus. The current plan is to 508 * add them to mstatush. For now, we just don't support it. 509 */ 510 mask |= MSTATUS_MPV | MSTATUS_GVA; 511 } 512 513 mstatus = (mstatus & ~mask) | (val & mask); 514 515 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 516 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 517 if (riscv_cpu_is_32bit(env)) { 518 mstatus = set_field(mstatus, MSTATUS32_SD, dirty); 519 } else { 520 mstatus = set_field(mstatus, MSTATUS64_SD, dirty); 521 } 522 env->mstatus = mstatus; 523 524 return RISCV_EXCP_NONE; 525 } 526 527 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 528 target_ulong *val) 529 { 530 *val = env->mstatus >> 32; 531 return RISCV_EXCP_NONE; 532 } 533 534 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 535 target_ulong val) 536 { 537 uint64_t valh = (uint64_t)val << 32; 538 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 539 540 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 541 tlb_flush(env_cpu(env)); 542 } 543 544 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 545 546 return RISCV_EXCP_NONE; 547 } 548 549 static RISCVException read_misa(CPURISCVState *env, int csrno, 550 target_ulong *val) 551 { 552 *val = env->misa; 553 return RISCV_EXCP_NONE; 554 } 555 556 static RISCVException write_misa(CPURISCVState *env, int csrno, 557 target_ulong val) 558 { 559 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 560 /* drop write to misa */ 561 return RISCV_EXCP_NONE; 562 } 563 564 /* 'I' or 'E' must be present */ 565 if (!(val & (RVI | RVE))) { 566 /* It is not, drop write to misa */ 567 return RISCV_EXCP_NONE; 568 } 569 570 /* 'E' excludes all other extensions */ 571 if (val & RVE) { 572 /* when we support 'E' we can do "val = RVE;" however 573 * for now we just drop writes if 'E' is present. 574 */ 575 return RISCV_EXCP_NONE; 576 } 577 578 /* Mask extensions that are not supported by this hart */ 579 val &= env->misa_mask; 580 581 /* Mask extensions that are not supported by QEMU */ 582 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 583 584 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 585 if ((val & RVD) && !(val & RVF)) { 586 val &= ~RVD; 587 } 588 589 /* Suppress 'C' if next instruction is not aligned 590 * TODO: this should check next_pc 591 */ 592 if ((val & RVC) && (GETPC() & ~3) != 0) { 593 val &= ~RVC; 594 } 595 596 /* misa.MXL writes are not supported by QEMU */ 597 if (riscv_cpu_is_32bit(env)) { 598 val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); 599 } else { 600 val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); 601 } 602 603 /* flush translation cache */ 604 if (val != env->misa) { 605 tb_flush(env_cpu(env)); 606 } 607 608 env->misa = val; 609 610 return RISCV_EXCP_NONE; 611 } 612 613 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 614 target_ulong *val) 615 { 616 *val = env->medeleg; 617 return RISCV_EXCP_NONE; 618 } 619 620 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 621 target_ulong val) 622 { 623 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 624 return RISCV_EXCP_NONE; 625 } 626 627 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 628 target_ulong *val) 629 { 630 *val = env->mideleg; 631 return RISCV_EXCP_NONE; 632 } 633 634 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 635 target_ulong val) 636 { 637 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 638 if (riscv_has_ext(env, RVH)) { 639 env->mideleg |= VS_MODE_INTERRUPTS; 640 } 641 return RISCV_EXCP_NONE; 642 } 643 644 static RISCVException read_mie(CPURISCVState *env, int csrno, 645 target_ulong *val) 646 { 647 *val = env->mie; 648 return RISCV_EXCP_NONE; 649 } 650 651 static RISCVException write_mie(CPURISCVState *env, int csrno, 652 target_ulong val) 653 { 654 env->mie = (env->mie & ~all_ints) | (val & all_ints); 655 return RISCV_EXCP_NONE; 656 } 657 658 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 659 target_ulong *val) 660 { 661 *val = env->mtvec; 662 return RISCV_EXCP_NONE; 663 } 664 665 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 666 target_ulong val) 667 { 668 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 669 if ((val & 3) < 2) { 670 env->mtvec = val; 671 } else { 672 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 673 } 674 return RISCV_EXCP_NONE; 675 } 676 677 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 678 target_ulong *val) 679 { 680 *val = env->mcounteren; 681 return RISCV_EXCP_NONE; 682 } 683 684 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 685 target_ulong val) 686 { 687 env->mcounteren = val; 688 return RISCV_EXCP_NONE; 689 } 690 691 /* Machine Trap Handling */ 692 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 693 target_ulong *val) 694 { 695 *val = env->mscratch; 696 return RISCV_EXCP_NONE; 697 } 698 699 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 700 target_ulong val) 701 { 702 env->mscratch = val; 703 return RISCV_EXCP_NONE; 704 } 705 706 static RISCVException read_mepc(CPURISCVState *env, int csrno, 707 target_ulong *val) 708 { 709 *val = env->mepc; 710 return RISCV_EXCP_NONE; 711 } 712 713 static RISCVException write_mepc(CPURISCVState *env, int csrno, 714 target_ulong val) 715 { 716 env->mepc = val; 717 return RISCV_EXCP_NONE; 718 } 719 720 static RISCVException read_mcause(CPURISCVState *env, int csrno, 721 target_ulong *val) 722 { 723 *val = env->mcause; 724 return RISCV_EXCP_NONE; 725 } 726 727 static RISCVException write_mcause(CPURISCVState *env, int csrno, 728 target_ulong val) 729 { 730 env->mcause = val; 731 return RISCV_EXCP_NONE; 732 } 733 734 static RISCVException read_mtval(CPURISCVState *env, int csrno, 735 target_ulong *val) 736 { 737 *val = env->mtval; 738 return RISCV_EXCP_NONE; 739 } 740 741 static RISCVException write_mtval(CPURISCVState *env, int csrno, 742 target_ulong val) 743 { 744 env->mtval = val; 745 return RISCV_EXCP_NONE; 746 } 747 748 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 749 target_ulong *ret_value, 750 target_ulong new_value, target_ulong write_mask) 751 { 752 RISCVCPU *cpu = env_archcpu(env); 753 /* Allow software control of delegable interrupts not claimed by hardware */ 754 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 755 uint32_t old_mip; 756 757 if (mask) { 758 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 759 } else { 760 old_mip = env->mip; 761 } 762 763 if (ret_value) { 764 *ret_value = old_mip; 765 } 766 767 return RISCV_EXCP_NONE; 768 } 769 770 /* Supervisor Trap Setup */ 771 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 772 target_ulong *val) 773 { 774 target_ulong mask = (sstatus_v1_10_mask); 775 776 if (riscv_cpu_is_32bit(env)) { 777 mask |= SSTATUS32_SD; 778 } else { 779 mask |= SSTATUS64_SD; 780 } 781 782 *val = env->mstatus & mask; 783 return RISCV_EXCP_NONE; 784 } 785 786 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 787 target_ulong val) 788 { 789 target_ulong mask = (sstatus_v1_10_mask); 790 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 791 return write_mstatus(env, CSR_MSTATUS, newval); 792 } 793 794 static RISCVException read_vsie(CPURISCVState *env, int csrno, 795 target_ulong *val) 796 { 797 /* Shift the VS bits to their S bit location in vsie */ 798 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 799 return RISCV_EXCP_NONE; 800 } 801 802 static RISCVException read_sie(CPURISCVState *env, int csrno, 803 target_ulong *val) 804 { 805 if (riscv_cpu_virt_enabled(env)) { 806 read_vsie(env, CSR_VSIE, val); 807 } else { 808 *val = env->mie & env->mideleg; 809 } 810 return RISCV_EXCP_NONE; 811 } 812 813 static RISCVException write_vsie(CPURISCVState *env, int csrno, 814 target_ulong val) 815 { 816 /* Shift the S bits to their VS bit location in mie */ 817 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 818 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 819 return write_mie(env, CSR_MIE, newval); 820 } 821 822 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 823 { 824 if (riscv_cpu_virt_enabled(env)) { 825 write_vsie(env, CSR_VSIE, val); 826 } else { 827 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 828 (val & S_MODE_INTERRUPTS); 829 write_mie(env, CSR_MIE, newval); 830 } 831 832 return RISCV_EXCP_NONE; 833 } 834 835 static RISCVException read_stvec(CPURISCVState *env, int csrno, 836 target_ulong *val) 837 { 838 *val = env->stvec; 839 return RISCV_EXCP_NONE; 840 } 841 842 static RISCVException write_stvec(CPURISCVState *env, int csrno, 843 target_ulong val) 844 { 845 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 846 if ((val & 3) < 2) { 847 env->stvec = val; 848 } else { 849 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 850 } 851 return RISCV_EXCP_NONE; 852 } 853 854 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 855 target_ulong *val) 856 { 857 *val = env->scounteren; 858 return RISCV_EXCP_NONE; 859 } 860 861 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 862 target_ulong val) 863 { 864 env->scounteren = val; 865 return RISCV_EXCP_NONE; 866 } 867 868 /* Supervisor Trap Handling */ 869 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 870 target_ulong *val) 871 { 872 *val = env->sscratch; 873 return RISCV_EXCP_NONE; 874 } 875 876 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 877 target_ulong val) 878 { 879 env->sscratch = val; 880 return RISCV_EXCP_NONE; 881 } 882 883 static RISCVException read_sepc(CPURISCVState *env, int csrno, 884 target_ulong *val) 885 { 886 *val = env->sepc; 887 return RISCV_EXCP_NONE; 888 } 889 890 static RISCVException write_sepc(CPURISCVState *env, int csrno, 891 target_ulong val) 892 { 893 env->sepc = val; 894 return RISCV_EXCP_NONE; 895 } 896 897 static RISCVException read_scause(CPURISCVState *env, int csrno, 898 target_ulong *val) 899 { 900 *val = env->scause; 901 return RISCV_EXCP_NONE; 902 } 903 904 static RISCVException write_scause(CPURISCVState *env, int csrno, 905 target_ulong val) 906 { 907 env->scause = val; 908 return RISCV_EXCP_NONE; 909 } 910 911 static RISCVException read_stval(CPURISCVState *env, int csrno, 912 target_ulong *val) 913 { 914 *val = env->stval; 915 return RISCV_EXCP_NONE; 916 } 917 918 static RISCVException write_stval(CPURISCVState *env, int csrno, 919 target_ulong val) 920 { 921 env->stval = val; 922 return RISCV_EXCP_NONE; 923 } 924 925 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 926 target_ulong *ret_value, 927 target_ulong new_value, target_ulong write_mask) 928 { 929 /* Shift the S bits to their VS bit location in mip */ 930 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 931 (write_mask << 1) & vsip_writable_mask & env->hideleg); 932 *ret_value &= VS_MODE_INTERRUPTS; 933 /* Shift the VS bits to their S bit location in vsip */ 934 *ret_value >>= 1; 935 return ret; 936 } 937 938 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 939 target_ulong *ret_value, 940 target_ulong new_value, target_ulong write_mask) 941 { 942 int ret; 943 944 if (riscv_cpu_virt_enabled(env)) { 945 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 946 } else { 947 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 948 write_mask & env->mideleg & sip_writable_mask); 949 } 950 951 *ret_value &= env->mideleg; 952 return ret; 953 } 954 955 /* Supervisor Protection and Translation */ 956 static RISCVException read_satp(CPURISCVState *env, int csrno, 957 target_ulong *val) 958 { 959 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 960 *val = 0; 961 return RISCV_EXCP_NONE; 962 } 963 964 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 965 return RISCV_EXCP_ILLEGAL_INST; 966 } else { 967 *val = env->satp; 968 } 969 970 return RISCV_EXCP_NONE; 971 } 972 973 static RISCVException write_satp(CPURISCVState *env, int csrno, 974 target_ulong val) 975 { 976 int vm, mask, asid; 977 978 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 979 return RISCV_EXCP_NONE; 980 } 981 982 if (riscv_cpu_is_32bit(env)) { 983 vm = validate_vm(env, get_field(val, SATP32_MODE)); 984 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 985 asid = (val ^ env->satp) & SATP32_ASID; 986 } else { 987 vm = validate_vm(env, get_field(val, SATP64_MODE)); 988 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 989 asid = (val ^ env->satp) & SATP64_ASID; 990 } 991 992 if (vm && mask) { 993 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 994 return RISCV_EXCP_ILLEGAL_INST; 995 } else { 996 if (asid) { 997 tlb_flush(env_cpu(env)); 998 } 999 env->satp = val; 1000 } 1001 } 1002 return RISCV_EXCP_NONE; 1003 } 1004 1005 /* Hypervisor Extensions */ 1006 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1007 target_ulong *val) 1008 { 1009 *val = env->hstatus; 1010 if (!riscv_cpu_is_32bit(env)) { 1011 /* We only support 64-bit VSXL */ 1012 *val = set_field(*val, HSTATUS_VSXL, 2); 1013 } 1014 /* We only support little endian */ 1015 *val = set_field(*val, HSTATUS_VSBE, 0); 1016 return RISCV_EXCP_NONE; 1017 } 1018 1019 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1020 target_ulong val) 1021 { 1022 env->hstatus = val; 1023 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { 1024 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1025 } 1026 if (get_field(val, HSTATUS_VSBE) != 0) { 1027 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1028 } 1029 return RISCV_EXCP_NONE; 1030 } 1031 1032 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1033 target_ulong *val) 1034 { 1035 *val = env->hedeleg; 1036 return RISCV_EXCP_NONE; 1037 } 1038 1039 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1040 target_ulong val) 1041 { 1042 env->hedeleg = val; 1043 return RISCV_EXCP_NONE; 1044 } 1045 1046 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1047 target_ulong *val) 1048 { 1049 *val = env->hideleg; 1050 return RISCV_EXCP_NONE; 1051 } 1052 1053 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1054 target_ulong val) 1055 { 1056 env->hideleg = val; 1057 return RISCV_EXCP_NONE; 1058 } 1059 1060 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1061 target_ulong *ret_value, 1062 target_ulong new_value, target_ulong write_mask) 1063 { 1064 int ret = rmw_mip(env, 0, ret_value, new_value, 1065 write_mask & hvip_writable_mask); 1066 1067 *ret_value &= hvip_writable_mask; 1068 1069 return ret; 1070 } 1071 1072 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1073 target_ulong *ret_value, 1074 target_ulong new_value, target_ulong write_mask) 1075 { 1076 int ret = rmw_mip(env, 0, ret_value, new_value, 1077 write_mask & hip_writable_mask); 1078 1079 *ret_value &= hip_writable_mask; 1080 1081 return ret; 1082 } 1083 1084 static RISCVException read_hie(CPURISCVState *env, int csrno, 1085 target_ulong *val) 1086 { 1087 *val = env->mie & VS_MODE_INTERRUPTS; 1088 return RISCV_EXCP_NONE; 1089 } 1090 1091 static RISCVException write_hie(CPURISCVState *env, int csrno, 1092 target_ulong val) 1093 { 1094 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1095 return write_mie(env, CSR_MIE, newval); 1096 } 1097 1098 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1099 target_ulong *val) 1100 { 1101 *val = env->hcounteren; 1102 return RISCV_EXCP_NONE; 1103 } 1104 1105 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1106 target_ulong val) 1107 { 1108 env->hcounteren = val; 1109 return RISCV_EXCP_NONE; 1110 } 1111 1112 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 1113 target_ulong *val) 1114 { 1115 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1116 return RISCV_EXCP_NONE; 1117 } 1118 1119 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1120 target_ulong val) 1121 { 1122 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1123 return RISCV_EXCP_NONE; 1124 } 1125 1126 static RISCVException read_htval(CPURISCVState *env, int csrno, 1127 target_ulong *val) 1128 { 1129 *val = env->htval; 1130 return RISCV_EXCP_NONE; 1131 } 1132 1133 static RISCVException write_htval(CPURISCVState *env, int csrno, 1134 target_ulong val) 1135 { 1136 env->htval = val; 1137 return RISCV_EXCP_NONE; 1138 } 1139 1140 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1141 target_ulong *val) 1142 { 1143 *val = env->htinst; 1144 return RISCV_EXCP_NONE; 1145 } 1146 1147 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1148 target_ulong val) 1149 { 1150 return RISCV_EXCP_NONE; 1151 } 1152 1153 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 1154 target_ulong *val) 1155 { 1156 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1157 return RISCV_EXCP_NONE; 1158 } 1159 1160 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1161 target_ulong val) 1162 { 1163 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1164 return RISCV_EXCP_NONE; 1165 } 1166 1167 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1168 target_ulong *val) 1169 { 1170 *val = env->hgatp; 1171 return RISCV_EXCP_NONE; 1172 } 1173 1174 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1175 target_ulong val) 1176 { 1177 env->hgatp = val; 1178 return RISCV_EXCP_NONE; 1179 } 1180 1181 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1182 target_ulong *val) 1183 { 1184 if (!env->rdtime_fn) { 1185 return RISCV_EXCP_ILLEGAL_INST; 1186 } 1187 1188 *val = env->htimedelta; 1189 return RISCV_EXCP_NONE; 1190 } 1191 1192 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1193 target_ulong val) 1194 { 1195 if (!env->rdtime_fn) { 1196 return RISCV_EXCP_ILLEGAL_INST; 1197 } 1198 1199 if (riscv_cpu_is_32bit(env)) { 1200 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1201 } else { 1202 env->htimedelta = val; 1203 } 1204 return RISCV_EXCP_NONE; 1205 } 1206 1207 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1208 target_ulong *val) 1209 { 1210 if (!env->rdtime_fn) { 1211 return RISCV_EXCP_ILLEGAL_INST; 1212 } 1213 1214 *val = env->htimedelta >> 32; 1215 return RISCV_EXCP_NONE; 1216 } 1217 1218 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1219 target_ulong val) 1220 { 1221 if (!env->rdtime_fn) { 1222 return RISCV_EXCP_ILLEGAL_INST; 1223 } 1224 1225 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1226 return RISCV_EXCP_NONE; 1227 } 1228 1229 /* Virtual CSR Registers */ 1230 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1231 target_ulong *val) 1232 { 1233 *val = env->vsstatus; 1234 return RISCV_EXCP_NONE; 1235 } 1236 1237 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1238 target_ulong val) 1239 { 1240 uint64_t mask = (target_ulong)-1; 1241 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1242 return RISCV_EXCP_NONE; 1243 } 1244 1245 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1246 { 1247 *val = env->vstvec; 1248 return RISCV_EXCP_NONE; 1249 } 1250 1251 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1252 target_ulong val) 1253 { 1254 env->vstvec = val; 1255 return RISCV_EXCP_NONE; 1256 } 1257 1258 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1259 target_ulong *val) 1260 { 1261 *val = env->vsscratch; 1262 return RISCV_EXCP_NONE; 1263 } 1264 1265 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1266 target_ulong val) 1267 { 1268 env->vsscratch = val; 1269 return RISCV_EXCP_NONE; 1270 } 1271 1272 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1273 target_ulong *val) 1274 { 1275 *val = env->vsepc; 1276 return RISCV_EXCP_NONE; 1277 } 1278 1279 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1280 target_ulong val) 1281 { 1282 env->vsepc = val; 1283 return RISCV_EXCP_NONE; 1284 } 1285 1286 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1287 target_ulong *val) 1288 { 1289 *val = env->vscause; 1290 return RISCV_EXCP_NONE; 1291 } 1292 1293 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1294 target_ulong val) 1295 { 1296 env->vscause = val; 1297 return RISCV_EXCP_NONE; 1298 } 1299 1300 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1301 target_ulong *val) 1302 { 1303 *val = env->vstval; 1304 return RISCV_EXCP_NONE; 1305 } 1306 1307 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1308 target_ulong val) 1309 { 1310 env->vstval = val; 1311 return RISCV_EXCP_NONE; 1312 } 1313 1314 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1315 target_ulong *val) 1316 { 1317 *val = env->vsatp; 1318 return RISCV_EXCP_NONE; 1319 } 1320 1321 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1322 target_ulong val) 1323 { 1324 env->vsatp = val; 1325 return RISCV_EXCP_NONE; 1326 } 1327 1328 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1329 target_ulong *val) 1330 { 1331 *val = env->mtval2; 1332 return RISCV_EXCP_NONE; 1333 } 1334 1335 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1336 target_ulong val) 1337 { 1338 env->mtval2 = val; 1339 return RISCV_EXCP_NONE; 1340 } 1341 1342 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1343 target_ulong *val) 1344 { 1345 *val = env->mtinst; 1346 return RISCV_EXCP_NONE; 1347 } 1348 1349 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1350 target_ulong val) 1351 { 1352 env->mtinst = val; 1353 return RISCV_EXCP_NONE; 1354 } 1355 1356 /* Physical Memory Protection */ 1357 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1358 target_ulong *val) 1359 { 1360 *val = mseccfg_csr_read(env); 1361 return RISCV_EXCP_NONE; 1362 } 1363 1364 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1365 target_ulong val) 1366 { 1367 mseccfg_csr_write(env, val); 1368 return RISCV_EXCP_NONE; 1369 } 1370 1371 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1372 target_ulong *val) 1373 { 1374 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1375 return RISCV_EXCP_NONE; 1376 } 1377 1378 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1379 target_ulong val) 1380 { 1381 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1382 return RISCV_EXCP_NONE; 1383 } 1384 1385 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1386 target_ulong *val) 1387 { 1388 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1389 return RISCV_EXCP_NONE; 1390 } 1391 1392 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1393 target_ulong val) 1394 { 1395 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1396 return RISCV_EXCP_NONE; 1397 } 1398 1399 #endif 1400 1401 /* 1402 * riscv_csrrw - read and/or update control and status register 1403 * 1404 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1405 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1406 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1407 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1408 */ 1409 1410 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1411 target_ulong *ret_value, 1412 target_ulong new_value, target_ulong write_mask) 1413 { 1414 RISCVException ret; 1415 target_ulong old_value; 1416 RISCVCPU *cpu = env_archcpu(env); 1417 1418 /* check privileges and return -1 if check fails */ 1419 #if !defined(CONFIG_USER_ONLY) 1420 int effective_priv = env->priv; 1421 int read_only = get_field(csrno, 0xC00) == 3; 1422 1423 if (riscv_has_ext(env, RVH) && 1424 env->priv == PRV_S && 1425 !riscv_cpu_virt_enabled(env)) { 1426 /* 1427 * We are in S mode without virtualisation, therefore we are in HS Mode. 1428 * Add 1 to the effective privledge level to allow us to access the 1429 * Hypervisor CSRs. 1430 */ 1431 effective_priv++; 1432 } 1433 1434 if ((write_mask && read_only) || 1435 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1436 return RISCV_EXCP_ILLEGAL_INST; 1437 } 1438 #endif 1439 1440 /* ensure the CSR extension is enabled. */ 1441 if (!cpu->cfg.ext_icsr) { 1442 return RISCV_EXCP_ILLEGAL_INST; 1443 } 1444 1445 /* check predicate */ 1446 if (!csr_ops[csrno].predicate) { 1447 return RISCV_EXCP_ILLEGAL_INST; 1448 } 1449 ret = csr_ops[csrno].predicate(env, csrno); 1450 if (ret != RISCV_EXCP_NONE) { 1451 return ret; 1452 } 1453 1454 /* execute combined read/write operation if it exists */ 1455 if (csr_ops[csrno].op) { 1456 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1457 } 1458 1459 /* if no accessor exists then return failure */ 1460 if (!csr_ops[csrno].read) { 1461 return RISCV_EXCP_ILLEGAL_INST; 1462 } 1463 /* read old value */ 1464 ret = csr_ops[csrno].read(env, csrno, &old_value); 1465 if (ret != RISCV_EXCP_NONE) { 1466 return ret; 1467 } 1468 1469 /* write value if writable and write mask set, otherwise drop writes */ 1470 if (write_mask) { 1471 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1472 if (csr_ops[csrno].write) { 1473 ret = csr_ops[csrno].write(env, csrno, new_value); 1474 if (ret != RISCV_EXCP_NONE) { 1475 return ret; 1476 } 1477 } 1478 } 1479 1480 /* return old value */ 1481 if (ret_value) { 1482 *ret_value = old_value; 1483 } 1484 1485 return RISCV_EXCP_NONE; 1486 } 1487 1488 /* 1489 * Debugger support. If not in user mode, set env->debugger before the 1490 * riscv_csrrw call and clear it after the call. 1491 */ 1492 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1493 target_ulong *ret_value, 1494 target_ulong new_value, 1495 target_ulong write_mask) 1496 { 1497 RISCVException ret; 1498 #if !defined(CONFIG_USER_ONLY) 1499 env->debugger = true; 1500 #endif 1501 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1502 #if !defined(CONFIG_USER_ONLY) 1503 env->debugger = false; 1504 #endif 1505 return ret; 1506 } 1507 1508 /* Control and Status Register function table */ 1509 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1510 /* User Floating-Point CSRs */ 1511 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1512 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1513 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1514 /* Vector CSRs */ 1515 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1516 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1517 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1518 [CSR_VL] = { "vl", vs, read_vl }, 1519 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1520 /* User Timers and Counters */ 1521 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1522 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1523 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1524 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1525 1526 /* 1527 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1528 * rdtime callback is not provided by machine/platform emulation. 1529 */ 1530 [CSR_TIME] = { "time", ctr, read_time }, 1531 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1532 1533 #if !defined(CONFIG_USER_ONLY) 1534 /* Machine Timers and Counters */ 1535 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1536 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1537 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1538 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1539 1540 /* Machine Information Registers */ 1541 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1542 [CSR_MARCHID] = { "marchid", any, read_zero }, 1543 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1544 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1545 1546 /* Machine Trap Setup */ 1547 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1548 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1549 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1550 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1551 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1552 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1553 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1554 1555 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1556 1557 /* Machine Trap Handling */ 1558 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1559 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1560 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1561 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1562 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1563 1564 /* Supervisor Trap Setup */ 1565 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1566 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1567 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1568 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1569 1570 /* Supervisor Trap Handling */ 1571 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1572 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1573 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1574 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1575 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1576 1577 /* Supervisor Protection and Translation */ 1578 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1579 1580 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1581 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1582 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1583 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1584 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1585 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1586 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1587 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, 1588 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1589 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1590 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, 1591 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1592 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1593 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1594 1595 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1596 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1597 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1598 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1599 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1600 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1601 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1602 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1603 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1604 1605 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1606 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1607 1608 /* Physical Memory Protection */ 1609 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1610 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1611 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1612 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1613 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1614 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1615 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1616 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1617 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1618 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1619 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1620 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1621 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1622 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1623 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1624 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1625 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1626 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1627 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1628 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1629 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1630 1631 /* Performance Counters */ 1632 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1633 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1634 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1635 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1636 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1637 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1638 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1639 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1640 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1641 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1642 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1643 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1644 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1645 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1646 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1647 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1648 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1649 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1650 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1651 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1652 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1653 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1654 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1655 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1656 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1657 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1658 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1659 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1660 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1661 1662 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1663 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1664 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1665 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1666 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1667 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1668 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1669 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1670 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1671 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1672 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1673 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1674 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1675 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1676 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1677 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1678 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1679 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1680 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1681 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1682 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1683 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1684 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1685 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 1686 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 1687 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 1688 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 1689 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 1690 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 1691 1692 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 1693 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 1694 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 1695 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 1696 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 1697 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 1698 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 1699 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 1700 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 1701 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 1702 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 1703 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 1704 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 1705 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 1706 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 1707 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 1708 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 1709 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 1710 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 1711 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 1712 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 1713 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 1714 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 1715 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 1716 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 1717 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 1718 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 1719 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 1720 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 1721 1722 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 1723 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 1724 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 1725 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 1726 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 1727 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 1728 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 1729 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 1730 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 1731 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 1732 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 1733 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 1734 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 1735 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 1736 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 1737 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 1738 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 1739 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 1740 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 1741 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 1742 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 1743 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 1744 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 1745 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 1746 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 1747 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 1748 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 1749 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 1750 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 1751 1752 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 1753 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 1754 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 1755 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 1756 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 1757 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 1758 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 1759 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 1760 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 1761 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 1762 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 1763 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 1764 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 1765 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 1766 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 1767 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 1768 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 1769 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 1770 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 1771 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 1772 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 1773 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 1774 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 1775 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 1776 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 1777 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 1778 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 1779 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 1780 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 1781 #endif /* !CONFIG_USER_ONLY */ 1782 }; 1783