1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/gdbstub.h" 28 #include "qemu/cpu-float.h" 29 #include "qom/object.h" 30 #include "qemu/int128.h" 31 #include "cpu_bits.h" 32 #include "cpu_cfg.h" 33 #include "qapi/qapi-types-common.h" 34 #include "cpu-qom.h" 35 36 typedef struct CPUArchState CPURISCVState; 37 38 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 39 40 #if defined(TARGET_RISCV32) 41 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 42 #elif defined(TARGET_RISCV64) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 44 #endif 45 46 /* 47 * RISC-V-specific extra insn start words: 48 * 1: Original instruction opcode 49 * 2: more information about instruction 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 2 52 /* 53 * b0: Whether a instruction always raise a store AMO or not. 54 */ 55 #define RISCV_UW2_ALWAYS_STORE_AMO 1 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 /* 60 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 61 * when adding new MISA bits here. 62 */ 63 #define RVI RV('I') 64 #define RVE RV('E') /* E and I are mutually exclusive */ 65 #define RVM RV('M') 66 #define RVA RV('A') 67 #define RVF RV('F') 68 #define RVD RV('D') 69 #define RVV RV('V') 70 #define RVC RV('C') 71 #define RVS RV('S') 72 #define RVU RV('U') 73 #define RVH RV('H') 74 #define RVG RV('G') 75 #define RVB RV('B') 76 77 extern const uint32_t misa_bits[]; 78 const char *riscv_get_misa_ext_name(uint32_t bit); 79 const char *riscv_get_misa_ext_description(uint32_t bit); 80 81 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 82 83 typedef struct riscv_cpu_profile { 84 struct riscv_cpu_profile *parent; 85 const char *name; 86 uint32_t misa_ext; 87 bool enabled; 88 bool user_set; 89 int priv_spec; 90 int satp_mode; 91 const int32_t ext_offsets[]; 92 } RISCVCPUProfile; 93 94 #define RISCV_PROFILE_EXT_LIST_END -1 95 #define RISCV_PROFILE_ATTR_UNUSED -1 96 97 extern RISCVCPUProfile *riscv_profiles[]; 98 99 /* Privileged specification version */ 100 #define PRIV_VER_1_10_0_STR "v1.10.0" 101 #define PRIV_VER_1_11_0_STR "v1.11.0" 102 #define PRIV_VER_1_12_0_STR "v1.12.0" 103 #define PRIV_VER_1_13_0_STR "v1.13.0" 104 enum { 105 PRIV_VERSION_1_10_0 = 0, 106 PRIV_VERSION_1_11_0, 107 PRIV_VERSION_1_12_0, 108 PRIV_VERSION_1_13_0, 109 110 PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, 111 }; 112 113 #define VEXT_VERSION_1_00_0 0x00010000 114 #define VEXT_VER_1_00_0_STR "v1.0" 115 116 enum { 117 TRANSLATE_SUCCESS, 118 TRANSLATE_FAIL, 119 TRANSLATE_PMP_FAIL, 120 TRANSLATE_G_STAGE_FAIL 121 }; 122 123 /* Extension context status */ 124 typedef enum { 125 EXT_STATUS_DISABLED = 0, 126 EXT_STATUS_INITIAL, 127 EXT_STATUS_CLEAN, 128 EXT_STATUS_DIRTY, 129 } RISCVExtStatus; 130 131 /* Enum holds PMM field values for Zjpm v1.0 extension */ 132 typedef enum { 133 PMM_FIELD_DISABLED = 0, 134 PMM_FIELD_RESERVED = 1, 135 PMM_FIELD_PMLEN7 = 2, 136 PMM_FIELD_PMLEN16 = 3, 137 } RISCVPmPmm; 138 139 typedef struct riscv_cpu_implied_exts_rule { 140 #ifndef CONFIG_USER_ONLY 141 /* 142 * Bitmask indicates the rule enabled status for the harts. 143 * This enhancement is only available in system-mode QEMU, 144 * as we don't have a good way (e.g. mhartid) to distinguish 145 * the SMP cores in user-mode QEMU. 146 */ 147 unsigned long *enabled; 148 #endif 149 /* True if this is a MISA implied rule. */ 150 bool is_misa; 151 /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ 152 const uint32_t ext; 153 const uint32_t implied_misa_exts; 154 const uint32_t implied_multi_exts[]; 155 } RISCVCPUImpliedExtsRule; 156 157 extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; 158 extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; 159 160 #define RISCV_IMPLIED_EXTS_RULE_END -1 161 162 #define MMU_USER_IDX 3 163 164 #define MAX_RISCV_PMPS (16) 165 166 #if !defined(CONFIG_USER_ONLY) 167 #include "pmp.h" 168 #include "debug.h" 169 #endif 170 171 #define RV_VLEN_MAX 1024 172 #define RV_MAX_MHPMEVENTS 32 173 #define RV_MAX_MHPMCOUNTERS 32 174 175 FIELD(VTYPE, VLMUL, 0, 3) 176 FIELD(VTYPE, VSEW, 3, 3) 177 FIELD(VTYPE, VTA, 6, 1) 178 FIELD(VTYPE, VMA, 7, 1) 179 FIELD(VTYPE, VEDIV, 8, 2) 180 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 181 182 typedef struct PMUCTRState { 183 /* Current value of a counter */ 184 target_ulong mhpmcounter_val; 185 /* Current value of a counter in RV32 */ 186 target_ulong mhpmcounterh_val; 187 /* Snapshot values of counter */ 188 target_ulong mhpmcounter_prev; 189 /* Snapshort value of a counter in RV32 */ 190 target_ulong mhpmcounterh_prev; 191 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 192 target_ulong irq_overflow_left; 193 } PMUCTRState; 194 195 typedef struct PMUFixedCtrState { 196 /* Track cycle and icount for each privilege mode */ 197 uint64_t counter[4]; 198 uint64_t counter_prev[4]; 199 /* Track cycle and icount for each privilege mode when V = 1*/ 200 uint64_t counter_virt[2]; 201 uint64_t counter_virt_prev[2]; 202 } PMUFixedCtrState; 203 204 struct CPUArchState { 205 target_ulong gpr[32]; 206 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 207 208 /* vector coprocessor state. */ 209 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 210 target_ulong vxrm; 211 target_ulong vxsat; 212 target_ulong vl; 213 target_ulong vstart; 214 target_ulong vtype; 215 bool vill; 216 217 target_ulong pc; 218 target_ulong load_res; 219 target_ulong load_val; 220 221 /* Floating-Point state */ 222 uint64_t fpr[32]; /* assume both F and D extensions */ 223 target_ulong frm; 224 float_status fp_status; 225 226 target_ulong badaddr; 227 target_ulong bins; 228 229 target_ulong guest_phys_fault_addr; 230 231 target_ulong priv_ver; 232 target_ulong vext_ver; 233 234 /* RISCVMXL, but uint32_t for vmstate migration */ 235 uint32_t misa_mxl; /* current mxl */ 236 uint32_t misa_ext; /* current extensions */ 237 uint32_t misa_ext_mask; /* max ext for this cpu */ 238 uint32_t xl; /* current xlen */ 239 240 /* 128-bit helpers upper part return value */ 241 target_ulong retxh; 242 243 target_ulong jvt; 244 245 /* elp state for zicfilp extension */ 246 bool elp; 247 /* shadow stack register for zicfiss extension */ 248 target_ulong ssp; 249 /* env place holder for extra word 2 during unwind */ 250 target_ulong excp_uw2; 251 /* sw check code for sw check exception */ 252 target_ulong sw_check_code; 253 #ifdef CONFIG_USER_ONLY 254 uint32_t elf_flags; 255 #endif 256 257 target_ulong priv; 258 /* CSRs for execution environment configuration */ 259 uint64_t menvcfg; 260 target_ulong senvcfg; 261 262 #ifndef CONFIG_USER_ONLY 263 /* This contains QEMU specific information about the virt state. */ 264 bool virt_enabled; 265 target_ulong geilen; 266 uint64_t resetvec; 267 268 target_ulong mhartid; 269 /* 270 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 271 * For RV64 this is a 64-bit mstatus. 272 */ 273 uint64_t mstatus; 274 275 uint64_t mip; 276 /* 277 * MIP contains the software writable version of SEIP ORed with the 278 * external interrupt value. The MIP register is always up-to-date. 279 * To keep track of the current source, we also save booleans of the values 280 * here. 281 */ 282 bool external_seip; 283 bool software_seip; 284 285 uint64_t miclaim; 286 287 uint64_t mie; 288 uint64_t mideleg; 289 290 /* 291 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 292 * alias of mie[i] and needs to be maintained separately. 293 */ 294 uint64_t sie; 295 296 /* 297 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 298 * alias of sie[i] (mie[i]) and needs to be maintained separately. 299 */ 300 uint64_t vsie; 301 302 target_ulong satp; /* since: priv-1.10.0 */ 303 target_ulong stval; 304 target_ulong medeleg; 305 306 target_ulong stvec; 307 target_ulong sepc; 308 target_ulong scause; 309 310 target_ulong mtvec; 311 target_ulong mepc; 312 target_ulong mcause; 313 target_ulong mtval; /* since: priv-1.10.0 */ 314 315 /* Machine and Supervisor interrupt priorities */ 316 uint8_t miprio[64]; 317 uint8_t siprio[64]; 318 319 /* AIA CSRs */ 320 target_ulong miselect; 321 target_ulong siselect; 322 uint64_t mvien; 323 uint64_t mvip; 324 325 /* Hypervisor CSRs */ 326 target_ulong hstatus; 327 target_ulong hedeleg; 328 uint64_t hideleg; 329 uint32_t hcounteren; 330 target_ulong htval; 331 target_ulong htinst; 332 target_ulong hgatp; 333 target_ulong hgeie; 334 target_ulong hgeip; 335 uint64_t htimedelta; 336 uint64_t hvien; 337 338 /* 339 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 340 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 341 * maintain in hvip. 342 */ 343 uint64_t hvip; 344 345 /* Hypervisor controlled virtual interrupt priorities */ 346 target_ulong hvictl; 347 uint8_t hviprio[64]; 348 349 /* Upper 64-bits of 128-bit CSRs */ 350 uint64_t mscratchh; 351 uint64_t sscratchh; 352 353 /* Virtual CSRs */ 354 /* 355 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 356 * For RV64 this is a 64-bit vsstatus. 357 */ 358 uint64_t vsstatus; 359 target_ulong vstvec; 360 target_ulong vsscratch; 361 target_ulong vsepc; 362 target_ulong vscause; 363 target_ulong vstval; 364 target_ulong vsatp; 365 366 /* AIA VS-mode CSRs */ 367 target_ulong vsiselect; 368 369 target_ulong mtval2; 370 target_ulong mtinst; 371 372 /* HS Backup CSRs */ 373 target_ulong stvec_hs; 374 target_ulong sscratch_hs; 375 target_ulong sepc_hs; 376 target_ulong scause_hs; 377 target_ulong stval_hs; 378 target_ulong satp_hs; 379 uint64_t mstatus_hs; 380 381 /* 382 * Signals whether the current exception occurred with two-stage address 383 * translation active. 384 */ 385 bool two_stage_lookup; 386 /* 387 * Signals whether the current exception occurred while doing two-stage 388 * address translation for the VS-stage page table walk. 389 */ 390 bool two_stage_indirect_lookup; 391 392 uint32_t scounteren; 393 uint32_t mcounteren; 394 395 uint32_t scountinhibit; 396 uint32_t mcountinhibit; 397 398 /* PMU cycle & instret privilege mode filtering */ 399 target_ulong mcyclecfg; 400 target_ulong mcyclecfgh; 401 target_ulong minstretcfg; 402 target_ulong minstretcfgh; 403 404 /* PMU counter state */ 405 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 406 407 /* PMU event selector configured values. First three are unused */ 408 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 409 410 /* PMU event selector configured values for RV32 */ 411 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 412 413 PMUFixedCtrState pmu_fixed_ctrs[2]; 414 415 target_ulong sscratch; 416 target_ulong mscratch; 417 418 /* Sstc CSRs */ 419 uint64_t stimecmp; 420 421 uint64_t vstimecmp; 422 423 /* physical memory protection */ 424 pmp_table_t pmp_state; 425 target_ulong mseccfg; 426 427 /* trigger module */ 428 target_ulong trigger_cur; 429 target_ulong tdata1[RV_MAX_TRIGGERS]; 430 target_ulong tdata2[RV_MAX_TRIGGERS]; 431 target_ulong tdata3[RV_MAX_TRIGGERS]; 432 target_ulong mcontext; 433 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 434 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 435 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 436 int64_t last_icount; 437 bool itrigger_enabled; 438 439 /* machine specific rdtime callback */ 440 uint64_t (*rdtime_fn)(void *); 441 void *rdtime_fn_arg; 442 443 /* machine specific AIA ireg read-modify-write callback */ 444 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 445 ((((__xlen) & 0xff) << 24) | \ 446 (((__vgein) & 0x3f) << 20) | \ 447 (((__virt) & 0x1) << 18) | \ 448 (((__priv) & 0x3) << 16) | \ 449 (__isel & 0xffff)) 450 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 451 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 452 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 453 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 454 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 455 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 456 target_ulong *val, target_ulong new_val, target_ulong write_mask); 457 void *aia_ireg_rmw_fn_arg[4]; 458 459 /* True if in debugger mode. */ 460 bool debugger; 461 462 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 463 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 464 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 465 uint64_t henvcfg; 466 #endif 467 468 /* Fields from here on are preserved across CPU reset. */ 469 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 470 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 471 bool vstime_irq; 472 473 hwaddr kernel_addr; 474 hwaddr fdt_addr; 475 476 #ifdef CONFIG_KVM 477 /* kvm timer */ 478 bool kvm_timer_dirty; 479 uint64_t kvm_timer_time; 480 uint64_t kvm_timer_compare; 481 uint64_t kvm_timer_state; 482 uint64_t kvm_timer_frequency; 483 #endif /* CONFIG_KVM */ 484 485 /* RNMI */ 486 target_ulong mnscratch; 487 target_ulong mnepc; 488 target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ 489 target_ulong mnstatus; 490 target_ulong rnmip; 491 uint64_t rnmi_irqvec; 492 uint64_t rnmi_excpvec; 493 }; 494 495 /* 496 * RISCVCPU: 497 * @env: #CPURISCVState 498 * 499 * A RISCV CPU. 500 */ 501 struct ArchCPU { 502 CPUState parent_obj; 503 504 CPURISCVState env; 505 506 GDBFeature dyn_csr_feature; 507 GDBFeature dyn_vreg_feature; 508 509 /* Configuration Settings */ 510 RISCVCPUConfig cfg; 511 512 QEMUTimer *pmu_timer; 513 /* A bitmask of Available programmable counters */ 514 uint32_t pmu_avail_ctrs; 515 /* Mapping of events to counters */ 516 GHashTable *pmu_event_ctr_map; 517 const GPtrArray *decoders; 518 }; 519 520 /** 521 * RISCVCPUClass: 522 * @parent_realize: The parent class' realize handler. 523 * @parent_phases: The parent class' reset phase handlers. 524 * 525 * A RISCV CPU model. 526 */ 527 struct RISCVCPUClass { 528 CPUClass parent_class; 529 530 DeviceRealize parent_realize; 531 ResettablePhases parent_phases; 532 uint32_t misa_mxl_max; /* max mxl for this cpu */ 533 }; 534 535 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 536 { 537 return (env->misa_ext & ext) != 0; 538 } 539 540 #include "cpu_user.h" 541 542 extern const char * const riscv_int_regnames[]; 543 extern const char * const riscv_int_regnamesh[]; 544 extern const char * const riscv_fpr_regnames[]; 545 546 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 547 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 548 int cpuid, DumpState *s); 549 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 550 int cpuid, DumpState *s); 551 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 552 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 553 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 554 uint8_t riscv_cpu_default_priority(int irq); 555 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 556 int riscv_cpu_mirq_pending(CPURISCVState *env); 557 int riscv_cpu_sirq_pending(CPURISCVState *env); 558 int riscv_cpu_vsirq_pending(CPURISCVState *env); 559 bool riscv_cpu_fp_enabled(CPURISCVState *env); 560 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 561 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 562 bool riscv_cpu_vector_enabled(CPURISCVState *env); 563 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 564 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 565 bool cpu_get_fcfien(CPURISCVState *env); 566 bool cpu_get_bcfien(CPURISCVState *env); 567 bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); 568 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 569 MMUAccessType access_type, 570 int mmu_idx, uintptr_t retaddr); 571 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 572 MMUAccessType access_type, int mmu_idx, 573 bool probe, uintptr_t retaddr); 574 char *riscv_isa_string(RISCVCPU *cpu); 575 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 576 bool riscv_cpu_option_set(const char *optname); 577 578 #ifndef CONFIG_USER_ONLY 579 void riscv_cpu_do_interrupt(CPUState *cpu); 580 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 581 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 582 vaddr addr, unsigned size, 583 MMUAccessType access_type, 584 int mmu_idx, MemTxAttrs attrs, 585 MemTxResult response, uintptr_t retaddr); 586 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 587 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 588 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 589 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 590 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 591 uint64_t value); 592 void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); 593 void riscv_cpu_interrupt(CPURISCVState *env); 594 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 595 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 596 void *arg); 597 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 598 int (*rmw_fn)(void *arg, 599 target_ulong reg, 600 target_ulong *val, 601 target_ulong new_val, 602 target_ulong write_mask), 603 void *rmw_fn_arg); 604 605 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 606 #endif /* !CONFIG_USER_ONLY */ 607 608 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en); 609 610 void riscv_translate_init(void); 611 void riscv_translate_code(CPUState *cs, TranslationBlock *tb, 612 int *max_insns, vaddr pc, void *host_pc); 613 614 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 615 RISCVException exception, 616 uintptr_t pc); 617 618 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 619 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 620 621 #include "exec/cpu-all.h" 622 623 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 624 FIELD(TB_FLAGS, FS, 3, 2) 625 /* Vector flags */ 626 FIELD(TB_FLAGS, VS, 5, 2) 627 FIELD(TB_FLAGS, LMUL, 7, 3) 628 FIELD(TB_FLAGS, SEW, 10, 3) 629 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 630 FIELD(TB_FLAGS, VILL, 14, 1) 631 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 632 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 633 FIELD(TB_FLAGS, XL, 16, 2) 634 /* If PointerMasking should be applied */ 635 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 636 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 637 FIELD(TB_FLAGS, VTA, 18, 1) 638 FIELD(TB_FLAGS, VMA, 19, 1) 639 /* Native debug itrigger */ 640 FIELD(TB_FLAGS, ITRIGGER, 20, 1) 641 /* Virtual mode enabled */ 642 FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) 643 FIELD(TB_FLAGS, PRIV, 22, 2) 644 FIELD(TB_FLAGS, AXL, 24, 2) 645 /* zicfilp needs a TB flag to track indirect branches */ 646 FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) 647 FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) 648 /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ 649 FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) 650 /* If pointer masking should be applied and address sign extended */ 651 FIELD(TB_FLAGS, PM_PMM, 29, 2) 652 FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) 653 654 #ifdef TARGET_RISCV32 655 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 656 #else 657 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 658 { 659 return env->misa_mxl; 660 } 661 #endif 662 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 663 664 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 665 { 666 return &env_archcpu(env)->cfg; 667 } 668 669 #if !defined(CONFIG_USER_ONLY) 670 static inline int cpu_address_mode(CPURISCVState *env) 671 { 672 int mode = env->priv; 673 674 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 675 mode = get_field(env->mstatus, MSTATUS_MPP); 676 } 677 return mode; 678 } 679 680 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 681 { 682 RISCVMXL xl = env->misa_mxl; 683 /* 684 * When emulating a 32-bit-only cpu, use RV32. 685 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 686 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 687 * back to RV64 for lower privs. 688 */ 689 if (xl != MXL_RV32) { 690 switch (mode) { 691 case PRV_M: 692 break; 693 case PRV_U: 694 xl = get_field(env->mstatus, MSTATUS64_UXL); 695 break; 696 default: /* PRV_S */ 697 xl = get_field(env->mstatus, MSTATUS64_SXL); 698 break; 699 } 700 } 701 return xl; 702 } 703 #endif 704 705 #if defined(TARGET_RISCV32) 706 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 707 #else 708 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 709 { 710 #if !defined(CONFIG_USER_ONLY) 711 return cpu_get_xl(env, env->priv); 712 #else 713 return env->misa_mxl; 714 #endif 715 } 716 #endif 717 718 #if defined(TARGET_RISCV32) 719 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 720 #else 721 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 722 { 723 #ifdef CONFIG_USER_ONLY 724 return env->xl; 725 #else 726 int mode = cpu_address_mode(env); 727 728 return cpu_get_xl(env, mode); 729 #endif 730 } 731 #endif 732 733 static inline int riscv_cpu_xlen(CPURISCVState *env) 734 { 735 return 16 << env->xl; 736 } 737 738 #ifdef TARGET_RISCV32 739 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 740 #else 741 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 742 { 743 #ifdef CONFIG_USER_ONLY 744 return env->misa_mxl; 745 #else 746 if (env->misa_mxl != MXL_RV32) { 747 return get_field(env->mstatus, MSTATUS64_SXL); 748 } 749 #endif 750 return MXL_RV32; 751 } 752 #endif 753 754 /* 755 * Encode LMUL to lmul as follows: 756 * LMUL vlmul lmul 757 * 1 000 0 758 * 2 001 1 759 * 4 010 2 760 * 8 011 3 761 * - 100 - 762 * 1/8 101 -3 763 * 1/4 110 -2 764 * 1/2 111 -1 765 * 766 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 767 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 768 * => VLMAX = vlen >> (1 + 3 - (-3)) 769 * = 256 >> 7 770 * = 2 771 */ 772 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 773 int8_t lmul) 774 { 775 uint32_t vlen = vlenb << 3; 776 777 /* 778 * We need to use 'vlen' instead of 'vlenb' to 779 * preserve the '+ 3' in the formula. Otherwise 780 * we risk a negative shift if vsew < lmul. 781 */ 782 return vlen >> (vsew + 3 - lmul); 783 } 784 785 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 786 uint64_t *cs_base, uint32_t *pflags); 787 788 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 789 790 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); 791 RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); 792 RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); 793 uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); 794 795 RISCVException riscv_csrr(CPURISCVState *env, int csrno, 796 target_ulong *ret_value); 797 798 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 799 target_ulong *ret_value, 800 target_ulong new_value, target_ulong write_mask); 801 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 802 target_ulong *ret_value, 803 target_ulong new_value, 804 target_ulong write_mask); 805 806 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 807 target_ulong val) 808 { 809 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 810 } 811 812 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 813 { 814 target_ulong val = 0; 815 riscv_csrrw(env, csrno, &val, 0, 0); 816 return val; 817 } 818 819 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 820 int csrno); 821 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 822 target_ulong *ret_value); 823 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 824 target_ulong new_value); 825 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 826 target_ulong *ret_value, 827 target_ulong new_value, 828 target_ulong write_mask); 829 830 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, 831 Int128 *ret_value); 832 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 833 Int128 *ret_value, 834 Int128 new_value, Int128 write_mask); 835 836 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 837 Int128 *ret_value); 838 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 839 Int128 new_value); 840 841 typedef struct { 842 const char *name; 843 riscv_csr_predicate_fn predicate; 844 riscv_csr_read_fn read; 845 riscv_csr_write_fn write; 846 riscv_csr_op_fn op; 847 riscv_csr_read128_fn read128; 848 riscv_csr_write128_fn write128; 849 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 850 uint32_t min_priv_ver; 851 } riscv_csr_operations; 852 853 /* CSR function table constants */ 854 enum { 855 CSR_TABLE_SIZE = 0x1000 856 }; 857 858 /* 859 * The event id are encoded based on the encoding specified in the 860 * SBI specification v0.3 861 */ 862 863 enum riscv_pmu_event_idx { 864 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 865 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 866 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 867 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 868 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 869 }; 870 871 /* used by tcg/tcg-cpu.c*/ 872 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 873 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 874 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 875 bool riscv_cpu_is_vendor(Object *cpu_obj); 876 877 typedef struct RISCVCPUMultiExtConfig { 878 const char *name; 879 uint32_t offset; 880 bool enabled; 881 } RISCVCPUMultiExtConfig; 882 883 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 884 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 885 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 886 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 887 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 888 889 typedef struct isa_ext_data { 890 const char *name; 891 int min_version; 892 int ext_enable_offset; 893 } RISCVIsaExtData; 894 extern const RISCVIsaExtData isa_edata_arr[]; 895 char *riscv_cpu_get_name(RISCVCPU *cpu); 896 897 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 898 void riscv_add_satp_mode_properties(Object *obj); 899 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 900 901 /* CSR function table */ 902 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 903 904 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 905 906 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 907 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 908 909 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 910 911 target_ulong riscv_new_csr_seed(target_ulong new_value, 912 target_ulong write_mask); 913 914 uint8_t satp_mode_max_from_map(uint32_t map); 915 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 916 917 /* Implemented in th_csr.c */ 918 void th_register_custom_csrs(RISCVCPU *cpu); 919 920 const char *priv_spec_to_str(int priv_version); 921 #endif /* RISCV_CPU_H */ 922