1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/gdbstub.h" 28 #include "qemu/cpu-float.h" 29 #include "qom/object.h" 30 #include "qemu/int128.h" 31 #include "cpu_bits.h" 32 #include "cpu_cfg.h" 33 #include "qapi/qapi-types-common.h" 34 #include "cpu-qom.h" 35 36 typedef struct CPUArchState CPURISCVState; 37 38 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 39 40 #if defined(TARGET_RISCV32) 41 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 42 #elif defined(TARGET_RISCV64) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 44 #endif 45 46 /* 47 * RISC-V-specific extra insn start words: 48 * 1: Original instruction opcode 49 * 2: more information about instruction 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 2 52 /* 53 * b0: Whether a instruction always raise a store AMO or not. 54 */ 55 #define RISCV_UW2_ALWAYS_STORE_AMO 1 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 /* 60 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 61 * when adding new MISA bits here. 62 */ 63 #define RVI RV('I') 64 #define RVE RV('E') /* E and I are mutually exclusive */ 65 #define RVM RV('M') 66 #define RVA RV('A') 67 #define RVF RV('F') 68 #define RVD RV('D') 69 #define RVV RV('V') 70 #define RVC RV('C') 71 #define RVS RV('S') 72 #define RVU RV('U') 73 #define RVH RV('H') 74 #define RVG RV('G') 75 #define RVB RV('B') 76 77 extern const uint32_t misa_bits[]; 78 const char *riscv_get_misa_ext_name(uint32_t bit); 79 const char *riscv_get_misa_ext_description(uint32_t bit); 80 81 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 82 83 typedef struct riscv_cpu_profile { 84 struct riscv_cpu_profile *u_parent; 85 struct riscv_cpu_profile *s_parent; 86 const char *name; 87 uint32_t misa_ext; 88 bool enabled; 89 bool user_set; 90 int priv_spec; 91 int satp_mode; 92 const int32_t ext_offsets[]; 93 } RISCVCPUProfile; 94 95 #define RISCV_PROFILE_EXT_LIST_END -1 96 #define RISCV_PROFILE_ATTR_UNUSED -1 97 98 extern RISCVCPUProfile *riscv_profiles[]; 99 100 /* Privileged specification version */ 101 #define PRIV_VER_1_10_0_STR "v1.10.0" 102 #define PRIV_VER_1_11_0_STR "v1.11.0" 103 #define PRIV_VER_1_12_0_STR "v1.12.0" 104 #define PRIV_VER_1_13_0_STR "v1.13.0" 105 enum { 106 PRIV_VERSION_1_10_0 = 0, 107 PRIV_VERSION_1_11_0, 108 PRIV_VERSION_1_12_0, 109 PRIV_VERSION_1_13_0, 110 111 PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, 112 }; 113 114 #define VEXT_VERSION_1_00_0 0x00010000 115 #define VEXT_VER_1_00_0_STR "v1.0" 116 117 enum { 118 TRANSLATE_SUCCESS, 119 TRANSLATE_FAIL, 120 TRANSLATE_PMP_FAIL, 121 TRANSLATE_G_STAGE_FAIL 122 }; 123 124 /* Extension context status */ 125 typedef enum { 126 EXT_STATUS_DISABLED = 0, 127 EXT_STATUS_INITIAL, 128 EXT_STATUS_CLEAN, 129 EXT_STATUS_DIRTY, 130 } RISCVExtStatus; 131 132 /* Enum holds PMM field values for Zjpm v1.0 extension */ 133 typedef enum { 134 PMM_FIELD_DISABLED = 0, 135 PMM_FIELD_RESERVED = 1, 136 PMM_FIELD_PMLEN7 = 2, 137 PMM_FIELD_PMLEN16 = 3, 138 } RISCVPmPmm; 139 140 typedef struct riscv_cpu_implied_exts_rule { 141 #ifndef CONFIG_USER_ONLY 142 /* 143 * Bitmask indicates the rule enabled status for the harts. 144 * This enhancement is only available in system-mode QEMU, 145 * as we don't have a good way (e.g. mhartid) to distinguish 146 * the SMP cores in user-mode QEMU. 147 */ 148 unsigned long *enabled; 149 #endif 150 /* True if this is a MISA implied rule. */ 151 bool is_misa; 152 /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ 153 const uint32_t ext; 154 const uint32_t implied_misa_exts; 155 const uint32_t implied_multi_exts[]; 156 } RISCVCPUImpliedExtsRule; 157 158 extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; 159 extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; 160 161 #define RISCV_IMPLIED_EXTS_RULE_END -1 162 163 #define MMU_USER_IDX 3 164 165 #define MAX_RISCV_PMPS (16) 166 167 #if !defined(CONFIG_USER_ONLY) 168 #include "pmp.h" 169 #include "debug.h" 170 #endif 171 172 #define RV_VLEN_MAX 1024 173 #define RV_MAX_MHPMEVENTS 32 174 #define RV_MAX_MHPMCOUNTERS 32 175 176 FIELD(VTYPE, VLMUL, 0, 3) 177 FIELD(VTYPE, VSEW, 3, 3) 178 FIELD(VTYPE, VTA, 6, 1) 179 FIELD(VTYPE, VMA, 7, 1) 180 FIELD(VTYPE, VEDIV, 8, 2) 181 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 182 183 typedef struct PMUCTRState { 184 /* Current value of a counter */ 185 target_ulong mhpmcounter_val; 186 /* Current value of a counter in RV32 */ 187 target_ulong mhpmcounterh_val; 188 /* Snapshot values of counter */ 189 target_ulong mhpmcounter_prev; 190 /* Snapshort value of a counter in RV32 */ 191 target_ulong mhpmcounterh_prev; 192 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 193 target_ulong irq_overflow_left; 194 } PMUCTRState; 195 196 typedef struct PMUFixedCtrState { 197 /* Track cycle and icount for each privilege mode */ 198 uint64_t counter[4]; 199 uint64_t counter_prev[4]; 200 /* Track cycle and icount for each privilege mode when V = 1*/ 201 uint64_t counter_virt[2]; 202 uint64_t counter_virt_prev[2]; 203 } PMUFixedCtrState; 204 205 struct CPUArchState { 206 target_ulong gpr[32]; 207 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 208 209 /* vector coprocessor state. */ 210 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 211 target_ulong vxrm; 212 target_ulong vxsat; 213 target_ulong vl; 214 target_ulong vstart; 215 target_ulong vtype; 216 bool vill; 217 218 target_ulong pc; 219 target_ulong load_res; 220 target_ulong load_val; 221 222 /* Floating-Point state */ 223 uint64_t fpr[32]; /* assume both F and D extensions */ 224 target_ulong frm; 225 float_status fp_status; 226 227 target_ulong badaddr; 228 target_ulong bins; 229 230 target_ulong guest_phys_fault_addr; 231 232 target_ulong priv_ver; 233 target_ulong vext_ver; 234 235 /* RISCVMXL, but uint32_t for vmstate migration */ 236 uint32_t misa_mxl; /* current mxl */ 237 uint32_t misa_ext; /* current extensions */ 238 uint32_t misa_ext_mask; /* max ext for this cpu */ 239 uint32_t xl; /* current xlen */ 240 241 /* 128-bit helpers upper part return value */ 242 target_ulong retxh; 243 244 target_ulong jvt; 245 246 /* elp state for zicfilp extension */ 247 bool elp; 248 /* shadow stack register for zicfiss extension */ 249 target_ulong ssp; 250 /* env place holder for extra word 2 during unwind */ 251 target_ulong excp_uw2; 252 /* sw check code for sw check exception */ 253 target_ulong sw_check_code; 254 #ifdef CONFIG_USER_ONLY 255 uint32_t elf_flags; 256 #endif 257 258 target_ulong priv; 259 /* CSRs for execution environment configuration */ 260 uint64_t menvcfg; 261 target_ulong senvcfg; 262 263 #ifndef CONFIG_USER_ONLY 264 /* This contains QEMU specific information about the virt state. */ 265 bool virt_enabled; 266 target_ulong geilen; 267 uint64_t resetvec; 268 269 target_ulong mhartid; 270 /* 271 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 272 * For RV64 this is a 64-bit mstatus. 273 */ 274 uint64_t mstatus; 275 276 uint64_t mip; 277 /* 278 * MIP contains the software writable version of SEIP ORed with the 279 * external interrupt value. The MIP register is always up-to-date. 280 * To keep track of the current source, we also save booleans of the values 281 * here. 282 */ 283 bool external_seip; 284 bool software_seip; 285 286 uint64_t miclaim; 287 288 uint64_t mie; 289 uint64_t mideleg; 290 291 /* 292 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 293 * alias of mie[i] and needs to be maintained separately. 294 */ 295 uint64_t sie; 296 297 /* 298 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 299 * alias of sie[i] (mie[i]) and needs to be maintained separately. 300 */ 301 uint64_t vsie; 302 303 target_ulong satp; /* since: priv-1.10.0 */ 304 target_ulong stval; 305 target_ulong medeleg; 306 307 target_ulong stvec; 308 target_ulong sepc; 309 target_ulong scause; 310 311 target_ulong mtvec; 312 target_ulong mepc; 313 target_ulong mcause; 314 target_ulong mtval; /* since: priv-1.10.0 */ 315 316 uint64_t mctrctl; 317 uint32_t sctrdepth; 318 uint32_t sctrstatus; 319 uint64_t vsctrctl; 320 321 uint64_t ctr_src[16 << SCTRDEPTH_MAX]; 322 uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; 323 uint64_t ctr_data[16 << SCTRDEPTH_MAX]; 324 325 /* Machine and Supervisor interrupt priorities */ 326 uint8_t miprio[64]; 327 uint8_t siprio[64]; 328 329 /* AIA CSRs */ 330 target_ulong miselect; 331 target_ulong siselect; 332 uint64_t mvien; 333 uint64_t mvip; 334 335 /* Hypervisor CSRs */ 336 target_ulong hstatus; 337 target_ulong hedeleg; 338 uint64_t hideleg; 339 uint32_t hcounteren; 340 target_ulong htval; 341 target_ulong htinst; 342 target_ulong hgatp; 343 target_ulong hgeie; 344 target_ulong hgeip; 345 uint64_t htimedelta; 346 uint64_t hvien; 347 348 /* 349 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 350 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 351 * maintain in hvip. 352 */ 353 uint64_t hvip; 354 355 /* Hypervisor controlled virtual interrupt priorities */ 356 target_ulong hvictl; 357 uint8_t hviprio[64]; 358 359 /* Upper 64-bits of 128-bit CSRs */ 360 uint64_t mscratchh; 361 uint64_t sscratchh; 362 363 /* Virtual CSRs */ 364 /* 365 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 366 * For RV64 this is a 64-bit vsstatus. 367 */ 368 uint64_t vsstatus; 369 target_ulong vstvec; 370 target_ulong vsscratch; 371 target_ulong vsepc; 372 target_ulong vscause; 373 target_ulong vstval; 374 target_ulong vsatp; 375 376 /* AIA VS-mode CSRs */ 377 target_ulong vsiselect; 378 379 target_ulong mtval2; 380 target_ulong mtinst; 381 382 /* HS Backup CSRs */ 383 target_ulong stvec_hs; 384 target_ulong sscratch_hs; 385 target_ulong sepc_hs; 386 target_ulong scause_hs; 387 target_ulong stval_hs; 388 target_ulong satp_hs; 389 uint64_t mstatus_hs; 390 391 /* 392 * Signals whether the current exception occurred with two-stage address 393 * translation active. 394 */ 395 bool two_stage_lookup; 396 /* 397 * Signals whether the current exception occurred while doing two-stage 398 * address translation for the VS-stage page table walk. 399 */ 400 bool two_stage_indirect_lookup; 401 402 uint32_t scounteren; 403 uint32_t mcounteren; 404 405 uint32_t scountinhibit; 406 uint32_t mcountinhibit; 407 408 /* PMU cycle & instret privilege mode filtering */ 409 target_ulong mcyclecfg; 410 target_ulong mcyclecfgh; 411 target_ulong minstretcfg; 412 target_ulong minstretcfgh; 413 414 /* PMU counter state */ 415 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 416 417 /* PMU event selector configured values. First three are unused */ 418 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 419 420 /* PMU event selector configured values for RV32 */ 421 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 422 423 PMUFixedCtrState pmu_fixed_ctrs[2]; 424 425 target_ulong sscratch; 426 target_ulong mscratch; 427 428 /* Sstc CSRs */ 429 uint64_t stimecmp; 430 431 uint64_t vstimecmp; 432 433 /* physical memory protection */ 434 pmp_table_t pmp_state; 435 target_ulong mseccfg; 436 437 /* trigger module */ 438 target_ulong trigger_cur; 439 target_ulong tdata1[RV_MAX_TRIGGERS]; 440 target_ulong tdata2[RV_MAX_TRIGGERS]; 441 target_ulong tdata3[RV_MAX_TRIGGERS]; 442 target_ulong mcontext; 443 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 444 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 445 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 446 int64_t last_icount; 447 bool itrigger_enabled; 448 449 /* machine specific rdtime callback */ 450 uint64_t (*rdtime_fn)(void *); 451 void *rdtime_fn_arg; 452 453 /* machine specific AIA ireg read-modify-write callback */ 454 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 455 ((((__xlen) & 0xff) << 24) | \ 456 (((__vgein) & 0x3f) << 20) | \ 457 (((__virt) & 0x1) << 18) | \ 458 (((__priv) & 0x3) << 16) | \ 459 (__isel & 0xffff)) 460 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 461 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 462 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 463 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 464 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 465 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 466 target_ulong *val, target_ulong new_val, target_ulong write_mask); 467 void *aia_ireg_rmw_fn_arg[4]; 468 469 /* True if in debugger mode. */ 470 bool debugger; 471 472 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 473 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 474 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 475 uint64_t henvcfg; 476 #endif 477 478 /* Fields from here on are preserved across CPU reset. */ 479 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 480 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 481 bool vstime_irq; 482 483 hwaddr kernel_addr; 484 hwaddr fdt_addr; 485 486 #ifdef CONFIG_KVM 487 /* kvm timer */ 488 bool kvm_timer_dirty; 489 uint64_t kvm_timer_time; 490 uint64_t kvm_timer_compare; 491 uint64_t kvm_timer_state; 492 uint64_t kvm_timer_frequency; 493 #endif /* CONFIG_KVM */ 494 495 /* RNMI */ 496 target_ulong mnscratch; 497 target_ulong mnepc; 498 target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ 499 target_ulong mnstatus; 500 target_ulong rnmip; 501 uint64_t rnmi_irqvec; 502 uint64_t rnmi_excpvec; 503 }; 504 505 /* 506 * RISCVCPU: 507 * @env: #CPURISCVState 508 * 509 * A RISCV CPU. 510 */ 511 struct ArchCPU { 512 CPUState parent_obj; 513 514 CPURISCVState env; 515 516 GDBFeature dyn_csr_feature; 517 GDBFeature dyn_vreg_feature; 518 519 /* Configuration Settings */ 520 RISCVCPUConfig cfg; 521 522 QEMUTimer *pmu_timer; 523 /* A bitmask of Available programmable counters */ 524 uint32_t pmu_avail_ctrs; 525 /* Mapping of events to counters */ 526 GHashTable *pmu_event_ctr_map; 527 const GPtrArray *decoders; 528 }; 529 530 /** 531 * RISCVCPUClass: 532 * @parent_realize: The parent class' realize handler. 533 * @parent_phases: The parent class' reset phase handlers. 534 * 535 * A RISCV CPU model. 536 */ 537 struct RISCVCPUClass { 538 CPUClass parent_class; 539 540 DeviceRealize parent_realize; 541 ResettablePhases parent_phases; 542 RISCVMXL misa_mxl_max; /* max mxl for this cpu */ 543 }; 544 545 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 546 { 547 return (env->misa_ext & ext) != 0; 548 } 549 550 #include "cpu_user.h" 551 552 extern const char * const riscv_int_regnames[]; 553 extern const char * const riscv_int_regnamesh[]; 554 extern const char * const riscv_fpr_regnames[]; 555 556 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 557 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 558 int cpuid, DumpState *s); 559 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 560 int cpuid, DumpState *s); 561 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 562 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 563 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 564 uint8_t riscv_cpu_default_priority(int irq); 565 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 566 int riscv_cpu_mirq_pending(CPURISCVState *env); 567 int riscv_cpu_sirq_pending(CPURISCVState *env); 568 int riscv_cpu_vsirq_pending(CPURISCVState *env); 569 bool riscv_cpu_fp_enabled(CPURISCVState *env); 570 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 571 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 572 bool riscv_cpu_vector_enabled(CPURISCVState *env); 573 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 574 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 575 bool cpu_get_fcfien(CPURISCVState *env); 576 bool cpu_get_bcfien(CPURISCVState *env); 577 bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); 578 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 579 MMUAccessType access_type, 580 int mmu_idx, uintptr_t retaddr); 581 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 582 MMUAccessType access_type, int mmu_idx, 583 bool probe, uintptr_t retaddr); 584 char *riscv_isa_string(RISCVCPU *cpu); 585 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 586 bool riscv_cpu_option_set(const char *optname); 587 588 #ifndef CONFIG_USER_ONLY 589 void riscv_cpu_do_interrupt(CPUState *cpu); 590 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 591 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 592 vaddr addr, unsigned size, 593 MMUAccessType access_type, 594 int mmu_idx, MemTxAttrs attrs, 595 MemTxResult response, uintptr_t retaddr); 596 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 597 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 598 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 599 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 600 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 601 uint64_t value); 602 void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); 603 void riscv_cpu_interrupt(CPURISCVState *env); 604 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 605 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 606 void *arg); 607 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 608 int (*rmw_fn)(void *arg, 609 target_ulong reg, 610 target_ulong *val, 611 target_ulong new_val, 612 target_ulong write_mask), 613 void *rmw_fn_arg); 614 615 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 616 #endif /* !CONFIG_USER_ONLY */ 617 618 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en); 619 620 void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst, 621 enum CTRType type, target_ulong prev_priv, bool prev_virt); 622 void riscv_ctr_clear(CPURISCVState *env); 623 624 void riscv_translate_init(void); 625 void riscv_translate_code(CPUState *cs, TranslationBlock *tb, 626 int *max_insns, vaddr pc, void *host_pc); 627 628 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 629 RISCVException exception, 630 uintptr_t pc); 631 632 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 633 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 634 635 #include "exec/cpu-all.h" 636 637 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 638 FIELD(TB_FLAGS, FS, 3, 2) 639 /* Vector flags */ 640 FIELD(TB_FLAGS, VS, 5, 2) 641 FIELD(TB_FLAGS, LMUL, 7, 3) 642 FIELD(TB_FLAGS, SEW, 10, 3) 643 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 644 FIELD(TB_FLAGS, VILL, 14, 1) 645 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 646 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 647 FIELD(TB_FLAGS, XL, 16, 2) 648 /* If PointerMasking should be applied */ 649 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 650 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 651 FIELD(TB_FLAGS, VTA, 18, 1) 652 FIELD(TB_FLAGS, VMA, 19, 1) 653 /* Native debug itrigger */ 654 FIELD(TB_FLAGS, ITRIGGER, 20, 1) 655 /* Virtual mode enabled */ 656 FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) 657 FIELD(TB_FLAGS, PRIV, 22, 2) 658 FIELD(TB_FLAGS, AXL, 24, 2) 659 /* zicfilp needs a TB flag to track indirect branches */ 660 FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) 661 FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) 662 /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ 663 FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) 664 /* If pointer masking should be applied and address sign extended */ 665 FIELD(TB_FLAGS, PM_PMM, 29, 2) 666 FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) 667 668 #ifdef TARGET_RISCV32 669 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 670 #else 671 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 672 { 673 return env->misa_mxl; 674 } 675 #endif 676 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 677 678 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 679 { 680 return &env_archcpu(env)->cfg; 681 } 682 683 #if !defined(CONFIG_USER_ONLY) 684 static inline int cpu_address_mode(CPURISCVState *env) 685 { 686 int mode = env->priv; 687 688 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 689 mode = get_field(env->mstatus, MSTATUS_MPP); 690 } 691 return mode; 692 } 693 694 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 695 { 696 RISCVMXL xl = env->misa_mxl; 697 /* 698 * When emulating a 32-bit-only cpu, use RV32. 699 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 700 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 701 * back to RV64 for lower privs. 702 */ 703 if (xl != MXL_RV32) { 704 switch (mode) { 705 case PRV_M: 706 break; 707 case PRV_U: 708 xl = get_field(env->mstatus, MSTATUS64_UXL); 709 break; 710 default: /* PRV_S */ 711 xl = get_field(env->mstatus, MSTATUS64_SXL); 712 break; 713 } 714 } 715 return xl; 716 } 717 #endif 718 719 #if defined(TARGET_RISCV32) 720 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 721 #else 722 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 723 { 724 #if !defined(CONFIG_USER_ONLY) 725 return cpu_get_xl(env, env->priv); 726 #else 727 return env->misa_mxl; 728 #endif 729 } 730 #endif 731 732 #if defined(TARGET_RISCV32) 733 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 734 #else 735 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 736 { 737 #ifdef CONFIG_USER_ONLY 738 return env->xl; 739 #else 740 int mode = cpu_address_mode(env); 741 742 return cpu_get_xl(env, mode); 743 #endif 744 } 745 #endif 746 747 static inline int riscv_cpu_xlen(CPURISCVState *env) 748 { 749 return 16 << env->xl; 750 } 751 752 #ifdef TARGET_RISCV32 753 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 754 #else 755 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 756 { 757 #ifdef CONFIG_USER_ONLY 758 return env->misa_mxl; 759 #else 760 if (env->misa_mxl != MXL_RV32) { 761 return get_field(env->mstatus, MSTATUS64_SXL); 762 } 763 #endif 764 return MXL_RV32; 765 } 766 #endif 767 768 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, 769 target_long priv_ver, 770 uint32_t misa_ext) 771 { 772 /* In priv spec version 1.12 or newer, C always implies Zca */ 773 if (priv_ver >= PRIV_VERSION_1_12_0) { 774 return cfg->ext_zca; 775 } else { 776 return misa_ext & RVC; 777 } 778 } 779 780 /* 781 * Encode LMUL to lmul as follows: 782 * LMUL vlmul lmul 783 * 1 000 0 784 * 2 001 1 785 * 4 010 2 786 * 8 011 3 787 * - 100 - 788 * 1/8 101 -3 789 * 1/4 110 -2 790 * 1/2 111 -1 791 * 792 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 793 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 794 * => VLMAX = vlen >> (1 + 3 - (-3)) 795 * = 256 >> 7 796 * = 2 797 */ 798 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 799 int8_t lmul) 800 { 801 uint32_t vlen = vlenb << 3; 802 803 /* 804 * We need to use 'vlen' instead of 'vlenb' to 805 * preserve the '+ 3' in the formula. Otherwise 806 * we risk a negative shift if vsew < lmul. 807 */ 808 return vlen >> (vsew + 3 - lmul); 809 } 810 811 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 812 uint64_t *cs_base, uint32_t *pflags); 813 814 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 815 816 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); 817 RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); 818 RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); 819 uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); 820 821 RISCVException riscv_csrr(CPURISCVState *env, int csrno, 822 target_ulong *ret_value); 823 824 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 825 target_ulong *ret_value, 826 target_ulong new_value, target_ulong write_mask); 827 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 828 target_ulong *ret_value, 829 target_ulong new_value, 830 target_ulong write_mask); 831 832 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 833 target_ulong val) 834 { 835 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 836 } 837 838 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 839 { 840 target_ulong val = 0; 841 riscv_csrrw(env, csrno, &val, 0, 0); 842 return val; 843 } 844 845 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 846 int csrno); 847 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 848 target_ulong *ret_value); 849 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 850 target_ulong new_value); 851 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 852 target_ulong *ret_value, 853 target_ulong new_value, 854 target_ulong write_mask); 855 856 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, 857 Int128 *ret_value); 858 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 859 Int128 *ret_value, 860 Int128 new_value, Int128 write_mask); 861 862 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 863 Int128 *ret_value); 864 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 865 Int128 new_value); 866 867 typedef struct { 868 const char *name; 869 riscv_csr_predicate_fn predicate; 870 riscv_csr_read_fn read; 871 riscv_csr_write_fn write; 872 riscv_csr_op_fn op; 873 riscv_csr_read128_fn read128; 874 riscv_csr_write128_fn write128; 875 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 876 uint32_t min_priv_ver; 877 } riscv_csr_operations; 878 879 /* CSR function table constants */ 880 enum { 881 CSR_TABLE_SIZE = 0x1000 882 }; 883 884 /* 885 * The event id are encoded based on the encoding specified in the 886 * SBI specification v0.3 887 */ 888 889 enum riscv_pmu_event_idx { 890 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 891 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 892 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 893 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 894 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 895 }; 896 897 /* used by tcg/tcg-cpu.c*/ 898 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 899 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 900 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 901 bool riscv_cpu_is_vendor(Object *cpu_obj); 902 903 typedef struct RISCVCPUMultiExtConfig { 904 const char *name; 905 uint32_t offset; 906 bool enabled; 907 } RISCVCPUMultiExtConfig; 908 909 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 910 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 911 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 912 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 913 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 914 915 typedef struct isa_ext_data { 916 const char *name; 917 int min_version; 918 int ext_enable_offset; 919 } RISCVIsaExtData; 920 extern const RISCVIsaExtData isa_edata_arr[]; 921 char *riscv_cpu_get_name(RISCVCPU *cpu); 922 923 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 924 void riscv_add_satp_mode_properties(Object *obj); 925 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 926 927 /* CSR function table */ 928 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 929 930 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 931 932 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 933 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 934 935 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 936 937 target_ulong riscv_new_csr_seed(target_ulong new_value, 938 target_ulong write_mask); 939 940 uint8_t satp_mode_max_from_map(uint32_t map); 941 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 942 943 /* Implemented in th_csr.c */ 944 void th_register_custom_csrs(RISCVCPU *cpu); 945 946 const char *priv_spec_to_str(int priv_version); 947 #endif /* RISCV_CPU_H */ 948