1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "exec/exec-all.h" 25 #include "exec/target_page.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "exec/translator.h" 34 #include "exec/translation-block.h" 35 #include "exec/log.h" 36 #include "qemu/atomic128.h" 37 #include "spr_common.h" 38 #include "power8-pmu.h" 39 40 #include "qemu/qemu-print.h" 41 #include "qapi/error.h" 42 43 #define HELPER_H "helper.h" 44 #include "exec/helper-info.c.inc" 45 #undef HELPER_H 46 47 #define CPU_SINGLE_STEP 0x1 48 #define CPU_BRANCH_STEP 0x2 49 50 /* Include definitions for instructions classes and implementations flags */ 51 /* #define PPC_DEBUG_DISAS */ 52 53 #ifdef PPC_DEBUG_DISAS 54 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 55 #else 56 # define LOG_DISAS(...) do { } while (0) 57 #endif 58 /*****************************************************************************/ 59 /* Code translation helpers */ 60 61 /* global register indexes */ 62 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 63 + 10 * 4 + 22 * 5 /* SPE GPRh */ 64 + 8 * 5 /* CRF */]; 65 static TCGv cpu_gpr[32]; 66 static TCGv cpu_gprh[32]; 67 static TCGv_i32 cpu_crf[8]; 68 static TCGv cpu_nip; 69 static TCGv cpu_msr; 70 static TCGv cpu_ctr; 71 static TCGv cpu_lr; 72 #if defined(TARGET_PPC64) 73 static TCGv cpu_cfar; 74 #endif 75 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 76 static TCGv cpu_reserve; 77 static TCGv cpu_reserve_length; 78 static TCGv cpu_reserve_val; 79 #if defined(TARGET_PPC64) 80 static TCGv cpu_reserve_val2; 81 #endif 82 static TCGv cpu_fpscr; 83 static TCGv_i32 cpu_access_type; 84 85 void ppc_translate_init(void) 86 { 87 int i; 88 char *p; 89 size_t cpu_reg_names_size; 90 91 p = cpu_reg_names; 92 cpu_reg_names_size = sizeof(cpu_reg_names); 93 94 for (i = 0; i < 8; i++) { 95 snprintf(p, cpu_reg_names_size, "crf%d", i); 96 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, 97 offsetof(CPUPPCState, crf[i]), p); 98 p += 5; 99 cpu_reg_names_size -= 5; 100 } 101 102 for (i = 0; i < 32; i++) { 103 snprintf(p, cpu_reg_names_size, "r%d", i); 104 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 105 offsetof(CPUPPCState, gpr[i]), p); 106 p += (i < 10) ? 3 : 4; 107 cpu_reg_names_size -= (i < 10) ? 3 : 4; 108 snprintf(p, cpu_reg_names_size, "r%dH", i); 109 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 110 offsetof(CPUPPCState, gprh[i]), p); 111 p += (i < 10) ? 4 : 5; 112 cpu_reg_names_size -= (i < 10) ? 4 : 5; 113 } 114 115 cpu_nip = tcg_global_mem_new(tcg_env, 116 offsetof(CPUPPCState, nip), "nip"); 117 118 cpu_msr = tcg_global_mem_new(tcg_env, 119 offsetof(CPUPPCState, msr), "msr"); 120 121 cpu_ctr = tcg_global_mem_new(tcg_env, 122 offsetof(CPUPPCState, ctr), "ctr"); 123 124 cpu_lr = tcg_global_mem_new(tcg_env, 125 offsetof(CPUPPCState, lr), "lr"); 126 127 #if defined(TARGET_PPC64) 128 cpu_cfar = tcg_global_mem_new(tcg_env, 129 offsetof(CPUPPCState, cfar), "cfar"); 130 #endif 131 132 cpu_xer = tcg_global_mem_new(tcg_env, 133 offsetof(CPUPPCState, xer), "xer"); 134 cpu_so = tcg_global_mem_new(tcg_env, 135 offsetof(CPUPPCState, so), "SO"); 136 cpu_ov = tcg_global_mem_new(tcg_env, 137 offsetof(CPUPPCState, ov), "OV"); 138 cpu_ca = tcg_global_mem_new(tcg_env, 139 offsetof(CPUPPCState, ca), "CA"); 140 cpu_ov32 = tcg_global_mem_new(tcg_env, 141 offsetof(CPUPPCState, ov32), "OV32"); 142 cpu_ca32 = tcg_global_mem_new(tcg_env, 143 offsetof(CPUPPCState, ca32), "CA32"); 144 145 cpu_reserve = tcg_global_mem_new(tcg_env, 146 offsetof(CPUPPCState, reserve_addr), 147 "reserve_addr"); 148 cpu_reserve_length = tcg_global_mem_new(tcg_env, 149 offsetof(CPUPPCState, 150 reserve_length), 151 "reserve_length"); 152 cpu_reserve_val = tcg_global_mem_new(tcg_env, 153 offsetof(CPUPPCState, reserve_val), 154 "reserve_val"); 155 #if defined(TARGET_PPC64) 156 cpu_reserve_val2 = tcg_global_mem_new(tcg_env, 157 offsetof(CPUPPCState, reserve_val2), 158 "reserve_val2"); 159 #endif 160 161 cpu_fpscr = tcg_global_mem_new(tcg_env, 162 offsetof(CPUPPCState, fpscr), "fpscr"); 163 164 cpu_access_type = tcg_global_mem_new_i32(tcg_env, 165 offsetof(CPUPPCState, access_type), 166 "access_type"); 167 } 168 169 /* internal defines */ 170 struct DisasContext { 171 DisasContextBase base; 172 target_ulong cia; /* current instruction address */ 173 uint32_t opcode; 174 /* Routine used to access memory */ 175 bool pr, hv, dr, le_mode; 176 bool lazy_tlb_flush; 177 bool need_access_type; 178 int mem_idx; 179 int access_type; 180 /* Translation flags */ 181 MemOp default_tcg_memop_mask; 182 #if defined(TARGET_PPC64) 183 powerpc_excp_t excp_model; 184 bool sf_mode; 185 bool has_cfar; 186 bool has_bhrb; 187 #endif 188 bool fpu_enabled; 189 bool altivec_enabled; 190 bool vsx_enabled; 191 bool spe_enabled; 192 bool tm_enabled; 193 bool gtse; 194 bool hr; 195 bool mmcr0_pmcc0; 196 bool mmcr0_pmcc1; 197 bool mmcr0_pmcjce; 198 bool pmc_other; 199 bool pmu_insn_cnt; 200 bool bhrb_enable; 201 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 202 int singlestep_enabled; 203 uint32_t flags; 204 uint64_t insns_flags; 205 uint64_t insns_flags2; 206 }; 207 208 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 209 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 210 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 211 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 212 213 /* Return true iff byteswap is needed in a scalar memop */ 214 static inline bool need_byteswap(const DisasContext *ctx) 215 { 216 #if TARGET_BIG_ENDIAN 217 return ctx->le_mode; 218 #else 219 return !ctx->le_mode; 220 #endif 221 } 222 223 /* True when active word size < size of target_long. */ 224 #ifdef TARGET_PPC64 225 # define NARROW_MODE(C) (!(C)->sf_mode) 226 #else 227 # define NARROW_MODE(C) 0 228 #endif 229 230 struct opc_handler_t { 231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 232 uint32_t inval1; 233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 234 uint32_t inval2; 235 /* instruction type */ 236 uint64_t type; 237 /* extended instruction type */ 238 uint64_t type2; 239 /* handler */ 240 void (*handler)(DisasContext *ctx); 241 }; 242 243 static inline bool gen_serialize(DisasContext *ctx) 244 { 245 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 246 /* Restart with exclusive lock. */ 247 gen_helper_exit_atomic(tcg_env); 248 ctx->base.is_jmp = DISAS_NORETURN; 249 return false; 250 } 251 return true; 252 } 253 254 #if !defined(CONFIG_USER_ONLY) 255 #if defined(TARGET_PPC64) 256 static inline bool gen_serialize_core(DisasContext *ctx) 257 { 258 if (ctx->flags & POWERPC_FLAG_SMT) { 259 return gen_serialize(ctx); 260 } 261 return true; 262 } 263 #endif 264 265 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 266 { 267 #if defined(TARGET_PPC64) 268 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 269 return gen_serialize(ctx); 270 } 271 #endif 272 return true; 273 } 274 #endif 275 276 /* SPR load/store helpers */ 277 static inline void gen_load_spr(TCGv t, int reg) 278 { 279 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 280 } 281 282 static inline void gen_store_spr(int reg, TCGv t) 283 { 284 tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 285 } 286 287 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 288 { 289 if (ctx->need_access_type && ctx->access_type != access_type) { 290 tcg_gen_movi_i32(cpu_access_type, access_type); 291 ctx->access_type = access_type; 292 } 293 } 294 295 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 296 { 297 if (NARROW_MODE(ctx)) { 298 nip = (uint32_t)nip; 299 } 300 tcg_gen_movi_tl(cpu_nip, nip); 301 } 302 303 static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp, 304 uint32_t error, target_ulong nip) 305 { 306 TCGv_i32 t0, t1; 307 308 gen_update_nip(ctx, nip); 309 t0 = tcg_constant_i32(excp); 310 t1 = tcg_constant_i32(error); 311 gen_helper_raise_exception_err(tcg_env, t0, t1); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, 316 uint32_t error) 317 { 318 /* 319 * These are all synchronous exceptions, we set the PC back to the 320 * faulting instruction 321 */ 322 gen_exception_err_nip(ctx, excp, error, ctx->cia); 323 } 324 325 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 326 target_ulong nip) 327 { 328 TCGv_i32 t0; 329 330 gen_update_nip(ctx, nip); 331 t0 = tcg_constant_i32(excp); 332 gen_helper_raise_exception(tcg_env, t0); 333 ctx->base.is_jmp = DISAS_NORETURN; 334 } 335 336 static inline void gen_exception(DisasContext *ctx, uint32_t excp) 337 { 338 /* 339 * These are all synchronous exceptions, we set the PC back to the 340 * faulting instruction 341 */ 342 gen_exception_nip(ctx, excp, ctx->cia); 343 } 344 345 #if !defined(CONFIG_USER_ONLY) 346 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 347 { 348 translator_io_start(&ctx->base); 349 gen_helper_ppc_maybe_interrupt(tcg_env); 350 } 351 #endif 352 353 /* 354 * Tells the caller what is the appropriate exception to generate and prepares 355 * SPR registers for this exception. 356 * 357 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 358 * POWERPC_EXCP_DEBUG (on BookE). 359 */ 360 static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 361 { 362 #if !defined(CONFIG_USER_ONLY) 363 if (ctx->flags & POWERPC_FLAG_DE) { 364 target_ulong dbsr = 0; 365 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 366 dbsr = DBCR0_ICMP; 367 } else { 368 /* Must have been branch */ 369 dbsr = DBCR0_BRT; 370 } 371 TCGv t0 = tcg_temp_new(); 372 gen_load_spr(t0, SPR_BOOKE_DBSR); 373 tcg_gen_ori_tl(t0, t0, dbsr); 374 gen_store_spr(SPR_BOOKE_DBSR, t0); 375 gen_helper_raise_exception(tcg_env, 376 tcg_constant_i32(POWERPC_EXCP_DEBUG)); 377 ctx->base.is_jmp = DISAS_NORETURN; 378 } else { 379 if (!rfi_type) { /* BookS does not single step rfi type instructions */ 380 TCGv t0 = tcg_temp_new(); 381 tcg_gen_movi_tl(t0, ctx->cia); 382 gen_helper_book3s_trace(tcg_env, t0); 383 ctx->base.is_jmp = DISAS_NORETURN; 384 } 385 } 386 #endif 387 } 388 389 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 390 { 391 /* Will be converted to program check if needed */ 392 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 393 } 394 395 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 396 { 397 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 398 } 399 400 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 401 { 402 /* Will be converted to program check if needed */ 403 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 404 } 405 406 /*****************************************************************************/ 407 /* SPR READ/WRITE CALLBACKS */ 408 409 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 410 { 411 #if 0 412 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 413 printf("ERROR: try to access SPR %d !\n", sprn); 414 #endif 415 } 416 417 /* #define PPC_DUMP_SPR_ACCESSES */ 418 419 /* 420 * Generic callbacks: 421 * do nothing but store/retrieve spr value 422 */ 423 static void spr_load_dump_spr(int sprn) 424 { 425 #ifdef PPC_DUMP_SPR_ACCESSES 426 TCGv_i32 t0 = tcg_constant_i32(sprn); 427 gen_helper_load_dump_spr(tcg_env, t0); 428 #endif 429 } 430 431 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 432 { 433 gen_load_spr(cpu_gpr[gprn], sprn); 434 spr_load_dump_spr(sprn); 435 } 436 437 static void spr_store_dump_spr(int sprn) 438 { 439 #ifdef PPC_DUMP_SPR_ACCESSES 440 TCGv_i32 t0 = tcg_constant_i32(sprn); 441 gen_helper_store_dump_spr(tcg_env, t0); 442 #endif 443 } 444 445 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 446 { 447 gen_store_spr(sprn, cpu_gpr[gprn]); 448 spr_store_dump_spr(sprn); 449 } 450 451 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 452 { 453 #ifdef TARGET_PPC64 454 TCGv t0 = tcg_temp_new(); 455 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 456 gen_store_spr(sprn, t0); 457 spr_store_dump_spr(sprn); 458 #else 459 spr_write_generic(ctx, sprn, gprn); 460 #endif 461 } 462 463 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 464 { 465 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 466 spr_write_generic(ctx, sprn, gprn); 467 return; 468 } 469 470 if (!gen_serialize(ctx)) { 471 return; 472 } 473 474 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), 475 cpu_gpr[gprn]); 476 spr_store_dump_spr(sprn); 477 } 478 479 void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) 480 { 481 TCGv t0; 482 483 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 484 spr_write_generic32(ctx, sprn, gprn); 485 return; 486 } 487 488 if (!gen_serialize(ctx)) { 489 return; 490 } 491 492 t0 = tcg_temp_new(); 493 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 494 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0); 495 spr_store_dump_spr(sprn); 496 } 497 498 void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn) 499 { 500 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 501 spr_core_write_generic(ctx, sprn, gprn); 502 } else { 503 spr_write_generic(ctx, sprn, gprn); 504 } 505 } 506 507 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 508 { 509 /* This does not implement >1 thread */ 510 TCGv t0 = tcg_temp_new(); 511 TCGv t1 = tcg_temp_new(); 512 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 513 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 514 tcg_gen_or_tl(t1, t1, t0); 515 gen_store_spr(sprn, t1); 516 } 517 518 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 519 { 520 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 521 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 522 spr_write_CTRL_ST(ctx, sprn, gprn); 523 goto out; 524 } 525 526 if (!gen_serialize(ctx)) { 527 return; 528 } 529 530 gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), 531 cpu_gpr[gprn]); 532 out: 533 spr_store_dump_spr(sprn); 534 535 /* 536 * SPR_CTRL writes must force a new translation block, 537 * allowing the PMU to calculate the run latch events with 538 * more accuracy. 539 */ 540 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 541 } 542 543 #if !defined(CONFIG_USER_ONLY) 544 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 545 { 546 TCGv t0 = tcg_temp_new(); 547 TCGv t1 = tcg_temp_new(); 548 gen_load_spr(t0, sprn); 549 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 550 tcg_gen_and_tl(t0, t0, t1); 551 gen_store_spr(sprn, t0); 552 } 553 554 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 555 { 556 } 557 558 #endif 559 560 /* SPR common to all PowerPC */ 561 /* XER */ 562 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 563 { 564 TCGv dst = cpu_gpr[gprn]; 565 TCGv t0 = tcg_temp_new(); 566 TCGv t1 = tcg_temp_new(); 567 TCGv t2 = tcg_temp_new(); 568 tcg_gen_mov_tl(dst, cpu_xer); 569 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 570 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 571 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 572 tcg_gen_or_tl(t0, t0, t1); 573 tcg_gen_or_tl(dst, dst, t2); 574 tcg_gen_or_tl(dst, dst, t0); 575 if (is_isa300(ctx)) { 576 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 577 tcg_gen_or_tl(dst, dst, t0); 578 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 579 tcg_gen_or_tl(dst, dst, t0); 580 } 581 } 582 583 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 584 { 585 TCGv src = cpu_gpr[gprn]; 586 /* Write all flags, while reading back check for isa300 */ 587 tcg_gen_andi_tl(cpu_xer, src, 588 ~((1u << XER_SO) | 589 (1u << XER_OV) | (1u << XER_OV32) | 590 (1u << XER_CA) | (1u << XER_CA32))); 591 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 592 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 593 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 594 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 595 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 596 } 597 598 /* LR */ 599 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 600 { 601 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 602 } 603 604 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 605 { 606 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 607 } 608 609 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 610 /* Debug facilities */ 611 /* CFAR */ 612 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 613 { 614 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 615 } 616 617 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 618 { 619 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 620 } 621 622 /* Breakpoint */ 623 void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 624 { 625 translator_io_start(&ctx->base); 626 gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); 627 } 628 629 /* Watchpoint */ 630 void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) 631 { 632 translator_io_start(&ctx->base); 633 gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); 634 } 635 636 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) 637 { 638 translator_io_start(&ctx->base); 639 gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); 640 } 641 642 void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn) 643 { 644 translator_io_start(&ctx->base); 645 gen_helper_store_dawr1(tcg_env, cpu_gpr[gprn]); 646 } 647 648 void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn) 649 { 650 translator_io_start(&ctx->base); 651 gen_helper_store_dawrx1(tcg_env, cpu_gpr[gprn]); 652 } 653 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 654 655 /* CTR */ 656 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 657 { 658 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 659 } 660 661 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 662 { 663 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 664 } 665 666 /* User read access to SPR */ 667 /* USPRx */ 668 /* UMMCRx */ 669 /* UPMCx */ 670 /* USIA */ 671 /* UDECR */ 672 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 673 { 674 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 675 } 676 677 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 678 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 679 { 680 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 681 } 682 #endif 683 684 /* SPR common to all non-embedded PowerPC */ 685 /* DECR */ 686 #if !defined(CONFIG_USER_ONLY) 687 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 688 { 689 translator_io_start(&ctx->base); 690 gen_helper_load_decr(cpu_gpr[gprn], tcg_env); 691 } 692 693 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 694 { 695 translator_io_start(&ctx->base); 696 gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); 697 } 698 #endif 699 700 /* SPR common to all non-embedded PowerPC, except 601 */ 701 /* Time base */ 702 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 703 { 704 translator_io_start(&ctx->base); 705 gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); 706 } 707 708 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 709 { 710 translator_io_start(&ctx->base); 711 gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); 712 } 713 714 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 715 { 716 gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); 717 } 718 719 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 720 { 721 gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); 722 } 723 724 #if !defined(CONFIG_USER_ONLY) 725 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 726 { 727 if (!gen_serialize_core_lpar(ctx)) { 728 return; 729 } 730 731 translator_io_start(&ctx->base); 732 gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); 733 } 734 735 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 736 { 737 if (!gen_serialize_core_lpar(ctx)) { 738 return; 739 } 740 741 translator_io_start(&ctx->base); 742 gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); 743 } 744 745 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 746 { 747 gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); 748 } 749 750 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 751 { 752 gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); 753 } 754 755 #if defined(TARGET_PPC64) 756 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 757 { 758 translator_io_start(&ctx->base); 759 gen_helper_load_purr(cpu_gpr[gprn], tcg_env); 760 } 761 762 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 763 { 764 if (!gen_serialize_core_lpar(ctx)) { 765 return; 766 } 767 translator_io_start(&ctx->base); 768 gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); 769 } 770 771 /* HDECR */ 772 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 773 { 774 translator_io_start(&ctx->base); 775 gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); 776 } 777 778 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 779 { 780 if (!gen_serialize_core_lpar(ctx)) { 781 return; 782 } 783 translator_io_start(&ctx->base); 784 gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); 785 } 786 787 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 788 { 789 translator_io_start(&ctx->base); 790 gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); 791 } 792 793 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 794 { 795 if (!gen_serialize_core_lpar(ctx)) { 796 return; 797 } 798 translator_io_start(&ctx->base); 799 gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); 800 } 801 802 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 803 { 804 if (!gen_serialize_core_lpar(ctx)) { 805 return; 806 } 807 translator_io_start(&ctx->base); 808 gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); 809 } 810 811 #endif 812 #endif 813 814 #if !defined(CONFIG_USER_ONLY) 815 /* IBAT0U...IBAT0U */ 816 /* IBAT0L...IBAT7L */ 817 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 818 { 819 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 820 offsetof(CPUPPCState, 821 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 822 } 823 824 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 825 { 826 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 827 offsetof(CPUPPCState, 828 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 829 } 830 831 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 832 { 833 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 834 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 835 } 836 837 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 838 { 839 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 840 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 841 } 842 843 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 844 { 845 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 846 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 847 } 848 849 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 850 { 851 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 852 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 853 } 854 855 /* DBAT0U...DBAT7U */ 856 /* DBAT0L...DBAT7L */ 857 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 858 { 859 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 860 offsetof(CPUPPCState, 861 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 862 } 863 864 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 865 { 866 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 867 offsetof(CPUPPCState, 868 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 869 } 870 871 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 872 { 873 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 874 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 875 } 876 877 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 878 { 879 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 880 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 881 } 882 883 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 884 { 885 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 886 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 887 } 888 889 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 890 { 891 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 892 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 893 } 894 895 /* SDR1 */ 896 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 897 { 898 gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); 899 } 900 901 #if defined(TARGET_PPC64) 902 /* 64 bits PowerPC specific SPRs */ 903 /* PIDR */ 904 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 905 { 906 gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); 907 } 908 909 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 910 { 911 gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); 912 } 913 914 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 915 { 916 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix)); 917 } 918 919 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 920 { 921 TCGv t0 = tcg_temp_new(); 922 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 923 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 924 } 925 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 926 { 927 if (!gen_serialize_core(ctx)) { 928 return; 929 } 930 931 gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); 932 } 933 934 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 935 { 936 gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); 937 } 938 939 /* DPDES */ 940 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 941 { 942 if (!gen_serialize_core_lpar(ctx)) { 943 return; 944 } 945 946 gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); 947 } 948 949 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 950 { 951 if (!gen_serialize_core_lpar(ctx)) { 952 return; 953 } 954 955 gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); 956 } 957 #endif 958 #endif 959 960 /* PowerPC 40x specific registers */ 961 #if !defined(CONFIG_USER_ONLY) 962 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 963 { 964 translator_io_start(&ctx->base); 965 gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); 966 } 967 968 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 969 { 970 translator_io_start(&ctx->base); 971 gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); 972 } 973 974 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 975 { 976 translator_io_start(&ctx->base); 977 gen_store_spr(sprn, cpu_gpr[gprn]); 978 gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); 979 /* We must stop translation as we may have rebooted */ 980 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 981 } 982 983 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 984 { 985 translator_io_start(&ctx->base); 986 gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); 987 } 988 989 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 990 { 991 translator_io_start(&ctx->base); 992 gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); 993 } 994 995 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 996 { 997 translator_io_start(&ctx->base); 998 gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); 999 } 1000 1001 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 1002 { 1003 TCGv t0 = tcg_temp_new(); 1004 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 1005 gen_helper_store_40x_pid(tcg_env, t0); 1006 } 1007 1008 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 1009 { 1010 translator_io_start(&ctx->base); 1011 gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); 1012 } 1013 1014 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 1015 { 1016 translator_io_start(&ctx->base); 1017 gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); 1018 } 1019 #endif 1020 1021 /* PIR */ 1022 #if !defined(CONFIG_USER_ONLY) 1023 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 1024 { 1025 TCGv t0 = tcg_temp_new(); 1026 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 1027 gen_store_spr(SPR_PIR, t0); 1028 } 1029 #endif 1030 1031 /* SPE specific registers */ 1032 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 1033 { 1034 TCGv_i32 t0 = tcg_temp_new_i32(); 1035 tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1036 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 1037 } 1038 1039 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 1040 { 1041 TCGv_i32 t0 = tcg_temp_new_i32(); 1042 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 1043 tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1044 } 1045 1046 #if !defined(CONFIG_USER_ONLY) 1047 /* Callback used to write the exception vector base */ 1048 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 1049 { 1050 TCGv t0 = tcg_temp_new(); 1051 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); 1052 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1053 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 1054 gen_store_spr(sprn, t0); 1055 } 1056 1057 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 1058 { 1059 int sprn_offs; 1060 1061 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 1062 sprn_offs = sprn - SPR_BOOKE_IVOR0; 1063 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 1064 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 1065 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 1066 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 1067 } else { 1068 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 1069 " vector 0x%03x\n", sprn); 1070 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1071 return; 1072 } 1073 1074 TCGv t0 = tcg_temp_new(); 1075 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); 1076 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1077 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 1078 gen_store_spr(sprn, t0); 1079 } 1080 #endif 1081 1082 #ifdef TARGET_PPC64 1083 #ifndef CONFIG_USER_ONLY 1084 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1085 { 1086 TCGv t0 = tcg_temp_new(); 1087 TCGv t1 = tcg_temp_new(); 1088 TCGv t2 = tcg_temp_new(); 1089 1090 /* 1091 * Note, the HV=1 PR=0 case is handled earlier by simply using 1092 * spr_write_generic for HV mode in the SPR table 1093 */ 1094 1095 /* Build insertion mask into t1 based on context */ 1096 if (ctx->pr) { 1097 gen_load_spr(t1, SPR_UAMOR); 1098 } else { 1099 gen_load_spr(t1, SPR_AMOR); 1100 } 1101 1102 /* Mask new bits into t2 */ 1103 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1104 1105 /* Load AMR and clear new bits in t0 */ 1106 gen_load_spr(t0, SPR_AMR); 1107 tcg_gen_andc_tl(t0, t0, t1); 1108 1109 /* Or'in new bits and write it out */ 1110 tcg_gen_or_tl(t0, t0, t2); 1111 gen_store_spr(SPR_AMR, t0); 1112 spr_store_dump_spr(SPR_AMR); 1113 } 1114 1115 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1116 { 1117 TCGv t0 = tcg_temp_new(); 1118 TCGv t1 = tcg_temp_new(); 1119 TCGv t2 = tcg_temp_new(); 1120 1121 /* 1122 * Note, the HV=1 case is handled earlier by simply using 1123 * spr_write_generic for HV mode in the SPR table 1124 */ 1125 1126 /* Build insertion mask into t1 based on context */ 1127 gen_load_spr(t1, SPR_AMOR); 1128 1129 /* Mask new bits into t2 */ 1130 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1131 1132 /* Load AMR and clear new bits in t0 */ 1133 gen_load_spr(t0, SPR_UAMOR); 1134 tcg_gen_andc_tl(t0, t0, t1); 1135 1136 /* Or'in new bits and write it out */ 1137 tcg_gen_or_tl(t0, t0, t2); 1138 gen_store_spr(SPR_UAMOR, t0); 1139 spr_store_dump_spr(SPR_UAMOR); 1140 } 1141 1142 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1143 { 1144 TCGv t0 = tcg_temp_new(); 1145 TCGv t1 = tcg_temp_new(); 1146 TCGv t2 = tcg_temp_new(); 1147 1148 /* 1149 * Note, the HV=1 case is handled earlier by simply using 1150 * spr_write_generic for HV mode in the SPR table 1151 */ 1152 1153 /* Build insertion mask into t1 based on context */ 1154 gen_load_spr(t1, SPR_AMOR); 1155 1156 /* Mask new bits into t2 */ 1157 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1158 1159 /* Load AMR and clear new bits in t0 */ 1160 gen_load_spr(t0, SPR_IAMR); 1161 tcg_gen_andc_tl(t0, t0, t1); 1162 1163 /* Or'in new bits and write it out */ 1164 tcg_gen_or_tl(t0, t0, t2); 1165 gen_store_spr(SPR_IAMR, t0); 1166 spr_store_dump_spr(SPR_IAMR); 1167 } 1168 #endif 1169 #endif 1170 1171 #ifndef CONFIG_USER_ONLY 1172 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1173 { 1174 gen_helper_fixup_thrm(tcg_env); 1175 gen_load_spr(cpu_gpr[gprn], sprn); 1176 spr_load_dump_spr(sprn); 1177 } 1178 #endif /* !CONFIG_USER_ONLY */ 1179 1180 #if !defined(CONFIG_USER_ONLY) 1181 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1182 { 1183 TCGv t0 = tcg_temp_new(); 1184 1185 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1186 gen_store_spr(sprn, t0); 1187 } 1188 1189 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1190 { 1191 TCGv t0 = tcg_temp_new(); 1192 1193 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1194 gen_store_spr(sprn, t0); 1195 } 1196 1197 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1198 { 1199 TCGv t0 = tcg_temp_new(); 1200 1201 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1202 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1203 gen_store_spr(sprn, t0); 1204 } 1205 1206 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1207 { 1208 gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); 1209 } 1210 1211 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1212 { 1213 TCGv_i32 t0 = tcg_constant_i32(sprn); 1214 gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); 1215 } 1216 1217 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1218 { 1219 gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); 1220 } 1221 1222 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1223 { 1224 gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); 1225 } 1226 1227 #endif 1228 1229 #if !defined(CONFIG_USER_ONLY) 1230 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1231 { 1232 TCGv val = tcg_temp_new(); 1233 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1234 gen_store_spr(SPR_BOOKE_MAS3, val); 1235 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1236 gen_store_spr(SPR_BOOKE_MAS7, val); 1237 } 1238 1239 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1240 { 1241 TCGv mas7 = tcg_temp_new(); 1242 TCGv mas3 = tcg_temp_new(); 1243 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1244 tcg_gen_shli_tl(mas7, mas7, 32); 1245 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1246 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1247 } 1248 1249 #endif 1250 1251 #ifdef TARGET_PPC64 1252 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1253 int bit, int sprn, int cause) 1254 { 1255 TCGv_i32 t1 = tcg_constant_i32(bit); 1256 TCGv_i32 t2 = tcg_constant_i32(sprn); 1257 TCGv_i32 t3 = tcg_constant_i32(cause); 1258 1259 gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); 1260 } 1261 1262 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1263 int bit, int sprn, int cause) 1264 { 1265 TCGv_i32 t1 = tcg_constant_i32(bit); 1266 TCGv_i32 t2 = tcg_constant_i32(sprn); 1267 TCGv_i32 t3 = tcg_constant_i32(cause); 1268 1269 gen_helper_msr_facility_check(tcg_env, t1, t2, t3); 1270 } 1271 1272 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1273 { 1274 TCGv spr_up = tcg_temp_new(); 1275 TCGv spr = tcg_temp_new(); 1276 1277 gen_load_spr(spr, sprn - 1); 1278 tcg_gen_shri_tl(spr_up, spr, 32); 1279 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1280 } 1281 1282 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1283 { 1284 TCGv spr = tcg_temp_new(); 1285 1286 gen_load_spr(spr, sprn - 1); 1287 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1288 gen_store_spr(sprn - 1, spr); 1289 } 1290 1291 #if !defined(CONFIG_USER_ONLY) 1292 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1293 { 1294 TCGv hmer = tcg_temp_new(); 1295 1296 gen_load_spr(hmer, sprn); 1297 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1298 gen_store_spr(sprn, hmer); 1299 spr_store_dump_spr(sprn); 1300 } 1301 1302 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1303 { 1304 /* Reading TFMR can cause it to be updated, so serialize threads here too */ 1305 if (!gen_serialize_core(ctx)) { 1306 return; 1307 } 1308 gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); 1309 } 1310 1311 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1312 { 1313 if (!gen_serialize_core(ctx)) { 1314 return; 1315 } 1316 gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); 1317 } 1318 1319 void spr_write_sprc(DisasContext *ctx, int sprn, int gprn) 1320 { 1321 gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]); 1322 } 1323 1324 void spr_read_sprd(DisasContext *ctx, int gprn, int sprn) 1325 { 1326 gen_helper_load_sprd(cpu_gpr[gprn], tcg_env); 1327 } 1328 1329 void spr_write_sprd(DisasContext *ctx, int sprn, int gprn) 1330 { 1331 if (!gen_serialize_core(ctx)) { 1332 return; 1333 } 1334 gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]); 1335 } 1336 1337 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1338 { 1339 translator_io_start(&ctx->base); 1340 gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); 1341 } 1342 1343 void spr_read_pmsr(DisasContext *ctx, int gprn, int sprn) 1344 { 1345 translator_io_start(&ctx->base); 1346 gen_helper_load_pmsr(cpu_gpr[gprn], tcg_env); 1347 } 1348 1349 void spr_write_pmcr(DisasContext *ctx, int sprn, int gprn) 1350 { 1351 if (!gen_serialize_core_lpar(ctx)) { 1352 return; 1353 } 1354 translator_io_start(&ctx->base); 1355 gen_helper_store_pmcr(tcg_env, cpu_gpr[gprn]); 1356 } 1357 1358 #endif /* !defined(CONFIG_USER_ONLY) */ 1359 1360 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1361 { 1362 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1363 spr_read_generic(ctx, gprn, sprn); 1364 } 1365 1366 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1367 { 1368 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1369 spr_write_generic(ctx, sprn, gprn); 1370 } 1371 1372 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1373 { 1374 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1375 spr_read_generic(ctx, gprn, sprn); 1376 } 1377 1378 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1379 { 1380 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1381 spr_write_generic(ctx, sprn, gprn); 1382 } 1383 1384 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1385 { 1386 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1387 spr_read_prev_upper32(ctx, gprn, sprn); 1388 } 1389 1390 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1391 { 1392 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1393 spr_write_prev_upper32(ctx, sprn, gprn); 1394 } 1395 1396 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1397 { 1398 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1399 spr_read_generic(ctx, gprn, sprn); 1400 } 1401 1402 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1403 { 1404 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1405 spr_write_generic(ctx, sprn, gprn); 1406 } 1407 1408 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1409 { 1410 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1411 spr_read_prev_upper32(ctx, gprn, sprn); 1412 } 1413 1414 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1415 { 1416 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1417 spr_write_prev_upper32(ctx, sprn, gprn); 1418 } 1419 1420 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1421 { 1422 TCGv t0 = tcg_temp_new(); 1423 1424 /* 1425 * Access to the (H)DEXCR in problem state is done using separated 1426 * SPR indexes which are 16 below the SPR indexes which have full 1427 * access to the (H)DEXCR in privileged state. Problem state can 1428 * only read bits 32:63, bits 0:31 return 0. 1429 * 1430 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1431 */ 1432 1433 gen_load_spr(t0, sprn + 16); 1434 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1435 } 1436 1437 /* The PPR32 SPR accesses the upper 32-bits of PPR */ 1438 void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn) 1439 { 1440 gen_load_spr(cpu_gpr[gprn], SPR_PPR); 1441 tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32); 1442 spr_load_dump_spr(SPR_PPR); 1443 } 1444 1445 void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) 1446 { 1447 TCGv t0 = tcg_temp_new(); 1448 1449 /* 1450 * Don't clobber the low 32-bits of the PPR. These are all reserved bits 1451 * but TCG does implement them, so it would be surprising to zero them 1452 * here. "Priority nops" are similarly careful not to clobber reserved 1453 * bits. 1454 */ 1455 gen_load_spr(t0, SPR_PPR); 1456 tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32); 1457 gen_store_spr(SPR_PPR, t0); 1458 spr_store_dump_spr(SPR_PPR); 1459 } 1460 #endif 1461 1462 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1463 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1464 1465 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1466 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1467 1468 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1469 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1470 1471 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1472 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1473 1474 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1475 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1476 1477 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1478 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1479 1480 typedef struct opcode_t { 1481 unsigned char opc1, opc2, opc3, opc4; 1482 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1483 unsigned char pad[4]; 1484 #endif 1485 opc_handler_t handler; 1486 const char *oname; 1487 } opcode_t; 1488 1489 static void gen_priv_opc(DisasContext *ctx) 1490 { 1491 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1492 } 1493 1494 /* Helpers for priv. check */ 1495 #define GEN_PRIV(CTX) \ 1496 do { \ 1497 gen_priv_opc(CTX); return; \ 1498 } while (0) 1499 1500 #if defined(CONFIG_USER_ONLY) 1501 #define CHK_HV(CTX) GEN_PRIV(CTX) 1502 #define CHK_SV(CTX) GEN_PRIV(CTX) 1503 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1504 #else 1505 #define CHK_HV(CTX) \ 1506 do { \ 1507 if (unlikely(ctx->pr || !ctx->hv)) {\ 1508 GEN_PRIV(CTX); \ 1509 } \ 1510 } while (0) 1511 #define CHK_SV(CTX) \ 1512 do { \ 1513 if (unlikely(ctx->pr)) { \ 1514 GEN_PRIV(CTX); \ 1515 } \ 1516 } while (0) 1517 #define CHK_HVRM(CTX) \ 1518 do { \ 1519 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1520 GEN_PRIV(CTX); \ 1521 } \ 1522 } while (0) 1523 #endif 1524 1525 #define CHK_NONE(CTX) 1526 1527 /*****************************************************************************/ 1528 /* PowerPC instructions table */ 1529 1530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1531 { \ 1532 .opc1 = op1, \ 1533 .opc2 = op2, \ 1534 .opc3 = op3, \ 1535 .opc4 = 0xff, \ 1536 .handler = { \ 1537 .inval1 = invl, \ 1538 .type = _typ, \ 1539 .type2 = _typ2, \ 1540 .handler = &gen_##name, \ 1541 }, \ 1542 .oname = stringify(name), \ 1543 } 1544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1545 { \ 1546 .opc1 = op1, \ 1547 .opc2 = op2, \ 1548 .opc3 = op3, \ 1549 .opc4 = 0xff, \ 1550 .handler = { \ 1551 .inval1 = invl1, \ 1552 .inval2 = invl2, \ 1553 .type = _typ, \ 1554 .type2 = _typ2, \ 1555 .handler = &gen_##name, \ 1556 }, \ 1557 .oname = stringify(name), \ 1558 } 1559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1560 { \ 1561 .opc1 = op1, \ 1562 .opc2 = op2, \ 1563 .opc3 = op3, \ 1564 .opc4 = 0xff, \ 1565 .handler = { \ 1566 .inval1 = invl, \ 1567 .type = _typ, \ 1568 .type2 = _typ2, \ 1569 .handler = &gen_##name, \ 1570 }, \ 1571 .oname = onam, \ 1572 } 1573 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1574 { \ 1575 .opc1 = op1, \ 1576 .opc2 = op2, \ 1577 .opc3 = op3, \ 1578 .opc4 = op4, \ 1579 .handler = { \ 1580 .inval1 = invl, \ 1581 .type = _typ, \ 1582 .type2 = _typ2, \ 1583 .handler = &gen_##name, \ 1584 }, \ 1585 .oname = stringify(name), \ 1586 } 1587 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1588 { \ 1589 .opc1 = op1, \ 1590 .opc2 = op2, \ 1591 .opc3 = op3, \ 1592 .opc4 = op4, \ 1593 .handler = { \ 1594 .inval1 = invl, \ 1595 .type = _typ, \ 1596 .type2 = _typ2, \ 1597 .handler = &gen_##name, \ 1598 }, \ 1599 .oname = onam, \ 1600 } 1601 1602 /* Invalid instruction */ 1603 static void gen_invalid(DisasContext *ctx) 1604 { 1605 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1606 } 1607 1608 static opc_handler_t invalid_handler = { 1609 .inval1 = 0xFFFFFFFF, 1610 .inval2 = 0xFFFFFFFF, 1611 .type = PPC_NONE, 1612 .type2 = PPC_NONE, 1613 .handler = gen_invalid, 1614 }; 1615 1616 /*** Integer comparison ***/ 1617 1618 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1619 { 1620 TCGv t0 = tcg_temp_new(); 1621 TCGv_i32 t = tcg_temp_new_i32(); 1622 1623 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1624 t0, arg0, arg1, 1625 tcg_constant_tl(CRF_LT), tcg_constant_tl(CRF_EQ)); 1626 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1627 t0, arg0, arg1, tcg_constant_tl(CRF_GT), t0); 1628 1629 tcg_gen_trunc_tl_i32(t, t0); 1630 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1631 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1632 } 1633 1634 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1635 { 1636 TCGv t0 = tcg_constant_tl(arg1); 1637 gen_op_cmp(arg0, t0, s, crf); 1638 } 1639 1640 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1641 { 1642 TCGv t0, t1; 1643 t0 = tcg_temp_new(); 1644 t1 = tcg_temp_new(); 1645 if (s) { 1646 tcg_gen_ext32s_tl(t0, arg0); 1647 tcg_gen_ext32s_tl(t1, arg1); 1648 } else { 1649 tcg_gen_ext32u_tl(t0, arg0); 1650 tcg_gen_ext32u_tl(t1, arg1); 1651 } 1652 gen_op_cmp(t0, t1, s, crf); 1653 } 1654 1655 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1656 { 1657 TCGv t0 = tcg_constant_tl(arg1); 1658 gen_op_cmp32(arg0, t0, s, crf); 1659 } 1660 1661 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1662 { 1663 if (NARROW_MODE(ctx)) { 1664 gen_op_cmpi32(reg, 0, 1, 0); 1665 } else { 1666 gen_op_cmpi(reg, 0, 1, 0); 1667 } 1668 } 1669 1670 /*** Integer arithmetic ***/ 1671 1672 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1673 TCGv arg1, TCGv arg2, int sub) 1674 { 1675 TCGv t0 = tcg_temp_new(); 1676 1677 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1678 tcg_gen_xor_tl(t0, arg1, arg2); 1679 if (sub) { 1680 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1681 } else { 1682 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1683 } 1684 if (NARROW_MODE(ctx)) { 1685 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1686 if (is_isa300(ctx)) { 1687 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1688 } 1689 } else { 1690 if (is_isa300(ctx)) { 1691 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1692 } 1693 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1694 } 1695 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1696 } 1697 1698 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1699 TCGv res, TCGv arg0, TCGv arg1, 1700 TCGv ca32, int sub) 1701 { 1702 TCGv t0; 1703 1704 if (!is_isa300(ctx)) { 1705 return; 1706 } 1707 1708 t0 = tcg_temp_new(); 1709 if (sub) { 1710 tcg_gen_eqv_tl(t0, arg0, arg1); 1711 } else { 1712 tcg_gen_xor_tl(t0, arg0, arg1); 1713 } 1714 tcg_gen_xor_tl(t0, t0, res); 1715 tcg_gen_extract_tl(ca32, t0, 32, 1); 1716 } 1717 1718 /* Common add function */ 1719 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1720 TCGv arg2, TCGv ca, TCGv ca32, 1721 bool add_ca, bool compute_ca, 1722 bool compute_ov, bool compute_rc0) 1723 { 1724 TCGv t0 = ret; 1725 1726 if (compute_ca || compute_ov) { 1727 t0 = tcg_temp_new(); 1728 } 1729 1730 if (compute_ca) { 1731 if (NARROW_MODE(ctx)) { 1732 /* 1733 * Caution: a non-obvious corner case of the spec is that 1734 * we must produce the *entire* 64-bit addition, but 1735 * produce the carry into bit 32. 1736 */ 1737 TCGv t1 = tcg_temp_new(); 1738 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1739 tcg_gen_add_tl(t0, arg1, arg2); 1740 if (add_ca) { 1741 tcg_gen_add_tl(t0, t0, ca); 1742 } 1743 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1744 tcg_gen_extract_tl(ca, ca, 32, 1); 1745 if (is_isa300(ctx)) { 1746 tcg_gen_mov_tl(ca32, ca); 1747 } 1748 } else { 1749 if (add_ca) { 1750 tcg_gen_addcio_tl(t0, ca, arg1, arg2, ca); 1751 } else { 1752 TCGv zero = tcg_constant_tl(0); 1753 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1754 } 1755 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1756 } 1757 } else { 1758 tcg_gen_add_tl(t0, arg1, arg2); 1759 if (add_ca) { 1760 tcg_gen_add_tl(t0, t0, ca); 1761 } 1762 } 1763 1764 if (compute_ov) { 1765 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1766 } 1767 if (unlikely(compute_rc0)) { 1768 gen_set_Rc0(ctx, t0); 1769 } 1770 1771 if (t0 != ret) { 1772 tcg_gen_mov_tl(ret, t0); 1773 } 1774 } 1775 1776 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, 1777 TCGv arg1, TCGv arg2, bool sign, 1778 bool compute_ov, bool compute_rc0) 1779 { 1780 TCGv_i32 t0 = tcg_temp_new_i32(); 1781 TCGv_i32 t1 = tcg_temp_new_i32(); 1782 TCGv_i32 t2 = tcg_temp_new_i32(); 1783 TCGv_i32 t3 = tcg_temp_new_i32(); 1784 1785 tcg_gen_trunc_tl_i32(t0, arg1); 1786 tcg_gen_trunc_tl_i32(t1, arg2); 1787 if (sign) { 1788 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1789 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1790 tcg_gen_and_i32(t2, t2, t3); 1791 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1792 tcg_gen_or_i32(t2, t2, t3); 1793 tcg_gen_movi_i32(t3, 0); 1794 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1795 tcg_gen_div_i32(t3, t0, t1); 1796 tcg_gen_extu_i32_tl(ret, t3); 1797 } else { 1798 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1799 tcg_gen_movi_i32(t3, 0); 1800 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1801 tcg_gen_divu_i32(t3, t0, t1); 1802 tcg_gen_extu_i32_tl(ret, t3); 1803 } 1804 if (compute_ov) { 1805 tcg_gen_extu_i32_tl(cpu_ov, t2); 1806 if (is_isa300(ctx)) { 1807 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1808 } 1809 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1810 } 1811 1812 if (unlikely(compute_rc0)) { 1813 gen_set_Rc0(ctx, ret); 1814 } 1815 } 1816 1817 #if defined(TARGET_PPC64) 1818 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, 1819 TCGv arg1, TCGv arg2, bool sign, 1820 bool compute_ov, bool compute_rc0) 1821 { 1822 TCGv_i64 t0 = tcg_temp_new_i64(); 1823 TCGv_i64 t1 = tcg_temp_new_i64(); 1824 TCGv_i64 t2 = tcg_temp_new_i64(); 1825 TCGv_i64 t3 = tcg_temp_new_i64(); 1826 1827 tcg_gen_mov_i64(t0, arg1); 1828 tcg_gen_mov_i64(t1, arg2); 1829 if (sign) { 1830 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1831 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1832 tcg_gen_and_i64(t2, t2, t3); 1833 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1834 tcg_gen_or_i64(t2, t2, t3); 1835 tcg_gen_movi_i64(t3, 0); 1836 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1837 tcg_gen_div_i64(ret, t0, t1); 1838 } else { 1839 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1840 tcg_gen_movi_i64(t3, 0); 1841 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1842 tcg_gen_divu_i64(ret, t0, t1); 1843 } 1844 if (compute_ov) { 1845 tcg_gen_mov_tl(cpu_ov, t2); 1846 if (is_isa300(ctx)) { 1847 tcg_gen_mov_tl(cpu_ov32, t2); 1848 } 1849 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1850 } 1851 1852 if (unlikely(compute_rc0)) { 1853 gen_set_Rc0(ctx, ret); 1854 } 1855 } 1856 #endif 1857 1858 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1859 TCGv arg2, int sign) 1860 { 1861 TCGv_i32 t0 = tcg_temp_new_i32(); 1862 TCGv_i32 t1 = tcg_temp_new_i32(); 1863 1864 tcg_gen_trunc_tl_i32(t0, arg1); 1865 tcg_gen_trunc_tl_i32(t1, arg2); 1866 if (sign) { 1867 TCGv_i32 t2 = tcg_temp_new_i32(); 1868 TCGv_i32 t3 = tcg_temp_new_i32(); 1869 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1870 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1871 tcg_gen_and_i32(t2, t2, t3); 1872 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1873 tcg_gen_or_i32(t2, t2, t3); 1874 tcg_gen_movi_i32(t3, 0); 1875 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1876 tcg_gen_rem_i32(t3, t0, t1); 1877 tcg_gen_ext_i32_tl(ret, t3); 1878 } else { 1879 TCGv_i32 t2 = tcg_constant_i32(1); 1880 TCGv_i32 t3 = tcg_constant_i32(0); 1881 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1882 tcg_gen_remu_i32(t0, t0, t1); 1883 tcg_gen_extu_i32_tl(ret, t0); 1884 } 1885 } 1886 1887 #if defined(TARGET_PPC64) 1888 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1889 TCGv arg2, int sign) 1890 { 1891 TCGv_i64 t0 = tcg_temp_new_i64(); 1892 TCGv_i64 t1 = tcg_temp_new_i64(); 1893 1894 tcg_gen_mov_i64(t0, arg1); 1895 tcg_gen_mov_i64(t1, arg2); 1896 if (sign) { 1897 TCGv_i64 t2 = tcg_temp_new_i64(); 1898 TCGv_i64 t3 = tcg_temp_new_i64(); 1899 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1900 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1901 tcg_gen_and_i64(t2, t2, t3); 1902 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1903 tcg_gen_or_i64(t2, t2, t3); 1904 tcg_gen_movi_i64(t3, 0); 1905 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1906 tcg_gen_rem_i64(ret, t0, t1); 1907 } else { 1908 TCGv_i64 t2 = tcg_constant_i64(1); 1909 TCGv_i64 t3 = tcg_constant_i64(0); 1910 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1911 tcg_gen_remu_i64(ret, t0, t1); 1912 } 1913 } 1914 #endif 1915 1916 /* Common subf function */ 1917 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1918 TCGv arg2, bool add_ca, bool compute_ca, 1919 bool compute_ov, bool compute_rc0) 1920 { 1921 TCGv t0 = ret; 1922 1923 if (compute_ca || compute_ov) { 1924 t0 = tcg_temp_new(); 1925 } 1926 1927 if (compute_ca) { 1928 /* dest = ~arg1 + arg2 [+ ca]. */ 1929 if (NARROW_MODE(ctx)) { 1930 /* 1931 * Caution: a non-obvious corner case of the spec is that 1932 * we must produce the *entire* 64-bit addition, but 1933 * produce the carry into bit 32. 1934 */ 1935 TCGv inv1 = tcg_temp_new(); 1936 TCGv t1 = tcg_temp_new(); 1937 tcg_gen_not_tl(inv1, arg1); 1938 if (add_ca) { 1939 tcg_gen_add_tl(t0, arg2, cpu_ca); 1940 } else { 1941 tcg_gen_addi_tl(t0, arg2, 1); 1942 } 1943 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1944 tcg_gen_add_tl(t0, t0, inv1); 1945 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1946 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1947 if (is_isa300(ctx)) { 1948 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1949 } 1950 } else if (add_ca) { 1951 TCGv inv1 = tcg_temp_new(); 1952 tcg_gen_not_tl(inv1, arg1); 1953 tcg_gen_addcio_tl(t0, cpu_ca, arg2, inv1, cpu_ca); 1954 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1955 } else { 1956 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1957 tcg_gen_sub_tl(t0, arg2, arg1); 1958 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1959 } 1960 } else if (add_ca) { 1961 /* 1962 * Since we're ignoring carry-out, we can simplify the 1963 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1964 */ 1965 tcg_gen_sub_tl(t0, arg2, arg1); 1966 tcg_gen_add_tl(t0, t0, cpu_ca); 1967 tcg_gen_subi_tl(t0, t0, 1); 1968 } else { 1969 tcg_gen_sub_tl(t0, arg2, arg1); 1970 } 1971 1972 if (compute_ov) { 1973 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1974 } 1975 if (unlikely(compute_rc0)) { 1976 gen_set_Rc0(ctx, t0); 1977 } 1978 1979 if (t0 != ret) { 1980 tcg_gen_mov_tl(ret, t0); 1981 } 1982 } 1983 1984 /*** Integer logical ***/ 1985 1986 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1987 static void gen_pause(DisasContext *ctx) 1988 { 1989 TCGv_i32 t0 = tcg_constant_i32(0); 1990 tcg_gen_st_i32(t0, tcg_env, 1991 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1992 1993 /* Stop translation, this gives other CPUs a chance to run */ 1994 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1995 } 1996 #endif /* defined(TARGET_PPC64) */ 1997 1998 /*** Integer rotate ***/ 1999 2000 /* rlwimi & rlwimi. */ 2001 static void gen_rlwimi(DisasContext *ctx) 2002 { 2003 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2004 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2005 uint32_t sh = SH(ctx->opcode); 2006 uint32_t mb = MB(ctx->opcode); 2007 uint32_t me = ME(ctx->opcode); 2008 2009 if (sh == (31 - me) && mb <= me) { 2010 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2011 } else { 2012 target_ulong mask; 2013 bool mask_in_32b = true; 2014 TCGv t1; 2015 2016 #if defined(TARGET_PPC64) 2017 mb += 32; 2018 me += 32; 2019 #endif 2020 mask = MASK(mb, me); 2021 2022 #if defined(TARGET_PPC64) 2023 if (mask > 0xffffffffu) { 2024 mask_in_32b = false; 2025 } 2026 #endif 2027 t1 = tcg_temp_new(); 2028 if (mask_in_32b) { 2029 TCGv_i32 t0 = tcg_temp_new_i32(); 2030 tcg_gen_trunc_tl_i32(t0, t_rs); 2031 tcg_gen_rotli_i32(t0, t0, sh); 2032 tcg_gen_extu_i32_tl(t1, t0); 2033 } else { 2034 #if defined(TARGET_PPC64) 2035 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2036 tcg_gen_rotli_i64(t1, t1, sh); 2037 #else 2038 g_assert_not_reached(); 2039 #endif 2040 } 2041 2042 tcg_gen_andi_tl(t1, t1, mask); 2043 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2044 tcg_gen_or_tl(t_ra, t_ra, t1); 2045 } 2046 if (unlikely(Rc(ctx->opcode) != 0)) { 2047 gen_set_Rc0(ctx, t_ra); 2048 } 2049 } 2050 2051 /* rlwinm & rlwinm. */ 2052 static void gen_rlwinm(DisasContext *ctx) 2053 { 2054 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2055 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2056 int sh = SH(ctx->opcode); 2057 int mb = MB(ctx->opcode); 2058 int me = ME(ctx->opcode); 2059 int len = me - mb + 1; 2060 int rsh = (32 - sh) & 31; 2061 2062 if (sh != 0 && len > 0 && me == (31 - sh)) { 2063 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2064 } else if (me == 31 && rsh + len <= 32) { 2065 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2066 } else { 2067 target_ulong mask; 2068 bool mask_in_32b = true; 2069 #if defined(TARGET_PPC64) 2070 mb += 32; 2071 me += 32; 2072 #endif 2073 mask = MASK(mb, me); 2074 #if defined(TARGET_PPC64) 2075 if (mask > 0xffffffffu) { 2076 mask_in_32b = false; 2077 } 2078 #endif 2079 if (mask_in_32b) { 2080 if (sh == 0) { 2081 tcg_gen_andi_tl(t_ra, t_rs, mask); 2082 } else { 2083 TCGv_i32 t0 = tcg_temp_new_i32(); 2084 tcg_gen_trunc_tl_i32(t0, t_rs); 2085 tcg_gen_rotli_i32(t0, t0, sh); 2086 tcg_gen_andi_i32(t0, t0, mask); 2087 tcg_gen_extu_i32_tl(t_ra, t0); 2088 } 2089 } else { 2090 #if defined(TARGET_PPC64) 2091 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2092 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2093 tcg_gen_andi_i64(t_ra, t_ra, mask); 2094 #else 2095 g_assert_not_reached(); 2096 #endif 2097 } 2098 } 2099 if (unlikely(Rc(ctx->opcode) != 0)) { 2100 gen_set_Rc0(ctx, t_ra); 2101 } 2102 } 2103 2104 /* rlwnm & rlwnm. */ 2105 static void gen_rlwnm(DisasContext *ctx) 2106 { 2107 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2108 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2109 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2110 uint32_t mb = MB(ctx->opcode); 2111 uint32_t me = ME(ctx->opcode); 2112 target_ulong mask; 2113 bool mask_in_32b = true; 2114 2115 #if defined(TARGET_PPC64) 2116 mb += 32; 2117 me += 32; 2118 #endif 2119 mask = MASK(mb, me); 2120 2121 #if defined(TARGET_PPC64) 2122 if (mask > 0xffffffffu) { 2123 mask_in_32b = false; 2124 } 2125 #endif 2126 if (mask_in_32b) { 2127 TCGv_i32 t0 = tcg_temp_new_i32(); 2128 TCGv_i32 t1 = tcg_temp_new_i32(); 2129 tcg_gen_trunc_tl_i32(t0, t_rb); 2130 tcg_gen_trunc_tl_i32(t1, t_rs); 2131 tcg_gen_andi_i32(t0, t0, 0x1f); 2132 tcg_gen_rotl_i32(t1, t1, t0); 2133 tcg_gen_extu_i32_tl(t_ra, t1); 2134 } else { 2135 #if defined(TARGET_PPC64) 2136 TCGv_i64 t0 = tcg_temp_new_i64(); 2137 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2138 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2139 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2140 #else 2141 g_assert_not_reached(); 2142 #endif 2143 } 2144 2145 tcg_gen_andi_tl(t_ra, t_ra, mask); 2146 2147 if (unlikely(Rc(ctx->opcode) != 0)) { 2148 gen_set_Rc0(ctx, t_ra); 2149 } 2150 } 2151 2152 #if defined(TARGET_PPC64) 2153 #define GEN_PPC64_R2(name, opc1, opc2) \ 2154 static void glue(gen_, name##0)(DisasContext *ctx) \ 2155 { \ 2156 gen_##name(ctx, 0); \ 2157 } \ 2158 \ 2159 static void glue(gen_, name##1)(DisasContext *ctx) \ 2160 { \ 2161 gen_##name(ctx, 1); \ 2162 } 2163 #define GEN_PPC64_R4(name, opc1, opc2) \ 2164 static void glue(gen_, name##0)(DisasContext *ctx) \ 2165 { \ 2166 gen_##name(ctx, 0, 0); \ 2167 } \ 2168 \ 2169 static void glue(gen_, name##1)(DisasContext *ctx) \ 2170 { \ 2171 gen_##name(ctx, 0, 1); \ 2172 } \ 2173 \ 2174 static void glue(gen_, name##2)(DisasContext *ctx) \ 2175 { \ 2176 gen_##name(ctx, 1, 0); \ 2177 } \ 2178 \ 2179 static void glue(gen_, name##3)(DisasContext *ctx) \ 2180 { \ 2181 gen_##name(ctx, 1, 1); \ 2182 } 2183 2184 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2185 { 2186 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2187 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2188 int len = me - mb + 1; 2189 int rsh = (64 - sh) & 63; 2190 2191 if (sh != 0 && len > 0 && me == (63 - sh)) { 2192 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2193 } else if (me == 63 && rsh + len <= 64) { 2194 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2195 } else { 2196 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2197 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2198 } 2199 if (unlikely(Rc(ctx->opcode) != 0)) { 2200 gen_set_Rc0(ctx, t_ra); 2201 } 2202 } 2203 2204 /* rldicl - rldicl. */ 2205 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2206 { 2207 uint32_t sh, mb; 2208 2209 sh = SH(ctx->opcode) | (shn << 5); 2210 mb = MB(ctx->opcode) | (mbn << 5); 2211 gen_rldinm(ctx, mb, 63, sh); 2212 } 2213 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2214 2215 /* rldicr - rldicr. */ 2216 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2217 { 2218 uint32_t sh, me; 2219 2220 sh = SH(ctx->opcode) | (shn << 5); 2221 me = MB(ctx->opcode) | (men << 5); 2222 gen_rldinm(ctx, 0, me, sh); 2223 } 2224 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2225 2226 /* rldic - rldic. */ 2227 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2228 { 2229 uint32_t sh, mb; 2230 2231 sh = SH(ctx->opcode) | (shn << 5); 2232 mb = MB(ctx->opcode) | (mbn << 5); 2233 gen_rldinm(ctx, mb, 63 - sh, sh); 2234 } 2235 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2236 2237 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2238 { 2239 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2240 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2241 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2242 TCGv t0; 2243 2244 t0 = tcg_temp_new(); 2245 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2246 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2247 2248 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2249 if (unlikely(Rc(ctx->opcode) != 0)) { 2250 gen_set_Rc0(ctx, t_ra); 2251 } 2252 } 2253 2254 /* rldcl - rldcl. */ 2255 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2256 { 2257 uint32_t mb; 2258 2259 mb = MB(ctx->opcode) | (mbn << 5); 2260 gen_rldnm(ctx, mb, 63); 2261 } 2262 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2263 2264 /* rldcr - rldcr. */ 2265 static inline void gen_rldcr(DisasContext *ctx, int men) 2266 { 2267 uint32_t me; 2268 2269 me = MB(ctx->opcode) | (men << 5); 2270 gen_rldnm(ctx, 0, me); 2271 } 2272 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2273 2274 /* rldimi - rldimi. */ 2275 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2276 { 2277 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2278 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2279 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2280 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2281 uint32_t me = 63 - sh; 2282 2283 if (mb <= me) { 2284 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2285 } else { 2286 target_ulong mask = MASK(mb, me); 2287 TCGv t1 = tcg_temp_new(); 2288 2289 tcg_gen_rotli_tl(t1, t_rs, sh); 2290 tcg_gen_andi_tl(t1, t1, mask); 2291 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2292 tcg_gen_or_tl(t_ra, t_ra, t1); 2293 } 2294 if (unlikely(Rc(ctx->opcode) != 0)) { 2295 gen_set_Rc0(ctx, t_ra); 2296 } 2297 } 2298 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2299 #endif 2300 2301 /*** Integer shift ***/ 2302 2303 /* slw & slw. */ 2304 static void gen_slw(DisasContext *ctx) 2305 { 2306 TCGv t0, t1; 2307 2308 t0 = tcg_temp_new(); 2309 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2310 #if defined(TARGET_PPC64) 2311 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2312 tcg_gen_sari_tl(t0, t0, 0x3f); 2313 #else 2314 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2315 tcg_gen_sari_tl(t0, t0, 0x1f); 2316 #endif 2317 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2318 t1 = tcg_temp_new(); 2319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2320 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2321 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2322 if (unlikely(Rc(ctx->opcode) != 0)) { 2323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2324 } 2325 } 2326 2327 /* sraw & sraw. */ 2328 static void gen_sraw(DisasContext *ctx) 2329 { 2330 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, 2331 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2332 if (unlikely(Rc(ctx->opcode) != 0)) { 2333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2334 } 2335 } 2336 2337 /* srawi & srawi. */ 2338 static void gen_srawi(DisasContext *ctx) 2339 { 2340 int sh = SH(ctx->opcode); 2341 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2342 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2343 if (sh == 0) { 2344 tcg_gen_ext32s_tl(dst, src); 2345 tcg_gen_movi_tl(cpu_ca, 0); 2346 if (is_isa300(ctx)) { 2347 tcg_gen_movi_tl(cpu_ca32, 0); 2348 } 2349 } else { 2350 TCGv t0; 2351 tcg_gen_ext32s_tl(dst, src); 2352 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2353 t0 = tcg_temp_new(); 2354 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2355 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2356 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2357 if (is_isa300(ctx)) { 2358 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2359 } 2360 tcg_gen_sari_tl(dst, dst, sh); 2361 } 2362 if (unlikely(Rc(ctx->opcode) != 0)) { 2363 gen_set_Rc0(ctx, dst); 2364 } 2365 } 2366 2367 /* srw & srw. */ 2368 static void gen_srw(DisasContext *ctx) 2369 { 2370 TCGv t0, t1; 2371 2372 t0 = tcg_temp_new(); 2373 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2374 #if defined(TARGET_PPC64) 2375 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2376 tcg_gen_sari_tl(t0, t0, 0x3f); 2377 #else 2378 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2379 tcg_gen_sari_tl(t0, t0, 0x1f); 2380 #endif 2381 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2382 tcg_gen_ext32u_tl(t0, t0); 2383 t1 = tcg_temp_new(); 2384 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2385 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2386 if (unlikely(Rc(ctx->opcode) != 0)) { 2387 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2388 } 2389 } 2390 2391 #if defined(TARGET_PPC64) 2392 /* sld & sld. */ 2393 static void gen_sld(DisasContext *ctx) 2394 { 2395 TCGv t0, t1; 2396 2397 t0 = tcg_temp_new(); 2398 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2399 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2400 tcg_gen_sari_tl(t0, t0, 0x3f); 2401 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2402 t1 = tcg_temp_new(); 2403 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2404 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2405 if (unlikely(Rc(ctx->opcode) != 0)) { 2406 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2407 } 2408 } 2409 2410 /* srad & srad. */ 2411 static void gen_srad(DisasContext *ctx) 2412 { 2413 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, 2414 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2415 if (unlikely(Rc(ctx->opcode) != 0)) { 2416 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2417 } 2418 } 2419 /* sradi & sradi. */ 2420 static inline void gen_sradi(DisasContext *ctx, int n) 2421 { 2422 int sh = SH(ctx->opcode) + (n << 5); 2423 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2424 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2425 if (sh == 0) { 2426 tcg_gen_mov_tl(dst, src); 2427 tcg_gen_movi_tl(cpu_ca, 0); 2428 if (is_isa300(ctx)) { 2429 tcg_gen_movi_tl(cpu_ca32, 0); 2430 } 2431 } else { 2432 TCGv t0; 2433 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2434 t0 = tcg_temp_new(); 2435 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2436 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2437 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2438 if (is_isa300(ctx)) { 2439 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2440 } 2441 tcg_gen_sari_tl(dst, src, sh); 2442 } 2443 if (unlikely(Rc(ctx->opcode) != 0)) { 2444 gen_set_Rc0(ctx, dst); 2445 } 2446 } 2447 2448 static void gen_sradi0(DisasContext *ctx) 2449 { 2450 gen_sradi(ctx, 0); 2451 } 2452 2453 static void gen_sradi1(DisasContext *ctx) 2454 { 2455 gen_sradi(ctx, 1); 2456 } 2457 2458 /* extswsli & extswsli. */ 2459 static inline void gen_extswsli(DisasContext *ctx, int n) 2460 { 2461 int sh = SH(ctx->opcode) + (n << 5); 2462 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2463 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2464 2465 tcg_gen_ext32s_tl(dst, src); 2466 tcg_gen_shli_tl(dst, dst, sh); 2467 if (unlikely(Rc(ctx->opcode) != 0)) { 2468 gen_set_Rc0(ctx, dst); 2469 } 2470 } 2471 2472 static void gen_extswsli0(DisasContext *ctx) 2473 { 2474 gen_extswsli(ctx, 0); 2475 } 2476 2477 static void gen_extswsli1(DisasContext *ctx) 2478 { 2479 gen_extswsli(ctx, 1); 2480 } 2481 2482 /* srd & srd. */ 2483 static void gen_srd(DisasContext *ctx) 2484 { 2485 TCGv t0, t1; 2486 2487 t0 = tcg_temp_new(); 2488 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2489 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2490 tcg_gen_sari_tl(t0, t0, 0x3f); 2491 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2492 t1 = tcg_temp_new(); 2493 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2494 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2495 if (unlikely(Rc(ctx->opcode) != 0)) { 2496 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2497 } 2498 } 2499 #endif 2500 2501 /*** Addressing modes ***/ 2502 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2503 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2504 target_long maskl) 2505 { 2506 target_long simm = SIMM(ctx->opcode); 2507 2508 simm &= ~maskl; 2509 if (rA(ctx->opcode) == 0) { 2510 if (NARROW_MODE(ctx)) { 2511 simm = (uint32_t)simm; 2512 } 2513 tcg_gen_movi_tl(EA, simm); 2514 } else if (likely(simm != 0)) { 2515 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2516 if (NARROW_MODE(ctx)) { 2517 tcg_gen_ext32u_tl(EA, EA); 2518 } 2519 } else { 2520 if (NARROW_MODE(ctx)) { 2521 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2522 } else { 2523 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2524 } 2525 } 2526 } 2527 2528 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2529 { 2530 if (rA(ctx->opcode) == 0) { 2531 if (NARROW_MODE(ctx)) { 2532 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2533 } else { 2534 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2535 } 2536 } else { 2537 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2538 if (NARROW_MODE(ctx)) { 2539 tcg_gen_ext32u_tl(EA, EA); 2540 } 2541 } 2542 } 2543 2544 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2545 { 2546 if (rA(ctx->opcode) == 0) { 2547 tcg_gen_movi_tl(EA, 0); 2548 } else if (NARROW_MODE(ctx)) { 2549 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2550 } else { 2551 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2552 } 2553 } 2554 2555 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2556 target_long val) 2557 { 2558 tcg_gen_addi_tl(ret, arg1, val); 2559 if (NARROW_MODE(ctx)) { 2560 tcg_gen_ext32u_tl(ret, ret); 2561 } 2562 } 2563 2564 static inline void gen_align_no_le(DisasContext *ctx) 2565 { 2566 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2567 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2568 } 2569 2570 /* EA <- {(ra == 0) ? 0 : GPR[ra]} + displ */ 2571 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 2572 { 2573 TCGv ea = tcg_temp_new(); 2574 if (ra) { 2575 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 2576 } else { 2577 tcg_gen_mov_tl(ea, displ); 2578 } 2579 if (NARROW_MODE(ctx)) { 2580 tcg_gen_ext32u_tl(ea, ea); 2581 } 2582 return ea; 2583 } 2584 2585 #if defined(TARGET_PPC64) 2586 /* EA <- (ra == 0) ? 0 : GPR[ra] */ 2587 static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) 2588 { 2589 TCGv EA = tcg_temp_new(); 2590 if (!ra) { 2591 tcg_gen_movi_tl(EA, 0); 2592 } else if (NARROW_MODE(ctx)) { 2593 tcg_gen_ext32u_tl(EA, cpu_gpr[ra]); 2594 } else { 2595 tcg_gen_mov_tl(EA, cpu_gpr[ra]); 2596 } 2597 return EA; 2598 } 2599 #endif 2600 2601 /*** Integer load ***/ 2602 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2603 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2604 2605 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2606 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2607 TCGv val, \ 2608 TCGv addr) \ 2609 { \ 2610 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2611 } 2612 2613 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2614 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2615 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2616 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2617 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2618 2619 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2620 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2621 2622 #define GEN_QEMU_LOAD_64(ldop, op) \ 2623 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2624 TCGv_i64 val, \ 2625 TCGv addr) \ 2626 { \ 2627 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2628 } 2629 2630 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2631 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2632 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2633 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2634 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 2635 2636 #if defined(TARGET_PPC64) 2637 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 2638 #endif 2639 2640 #define GEN_QEMU_STORE_TL(stop, op) \ 2641 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2642 TCGv val, \ 2643 TCGv addr) \ 2644 { \ 2645 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2646 } 2647 2648 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 2649 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2650 #endif 2651 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2652 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2653 2654 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2655 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2656 2657 #define GEN_QEMU_STORE_64(stop, op) \ 2658 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2659 TCGv_i64 val, \ 2660 TCGv addr) \ 2661 { \ 2662 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2663 } 2664 2665 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2666 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2667 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2668 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 2669 2670 #if defined(TARGET_PPC64) 2671 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 2672 #endif 2673 2674 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2675 static void glue(gen_, name##x)(DisasContext *ctx) \ 2676 { \ 2677 TCGv EA; \ 2678 chk(ctx); \ 2679 gen_set_access_type(ctx, ACCESS_INT); \ 2680 EA = tcg_temp_new(); \ 2681 gen_addr_reg_index(ctx, EA); \ 2682 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2683 } 2684 2685 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2686 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2687 2688 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2689 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2690 2691 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2692 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2693 { \ 2694 TCGv EA; \ 2695 CHK_SV(ctx); \ 2696 gen_set_access_type(ctx, ACCESS_INT); \ 2697 EA = tcg_temp_new(); \ 2698 gen_addr_reg_index(ctx, EA); \ 2699 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2700 } 2701 2702 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2703 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2704 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2705 #if defined(TARGET_PPC64) 2706 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 2707 #endif 2708 2709 #if defined(TARGET_PPC64) 2710 /* CI load/store variants */ 2711 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2712 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2713 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2714 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2715 #endif 2716 2717 /*** Integer store ***/ 2718 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2719 static void glue(gen_, name##x)(DisasContext *ctx) \ 2720 { \ 2721 TCGv EA; \ 2722 chk(ctx); \ 2723 gen_set_access_type(ctx, ACCESS_INT); \ 2724 EA = tcg_temp_new(); \ 2725 gen_addr_reg_index(ctx, EA); \ 2726 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2727 } 2728 #define GEN_STX(name, stop, opc2, opc3, type) \ 2729 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2730 2731 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2732 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2733 2734 #define GEN_STEPX(name, stop, opc2, opc3) \ 2735 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2736 { \ 2737 TCGv EA; \ 2738 CHK_SV(ctx); \ 2739 gen_set_access_type(ctx, ACCESS_INT); \ 2740 EA = tcg_temp_new(); \ 2741 gen_addr_reg_index(ctx, EA); \ 2742 tcg_gen_qemu_st_tl( \ 2743 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2744 } 2745 2746 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2747 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2748 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2749 #if defined(TARGET_PPC64) 2750 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 2751 #endif 2752 2753 #if defined(TARGET_PPC64) 2754 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2755 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2756 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2757 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2758 #endif 2759 /*** Integer load and store with byte reverse ***/ 2760 2761 /* lhbrx */ 2762 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2763 2764 /* lwbrx */ 2765 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2766 2767 #if defined(TARGET_PPC64) 2768 /* ldbrx */ 2769 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2770 /* stdbrx */ 2771 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2772 #endif /* TARGET_PPC64 */ 2773 2774 /* sthbrx */ 2775 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2776 /* stwbrx */ 2777 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2778 2779 /*** Integer load and store multiple ***/ 2780 2781 /* lmw */ 2782 static void gen_lmw(DisasContext *ctx) 2783 { 2784 TCGv t0; 2785 TCGv_i32 t1; 2786 2787 if (ctx->le_mode) { 2788 gen_align_no_le(ctx); 2789 return; 2790 } 2791 gen_set_access_type(ctx, ACCESS_INT); 2792 t0 = tcg_temp_new(); 2793 t1 = tcg_constant_i32(rD(ctx->opcode)); 2794 gen_addr_imm_index(ctx, t0, 0); 2795 gen_helper_lmw(tcg_env, t0, t1); 2796 } 2797 2798 /* stmw */ 2799 static void gen_stmw(DisasContext *ctx) 2800 { 2801 TCGv t0; 2802 TCGv_i32 t1; 2803 2804 if (ctx->le_mode) { 2805 gen_align_no_le(ctx); 2806 return; 2807 } 2808 gen_set_access_type(ctx, ACCESS_INT); 2809 t0 = tcg_temp_new(); 2810 t1 = tcg_constant_i32(rS(ctx->opcode)); 2811 gen_addr_imm_index(ctx, t0, 0); 2812 gen_helper_stmw(tcg_env, t0, t1); 2813 } 2814 2815 /*** Integer load and store strings ***/ 2816 2817 /* lswi */ 2818 /* 2819 * PowerPC32 specification says we must generate an exception if rA is 2820 * in the range of registers to be loaded. In an other hand, IBM says 2821 * this is valid, but rA won't be loaded. For now, I'll follow the 2822 * spec... 2823 */ 2824 static void gen_lswi(DisasContext *ctx) 2825 { 2826 TCGv t0; 2827 TCGv_i32 t1, t2; 2828 int nb = NB(ctx->opcode); 2829 int start = rD(ctx->opcode); 2830 int ra = rA(ctx->opcode); 2831 int nr; 2832 2833 if (ctx->le_mode) { 2834 gen_align_no_le(ctx); 2835 return; 2836 } 2837 if (nb == 0) { 2838 nb = 32; 2839 } 2840 nr = DIV_ROUND_UP(nb, 4); 2841 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2842 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2843 return; 2844 } 2845 gen_set_access_type(ctx, ACCESS_INT); 2846 t0 = tcg_temp_new(); 2847 gen_addr_register(ctx, t0); 2848 t1 = tcg_constant_i32(nb); 2849 t2 = tcg_constant_i32(start); 2850 gen_helper_lsw(tcg_env, t0, t1, t2); 2851 } 2852 2853 /* lswx */ 2854 static void gen_lswx(DisasContext *ctx) 2855 { 2856 TCGv t0; 2857 TCGv_i32 t1, t2, t3; 2858 2859 if (ctx->le_mode) { 2860 gen_align_no_le(ctx); 2861 return; 2862 } 2863 gen_set_access_type(ctx, ACCESS_INT); 2864 t0 = tcg_temp_new(); 2865 gen_addr_reg_index(ctx, t0); 2866 t1 = tcg_constant_i32(rD(ctx->opcode)); 2867 t2 = tcg_constant_i32(rA(ctx->opcode)); 2868 t3 = tcg_constant_i32(rB(ctx->opcode)); 2869 gen_helper_lswx(tcg_env, t0, t1, t2, t3); 2870 } 2871 2872 /* stswi */ 2873 static void gen_stswi(DisasContext *ctx) 2874 { 2875 TCGv t0; 2876 TCGv_i32 t1, t2; 2877 int nb = NB(ctx->opcode); 2878 2879 if (ctx->le_mode) { 2880 gen_align_no_le(ctx); 2881 return; 2882 } 2883 gen_set_access_type(ctx, ACCESS_INT); 2884 t0 = tcg_temp_new(); 2885 gen_addr_register(ctx, t0); 2886 if (nb == 0) { 2887 nb = 32; 2888 } 2889 t1 = tcg_constant_i32(nb); 2890 t2 = tcg_constant_i32(rS(ctx->opcode)); 2891 gen_helper_stsw(tcg_env, t0, t1, t2); 2892 } 2893 2894 /* stswx */ 2895 static void gen_stswx(DisasContext *ctx) 2896 { 2897 TCGv t0; 2898 TCGv_i32 t1, t2; 2899 2900 if (ctx->le_mode) { 2901 gen_align_no_le(ctx); 2902 return; 2903 } 2904 gen_set_access_type(ctx, ACCESS_INT); 2905 t0 = tcg_temp_new(); 2906 gen_addr_reg_index(ctx, t0); 2907 t1 = tcg_temp_new_i32(); 2908 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2909 tcg_gen_andi_i32(t1, t1, 0x7F); 2910 t2 = tcg_constant_i32(rS(ctx->opcode)); 2911 gen_helper_stsw(tcg_env, t0, t1, t2); 2912 } 2913 2914 #if !defined(CONFIG_USER_ONLY) 2915 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2916 { 2917 TCGv_i32 t; 2918 TCGLabel *l; 2919 2920 if (!ctx->lazy_tlb_flush) { 2921 return; 2922 } 2923 l = gen_new_label(); 2924 t = tcg_temp_new_i32(); 2925 tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); 2926 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2927 if (global) { 2928 gen_helper_check_tlb_flush_global(tcg_env); 2929 } else { 2930 gen_helper_check_tlb_flush_local(tcg_env); 2931 } 2932 gen_set_label(l); 2933 if (global) { 2934 /* 2935 * Global TLB flush uses async-work which must run before the 2936 * next instruction, so this must be the last in the TB. 2937 */ 2938 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2939 } 2940 } 2941 #else 2942 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2943 #endif 2944 2945 /* isync */ 2946 static void gen_isync(DisasContext *ctx) 2947 { 2948 /* 2949 * We need to check for a pending TLB flush. This can only happen in 2950 * kernel mode however so check MSR_PR 2951 */ 2952 if (!ctx->pr) { 2953 gen_check_tlb_flush(ctx, false); 2954 } 2955 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2956 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2957 } 2958 2959 static void gen_load_locked(DisasContext *ctx, MemOp memop) 2960 { 2961 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 2962 TCGv t0 = tcg_temp_new(); 2963 2964 gen_set_access_type(ctx, ACCESS_RES); 2965 gen_addr_reg_index(ctx, t0); 2966 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); 2967 tcg_gen_mov_tl(cpu_reserve, t0); 2968 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 2969 tcg_gen_mov_tl(cpu_reserve_val, gpr); 2970 } 2971 2972 #define LARX(name, memop) \ 2973 static void gen_##name(DisasContext *ctx) \ 2974 { \ 2975 gen_load_locked(ctx, memop); \ 2976 } 2977 2978 /* lwarx */ 2979 LARX(lbarx, MO_UB) 2980 LARX(lharx, MO_UW) 2981 LARX(lwarx, MO_UL) 2982 2983 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 2984 TCGv EA, TCGCond cond, int addend) 2985 { 2986 TCGv t = tcg_temp_new(); 2987 TCGv t2 = tcg_temp_new(); 2988 TCGv u = tcg_temp_new(); 2989 2990 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 2991 tcg_gen_addi_tl(t2, EA, memop_size(memop)); 2992 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 2993 tcg_gen_addi_tl(u, t, addend); 2994 2995 /* E.g. for fetch and increment bounded... */ 2996 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 2997 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 2998 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 2999 3000 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3001 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, 3002 tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); 3003 } 3004 3005 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3006 { 3007 uint32_t gpr_FC = FC(ctx->opcode); 3008 TCGv EA = tcg_temp_new(); 3009 int rt = rD(ctx->opcode); 3010 bool need_serial; 3011 TCGv src, dst; 3012 3013 gen_addr_register(ctx, EA); 3014 dst = cpu_gpr[rt]; 3015 src = cpu_gpr[(rt + 1) & 31]; 3016 3017 need_serial = false; 3018 memop |= MO_ALIGN; 3019 switch (gpr_FC) { 3020 case 0: /* Fetch and add */ 3021 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3022 break; 3023 case 1: /* Fetch and xor */ 3024 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3025 break; 3026 case 2: /* Fetch and or */ 3027 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3028 break; 3029 case 3: /* Fetch and 'and' */ 3030 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3031 break; 3032 case 4: /* Fetch and max unsigned */ 3033 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3034 break; 3035 case 5: /* Fetch and max signed */ 3036 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3037 break; 3038 case 6: /* Fetch and min unsigned */ 3039 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3040 break; 3041 case 7: /* Fetch and min signed */ 3042 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3043 break; 3044 case 8: /* Swap */ 3045 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3046 break; 3047 3048 case 16: /* Compare and swap not equal */ 3049 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3050 need_serial = true; 3051 } else { 3052 TCGv t0 = tcg_temp_new(); 3053 TCGv t1 = tcg_temp_new(); 3054 3055 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3056 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3057 tcg_gen_mov_tl(t1, src); 3058 } else { 3059 tcg_gen_ext32u_tl(t1, src); 3060 } 3061 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3062 cpu_gpr[(rt + 2) & 31], t0); 3063 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3064 tcg_gen_mov_tl(dst, t0); 3065 } 3066 break; 3067 3068 case 24: /* Fetch and increment bounded */ 3069 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3070 need_serial = true; 3071 } else { 3072 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3073 } 3074 break; 3075 case 25: /* Fetch and increment equal */ 3076 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3077 need_serial = true; 3078 } else { 3079 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3080 } 3081 break; 3082 case 28: /* Fetch and decrement bounded */ 3083 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3084 need_serial = true; 3085 } else { 3086 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3087 } 3088 break; 3089 3090 default: 3091 /* invoke data storage error handler */ 3092 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3093 } 3094 3095 if (need_serial) { 3096 /* Restart with exclusive lock. */ 3097 gen_helper_exit_atomic(tcg_env); 3098 ctx->base.is_jmp = DISAS_NORETURN; 3099 } 3100 } 3101 3102 static void gen_lwat(DisasContext *ctx) 3103 { 3104 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3105 } 3106 3107 #ifdef TARGET_PPC64 3108 static void gen_ldat(DisasContext *ctx) 3109 { 3110 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3111 } 3112 #endif 3113 3114 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3115 { 3116 uint32_t gpr_FC = FC(ctx->opcode); 3117 TCGv EA = tcg_temp_new(); 3118 TCGv src, discard; 3119 3120 gen_addr_register(ctx, EA); 3121 src = cpu_gpr[rD(ctx->opcode)]; 3122 discard = tcg_temp_new(); 3123 3124 memop |= MO_ALIGN; 3125 switch (gpr_FC) { 3126 case 0: /* add and Store */ 3127 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3128 break; 3129 case 1: /* xor and Store */ 3130 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3131 break; 3132 case 2: /* Or and Store */ 3133 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3134 break; 3135 case 3: /* 'and' and Store */ 3136 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3137 break; 3138 case 4: /* Store max unsigned */ 3139 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3140 break; 3141 case 5: /* Store max signed */ 3142 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3143 break; 3144 case 6: /* Store min unsigned */ 3145 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3146 break; 3147 case 7: /* Store min signed */ 3148 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3149 break; 3150 case 24: /* Store twin */ 3151 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3152 /* Restart with exclusive lock. */ 3153 gen_helper_exit_atomic(tcg_env); 3154 ctx->base.is_jmp = DISAS_NORETURN; 3155 } else { 3156 TCGv t = tcg_temp_new(); 3157 TCGv t2 = tcg_temp_new(); 3158 TCGv s = tcg_temp_new(); 3159 TCGv s2 = tcg_temp_new(); 3160 TCGv ea_plus_s = tcg_temp_new(); 3161 3162 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3163 tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); 3164 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3165 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3166 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3167 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3168 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3169 } 3170 break; 3171 default: 3172 /* invoke data storage error handler */ 3173 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3174 } 3175 } 3176 3177 static void gen_stwat(DisasContext *ctx) 3178 { 3179 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3180 } 3181 3182 #ifdef TARGET_PPC64 3183 static void gen_stdat(DisasContext *ctx) 3184 { 3185 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3186 } 3187 #endif 3188 3189 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3190 { 3191 TCGLabel *lfail; 3192 TCGv EA; 3193 TCGv cr0; 3194 TCGv t0; 3195 int rs = rS(ctx->opcode); 3196 3197 lfail = gen_new_label(); 3198 EA = tcg_temp_new(); 3199 cr0 = tcg_temp_new(); 3200 t0 = tcg_temp_new(); 3201 3202 tcg_gen_mov_tl(cr0, cpu_so); 3203 gen_set_access_type(ctx, ACCESS_RES); 3204 gen_addr_reg_index(ctx, EA); 3205 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3206 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3207 3208 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3209 cpu_gpr[rs], ctx->mem_idx, 3210 DEF_MEMOP(memop) | MO_ALIGN); 3211 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3212 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3213 tcg_gen_or_tl(cr0, cr0, t0); 3214 3215 gen_set_label(lfail); 3216 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3217 tcg_gen_movi_tl(cpu_reserve, -1); 3218 } 3219 3220 #define STCX(name, memop) \ 3221 static void gen_##name(DisasContext *ctx) \ 3222 { \ 3223 gen_conditional_store(ctx, memop); \ 3224 } 3225 3226 STCX(stbcx_, MO_UB) 3227 STCX(sthcx_, MO_UW) 3228 STCX(stwcx_, MO_UL) 3229 3230 #if defined(TARGET_PPC64) 3231 /* ldarx */ 3232 LARX(ldarx, MO_UQ) 3233 /* stdcx. */ 3234 STCX(stdcx_, MO_UQ) 3235 3236 /* lqarx */ 3237 static void gen_lqarx(DisasContext *ctx) 3238 { 3239 int rd = rD(ctx->opcode); 3240 TCGv EA, hi, lo; 3241 TCGv_i128 t16; 3242 3243 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3244 (rd == rB(ctx->opcode)))) { 3245 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3246 return; 3247 } 3248 3249 gen_set_access_type(ctx, ACCESS_RES); 3250 EA = tcg_temp_new(); 3251 gen_addr_reg_index(ctx, EA); 3252 3253 /* Note that the low part is always in RD+1, even in LE mode. */ 3254 lo = cpu_gpr[rd + 1]; 3255 hi = cpu_gpr[rd]; 3256 3257 t16 = tcg_temp_new_i128(); 3258 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3259 tcg_gen_extr_i128_i64(lo, hi, t16); 3260 3261 tcg_gen_mov_tl(cpu_reserve, EA); 3262 tcg_gen_movi_tl(cpu_reserve_length, 16); 3263 tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); 3264 tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); 3265 } 3266 3267 /* stqcx. */ 3268 static void gen_stqcx_(DisasContext *ctx) 3269 { 3270 TCGLabel *lfail; 3271 TCGv EA, t0, t1; 3272 TCGv cr0; 3273 TCGv_i128 cmp, val; 3274 int rs = rS(ctx->opcode); 3275 3276 if (unlikely(rs & 1)) { 3277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3278 return; 3279 } 3280 3281 lfail = gen_new_label(); 3282 EA = tcg_temp_new(); 3283 cr0 = tcg_temp_new(); 3284 3285 tcg_gen_mov_tl(cr0, cpu_so); 3286 gen_set_access_type(ctx, ACCESS_RES); 3287 gen_addr_reg_index(ctx, EA); 3288 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3289 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3290 3291 cmp = tcg_temp_new_i128(); 3292 val = tcg_temp_new_i128(); 3293 3294 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3295 3296 /* Note that the low part is always in RS+1, even in LE mode. */ 3297 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3298 3299 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3300 DEF_MEMOP(MO_128 | MO_ALIGN)); 3301 3302 t0 = tcg_temp_new(); 3303 t1 = tcg_temp_new(); 3304 tcg_gen_extr_i128_i64(t1, t0, val); 3305 3306 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3307 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3308 tcg_gen_or_tl(t0, t0, t1); 3309 3310 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3311 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3312 tcg_gen_or_tl(cr0, cr0, t0); 3313 3314 gen_set_label(lfail); 3315 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3316 tcg_gen_movi_tl(cpu_reserve, -1); 3317 } 3318 #endif /* defined(TARGET_PPC64) */ 3319 3320 /* wait */ 3321 static void gen_wait(DisasContext *ctx) 3322 { 3323 uint32_t wc; 3324 3325 if (ctx->insns_flags & PPC_WAIT) { 3326 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3327 3328 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3329 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3330 wc = WC(ctx->opcode); 3331 } else { 3332 wc = 0; 3333 } 3334 3335 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3336 /* v3.0 defines a new 'wait' encoding. */ 3337 wc = WC(ctx->opcode); 3338 if (ctx->insns_flags2 & PPC2_ISA310) { 3339 uint32_t pl = PL(ctx->opcode); 3340 3341 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3342 if (wc == 3) { 3343 gen_invalid(ctx); 3344 return; 3345 } 3346 3347 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3348 if (pl > 0 && wc != 2) { 3349 gen_invalid(ctx); 3350 return; 3351 } 3352 3353 } else { /* ISA300 */ 3354 /* WC 1-3 are reserved */ 3355 if (wc > 0) { 3356 gen_invalid(ctx); 3357 return; 3358 } 3359 } 3360 3361 } else { 3362 warn_report("wait instruction decoded with wrong ISA flags."); 3363 gen_invalid(ctx); 3364 return; 3365 } 3366 3367 /* 3368 * wait without WC field or with WC=0 waits for an exception / interrupt 3369 * to occur. 3370 */ 3371 if (wc == 0) { 3372 TCGv_i32 t0 = tcg_constant_i32(1); 3373 tcg_gen_st_i32(t0, tcg_env, 3374 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3375 /* Stop translation, as the CPU is supposed to sleep from now */ 3376 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3377 } 3378 3379 /* 3380 * Other wait types must not just wait until an exception occurs because 3381 * ignoring their other wake-up conditions could cause a hang. 3382 * 3383 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3384 * no-ops. 3385 * 3386 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3387 * 3388 * wc=2 waits for an implementation-specific condition, such could be 3389 * always true, so it can be implemented as a no-op. 3390 * 3391 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3392 * 3393 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3394 * Reservation-loss may have implementation-specific conditions, so it 3395 * can be implemented as a no-op. 3396 * 3397 * wc=2 waits for an exception or an amount of time to pass. This 3398 * amount is implementation-specific so it can be implemented as a 3399 * no-op. 3400 * 3401 * ISA v3.1 allows for execution to resume "in the rare case of 3402 * an implementation-dependent event", so in any case software must 3403 * not depend on the architected resumption condition to become 3404 * true, so no-op implementations should be architecturally correct 3405 * (if suboptimal). 3406 */ 3407 } 3408 3409 #if defined(TARGET_PPC64) 3410 static void gen_doze(DisasContext *ctx) 3411 { 3412 #if defined(CONFIG_USER_ONLY) 3413 GEN_PRIV(ctx); 3414 #else 3415 TCGv_i32 t; 3416 3417 CHK_HV(ctx); 3418 translator_io_start(&ctx->base); 3419 t = tcg_constant_i32(PPC_PM_DOZE); 3420 gen_helper_pminsn(tcg_env, t); 3421 /* Stop translation, as the CPU is supposed to sleep from now */ 3422 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3423 #endif /* defined(CONFIG_USER_ONLY) */ 3424 } 3425 3426 static void gen_nap(DisasContext *ctx) 3427 { 3428 #if defined(CONFIG_USER_ONLY) 3429 GEN_PRIV(ctx); 3430 #else 3431 TCGv_i32 t; 3432 3433 CHK_HV(ctx); 3434 translator_io_start(&ctx->base); 3435 t = tcg_constant_i32(PPC_PM_NAP); 3436 gen_helper_pminsn(tcg_env, t); 3437 /* Stop translation, as the CPU is supposed to sleep from now */ 3438 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3439 #endif /* defined(CONFIG_USER_ONLY) */ 3440 } 3441 3442 static void gen_stop(DisasContext *ctx) 3443 { 3444 #if defined(CONFIG_USER_ONLY) 3445 GEN_PRIV(ctx); 3446 #else 3447 TCGv_i32 t; 3448 3449 CHK_HV(ctx); 3450 translator_io_start(&ctx->base); 3451 t = tcg_constant_i32(PPC_PM_STOP); 3452 gen_helper_pminsn(tcg_env, t); 3453 /* Stop translation, as the CPU is supposed to sleep from now */ 3454 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3455 #endif /* defined(CONFIG_USER_ONLY) */ 3456 } 3457 3458 static void gen_sleep(DisasContext *ctx) 3459 { 3460 #if defined(CONFIG_USER_ONLY) 3461 GEN_PRIV(ctx); 3462 #else 3463 TCGv_i32 t; 3464 3465 CHK_HV(ctx); 3466 translator_io_start(&ctx->base); 3467 t = tcg_constant_i32(PPC_PM_SLEEP); 3468 gen_helper_pminsn(tcg_env, t); 3469 /* Stop translation, as the CPU is supposed to sleep from now */ 3470 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3471 #endif /* defined(CONFIG_USER_ONLY) */ 3472 } 3473 3474 static void gen_rvwinkle(DisasContext *ctx) 3475 { 3476 #if defined(CONFIG_USER_ONLY) 3477 GEN_PRIV(ctx); 3478 #else 3479 TCGv_i32 t; 3480 3481 CHK_HV(ctx); 3482 translator_io_start(&ctx->base); 3483 t = tcg_constant_i32(PPC_PM_RVWINKLE); 3484 gen_helper_pminsn(tcg_env, t); 3485 /* Stop translation, as the CPU is supposed to sleep from now */ 3486 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3487 #endif /* defined(CONFIG_USER_ONLY) */ 3488 } 3489 3490 static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value) 3491 { 3492 TCGv_ptr tmp = tcg_temp_new_ptr(); 3493 3494 /* add base and offset to get address of bhrb entry */ 3495 tcg_gen_add_ptr(tmp, base, (TCGv_ptr)offset); 3496 3497 /* store value into bhrb at bhrb_offset */ 3498 tcg_gen_st_i64(value, tmp, 0); 3499 3500 /* add 8 to current bhrb_offset */ 3501 tcg_gen_addi_tl(offset, offset, 8); 3502 3503 /* apply offset mask */ 3504 tcg_gen_and_tl(offset, offset, mask); 3505 3506 return offset; 3507 } 3508 #endif /* #if defined(TARGET_PPC64) */ 3509 3510 static inline void gen_update_branch_history(DisasContext *ctx, 3511 target_ulong nip, 3512 TCGv target, 3513 target_long inst_type) 3514 { 3515 #if defined(TARGET_PPC64) 3516 TCGv_ptr base; 3517 TCGv tmp; 3518 TCGv offset; 3519 TCGv mask; 3520 TCGLabel *no_update; 3521 3522 if (ctx->has_cfar) { 3523 tcg_gen_movi_tl(cpu_cfar, nip); 3524 } 3525 3526 if (!ctx->has_bhrb || 3527 !ctx->bhrb_enable || 3528 inst_type == BHRB_TYPE_NORECORD) { 3529 return; 3530 } 3531 3532 tmp = tcg_temp_new(); 3533 no_update = gen_new_label(); 3534 3535 /* check for bhrb filtering */ 3536 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter)); 3537 tcg_gen_andi_tl(tmp, tmp, inst_type); 3538 tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update); 3539 3540 base = tcg_temp_new_ptr(); 3541 offset = tcg_temp_new(); 3542 mask = tcg_temp_new(); 3543 3544 /* load bhrb base address */ 3545 tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base)); 3546 3547 /* load current bhrb_offset */ 3548 tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3549 3550 /* load a BHRB offset mask */ 3551 tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask)); 3552 3553 offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip)); 3554 3555 /* Also record the target address for XL-Form branches */ 3556 if (inst_type & BHRB_TYPE_XL_FORM) { 3557 3558 /* Set the 'T' bit for target entries */ 3559 tcg_gen_ori_tl(tmp, target, 0x2); 3560 3561 offset = gen_write_bhrb(base, offset, mask, tmp); 3562 } 3563 3564 /* save updated bhrb_offset for next time */ 3565 tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3566 3567 gen_set_label(no_update); 3568 #endif 3569 } 3570 3571 #if defined(TARGET_PPC64) 3572 static void pmu_count_insns(DisasContext *ctx) 3573 { 3574 /* 3575 * Do not bother calling the helper if the PMU isn't counting 3576 * instructions. 3577 */ 3578 if (!ctx->pmu_insn_cnt) { 3579 return; 3580 } 3581 3582 #if !defined(CONFIG_USER_ONLY) 3583 TCGLabel *l; 3584 TCGv t0; 3585 3586 /* 3587 * The PMU insns_inc() helper stops the internal PMU timer if a 3588 * counter overflows happens. In that case, if the guest is 3589 * running with icount and we do not handle it beforehand, 3590 * the helper can trigger a 'bad icount read'. 3591 */ 3592 translator_io_start(&ctx->base); 3593 3594 /* Avoid helper calls when only PMC5-6 are enabled. */ 3595 if (!ctx->pmc_other) { 3596 l = gen_new_label(); 3597 t0 = tcg_temp_new(); 3598 3599 gen_load_spr(t0, SPR_POWER_PMC5); 3600 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3601 gen_store_spr(SPR_POWER_PMC5, t0); 3602 /* Check for overflow, if it's enabled */ 3603 if (ctx->mmcr0_pmcjce) { 3604 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 3605 gen_helper_handle_pmc5_overflow(tcg_env); 3606 } 3607 3608 gen_set_label(l); 3609 } else { 3610 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); 3611 } 3612 #else 3613 /* 3614 * User mode can read (but not write) PMC5 and start/stop 3615 * the PMU via MMCR0_FC. In this case just increment 3616 * PMC5 with base.num_insns. 3617 */ 3618 TCGv t0 = tcg_temp_new(); 3619 3620 gen_load_spr(t0, SPR_POWER_PMC5); 3621 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3622 gen_store_spr(SPR_POWER_PMC5, t0); 3623 #endif /* #if !defined(CONFIG_USER_ONLY) */ 3624 } 3625 #else 3626 static void pmu_count_insns(DisasContext *ctx) 3627 { 3628 } 3629 #endif /* #if defined(TARGET_PPC64) */ 3630 3631 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3632 { 3633 if (unlikely(ctx->singlestep_enabled)) { 3634 return false; 3635 } 3636 return translator_use_goto_tb(&ctx->base, dest); 3637 } 3638 3639 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3640 { 3641 if (unlikely(ctx->singlestep_enabled)) { 3642 gen_debug_exception(ctx, false); 3643 } else { 3644 /* 3645 * tcg_gen_lookup_and_goto_ptr will exit the TB if 3646 * CF_NO_GOTO_PTR is set. Count insns now. 3647 */ 3648 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 3649 pmu_count_insns(ctx); 3650 } 3651 3652 tcg_gen_lookup_and_goto_ptr(); 3653 } 3654 } 3655 3656 /*** Branch ***/ 3657 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3658 { 3659 if (NARROW_MODE(ctx)) { 3660 dest = (uint32_t) dest; 3661 } 3662 if (use_goto_tb(ctx, dest)) { 3663 pmu_count_insns(ctx); 3664 tcg_gen_goto_tb(n); 3665 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3666 tcg_gen_exit_tb(ctx->base.tb, n); 3667 } else { 3668 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3669 gen_lookup_and_goto_ptr(ctx); 3670 } 3671 } 3672 3673 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3674 { 3675 if (NARROW_MODE(ctx)) { 3676 nip = (uint32_t)nip; 3677 } 3678 tcg_gen_movi_tl(cpu_lr, nip); 3679 } 3680 3681 /* b ba bl bla */ 3682 static void gen_b(DisasContext *ctx) 3683 { 3684 target_ulong li, target; 3685 3686 /* sign extend LI */ 3687 li = LI(ctx->opcode); 3688 li = (li ^ 0x02000000) - 0x02000000; 3689 if (likely(AA(ctx->opcode) == 0)) { 3690 target = ctx->cia + li; 3691 } else { 3692 target = li; 3693 } 3694 if (LK(ctx->opcode)) { 3695 gen_setlr(ctx, ctx->base.pc_next); 3696 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); 3697 } else { 3698 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); 3699 } 3700 gen_goto_tb(ctx, 0, target); 3701 ctx->base.is_jmp = DISAS_NORETURN; 3702 } 3703 3704 #define BCOND_IM 0 3705 #define BCOND_LR 1 3706 #define BCOND_CTR 2 3707 #define BCOND_TAR 3 3708 3709 static void gen_bcond(DisasContext *ctx, int type) 3710 { 3711 uint32_t bo = BO(ctx->opcode); 3712 TCGLabel *l1; 3713 TCGv target; 3714 target_long bhrb_type = BHRB_TYPE_OTHER; 3715 3716 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3717 target = tcg_temp_new(); 3718 if (type == BCOND_CTR) { 3719 tcg_gen_mov_tl(target, cpu_ctr); 3720 } else if (type == BCOND_TAR) { 3721 gen_load_spr(target, SPR_TAR); 3722 } else { 3723 tcg_gen_mov_tl(target, cpu_lr); 3724 } 3725 if (!LK(ctx->opcode)) { 3726 bhrb_type |= BHRB_TYPE_INDIRECT; 3727 } 3728 bhrb_type |= BHRB_TYPE_XL_FORM; 3729 } else { 3730 target = NULL; 3731 } 3732 if (LK(ctx->opcode)) { 3733 gen_setlr(ctx, ctx->base.pc_next); 3734 bhrb_type |= BHRB_TYPE_CALL; 3735 } 3736 l1 = gen_new_label(); 3737 if ((bo & 0x4) == 0) { 3738 /* Decrement and test CTR */ 3739 TCGv temp = tcg_temp_new(); 3740 3741 if (type == BCOND_CTR) { 3742 /* 3743 * All ISAs up to v3 describe this form of bcctr as invalid but 3744 * some processors, ie. 64-bit server processors compliant with 3745 * arch 2.x, do implement a "test and decrement" logic instead, 3746 * as described in their respective UMs. This logic involves CTR 3747 * to act as both the branch target and a counter, which makes 3748 * it basically useless and thus never used in real code. 3749 * 3750 * This form was hence chosen to trigger extra micro-architectural 3751 * side-effect on real HW needed for the Spectre v2 workaround. 3752 * It is up to guests that implement such workaround, ie. linux, to 3753 * use this form in a way it just triggers the side-effect without 3754 * doing anything else harmful. 3755 */ 3756 if (unlikely(!is_book3s_arch2x(ctx))) { 3757 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3758 return; 3759 } 3760 3761 if (NARROW_MODE(ctx)) { 3762 tcg_gen_ext32u_tl(temp, cpu_ctr); 3763 } else { 3764 tcg_gen_mov_tl(temp, cpu_ctr); 3765 } 3766 if (bo & 0x2) { 3767 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3768 } else { 3769 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3770 } 3771 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3772 } else { 3773 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3774 if (NARROW_MODE(ctx)) { 3775 tcg_gen_ext32u_tl(temp, cpu_ctr); 3776 } else { 3777 tcg_gen_mov_tl(temp, cpu_ctr); 3778 } 3779 if (bo & 0x2) { 3780 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3781 } else { 3782 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3783 } 3784 } 3785 bhrb_type |= BHRB_TYPE_COND; 3786 } 3787 if ((bo & 0x10) == 0) { 3788 /* Test CR */ 3789 uint32_t bi = BI(ctx->opcode); 3790 uint32_t mask = 0x08 >> (bi & 0x03); 3791 TCGv_i32 temp = tcg_temp_new_i32(); 3792 3793 if (bo & 0x8) { 3794 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3795 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3796 } else { 3797 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3798 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3799 } 3800 bhrb_type |= BHRB_TYPE_COND; 3801 } 3802 3803 gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); 3804 3805 if (type == BCOND_IM) { 3806 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3807 if (likely(AA(ctx->opcode) == 0)) { 3808 gen_goto_tb(ctx, 0, ctx->cia + li); 3809 } else { 3810 gen_goto_tb(ctx, 0, li); 3811 } 3812 } else { 3813 if (NARROW_MODE(ctx)) { 3814 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3815 } else { 3816 tcg_gen_andi_tl(cpu_nip, target, ~3); 3817 } 3818 gen_lookup_and_goto_ptr(ctx); 3819 } 3820 if ((bo & 0x14) != 0x14) { 3821 /* fallthrough case */ 3822 gen_set_label(l1); 3823 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3824 } 3825 ctx->base.is_jmp = DISAS_NORETURN; 3826 } 3827 3828 static void gen_bc(DisasContext *ctx) 3829 { 3830 gen_bcond(ctx, BCOND_IM); 3831 } 3832 3833 static void gen_bcctr(DisasContext *ctx) 3834 { 3835 gen_bcond(ctx, BCOND_CTR); 3836 } 3837 3838 static void gen_bclr(DisasContext *ctx) 3839 { 3840 gen_bcond(ctx, BCOND_LR); 3841 } 3842 3843 static void gen_bctar(DisasContext *ctx) 3844 { 3845 gen_bcond(ctx, BCOND_TAR); 3846 } 3847 3848 /*** Condition register logical ***/ 3849 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3850 static void glue(gen_, name)(DisasContext *ctx) \ 3851 { \ 3852 uint8_t bitmask; \ 3853 int sh; \ 3854 TCGv_i32 t0, t1; \ 3855 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3856 t0 = tcg_temp_new_i32(); \ 3857 if (sh > 0) \ 3858 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3859 else if (sh < 0) \ 3860 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3861 else \ 3862 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3863 t1 = tcg_temp_new_i32(); \ 3864 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3865 if (sh > 0) \ 3866 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3867 else if (sh < 0) \ 3868 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3869 else \ 3870 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3871 tcg_op(t0, t0, t1); \ 3872 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3873 tcg_gen_andi_i32(t0, t0, bitmask); \ 3874 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3875 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3876 } 3877 3878 /* crand */ 3879 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3880 /* crandc */ 3881 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3882 /* creqv */ 3883 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3884 /* crnand */ 3885 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3886 /* crnor */ 3887 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3888 /* cror */ 3889 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3890 /* crorc */ 3891 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3892 /* crxor */ 3893 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3894 3895 /* mcrf */ 3896 static void gen_mcrf(DisasContext *ctx) 3897 { 3898 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3899 } 3900 3901 /*** System linkage ***/ 3902 3903 /* rfi (supervisor only) */ 3904 static void gen_rfi(DisasContext *ctx) 3905 { 3906 #if defined(CONFIG_USER_ONLY) 3907 GEN_PRIV(ctx); 3908 #else 3909 /* 3910 * This instruction doesn't exist anymore on 64-bit server 3911 * processors compliant with arch 2.x 3912 */ 3913 if (is_book3s_arch2x(ctx)) { 3914 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3915 return; 3916 } 3917 /* Restore CPU state */ 3918 CHK_SV(ctx); 3919 translator_io_start(&ctx->base); 3920 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3921 gen_helper_rfi(tcg_env); 3922 ctx->base.is_jmp = DISAS_EXIT; 3923 #endif 3924 } 3925 3926 #if defined(TARGET_PPC64) 3927 static void gen_rfid(DisasContext *ctx) 3928 { 3929 #if defined(CONFIG_USER_ONLY) 3930 GEN_PRIV(ctx); 3931 #else 3932 /* Restore CPU state */ 3933 CHK_SV(ctx); 3934 translator_io_start(&ctx->base); 3935 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3936 gen_helper_rfid(tcg_env); 3937 ctx->base.is_jmp = DISAS_EXIT; 3938 #endif 3939 } 3940 3941 #if !defined(CONFIG_USER_ONLY) 3942 static void gen_rfscv(DisasContext *ctx) 3943 { 3944 #if defined(CONFIG_USER_ONLY) 3945 GEN_PRIV(ctx); 3946 #else 3947 /* Restore CPU state */ 3948 CHK_SV(ctx); 3949 translator_io_start(&ctx->base); 3950 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3951 gen_helper_rfscv(tcg_env); 3952 ctx->base.is_jmp = DISAS_EXIT; 3953 #endif 3954 } 3955 #endif 3956 3957 static void gen_hrfid(DisasContext *ctx) 3958 { 3959 #if defined(CONFIG_USER_ONLY) 3960 GEN_PRIV(ctx); 3961 #else 3962 /* Restore CPU state */ 3963 CHK_HV(ctx); 3964 translator_io_start(&ctx->base); 3965 gen_helper_hrfid(tcg_env); 3966 ctx->base.is_jmp = DISAS_EXIT; 3967 #endif 3968 } 3969 #endif 3970 3971 /* sc */ 3972 #if defined(CONFIG_USER_ONLY) 3973 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3974 #else 3975 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3976 #endif 3977 static void gen_sc(DisasContext *ctx) 3978 { 3979 uint32_t lev; 3980 3981 /* 3982 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 3983 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 3984 * for Ultravisor which TCG does not support, so just ignore the top 6. 3985 */ 3986 lev = (ctx->opcode >> 5) & 0x1; 3987 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3988 } 3989 3990 #if defined(TARGET_PPC64) 3991 #if !defined(CONFIG_USER_ONLY) 3992 static void gen_scv(DisasContext *ctx) 3993 { 3994 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 3995 3996 /* Set the PC back to the faulting instruction. */ 3997 gen_update_nip(ctx, ctx->cia); 3998 gen_helper_scv(tcg_env, tcg_constant_i32(lev)); 3999 4000 ctx->base.is_jmp = DISAS_NORETURN; 4001 } 4002 #endif 4003 #endif 4004 4005 /*** Trap ***/ 4006 4007 /* Check for unconditional traps (always or never) */ 4008 static bool check_unconditional_trap(DisasContext *ctx, int to) 4009 { 4010 /* Trap never */ 4011 if (to == 0) { 4012 return true; 4013 } 4014 /* Trap always */ 4015 if (to == 31) { 4016 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4017 return true; 4018 } 4019 return false; 4020 } 4021 4022 /*** Processor control ***/ 4023 4024 /* mcrxr */ 4025 static void gen_mcrxr(DisasContext *ctx) 4026 { 4027 TCGv_i32 t0 = tcg_temp_new_i32(); 4028 TCGv_i32 t1 = tcg_temp_new_i32(); 4029 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4030 4031 tcg_gen_trunc_tl_i32(t0, cpu_so); 4032 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4033 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4034 tcg_gen_shli_i32(t0, t0, 3); 4035 tcg_gen_shli_i32(t1, t1, 2); 4036 tcg_gen_shli_i32(dst, dst, 1); 4037 tcg_gen_or_i32(dst, dst, t0); 4038 tcg_gen_or_i32(dst, dst, t1); 4039 4040 tcg_gen_movi_tl(cpu_so, 0); 4041 tcg_gen_movi_tl(cpu_ov, 0); 4042 tcg_gen_movi_tl(cpu_ca, 0); 4043 } 4044 4045 #ifdef TARGET_PPC64 4046 /* mcrxrx */ 4047 static void gen_mcrxrx(DisasContext *ctx) 4048 { 4049 TCGv t0 = tcg_temp_new(); 4050 TCGv t1 = tcg_temp_new(); 4051 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4052 4053 /* copy OV and OV32 */ 4054 tcg_gen_shli_tl(t0, cpu_ov, 1); 4055 tcg_gen_or_tl(t0, t0, cpu_ov32); 4056 tcg_gen_shli_tl(t0, t0, 2); 4057 /* copy CA and CA32 */ 4058 tcg_gen_shli_tl(t1, cpu_ca, 1); 4059 tcg_gen_or_tl(t1, t1, cpu_ca32); 4060 tcg_gen_or_tl(t0, t0, t1); 4061 tcg_gen_trunc_tl_i32(dst, t0); 4062 } 4063 #endif 4064 4065 /* mfcr mfocrf */ 4066 static void gen_mfcr(DisasContext *ctx) 4067 { 4068 uint32_t crm, crn; 4069 4070 if (likely(ctx->opcode & 0x00100000)) { 4071 crm = CRM(ctx->opcode); 4072 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4073 crn = ctz32(crm); 4074 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4075 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4076 cpu_gpr[rD(ctx->opcode)], crn * 4); 4077 } 4078 } else { 4079 TCGv_i32 t0 = tcg_temp_new_i32(); 4080 tcg_gen_mov_i32(t0, cpu_crf[0]); 4081 tcg_gen_shli_i32(t0, t0, 4); 4082 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4083 tcg_gen_shli_i32(t0, t0, 4); 4084 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4085 tcg_gen_shli_i32(t0, t0, 4); 4086 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4087 tcg_gen_shli_i32(t0, t0, 4); 4088 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4089 tcg_gen_shli_i32(t0, t0, 4); 4090 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4091 tcg_gen_shli_i32(t0, t0, 4); 4092 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4093 tcg_gen_shli_i32(t0, t0, 4); 4094 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4096 } 4097 } 4098 4099 /* mfmsr */ 4100 static void gen_mfmsr(DisasContext *ctx) 4101 { 4102 CHK_SV(ctx); 4103 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4104 } 4105 4106 /* mfspr */ 4107 static inline void gen_op_mfspr(DisasContext *ctx) 4108 { 4109 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4110 uint32_t sprn = SPR(ctx->opcode); 4111 4112 #if defined(CONFIG_USER_ONLY) 4113 read_cb = ctx->spr_cb[sprn].uea_read; 4114 #else 4115 if (ctx->pr) { 4116 read_cb = ctx->spr_cb[sprn].uea_read; 4117 } else if (ctx->hv) { 4118 read_cb = ctx->spr_cb[sprn].hea_read; 4119 } else { 4120 read_cb = ctx->spr_cb[sprn].oea_read; 4121 } 4122 #endif 4123 if (likely(read_cb != NULL)) { 4124 if (likely(read_cb != SPR_NOACCESS)) { 4125 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4126 } else { 4127 /* Privilege exception */ 4128 /* 4129 * This is a hack to avoid warnings when running Linux: 4130 * this OS breaks the PowerPC virtualisation model, 4131 * allowing userland application to read the PVR 4132 */ 4133 if (sprn != SPR_PVR) { 4134 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4135 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4136 ctx->cia); 4137 } 4138 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4139 } 4140 } else { 4141 /* ISA 2.07 defines these as no-ops */ 4142 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4143 (sprn >= 808 && sprn <= 811)) { 4144 /* This is a nop */ 4145 return; 4146 } 4147 /* Not defined */ 4148 qemu_log_mask(LOG_GUEST_ERROR, 4149 "Trying to read invalid spr %d (0x%03x) at " 4150 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4151 4152 /* 4153 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4154 * generate a priv, a hv emu or a no-op 4155 */ 4156 if (sprn & 0x10) { 4157 if (ctx->pr) { 4158 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4159 } 4160 } else { 4161 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4162 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4163 } 4164 } 4165 } 4166 } 4167 4168 static void gen_mfspr(DisasContext *ctx) 4169 { 4170 gen_op_mfspr(ctx); 4171 } 4172 4173 /* mftb */ 4174 static void gen_mftb(DisasContext *ctx) 4175 { 4176 gen_op_mfspr(ctx); 4177 } 4178 4179 /* mtcrf mtocrf*/ 4180 static void gen_mtcrf(DisasContext *ctx) 4181 { 4182 uint32_t crm, crn; 4183 4184 crm = CRM(ctx->opcode); 4185 if (likely((ctx->opcode & 0x00100000))) { 4186 if (crm && ((crm & (crm - 1)) == 0)) { 4187 TCGv_i32 temp = tcg_temp_new_i32(); 4188 crn = ctz32(crm); 4189 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4190 tcg_gen_shri_i32(temp, temp, crn * 4); 4191 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4192 } 4193 } else { 4194 TCGv_i32 temp = tcg_temp_new_i32(); 4195 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4196 for (crn = 0 ; crn < 8 ; crn++) { 4197 if (crm & (1 << crn)) { 4198 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4199 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4200 } 4201 } 4202 } 4203 } 4204 4205 /* mtmsr */ 4206 #if defined(TARGET_PPC64) 4207 static void gen_mtmsrd(DisasContext *ctx) 4208 { 4209 if (unlikely(!is_book3s_arch2x(ctx))) { 4210 gen_invalid(ctx); 4211 return; 4212 } 4213 4214 CHK_SV(ctx); 4215 4216 #if !defined(CONFIG_USER_ONLY) 4217 TCGv t0, t1; 4218 target_ulong mask; 4219 4220 t0 = tcg_temp_new(); 4221 t1 = tcg_temp_new(); 4222 4223 translator_io_start(&ctx->base); 4224 4225 if (ctx->opcode & 0x00010000) { 4226 /* L=1 form only updates EE and RI */ 4227 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4228 } else { 4229 /* mtmsrd does not alter HV, S, ME, or LE */ 4230 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4231 (1ULL << MSR_HV)); 4232 /* 4233 * XXX: we need to update nip before the store if we enter 4234 * power saving mode, we will exit the loop directly from 4235 * ppc_store_msr 4236 */ 4237 gen_update_nip(ctx, ctx->base.pc_next); 4238 } 4239 4240 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4241 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4242 tcg_gen_or_tl(t0, t0, t1); 4243 4244 gen_helper_store_msr(tcg_env, t0); 4245 4246 /* Must stop the translation as machine state (may have) changed */ 4247 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4248 #endif /* !defined(CONFIG_USER_ONLY) */ 4249 } 4250 #endif /* defined(TARGET_PPC64) */ 4251 4252 static void gen_mtmsr(DisasContext *ctx) 4253 { 4254 CHK_SV(ctx); 4255 4256 #if !defined(CONFIG_USER_ONLY) 4257 TCGv t0, t1; 4258 target_ulong mask = 0xFFFFFFFF; 4259 4260 t0 = tcg_temp_new(); 4261 t1 = tcg_temp_new(); 4262 4263 translator_io_start(&ctx->base); 4264 if (ctx->opcode & 0x00010000) { 4265 /* L=1 form only updates EE and RI */ 4266 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4267 } else { 4268 /* mtmsr does not alter S, ME, or LE */ 4269 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4270 4271 /* 4272 * XXX: we need to update nip before the store if we enter 4273 * power saving mode, we will exit the loop directly from 4274 * ppc_store_msr 4275 */ 4276 gen_update_nip(ctx, ctx->base.pc_next); 4277 } 4278 4279 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4280 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4281 tcg_gen_or_tl(t0, t0, t1); 4282 4283 gen_helper_store_msr(tcg_env, t0); 4284 4285 /* Must stop the translation as machine state (may have) changed */ 4286 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4287 #endif 4288 } 4289 4290 /* mtspr */ 4291 static void gen_mtspr(DisasContext *ctx) 4292 { 4293 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4294 uint32_t sprn = SPR(ctx->opcode); 4295 4296 #if defined(CONFIG_USER_ONLY) 4297 write_cb = ctx->spr_cb[sprn].uea_write; 4298 #else 4299 if (ctx->pr) { 4300 write_cb = ctx->spr_cb[sprn].uea_write; 4301 } else if (ctx->hv) { 4302 write_cb = ctx->spr_cb[sprn].hea_write; 4303 } else { 4304 write_cb = ctx->spr_cb[sprn].oea_write; 4305 } 4306 #endif 4307 if (likely(write_cb != NULL)) { 4308 if (likely(write_cb != SPR_NOACCESS)) { 4309 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4310 } else { 4311 /* Privilege exception */ 4312 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4313 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4314 ctx->cia); 4315 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4316 } 4317 } else { 4318 /* ISA 2.07 defines these as no-ops */ 4319 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4320 (sprn >= 808 && sprn <= 811)) { 4321 /* This is a nop */ 4322 return; 4323 } 4324 4325 /* Not defined */ 4326 qemu_log_mask(LOG_GUEST_ERROR, 4327 "Trying to write invalid spr %d (0x%03x) at " 4328 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4329 4330 4331 /* 4332 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4333 * generate a priv, a hv emu or a no-op 4334 */ 4335 if (sprn & 0x10) { 4336 if (ctx->pr) { 4337 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4338 } 4339 } else { 4340 if (ctx->pr || sprn == 0) { 4341 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4342 } 4343 } 4344 } 4345 } 4346 4347 #if defined(TARGET_PPC64) 4348 /* setb */ 4349 static void gen_setb(DisasContext *ctx) 4350 { 4351 TCGv_i32 t0 = tcg_temp_new_i32(); 4352 TCGv_i32 t8 = tcg_constant_i32(8); 4353 TCGv_i32 tm1 = tcg_constant_i32(-1); 4354 int crf = crfS(ctx->opcode); 4355 4356 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4357 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4358 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4359 } 4360 #endif 4361 4362 /*** Cache management ***/ 4363 4364 /* dcbf */ 4365 static void gen_dcbf(DisasContext *ctx) 4366 { 4367 /* XXX: specification says this is treated as a load by the MMU */ 4368 TCGv t0; 4369 gen_set_access_type(ctx, ACCESS_CACHE); 4370 t0 = tcg_temp_new(); 4371 gen_addr_reg_index(ctx, t0); 4372 gen_qemu_ld8u(ctx, t0, t0); 4373 } 4374 4375 /* dcbfep (external PID dcbf) */ 4376 static void gen_dcbfep(DisasContext *ctx) 4377 { 4378 /* XXX: specification says this is treated as a load by the MMU */ 4379 TCGv t0; 4380 CHK_SV(ctx); 4381 gen_set_access_type(ctx, ACCESS_CACHE); 4382 t0 = tcg_temp_new(); 4383 gen_addr_reg_index(ctx, t0); 4384 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4385 } 4386 4387 /* dcbi (Supervisor only) */ 4388 static void gen_dcbi(DisasContext *ctx) 4389 { 4390 #if defined(CONFIG_USER_ONLY) 4391 GEN_PRIV(ctx); 4392 #else 4393 TCGv EA, val; 4394 4395 CHK_SV(ctx); 4396 EA = tcg_temp_new(); 4397 gen_set_access_type(ctx, ACCESS_CACHE); 4398 gen_addr_reg_index(ctx, EA); 4399 val = tcg_temp_new(); 4400 /* XXX: specification says this should be treated as a store by the MMU */ 4401 gen_qemu_ld8u(ctx, val, EA); 4402 gen_qemu_st8(ctx, val, EA); 4403 #endif /* defined(CONFIG_USER_ONLY) */ 4404 } 4405 4406 /* dcdst */ 4407 static void gen_dcbst(DisasContext *ctx) 4408 { 4409 /* XXX: specification say this is treated as a load by the MMU */ 4410 TCGv t0; 4411 gen_set_access_type(ctx, ACCESS_CACHE); 4412 t0 = tcg_temp_new(); 4413 gen_addr_reg_index(ctx, t0); 4414 gen_qemu_ld8u(ctx, t0, t0); 4415 } 4416 4417 /* dcbstep (dcbstep External PID version) */ 4418 static void gen_dcbstep(DisasContext *ctx) 4419 { 4420 /* XXX: specification say this is treated as a load by the MMU */ 4421 TCGv t0; 4422 gen_set_access_type(ctx, ACCESS_CACHE); 4423 t0 = tcg_temp_new(); 4424 gen_addr_reg_index(ctx, t0); 4425 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4426 } 4427 4428 /* dcbt */ 4429 static void gen_dcbt(DisasContext *ctx) 4430 { 4431 /* 4432 * interpreted as no-op 4433 * XXX: specification say this is treated as a load by the MMU but 4434 * does not generate any exception 4435 */ 4436 } 4437 4438 /* dcbtep */ 4439 static void gen_dcbtep(DisasContext *ctx) 4440 { 4441 /* 4442 * interpreted as no-op 4443 * XXX: specification say this is treated as a load by the MMU but 4444 * does not generate any exception 4445 */ 4446 } 4447 4448 /* dcbtst */ 4449 static void gen_dcbtst(DisasContext *ctx) 4450 { 4451 /* 4452 * interpreted as no-op 4453 * XXX: specification say this is treated as a load by the MMU but 4454 * does not generate any exception 4455 */ 4456 } 4457 4458 /* dcbtstep */ 4459 static void gen_dcbtstep(DisasContext *ctx) 4460 { 4461 /* 4462 * interpreted as no-op 4463 * XXX: specification say this is treated as a load by the MMU but 4464 * does not generate any exception 4465 */ 4466 } 4467 4468 /* dcbtls */ 4469 static void gen_dcbtls(DisasContext *ctx) 4470 { 4471 /* Always fails locking the cache */ 4472 TCGv t0 = tcg_temp_new(); 4473 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4474 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4475 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4476 } 4477 4478 /* dcblc */ 4479 static void gen_dcblc(DisasContext *ctx) 4480 { 4481 /* 4482 * interpreted as no-op 4483 */ 4484 } 4485 4486 /* dcbz */ 4487 static void gen_dcbz(DisasContext *ctx) 4488 { 4489 TCGv tcgv_addr = tcg_temp_new(); 4490 4491 gen_set_access_type(ctx, ACCESS_CACHE); 4492 gen_addr_reg_index(ctx, tcgv_addr); 4493 4494 #ifdef TARGET_PPC64 4495 if (ctx->excp_model == POWERPC_EXCP_970 && !(ctx->opcode & 0x00200000)) { 4496 gen_helper_dcbzl(tcg_env, tcgv_addr); 4497 return; 4498 } 4499 #endif 4500 4501 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx)); 4502 } 4503 4504 /* dcbzep */ 4505 static void gen_dcbzep(DisasContext *ctx) 4506 { 4507 TCGv tcgv_addr = tcg_temp_new(); 4508 4509 gen_set_access_type(ctx, ACCESS_CACHE); 4510 gen_addr_reg_index(ctx, tcgv_addr); 4511 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STORE)); 4512 } 4513 4514 /* dst / dstt */ 4515 static void gen_dst(DisasContext *ctx) 4516 { 4517 if (rA(ctx->opcode) == 0) { 4518 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4519 } else { 4520 /* interpreted as no-op */ 4521 } 4522 } 4523 4524 /* dstst /dststt */ 4525 static void gen_dstst(DisasContext *ctx) 4526 { 4527 if (rA(ctx->opcode) == 0) { 4528 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4529 } else { 4530 /* interpreted as no-op */ 4531 } 4532 4533 } 4534 4535 /* dss / dssall */ 4536 static void gen_dss(DisasContext *ctx) 4537 { 4538 /* interpreted as no-op */ 4539 } 4540 4541 /* icbi */ 4542 static void gen_icbi(DisasContext *ctx) 4543 { 4544 TCGv t0; 4545 gen_set_access_type(ctx, ACCESS_CACHE); 4546 t0 = tcg_temp_new(); 4547 gen_addr_reg_index(ctx, t0); 4548 gen_helper_icbi(tcg_env, t0); 4549 } 4550 4551 /* icbiep */ 4552 static void gen_icbiep(DisasContext *ctx) 4553 { 4554 TCGv t0; 4555 gen_set_access_type(ctx, ACCESS_CACHE); 4556 t0 = tcg_temp_new(); 4557 gen_addr_reg_index(ctx, t0); 4558 gen_helper_icbiep(tcg_env, t0); 4559 } 4560 4561 /* Optional: */ 4562 /* dcba */ 4563 static void gen_dcba(DisasContext *ctx) 4564 { 4565 /* 4566 * interpreted as no-op 4567 * XXX: specification say this is treated as a store by the MMU 4568 * but does not generate any exception 4569 */ 4570 } 4571 4572 /*** Segment register manipulation ***/ 4573 /* Supervisor only: */ 4574 4575 /* mfsr */ 4576 static void gen_mfsr(DisasContext *ctx) 4577 { 4578 #if defined(CONFIG_USER_ONLY) 4579 GEN_PRIV(ctx); 4580 #else 4581 TCGv t0; 4582 4583 CHK_SV(ctx); 4584 t0 = tcg_constant_tl(SR(ctx->opcode)); 4585 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4586 #endif /* defined(CONFIG_USER_ONLY) */ 4587 } 4588 4589 /* mfsrin */ 4590 static void gen_mfsrin(DisasContext *ctx) 4591 { 4592 #if defined(CONFIG_USER_ONLY) 4593 GEN_PRIV(ctx); 4594 #else 4595 TCGv t0; 4596 4597 CHK_SV(ctx); 4598 t0 = tcg_temp_new(); 4599 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4600 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4601 #endif /* defined(CONFIG_USER_ONLY) */ 4602 } 4603 4604 /* mtsr */ 4605 static void gen_mtsr(DisasContext *ctx) 4606 { 4607 #if defined(CONFIG_USER_ONLY) 4608 GEN_PRIV(ctx); 4609 #else 4610 TCGv t0; 4611 4612 CHK_SV(ctx); 4613 t0 = tcg_constant_tl(SR(ctx->opcode)); 4614 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4615 #endif /* defined(CONFIG_USER_ONLY) */ 4616 } 4617 4618 /* mtsrin */ 4619 static void gen_mtsrin(DisasContext *ctx) 4620 { 4621 #if defined(CONFIG_USER_ONLY) 4622 GEN_PRIV(ctx); 4623 #else 4624 TCGv t0; 4625 CHK_SV(ctx); 4626 4627 t0 = tcg_temp_new(); 4628 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4629 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); 4630 #endif /* defined(CONFIG_USER_ONLY) */ 4631 } 4632 4633 #if defined(TARGET_PPC64) 4634 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4635 4636 /* mfsr */ 4637 static void gen_mfsr_64b(DisasContext *ctx) 4638 { 4639 #if defined(CONFIG_USER_ONLY) 4640 GEN_PRIV(ctx); 4641 #else 4642 TCGv t0; 4643 4644 CHK_SV(ctx); 4645 t0 = tcg_constant_tl(SR(ctx->opcode)); 4646 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4647 #endif /* defined(CONFIG_USER_ONLY) */ 4648 } 4649 4650 /* mfsrin */ 4651 static void gen_mfsrin_64b(DisasContext *ctx) 4652 { 4653 #if defined(CONFIG_USER_ONLY) 4654 GEN_PRIV(ctx); 4655 #else 4656 TCGv t0; 4657 4658 CHK_SV(ctx); 4659 t0 = tcg_temp_new(); 4660 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4661 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4662 #endif /* defined(CONFIG_USER_ONLY) */ 4663 } 4664 4665 /* mtsr */ 4666 static void gen_mtsr_64b(DisasContext *ctx) 4667 { 4668 #if defined(CONFIG_USER_ONLY) 4669 GEN_PRIV(ctx); 4670 #else 4671 TCGv t0; 4672 4673 CHK_SV(ctx); 4674 t0 = tcg_constant_tl(SR(ctx->opcode)); 4675 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4676 #endif /* defined(CONFIG_USER_ONLY) */ 4677 } 4678 4679 /* mtsrin */ 4680 static void gen_mtsrin_64b(DisasContext *ctx) 4681 { 4682 #if defined(CONFIG_USER_ONLY) 4683 GEN_PRIV(ctx); 4684 #else 4685 TCGv t0; 4686 4687 CHK_SV(ctx); 4688 t0 = tcg_temp_new(); 4689 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4690 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4691 #endif /* defined(CONFIG_USER_ONLY) */ 4692 } 4693 4694 #endif /* defined(TARGET_PPC64) */ 4695 4696 /*** Lookaside buffer management ***/ 4697 /* Optional & supervisor only: */ 4698 4699 /* tlbia */ 4700 static void gen_tlbia(DisasContext *ctx) 4701 { 4702 #if defined(CONFIG_USER_ONLY) 4703 GEN_PRIV(ctx); 4704 #else 4705 CHK_HV(ctx); 4706 4707 gen_helper_tlbia(tcg_env); 4708 #endif /* defined(CONFIG_USER_ONLY) */ 4709 } 4710 4711 /* tlbsync */ 4712 static void gen_tlbsync(DisasContext *ctx) 4713 { 4714 #if defined(CONFIG_USER_ONLY) 4715 GEN_PRIV(ctx); 4716 #else 4717 4718 if (ctx->gtse) { 4719 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 4720 } else { 4721 CHK_HV(ctx); /* Else hypervisor privileged */ 4722 } 4723 4724 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4725 if (ctx->insns_flags & PPC_BOOKE) { 4726 gen_check_tlb_flush(ctx, true); 4727 } 4728 #endif /* defined(CONFIG_USER_ONLY) */ 4729 } 4730 4731 /*** External control ***/ 4732 /* Optional: */ 4733 4734 /* eciwx */ 4735 static void gen_eciwx(DisasContext *ctx) 4736 { 4737 TCGv t0; 4738 /* Should check EAR[E] ! */ 4739 gen_set_access_type(ctx, ACCESS_EXT); 4740 t0 = tcg_temp_new(); 4741 gen_addr_reg_index(ctx, t0); 4742 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4743 DEF_MEMOP(MO_UL | MO_ALIGN)); 4744 } 4745 4746 /* ecowx */ 4747 static void gen_ecowx(DisasContext *ctx) 4748 { 4749 TCGv t0; 4750 /* Should check EAR[E] ! */ 4751 gen_set_access_type(ctx, ACCESS_EXT); 4752 t0 = tcg_temp_new(); 4753 gen_addr_reg_index(ctx, t0); 4754 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4755 DEF_MEMOP(MO_UL | MO_ALIGN)); 4756 } 4757 4758 /* 602 - 603 - G2 TLB management */ 4759 4760 /* tlbld */ 4761 static void gen_tlbld_6xx(DisasContext *ctx) 4762 { 4763 #if defined(CONFIG_USER_ONLY) 4764 GEN_PRIV(ctx); 4765 #else 4766 CHK_SV(ctx); 4767 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4768 #endif /* defined(CONFIG_USER_ONLY) */ 4769 } 4770 4771 /* tlbli */ 4772 static void gen_tlbli_6xx(DisasContext *ctx) 4773 { 4774 #if defined(CONFIG_USER_ONLY) 4775 GEN_PRIV(ctx); 4776 #else 4777 CHK_SV(ctx); 4778 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4779 #endif /* defined(CONFIG_USER_ONLY) */ 4780 } 4781 4782 /* BookE specific instructions */ 4783 4784 /* XXX: not implemented on 440 ? */ 4785 static void gen_mfapidi(DisasContext *ctx) 4786 { 4787 /* XXX: TODO */ 4788 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4789 } 4790 4791 /* XXX: not implemented on 440 ? */ 4792 static void gen_tlbiva(DisasContext *ctx) 4793 { 4794 #if defined(CONFIG_USER_ONLY) 4795 GEN_PRIV(ctx); 4796 #else 4797 TCGv t0; 4798 4799 CHK_SV(ctx); 4800 t0 = tcg_temp_new(); 4801 gen_addr_reg_index(ctx, t0); 4802 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4803 #endif /* defined(CONFIG_USER_ONLY) */ 4804 } 4805 4806 /* All 405 MAC instructions are translated here */ 4807 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 4808 int ra, int rb, int rt, int Rc) 4809 { 4810 TCGv t0, t1; 4811 4812 t0 = tcg_temp_new(); 4813 t1 = tcg_temp_new(); 4814 4815 switch (opc3 & 0x0D) { 4816 case 0x05: 4817 /* macchw - macchw. - macchwo - macchwo. */ 4818 /* macchws - macchws. - macchwso - macchwso. */ 4819 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 4820 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 4821 /* mulchw - mulchw. */ 4822 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4823 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4824 tcg_gen_ext16s_tl(t1, t1); 4825 break; 4826 case 0x04: 4827 /* macchwu - macchwu. - macchwuo - macchwuo. */ 4828 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 4829 /* mulchwu - mulchwu. */ 4830 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4831 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4832 tcg_gen_ext16u_tl(t1, t1); 4833 break; 4834 case 0x01: 4835 /* machhw - machhw. - machhwo - machhwo. */ 4836 /* machhws - machhws. - machhwso - machhwso. */ 4837 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 4838 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 4839 /* mulhhw - mulhhw. */ 4840 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 4841 tcg_gen_ext16s_tl(t0, t0); 4842 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4843 tcg_gen_ext16s_tl(t1, t1); 4844 break; 4845 case 0x00: 4846 /* machhwu - machhwu. - machhwuo - machhwuo. */ 4847 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 4848 /* mulhhwu - mulhhwu. */ 4849 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 4850 tcg_gen_ext16u_tl(t0, t0); 4851 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4852 tcg_gen_ext16u_tl(t1, t1); 4853 break; 4854 case 0x0D: 4855 /* maclhw - maclhw. - maclhwo - maclhwo. */ 4856 /* maclhws - maclhws. - maclhwso - maclhwso. */ 4857 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 4858 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 4859 /* mullhw - mullhw. */ 4860 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4861 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 4862 break; 4863 case 0x0C: 4864 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 4865 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 4866 /* mullhwu - mullhwu. */ 4867 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4868 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 4869 break; 4870 } 4871 if (opc2 & 0x04) { 4872 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 4873 tcg_gen_mul_tl(t1, t0, t1); 4874 if (opc2 & 0x02) { 4875 /* nmultiply-and-accumulate (0x0E) */ 4876 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 4877 } else { 4878 /* multiply-and-accumulate (0x0C) */ 4879 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 4880 } 4881 4882 if (opc3 & 0x12) { 4883 /* Check overflow and/or saturate */ 4884 TCGLabel *l1 = gen_new_label(); 4885 4886 if (opc3 & 0x10) { 4887 /* Start with XER OV disabled, the most likely case */ 4888 tcg_gen_movi_tl(cpu_ov, 0); 4889 } 4890 if (opc3 & 0x01) { 4891 /* Signed */ 4892 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 4893 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 4894 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 4895 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 4896 if (opc3 & 0x02) { 4897 /* Saturate */ 4898 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 4899 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 4900 } 4901 } else { 4902 /* Unsigned */ 4903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4904 if (opc3 & 0x02) { 4905 /* Saturate */ 4906 tcg_gen_movi_tl(t0, UINT32_MAX); 4907 } 4908 } 4909 if (opc3 & 0x10) { 4910 /* Check overflow */ 4911 tcg_gen_movi_tl(cpu_ov, 1); 4912 tcg_gen_movi_tl(cpu_so, 1); 4913 } 4914 gen_set_label(l1); 4915 tcg_gen_mov_tl(cpu_gpr[rt], t0); 4916 } 4917 } else { 4918 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 4919 } 4920 if (unlikely(Rc) != 0) { 4921 /* Update Rc0 */ 4922 gen_set_Rc0(ctx, cpu_gpr[rt]); 4923 } 4924 } 4925 4926 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 4927 static void glue(gen_, name)(DisasContext *ctx) \ 4928 { \ 4929 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 4930 rD(ctx->opcode), Rc(ctx->opcode)); \ 4931 } 4932 4933 /* macchw - macchw. */ 4934 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 4935 /* macchwo - macchwo. */ 4936 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 4937 /* macchws - macchws. */ 4938 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 4939 /* macchwso - macchwso. */ 4940 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 4941 /* macchwsu - macchwsu. */ 4942 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 4943 /* macchwsuo - macchwsuo. */ 4944 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 4945 /* macchwu - macchwu. */ 4946 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 4947 /* macchwuo - macchwuo. */ 4948 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 4949 /* machhw - machhw. */ 4950 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 4951 /* machhwo - machhwo. */ 4952 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 4953 /* machhws - machhws. */ 4954 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 4955 /* machhwso - machhwso. */ 4956 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 4957 /* machhwsu - machhwsu. */ 4958 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 4959 /* machhwsuo - machhwsuo. */ 4960 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 4961 /* machhwu - machhwu. */ 4962 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 4963 /* machhwuo - machhwuo. */ 4964 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 4965 /* maclhw - maclhw. */ 4966 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 4967 /* maclhwo - maclhwo. */ 4968 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 4969 /* maclhws - maclhws. */ 4970 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 4971 /* maclhwso - maclhwso. */ 4972 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 4973 /* maclhwu - maclhwu. */ 4974 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 4975 /* maclhwuo - maclhwuo. */ 4976 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 4977 /* maclhwsu - maclhwsu. */ 4978 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 4979 /* maclhwsuo - maclhwsuo. */ 4980 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 4981 /* nmacchw - nmacchw. */ 4982 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 4983 /* nmacchwo - nmacchwo. */ 4984 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 4985 /* nmacchws - nmacchws. */ 4986 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 4987 /* nmacchwso - nmacchwso. */ 4988 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 4989 /* nmachhw - nmachhw. */ 4990 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 4991 /* nmachhwo - nmachhwo. */ 4992 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 4993 /* nmachhws - nmachhws. */ 4994 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 4995 /* nmachhwso - nmachhwso. */ 4996 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 4997 /* nmaclhw - nmaclhw. */ 4998 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 4999 /* nmaclhwo - nmaclhwo. */ 5000 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5001 /* nmaclhws - nmaclhws. */ 5002 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5003 /* nmaclhwso - nmaclhwso. */ 5004 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5005 5006 /* mulchw - mulchw. */ 5007 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5008 /* mulchwu - mulchwu. */ 5009 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5010 /* mulhhw - mulhhw. */ 5011 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5012 /* mulhhwu - mulhhwu. */ 5013 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5014 /* mullhw - mullhw. */ 5015 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5016 /* mullhwu - mullhwu. */ 5017 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5018 5019 /* mfdcr */ 5020 static void gen_mfdcr(DisasContext *ctx) 5021 { 5022 #if defined(CONFIG_USER_ONLY) 5023 GEN_PRIV(ctx); 5024 #else 5025 TCGv dcrn; 5026 5027 CHK_SV(ctx); 5028 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5029 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); 5030 #endif /* defined(CONFIG_USER_ONLY) */ 5031 } 5032 5033 /* mtdcr */ 5034 static void gen_mtdcr(DisasContext *ctx) 5035 { 5036 #if defined(CONFIG_USER_ONLY) 5037 GEN_PRIV(ctx); 5038 #else 5039 TCGv dcrn; 5040 5041 CHK_SV(ctx); 5042 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5043 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5044 #endif /* defined(CONFIG_USER_ONLY) */ 5045 } 5046 5047 /* mfdcrx */ 5048 /* XXX: not implemented on 440 ? */ 5049 static void gen_mfdcrx(DisasContext *ctx) 5050 { 5051 #if defined(CONFIG_USER_ONLY) 5052 GEN_PRIV(ctx); 5053 #else 5054 CHK_SV(ctx); 5055 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, 5056 cpu_gpr[rA(ctx->opcode)]); 5057 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5058 #endif /* defined(CONFIG_USER_ONLY) */ 5059 } 5060 5061 /* mtdcrx */ 5062 /* XXX: not implemented on 440 ? */ 5063 static void gen_mtdcrx(DisasContext *ctx) 5064 { 5065 #if defined(CONFIG_USER_ONLY) 5066 GEN_PRIV(ctx); 5067 #else 5068 CHK_SV(ctx); 5069 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], 5070 cpu_gpr[rS(ctx->opcode)]); 5071 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5072 #endif /* defined(CONFIG_USER_ONLY) */ 5073 } 5074 5075 /* dccci */ 5076 static void gen_dccci(DisasContext *ctx) 5077 { 5078 CHK_SV(ctx); 5079 /* interpreted as no-op */ 5080 } 5081 5082 /* dcread */ 5083 static void gen_dcread(DisasContext *ctx) 5084 { 5085 #if defined(CONFIG_USER_ONLY) 5086 GEN_PRIV(ctx); 5087 #else 5088 TCGv EA, val; 5089 5090 CHK_SV(ctx); 5091 gen_set_access_type(ctx, ACCESS_CACHE); 5092 EA = tcg_temp_new(); 5093 gen_addr_reg_index(ctx, EA); 5094 val = tcg_temp_new(); 5095 gen_qemu_ld32u(ctx, val, EA); 5096 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5097 #endif /* defined(CONFIG_USER_ONLY) */ 5098 } 5099 5100 /* icbt */ 5101 static void gen_icbt_40x(DisasContext *ctx) 5102 { 5103 /* 5104 * interpreted as no-op 5105 * XXX: specification say this is treated as a load by the MMU but 5106 * does not generate any exception 5107 */ 5108 } 5109 5110 /* iccci */ 5111 static void gen_iccci(DisasContext *ctx) 5112 { 5113 CHK_SV(ctx); 5114 /* interpreted as no-op */ 5115 } 5116 5117 /* icread */ 5118 static void gen_icread(DisasContext *ctx) 5119 { 5120 CHK_SV(ctx); 5121 /* interpreted as no-op */ 5122 } 5123 5124 /* rfci (supervisor only) */ 5125 static void gen_rfci_40x(DisasContext *ctx) 5126 { 5127 #if defined(CONFIG_USER_ONLY) 5128 GEN_PRIV(ctx); 5129 #else 5130 CHK_SV(ctx); 5131 /* Restore CPU state */ 5132 gen_helper_40x_rfci(tcg_env); 5133 ctx->base.is_jmp = DISAS_EXIT; 5134 #endif /* defined(CONFIG_USER_ONLY) */ 5135 } 5136 5137 static void gen_rfci(DisasContext *ctx) 5138 { 5139 #if defined(CONFIG_USER_ONLY) 5140 GEN_PRIV(ctx); 5141 #else 5142 CHK_SV(ctx); 5143 /* Restore CPU state */ 5144 gen_helper_rfci(tcg_env); 5145 ctx->base.is_jmp = DISAS_EXIT; 5146 #endif /* defined(CONFIG_USER_ONLY) */ 5147 } 5148 5149 /* BookE specific */ 5150 5151 /* XXX: not implemented on 440 ? */ 5152 static void gen_rfdi(DisasContext *ctx) 5153 { 5154 #if defined(CONFIG_USER_ONLY) 5155 GEN_PRIV(ctx); 5156 #else 5157 CHK_SV(ctx); 5158 /* Restore CPU state */ 5159 gen_helper_rfdi(tcg_env); 5160 ctx->base.is_jmp = DISAS_EXIT; 5161 #endif /* defined(CONFIG_USER_ONLY) */ 5162 } 5163 5164 /* XXX: not implemented on 440 ? */ 5165 static void gen_rfmci(DisasContext *ctx) 5166 { 5167 #if defined(CONFIG_USER_ONLY) 5168 GEN_PRIV(ctx); 5169 #else 5170 CHK_SV(ctx); 5171 /* Restore CPU state */ 5172 gen_helper_rfmci(tcg_env); 5173 ctx->base.is_jmp = DISAS_EXIT; 5174 #endif /* defined(CONFIG_USER_ONLY) */ 5175 } 5176 5177 /* TLB management - PowerPC 405 implementation */ 5178 5179 /* tlbre */ 5180 static void gen_tlbre_40x(DisasContext *ctx) 5181 { 5182 #if defined(CONFIG_USER_ONLY) 5183 GEN_PRIV(ctx); 5184 #else 5185 CHK_SV(ctx); 5186 switch (rB(ctx->opcode)) { 5187 case 0: 5188 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, 5189 cpu_gpr[rA(ctx->opcode)]); 5190 break; 5191 case 1: 5192 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, 5193 cpu_gpr[rA(ctx->opcode)]); 5194 break; 5195 default: 5196 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5197 break; 5198 } 5199 #endif /* defined(CONFIG_USER_ONLY) */ 5200 } 5201 5202 /* tlbsx - tlbsx. */ 5203 static void gen_tlbsx_40x(DisasContext *ctx) 5204 { 5205 #if defined(CONFIG_USER_ONLY) 5206 GEN_PRIV(ctx); 5207 #else 5208 TCGv t0; 5209 5210 CHK_SV(ctx); 5211 t0 = tcg_temp_new(); 5212 gen_addr_reg_index(ctx, t0); 5213 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5214 if (Rc(ctx->opcode)) { 5215 TCGLabel *l1 = gen_new_label(); 5216 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5217 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5218 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5219 gen_set_label(l1); 5220 } 5221 #endif /* defined(CONFIG_USER_ONLY) */ 5222 } 5223 5224 /* tlbwe */ 5225 static void gen_tlbwe_40x(DisasContext *ctx) 5226 { 5227 #if defined(CONFIG_USER_ONLY) 5228 GEN_PRIV(ctx); 5229 #else 5230 CHK_SV(ctx); 5231 5232 switch (rB(ctx->opcode)) { 5233 case 0: 5234 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], 5235 cpu_gpr[rS(ctx->opcode)]); 5236 break; 5237 case 1: 5238 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], 5239 cpu_gpr[rS(ctx->opcode)]); 5240 break; 5241 default: 5242 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5243 break; 5244 } 5245 #endif /* defined(CONFIG_USER_ONLY) */ 5246 } 5247 5248 /* TLB management - PowerPC 440 implementation */ 5249 5250 /* tlbre */ 5251 static void gen_tlbre_440(DisasContext *ctx) 5252 { 5253 #if defined(CONFIG_USER_ONLY) 5254 GEN_PRIV(ctx); 5255 #else 5256 CHK_SV(ctx); 5257 5258 switch (rB(ctx->opcode)) { 5259 case 0: 5260 case 1: 5261 case 2: 5262 { 5263 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5264 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, 5265 t0, cpu_gpr[rA(ctx->opcode)]); 5266 } 5267 break; 5268 default: 5269 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5270 break; 5271 } 5272 #endif /* defined(CONFIG_USER_ONLY) */ 5273 } 5274 5275 /* tlbsx - tlbsx. */ 5276 static void gen_tlbsx_440(DisasContext *ctx) 5277 { 5278 #if defined(CONFIG_USER_ONLY) 5279 GEN_PRIV(ctx); 5280 #else 5281 TCGv t0; 5282 5283 CHK_SV(ctx); 5284 t0 = tcg_temp_new(); 5285 gen_addr_reg_index(ctx, t0); 5286 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5287 if (Rc(ctx->opcode)) { 5288 TCGLabel *l1 = gen_new_label(); 5289 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5290 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5291 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5292 gen_set_label(l1); 5293 } 5294 #endif /* defined(CONFIG_USER_ONLY) */ 5295 } 5296 5297 /* tlbwe */ 5298 static void gen_tlbwe_440(DisasContext *ctx) 5299 { 5300 #if defined(CONFIG_USER_ONLY) 5301 GEN_PRIV(ctx); 5302 #else 5303 CHK_SV(ctx); 5304 switch (rB(ctx->opcode)) { 5305 case 0: 5306 case 1: 5307 case 2: 5308 { 5309 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5310 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], 5311 cpu_gpr[rS(ctx->opcode)]); 5312 } 5313 break; 5314 default: 5315 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5316 break; 5317 } 5318 #endif /* defined(CONFIG_USER_ONLY) */ 5319 } 5320 5321 /* TLB management - PowerPC BookE 2.06 implementation */ 5322 5323 /* tlbre */ 5324 static void gen_tlbre_booke206(DisasContext *ctx) 5325 { 5326 #if defined(CONFIG_USER_ONLY) 5327 GEN_PRIV(ctx); 5328 #else 5329 CHK_SV(ctx); 5330 gen_helper_booke206_tlbre(tcg_env); 5331 #endif /* defined(CONFIG_USER_ONLY) */ 5332 } 5333 5334 /* tlbsx - tlbsx. */ 5335 static void gen_tlbsx_booke206(DisasContext *ctx) 5336 { 5337 #if defined(CONFIG_USER_ONLY) 5338 GEN_PRIV(ctx); 5339 #else 5340 TCGv t0; 5341 5342 CHK_SV(ctx); 5343 if (rA(ctx->opcode)) { 5344 t0 = tcg_temp_new(); 5345 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5346 } else { 5347 t0 = cpu_gpr[rB(ctx->opcode)]; 5348 } 5349 gen_helper_booke206_tlbsx(tcg_env, t0); 5350 #endif /* defined(CONFIG_USER_ONLY) */ 5351 } 5352 5353 /* tlbwe */ 5354 static void gen_tlbwe_booke206(DisasContext *ctx) 5355 { 5356 #if defined(CONFIG_USER_ONLY) 5357 GEN_PRIV(ctx); 5358 #else 5359 CHK_SV(ctx); 5360 gen_helper_booke206_tlbwe(tcg_env); 5361 #endif /* defined(CONFIG_USER_ONLY) */ 5362 } 5363 5364 static void gen_tlbivax_booke206(DisasContext *ctx) 5365 { 5366 #if defined(CONFIG_USER_ONLY) 5367 GEN_PRIV(ctx); 5368 #else 5369 TCGv t0; 5370 5371 CHK_SV(ctx); 5372 t0 = tcg_temp_new(); 5373 gen_addr_reg_index(ctx, t0); 5374 gen_helper_booke206_tlbivax(tcg_env, t0); 5375 #endif /* defined(CONFIG_USER_ONLY) */ 5376 } 5377 5378 static void gen_tlbilx_booke206(DisasContext *ctx) 5379 { 5380 #if defined(CONFIG_USER_ONLY) 5381 GEN_PRIV(ctx); 5382 #else 5383 TCGv t0; 5384 5385 CHK_SV(ctx); 5386 t0 = tcg_temp_new(); 5387 gen_addr_reg_index(ctx, t0); 5388 5389 switch ((ctx->opcode >> 21) & 0x3) { 5390 case 0: 5391 gen_helper_booke206_tlbilx0(tcg_env, t0); 5392 break; 5393 case 1: 5394 gen_helper_booke206_tlbilx1(tcg_env, t0); 5395 break; 5396 case 3: 5397 gen_helper_booke206_tlbilx3(tcg_env, t0); 5398 break; 5399 default: 5400 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5401 break; 5402 } 5403 #endif /* defined(CONFIG_USER_ONLY) */ 5404 } 5405 5406 /* wrtee */ 5407 static void gen_wrtee(DisasContext *ctx) 5408 { 5409 #if defined(CONFIG_USER_ONLY) 5410 GEN_PRIV(ctx); 5411 #else 5412 TCGv t0; 5413 5414 CHK_SV(ctx); 5415 t0 = tcg_temp_new(); 5416 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5417 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5418 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5419 gen_ppc_maybe_interrupt(ctx); 5420 /* 5421 * Stop translation to have a chance to raise an exception if we 5422 * just set msr_ee to 1 5423 */ 5424 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5425 #endif /* defined(CONFIG_USER_ONLY) */ 5426 } 5427 5428 /* wrteei */ 5429 static void gen_wrteei(DisasContext *ctx) 5430 { 5431 #if defined(CONFIG_USER_ONLY) 5432 GEN_PRIV(ctx); 5433 #else 5434 CHK_SV(ctx); 5435 if (ctx->opcode & 0x00008000) { 5436 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5437 gen_ppc_maybe_interrupt(ctx); 5438 /* Stop translation to have a chance to raise an exception */ 5439 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5440 } else { 5441 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5442 } 5443 #endif /* defined(CONFIG_USER_ONLY) */ 5444 } 5445 5446 /* PowerPC 440 specific instructions */ 5447 5448 /* dlmzb */ 5449 static void gen_dlmzb(DisasContext *ctx) 5450 { 5451 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5452 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, 5453 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5454 } 5455 5456 /* icbt */ 5457 static void gen_icbt_440(DisasContext *ctx) 5458 { 5459 /* 5460 * interpreted as no-op 5461 * XXX: specification say this is treated as a load by the MMU but 5462 * does not generate any exception 5463 */ 5464 } 5465 5466 static void gen_tbegin(DisasContext *ctx) 5467 { 5468 if (unlikely(!ctx->tm_enabled)) { 5469 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5470 return; 5471 } 5472 gen_helper_tbegin(tcg_env); 5473 } 5474 5475 #define GEN_TM_NOOP(name) \ 5476 static inline void gen_##name(DisasContext *ctx) \ 5477 { \ 5478 if (unlikely(!ctx->tm_enabled)) { \ 5479 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5480 return; \ 5481 } \ 5482 /* \ 5483 * Because tbegin always fails in QEMU, these user \ 5484 * space instructions all have a simple implementation: \ 5485 * \ 5486 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5487 * = 0b0 || 0b00 || 0b0 \ 5488 */ \ 5489 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5490 } 5491 5492 GEN_TM_NOOP(tend); 5493 GEN_TM_NOOP(tabort); 5494 GEN_TM_NOOP(tabortwc); 5495 GEN_TM_NOOP(tabortwci); 5496 GEN_TM_NOOP(tabortdc); 5497 GEN_TM_NOOP(tabortdci); 5498 GEN_TM_NOOP(tsr); 5499 5500 static inline void gen_cp_abort(DisasContext *ctx) 5501 { 5502 /* Do Nothing */ 5503 } 5504 5505 #define GEN_CP_PASTE_NOOP(name) \ 5506 static inline void gen_##name(DisasContext *ctx) \ 5507 { \ 5508 /* \ 5509 * Generate invalid exception until we have an \ 5510 * implementation of the copy paste facility \ 5511 */ \ 5512 gen_invalid(ctx); \ 5513 } 5514 5515 GEN_CP_PASTE_NOOP(copy) 5516 GEN_CP_PASTE_NOOP(paste) 5517 5518 static void gen_tcheck(DisasContext *ctx) 5519 { 5520 if (unlikely(!ctx->tm_enabled)) { 5521 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5522 return; 5523 } 5524 /* 5525 * Because tbegin always fails, the tcheck implementation is 5526 * simple: 5527 * 5528 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 5529 * = 0b1 || 0b00 || 0b0 5530 */ 5531 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 5532 } 5533 5534 #if defined(CONFIG_USER_ONLY) 5535 #define GEN_TM_PRIV_NOOP(name) \ 5536 static inline void gen_##name(DisasContext *ctx) \ 5537 { \ 5538 gen_priv_opc(ctx); \ 5539 } 5540 5541 #else 5542 5543 #define GEN_TM_PRIV_NOOP(name) \ 5544 static inline void gen_##name(DisasContext *ctx) \ 5545 { \ 5546 CHK_SV(ctx); \ 5547 if (unlikely(!ctx->tm_enabled)) { \ 5548 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5549 return; \ 5550 } \ 5551 /* \ 5552 * Because tbegin always fails, the implementation is \ 5553 * simple: \ 5554 * \ 5555 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5556 * = 0b0 || 0b00 | 0b0 \ 5557 */ \ 5558 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5559 } 5560 5561 #endif 5562 5563 GEN_TM_PRIV_NOOP(treclaim); 5564 GEN_TM_PRIV_NOOP(trechkpt); 5565 5566 static inline void get_fpr(TCGv_i64 dst, int regno) 5567 { 5568 tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); 5569 } 5570 5571 static inline void set_fpr(int regno, TCGv_i64 src) 5572 { 5573 tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); 5574 /* 5575 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 5576 * corresponding to the target FPR was undefined. However, 5577 * most (if not all) real hardware were setting the result to 0. 5578 * Starting at ISA v3.1, the result for doubleword 1 is now defined 5579 * to be 0. 5580 */ 5581 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false)); 5582 } 5583 5584 /* 5585 * Helpers for decodetree used by !function for decoding arguments. 5586 */ 5587 static int times_2(DisasContext *ctx, int x) 5588 { 5589 return x * 2; 5590 } 5591 5592 static int times_4(DisasContext *ctx, int x) 5593 { 5594 return x * 4; 5595 } 5596 5597 static int times_16(DisasContext *ctx, int x) 5598 { 5599 return x * 16; 5600 } 5601 5602 static int64_t dw_compose_ea(DisasContext *ctx, int x) 5603 { 5604 return deposit64(0xfffffffffffffe00, 3, 6, x); 5605 } 5606 5607 /* 5608 * Helpers for trans_* functions to check for specific insns flags. 5609 * Use token pasting to ensure that we use the proper flag with the 5610 * proper variable. 5611 */ 5612 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 5613 do { \ 5614 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 5615 return false; \ 5616 } \ 5617 } while (0) 5618 5619 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 5620 do { \ 5621 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 5622 return false; \ 5623 } \ 5624 } while (0) 5625 5626 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 5627 #if TARGET_LONG_BITS == 32 5628 # define REQUIRE_64BIT(CTX) return false 5629 #else 5630 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 5631 #endif 5632 5633 #define REQUIRE_VECTOR(CTX) \ 5634 do { \ 5635 if (unlikely(!(CTX)->altivec_enabled)) { \ 5636 gen_exception((CTX), POWERPC_EXCP_VPU); \ 5637 return true; \ 5638 } \ 5639 } while (0) 5640 5641 #define REQUIRE_VSX(CTX) \ 5642 do { \ 5643 if (unlikely(!(CTX)->vsx_enabled)) { \ 5644 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 5645 return true; \ 5646 } \ 5647 } while (0) 5648 5649 #define REQUIRE_FPU(ctx) \ 5650 do { \ 5651 if (unlikely(!(ctx)->fpu_enabled)) { \ 5652 gen_exception((ctx), POWERPC_EXCP_FPU); \ 5653 return true; \ 5654 } \ 5655 } while (0) 5656 5657 #if !defined(CONFIG_USER_ONLY) 5658 #define REQUIRE_SV(CTX) \ 5659 do { \ 5660 if (unlikely((CTX)->pr)) { \ 5661 gen_priv_opc(CTX); \ 5662 return true; \ 5663 } \ 5664 } while (0) 5665 5666 #define REQUIRE_HV(CTX) \ 5667 do { \ 5668 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 5669 gen_priv_opc(CTX); \ 5670 return true; \ 5671 } \ 5672 } while (0) 5673 #else 5674 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5675 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5676 #endif 5677 5678 /* 5679 * Helpers for implementing sets of trans_* functions. 5680 * Defer the implementation of NAME to FUNC, with optional extra arguments. 5681 */ 5682 #define TRANS(NAME, FUNC, ...) \ 5683 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5684 { return FUNC(ctx, a, __VA_ARGS__); } 5685 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 5686 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5687 { \ 5688 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 5689 return FUNC(ctx, a, __VA_ARGS__); \ 5690 } 5691 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5692 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5693 { \ 5694 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5695 return FUNC(ctx, a, __VA_ARGS__); \ 5696 } 5697 5698 #define TRANS64(NAME, FUNC, ...) \ 5699 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5700 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 5701 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5702 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5703 { \ 5704 REQUIRE_64BIT(ctx); \ 5705 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5706 return FUNC(ctx, a, __VA_ARGS__); \ 5707 } 5708 5709 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 5710 5711 5712 #include "decode-insn32.c.inc" 5713 #include "decode-insn64.c.inc" 5714 #include "power8-pmu-regs.c.inc" 5715 5716 /* 5717 * Incorporate CIA into the constant when R=1. 5718 * Validate that when R=1, RA=0. 5719 */ 5720 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 5721 { 5722 d->rt = a->rt; 5723 d->ra = a->ra; 5724 d->si = a->si; 5725 if (a->r) { 5726 if (unlikely(a->ra != 0)) { 5727 gen_invalid(ctx); 5728 return false; 5729 } 5730 d->si += ctx->cia; 5731 } 5732 return true; 5733 } 5734 5735 #include "translate/fixedpoint-impl.c.inc" 5736 5737 #include "translate/fp-impl.c.inc" 5738 5739 #include "translate/vmx-impl.c.inc" 5740 5741 #include "translate/vsx-impl.c.inc" 5742 5743 #include "translate/dfp-impl.c.inc" 5744 5745 #include "translate/spe-impl.c.inc" 5746 5747 #include "translate/branch-impl.c.inc" 5748 5749 #include "translate/processor-ctrl-impl.c.inc" 5750 5751 #include "translate/storage-ctrl-impl.c.inc" 5752 5753 #include "translate/misc-impl.c.inc" 5754 5755 #include "translate/bhrb-impl.c.inc" 5756 5757 /* Handles lfdp */ 5758 static void gen_dform39(DisasContext *ctx) 5759 { 5760 if ((ctx->opcode & 0x3) == 0) { 5761 if (ctx->insns_flags2 & PPC2_ISA205) { 5762 return gen_lfdp(ctx); 5763 } 5764 } 5765 return gen_invalid(ctx); 5766 } 5767 5768 /* Handles stfdp */ 5769 static void gen_dform3D(DisasContext *ctx) 5770 { 5771 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 5772 /* stfdp */ 5773 if (ctx->insns_flags2 & PPC2_ISA205) { 5774 return gen_stfdp(ctx); 5775 } 5776 } 5777 return gen_invalid(ctx); 5778 } 5779 5780 #if defined(TARGET_PPC64) 5781 /* brd */ 5782 static void gen_brd(DisasContext *ctx) 5783 { 5784 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5785 } 5786 5787 /* brw */ 5788 static void gen_brw(DisasContext *ctx) 5789 { 5790 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5791 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 5792 5793 } 5794 5795 /* brh */ 5796 static void gen_brh(DisasContext *ctx) 5797 { 5798 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 5799 TCGv_i64 t1 = tcg_temp_new_i64(); 5800 TCGv_i64 t2 = tcg_temp_new_i64(); 5801 5802 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 5803 tcg_gen_and_i64(t2, t1, mask); 5804 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 5805 tcg_gen_shli_i64(t1, t1, 8); 5806 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 5807 } 5808 #endif 5809 5810 static opcode_t opcodes[] = { 5811 #if defined(TARGET_PPC64) 5812 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 5813 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 5814 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 5815 #endif 5816 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 5817 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 5818 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5819 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 5820 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5821 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5822 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5823 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 5824 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 5825 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 5826 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 5827 #if defined(TARGET_PPC64) 5828 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 5829 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 5830 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 5831 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 5832 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 5833 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 5834 PPC_NONE, PPC2_ISA300), 5835 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 5836 PPC_NONE, PPC2_ISA300), 5837 #endif 5838 /* handles lfdp, lxsd, lxssp */ 5839 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5840 /* handles stfdp, stxsd, stxssp */ 5841 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5842 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5843 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5844 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 5845 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 5846 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 5847 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 5848 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 5849 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5850 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5851 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 5852 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 5853 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 5854 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5855 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5856 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 5857 #if defined(TARGET_PPC64) 5858 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 5859 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 5860 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 5861 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 5862 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 5863 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 5864 #endif 5865 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 5866 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 5867 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 5868 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5869 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5870 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 5871 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 5872 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 5873 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 5874 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 5875 #if defined(TARGET_PPC64) 5876 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 5877 #if !defined(CONFIG_USER_ONLY) 5878 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5879 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5880 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5881 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 5882 #endif 5883 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5884 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5885 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5886 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5887 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5888 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 5889 #endif 5890 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5891 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 5892 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 5893 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 5894 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 5895 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 5896 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 5897 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 5898 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 5899 #if defined(TARGET_PPC64) 5900 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 5901 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 5902 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 5903 #endif 5904 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 5905 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 5906 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 5907 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5908 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 5909 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 5910 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5911 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 5912 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5913 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 5914 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5915 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5916 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5917 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 5918 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5919 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 5920 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 5921 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 5922 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 5923 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5924 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 5925 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 5926 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 5927 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 5928 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 5929 #if defined(TARGET_PPC64) 5930 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 5931 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 5932 PPC_SEGMENT_64B), 5933 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 5934 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 5935 PPC_SEGMENT_64B), 5936 #endif 5937 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 5938 /* 5939 * XXX Those instructions will need to be handled differently for 5940 * different ISA versions 5941 */ 5942 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 5943 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 5944 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 5945 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 5946 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 5947 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 5948 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 5949 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 5950 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 5951 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 5952 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 5953 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 5954 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 5955 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 5956 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 5957 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 5958 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 5959 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 5960 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 5961 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 5962 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 5963 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 5964 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 5965 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 5966 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 5967 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 5968 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 5969 PPC_NONE, PPC2_BOOKE206), 5970 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 5971 PPC_NONE, PPC2_BOOKE206), 5972 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 5973 PPC_NONE, PPC2_BOOKE206), 5974 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 5975 PPC_NONE, PPC2_BOOKE206), 5976 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 5977 PPC_NONE, PPC2_BOOKE206), 5978 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 5979 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 5980 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 5981 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 5982 PPC_BOOKE, PPC2_BOOKE206), 5983 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 5984 PPC_440_SPEC), 5985 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 5986 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 5987 5988 #if defined(TARGET_PPC64) 5989 #undef GEN_PPC64_R2 5990 #undef GEN_PPC64_R4 5991 #define GEN_PPC64_R2(name, opc1, opc2) \ 5992 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 5993 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 5994 PPC_64B) 5995 #define GEN_PPC64_R4(name, opc1, opc2) \ 5996 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 5997 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 5998 PPC_64B), \ 5999 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6000 PPC_64B), \ 6001 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6002 PPC_64B) 6003 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6004 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6005 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6006 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6007 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6008 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6009 #endif 6010 6011 #undef GEN_LDX_E 6012 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6013 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6014 6015 #if defined(TARGET_PPC64) 6016 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6017 6018 /* HV/P7 and later only */ 6019 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6020 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6021 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6022 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6023 #endif 6024 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6025 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6026 6027 /* External PID based load */ 6028 #undef GEN_LDEPX 6029 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6030 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6031 0x00000001, PPC_NONE, PPC2_BOOKE206), 6032 6033 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6034 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6035 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6036 #if defined(TARGET_PPC64) 6037 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6038 #endif 6039 6040 #undef GEN_STX_E 6041 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6042 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6043 6044 #if defined(TARGET_PPC64) 6045 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6046 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6047 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6048 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6049 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6050 #endif 6051 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6052 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6053 6054 #undef GEN_STEPX 6055 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6056 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6057 0x00000001, PPC_NONE, PPC2_BOOKE206), 6058 6059 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6060 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6061 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6062 #if defined(TARGET_PPC64) 6063 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6064 #endif 6065 6066 #undef GEN_CRLOGIC 6067 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6068 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6069 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6070 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6071 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6072 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6073 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6074 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6075 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6076 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6077 6078 #undef GEN_MAC_HANDLER 6079 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6080 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6081 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6082 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6083 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6084 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6085 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6086 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6087 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6088 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6089 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6090 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6091 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6092 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6093 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6094 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6095 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6096 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6097 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6098 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6099 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6100 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6101 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6102 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6103 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6104 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6105 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6106 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6107 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6108 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6109 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6110 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6111 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6112 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6113 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6114 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6115 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6116 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6117 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6118 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6119 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6120 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6121 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6122 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6123 6124 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6125 PPC_NONE, PPC2_TM), 6126 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6127 PPC_NONE, PPC2_TM), 6128 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6129 PPC_NONE, PPC2_TM), 6130 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6131 PPC_NONE, PPC2_TM), 6132 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6133 PPC_NONE, PPC2_TM), 6134 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6135 PPC_NONE, PPC2_TM), 6136 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6137 PPC_NONE, PPC2_TM), 6138 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6139 PPC_NONE, PPC2_TM), 6140 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6141 PPC_NONE, PPC2_TM), 6142 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6143 PPC_NONE, PPC2_TM), 6144 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6145 PPC_NONE, PPC2_TM), 6146 6147 #include "translate/fp-ops.c.inc" 6148 6149 #include "translate/vmx-ops.c.inc" 6150 6151 #include "translate/vsx-ops.c.inc" 6152 6153 #include "translate/spe-ops.c.inc" 6154 }; 6155 6156 /*****************************************************************************/ 6157 /* Opcode types */ 6158 enum { 6159 PPC_DIRECT = 0, /* Opcode routine */ 6160 PPC_INDIRECT = 1, /* Indirect opcode table */ 6161 }; 6162 6163 #define PPC_OPCODE_MASK 0x3 6164 6165 static inline int is_indirect_opcode(void *handler) 6166 { 6167 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6168 } 6169 6170 static inline opc_handler_t **ind_table(void *handler) 6171 { 6172 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6173 } 6174 6175 /* Instruction table creation */ 6176 /* Opcodes tables creation */ 6177 static void fill_new_table(opc_handler_t **table, int len) 6178 { 6179 int i; 6180 6181 for (i = 0; i < len; i++) { 6182 table[i] = &invalid_handler; 6183 } 6184 } 6185 6186 static int create_new_table(opc_handler_t **table, unsigned char idx) 6187 { 6188 opc_handler_t **tmp; 6189 6190 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6191 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6192 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6193 6194 return 0; 6195 } 6196 6197 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6198 opc_handler_t *handler) 6199 { 6200 if (table[idx] != &invalid_handler) { 6201 return -1; 6202 } 6203 table[idx] = handler; 6204 6205 return 0; 6206 } 6207 6208 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6209 unsigned char idx, opc_handler_t *handler) 6210 { 6211 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6212 printf("*** ERROR: opcode %02x already assigned in main " 6213 "opcode table\n", idx); 6214 return -1; 6215 } 6216 6217 return 0; 6218 } 6219 6220 static int register_ind_in_table(opc_handler_t **table, 6221 unsigned char idx1, unsigned char idx2, 6222 opc_handler_t *handler) 6223 { 6224 if (table[idx1] == &invalid_handler) { 6225 if (create_new_table(table, idx1) < 0) { 6226 printf("*** ERROR: unable to create indirect table " 6227 "idx=%02x\n", idx1); 6228 return -1; 6229 } 6230 } else { 6231 if (!is_indirect_opcode(table[idx1])) { 6232 printf("*** ERROR: idx %02x already assigned to a direct " 6233 "opcode\n", idx1); 6234 return -1; 6235 } 6236 } 6237 if (handler != NULL && 6238 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6239 printf("*** ERROR: opcode %02x already assigned in " 6240 "opcode table %02x\n", idx2, idx1); 6241 return -1; 6242 } 6243 6244 return 0; 6245 } 6246 6247 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6248 unsigned char idx1, unsigned char idx2, 6249 opc_handler_t *handler) 6250 { 6251 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6252 } 6253 6254 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6255 unsigned char idx1, unsigned char idx2, 6256 unsigned char idx3, opc_handler_t *handler) 6257 { 6258 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6259 printf("*** ERROR: unable to join indirect table idx " 6260 "[%02x-%02x]\n", idx1, idx2); 6261 return -1; 6262 } 6263 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6264 handler) < 0) { 6265 printf("*** ERROR: unable to insert opcode " 6266 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6267 return -1; 6268 } 6269 6270 return 0; 6271 } 6272 6273 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6274 unsigned char idx1, unsigned char idx2, 6275 unsigned char idx3, unsigned char idx4, 6276 opc_handler_t *handler) 6277 { 6278 opc_handler_t **table; 6279 6280 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6281 printf("*** ERROR: unable to join indirect table idx " 6282 "[%02x-%02x]\n", idx1, idx2); 6283 return -1; 6284 } 6285 table = ind_table(ppc_opcodes[idx1]); 6286 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 6287 printf("*** ERROR: unable to join 2nd-level indirect table idx " 6288 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6289 return -1; 6290 } 6291 table = ind_table(table[idx2]); 6292 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 6293 printf("*** ERROR: unable to insert opcode " 6294 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 6295 return -1; 6296 } 6297 return 0; 6298 } 6299 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 6300 { 6301 if (insn->opc2 != 0xFF) { 6302 if (insn->opc3 != 0xFF) { 6303 if (insn->opc4 != 0xFF) { 6304 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6305 insn->opc3, insn->opc4, 6306 &insn->handler) < 0) { 6307 return -1; 6308 } 6309 } else { 6310 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6311 insn->opc3, &insn->handler) < 0) { 6312 return -1; 6313 } 6314 } 6315 } else { 6316 if (register_ind_insn(ppc_opcodes, insn->opc1, 6317 insn->opc2, &insn->handler) < 0) { 6318 return -1; 6319 } 6320 } 6321 } else { 6322 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 6323 return -1; 6324 } 6325 } 6326 6327 return 0; 6328 } 6329 6330 static int test_opcode_table(opc_handler_t **table, int len) 6331 { 6332 int i, count, tmp; 6333 6334 for (i = 0, count = 0; i < len; i++) { 6335 /* Consistency fixup */ 6336 if (table[i] == NULL) { 6337 table[i] = &invalid_handler; 6338 } 6339 if (table[i] != &invalid_handler) { 6340 if (is_indirect_opcode(table[i])) { 6341 tmp = test_opcode_table(ind_table(table[i]), 6342 PPC_CPU_INDIRECT_OPCODES_LEN); 6343 if (tmp == 0) { 6344 g_free(table[i]); 6345 table[i] = &invalid_handler; 6346 } else { 6347 count++; 6348 } 6349 } else { 6350 count++; 6351 } 6352 } 6353 } 6354 6355 return count; 6356 } 6357 6358 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 6359 { 6360 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 6361 printf("*** WARNING: no opcode defined !\n"); 6362 } 6363 } 6364 6365 /*****************************************************************************/ 6366 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 6367 { 6368 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6369 opcode_t *opc; 6370 6371 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 6372 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 6373 if (((opc->handler.type & pcc->insns_flags) != 0) || 6374 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 6375 if (register_insn(cpu->opcodes, opc) < 0) { 6376 error_setg(errp, "ERROR initializing PowerPC instruction " 6377 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 6378 opc->opc3); 6379 return; 6380 } 6381 } 6382 } 6383 fix_opcode_tables(cpu->opcodes); 6384 fflush(stdout); 6385 fflush(stderr); 6386 } 6387 6388 void destroy_ppc_opcodes(PowerPCCPU *cpu) 6389 { 6390 opc_handler_t **table, **table_2; 6391 int i, j, k; 6392 6393 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 6394 if (cpu->opcodes[i] == &invalid_handler) { 6395 continue; 6396 } 6397 if (is_indirect_opcode(cpu->opcodes[i])) { 6398 table = ind_table(cpu->opcodes[i]); 6399 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 6400 if (table[j] == &invalid_handler) { 6401 continue; 6402 } 6403 if (is_indirect_opcode(table[j])) { 6404 table_2 = ind_table(table[j]); 6405 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 6406 if (table_2[k] != &invalid_handler && 6407 is_indirect_opcode(table_2[k])) { 6408 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 6409 ~PPC_INDIRECT)); 6410 } 6411 } 6412 g_free((opc_handler_t *)((uintptr_t)table[j] & 6413 ~PPC_INDIRECT)); 6414 } 6415 } 6416 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 6417 ~PPC_INDIRECT)); 6418 } 6419 } 6420 } 6421 6422 int ppc_fixup_cpu(PowerPCCPU *cpu) 6423 { 6424 CPUPPCState *env = &cpu->env; 6425 6426 /* 6427 * TCG doesn't (yet) emulate some groups of instructions that are 6428 * implemented on some otherwise supported CPUs (e.g. VSX and 6429 * decimal floating point instructions on POWER7). We remove 6430 * unsupported instruction groups from the cpu state's instruction 6431 * masks and hope the guest can cope. For at least the pseries 6432 * machine, the unavailability of these instructions can be 6433 * advertised to the guest via the device tree. 6434 */ 6435 if ((env->insns_flags & ~PPC_TCG_INSNS) 6436 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 6437 warn_report("Disabling some instructions which are not " 6438 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 6439 env->insns_flags & ~PPC_TCG_INSNS, 6440 env->insns_flags2 & ~PPC_TCG_INSNS2); 6441 } 6442 env->insns_flags &= PPC_TCG_INSNS; 6443 env->insns_flags2 &= PPC_TCG_INSNS2; 6444 return 0; 6445 } 6446 6447 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 6448 { 6449 opc_handler_t **table, *handler; 6450 uint32_t inval; 6451 6452 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 6453 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6454 ctx->le_mode ? "little" : "big"); 6455 6456 table = cpu->opcodes; 6457 handler = table[opc1(insn)]; 6458 if (is_indirect_opcode(handler)) { 6459 table = ind_table(handler); 6460 handler = table[opc2(insn)]; 6461 if (is_indirect_opcode(handler)) { 6462 table = ind_table(handler); 6463 handler = table[opc3(insn)]; 6464 if (is_indirect_opcode(handler)) { 6465 table = ind_table(handler); 6466 handler = table[opc4(insn)]; 6467 } 6468 } 6469 } 6470 6471 /* Is opcode *REALLY* valid ? */ 6472 if (unlikely(handler->handler == &gen_invalid)) { 6473 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 6474 "%02x - %02x - %02x - %02x (%08x) " 6475 TARGET_FMT_lx "\n", 6476 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6477 insn, ctx->cia); 6478 return false; 6479 } 6480 6481 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 6482 && Rc(insn))) { 6483 inval = handler->inval2; 6484 } else { 6485 inval = handler->inval1; 6486 } 6487 6488 if (unlikely((insn & inval) != 0)) { 6489 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 6490 "%02x - %02x - %02x - %02x (%08x) " 6491 TARGET_FMT_lx "\n", insn & inval, 6492 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6493 insn, ctx->cia); 6494 return false; 6495 } 6496 6497 handler->handler(ctx); 6498 return true; 6499 } 6500 6501 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 6502 { 6503 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6504 CPUPPCState *env = cpu_env(cs); 6505 uint32_t hflags = ctx->base.tb->flags; 6506 6507 ctx->spr_cb = env->spr_cb; 6508 ctx->pr = (hflags >> HFLAGS_PR) & 1; 6509 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 6510 ctx->dr = (hflags >> HFLAGS_DR) & 1; 6511 ctx->hv = (hflags >> HFLAGS_HV) & 1; 6512 ctx->insns_flags = env->insns_flags; 6513 ctx->insns_flags2 = env->insns_flags2; 6514 ctx->access_type = -1; 6515 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 6516 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 6517 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 6518 ctx->flags = env->flags; 6519 #if defined(TARGET_PPC64) 6520 ctx->excp_model = env->excp_model; 6521 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 6522 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 6523 ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB); 6524 #endif 6525 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 6526 || env->mmu_model & POWERPC_MMU_64; 6527 6528 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 6529 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 6530 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 6531 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 6532 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 6533 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 6534 ctx->hr = (hflags >> HFLAGS_HR) & 1; 6535 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 6536 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 6537 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 6538 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 6539 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 6540 ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1; 6541 6542 ctx->singlestep_enabled = 0; 6543 if ((hflags >> HFLAGS_SE) & 1) { 6544 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 6545 ctx->base.max_insns = 1; 6546 } 6547 if ((hflags >> HFLAGS_BE) & 1) { 6548 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 6549 } 6550 } 6551 6552 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 6553 { 6554 } 6555 6556 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 6557 { 6558 tcg_gen_insn_start(dcbase->pc_next); 6559 } 6560 6561 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 6562 { 6563 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 6564 return opc1(insn) == 1; 6565 } 6566 6567 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 6568 { 6569 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6570 PowerPCCPU *cpu = POWERPC_CPU(cs); 6571 CPUPPCState *env = cpu_env(cs); 6572 target_ulong pc; 6573 uint32_t insn; 6574 bool ok; 6575 6576 LOG_DISAS("----------------\n"); 6577 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 6578 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 6579 6580 ctx->cia = pc = ctx->base.pc_next; 6581 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 6582 ctx->base.pc_next = pc += 4; 6583 6584 if (!is_prefix_insn(ctx, insn)) { 6585 ctx->opcode = insn; 6586 ok = (decode_insn32(ctx, insn) || 6587 decode_legacy(cpu, ctx, insn)); 6588 } else if ((pc & 63) == 0) { 6589 /* 6590 * Power v3.1, section 1.9 Exceptions: 6591 * attempt to execute a prefixed instruction that crosses a 6592 * 64-byte address boundary (system alignment error). 6593 */ 6594 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 6595 ok = true; 6596 } else { 6597 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 6598 need_byteswap(ctx)); 6599 ctx->base.pc_next = pc += 4; 6600 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 6601 } 6602 if (!ok) { 6603 gen_invalid(ctx); 6604 } 6605 6606 /* End the TB when crossing a page boundary. */ 6607 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 6608 ctx->base.is_jmp = DISAS_TOO_MANY; 6609 } 6610 } 6611 6612 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 6613 { 6614 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6615 DisasJumpType is_jmp = ctx->base.is_jmp; 6616 target_ulong nip = ctx->base.pc_next; 6617 6618 if (is_jmp == DISAS_NORETURN) { 6619 /* We have already exited the TB. */ 6620 return; 6621 } 6622 6623 /* Honor single stepping. */ 6624 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 6625 bool rfi_type = false; 6626 6627 switch (is_jmp) { 6628 case DISAS_TOO_MANY: 6629 case DISAS_EXIT_UPDATE: 6630 case DISAS_CHAIN_UPDATE: 6631 gen_update_nip(ctx, nip); 6632 break; 6633 case DISAS_EXIT: 6634 case DISAS_CHAIN: 6635 /* 6636 * This is a heuristic, to put it kindly. The rfi class of 6637 * instructions are among the few outside branches that change 6638 * NIP without taking an interrupt. Single step trace interrupts 6639 * do not fire on completion of these instructions. 6640 */ 6641 rfi_type = true; 6642 break; 6643 default: 6644 g_assert_not_reached(); 6645 } 6646 6647 gen_debug_exception(ctx, rfi_type); 6648 return; 6649 } 6650 6651 switch (is_jmp) { 6652 case DISAS_TOO_MANY: 6653 if (use_goto_tb(ctx, nip)) { 6654 pmu_count_insns(ctx); 6655 tcg_gen_goto_tb(0); 6656 gen_update_nip(ctx, nip); 6657 tcg_gen_exit_tb(ctx->base.tb, 0); 6658 break; 6659 } 6660 /* fall through */ 6661 case DISAS_CHAIN_UPDATE: 6662 gen_update_nip(ctx, nip); 6663 /* fall through */ 6664 case DISAS_CHAIN: 6665 /* 6666 * tcg_gen_lookup_and_goto_ptr will exit the TB if 6667 * CF_NO_GOTO_PTR is set. Count insns now. 6668 */ 6669 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 6670 pmu_count_insns(ctx); 6671 } 6672 6673 tcg_gen_lookup_and_goto_ptr(); 6674 break; 6675 6676 case DISAS_EXIT_UPDATE: 6677 gen_update_nip(ctx, nip); 6678 /* fall through */ 6679 case DISAS_EXIT: 6680 pmu_count_insns(ctx); 6681 tcg_gen_exit_tb(NULL, 0); 6682 break; 6683 6684 default: 6685 g_assert_not_reached(); 6686 } 6687 } 6688 6689 static const TranslatorOps ppc_tr_ops = { 6690 .init_disas_context = ppc_tr_init_disas_context, 6691 .tb_start = ppc_tr_tb_start, 6692 .insn_start = ppc_tr_insn_start, 6693 .translate_insn = ppc_tr_translate_insn, 6694 .tb_stop = ppc_tr_tb_stop, 6695 }; 6696 6697 void ppc_translate_code(CPUState *cs, TranslationBlock *tb, 6698 int *max_insns, vaddr pc, void *host_pc) 6699 { 6700 DisasContext ctx; 6701 6702 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 6703 } 6704