1 /* 2 * Miscellaneous PowerPC emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "qemu/error-report.h" 25 #include "qemu/main-loop.h" 26 27 #include "helper_regs.h" 28 29 /*****************************************************************************/ 30 /* SPR accesses */ 31 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) 32 { 33 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, 34 env->spr[sprn]); 35 } 36 37 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) 38 { 39 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, 40 env->spr[sprn]); 41 } 42 43 #ifdef TARGET_PPC64 44 static void raise_fu_exception(CPUPPCState *env, uint32_t bit, 45 uint32_t sprn, uint32_t cause, 46 uintptr_t raddr) 47 { 48 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit); 49 50 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 51 cause &= FSCR_IC_MASK; 52 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; 53 54 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); 55 } 56 #endif 57 58 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, 59 uint32_t sprn, uint32_t cause) 60 { 61 #ifdef TARGET_PPC64 62 if (env->spr[SPR_FSCR] & (1ULL << bit)) { 63 /* Facility is enabled, continue */ 64 return; 65 } 66 raise_fu_exception(env, bit, sprn, cause, GETPC()); 67 #endif 68 } 69 70 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, 71 uint32_t sprn, uint32_t cause) 72 { 73 #ifdef TARGET_PPC64 74 if (env->msr & (1ULL << bit)) { 75 /* Facility is enabled, continue */ 76 return; 77 } 78 raise_fu_exception(env, bit, sprn, cause, GETPC()); 79 #endif 80 } 81 82 #if !defined(CONFIG_USER_ONLY) 83 84 void helper_store_sdr1(CPUPPCState *env, target_ulong val) 85 { 86 if (env->spr[SPR_SDR1] != val) { 87 ppc_store_sdr1(env, val); 88 tlb_flush(env_cpu(env)); 89 } 90 } 91 92 #if defined(TARGET_PPC64) 93 void helper_store_ptcr(CPUPPCState *env, target_ulong val) 94 { 95 if (env->spr[SPR_PTCR] != val) { 96 ppc_store_ptcr(env, val); 97 tlb_flush(env_cpu(env)); 98 } 99 } 100 101 void helper_store_pcr(CPUPPCState *env, target_ulong value) 102 { 103 PowerPCCPU *cpu = env_archcpu(env); 104 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 105 106 env->spr[SPR_PCR] = value & pcc->pcr_mask; 107 } 108 109 /* 110 * DPDES register is shared. Each bit reflects the state of the 111 * doorbell interrupt of a thread of the same core. 112 */ 113 target_ulong helper_load_dpdes(CPUPPCState *env) 114 { 115 target_ulong dpdes = 0; 116 117 /* TODO: TCG supports only one thread */ 118 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { 119 dpdes = 1; 120 } 121 122 return dpdes; 123 } 124 125 void helper_store_dpdes(CPUPPCState *env, target_ulong val) 126 { 127 PowerPCCPU *cpu = env_archcpu(env); 128 CPUState *cs = CPU(cpu); 129 130 /* TODO: TCG supports only one thread */ 131 if (val & ~0x1) { 132 qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " 133 TARGET_FMT_lx"\n", val); 134 return; 135 } 136 137 if (val & 0x1) { 138 env->pending_interrupts |= 1 << PPC_INTERRUPT_DOORBELL; 139 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 140 } else { 141 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); 142 } 143 } 144 #endif /* defined(TARGET_PPC64) */ 145 146 void helper_store_pidr(CPUPPCState *env, target_ulong val) 147 { 148 env->spr[SPR_BOOKS_PID] = val; 149 tlb_flush(env_cpu(env)); 150 } 151 152 void helper_store_lpidr(CPUPPCState *env, target_ulong val) 153 { 154 env->spr[SPR_LPIDR] = val; 155 156 /* 157 * We need to flush the TLB on LPID changes as we only tag HV vs 158 * guest in TCG TLB. Also the quadrants means the HV will 159 * potentially access and cache entries for the current LPID as 160 * well. 161 */ 162 tlb_flush(env_cpu(env)); 163 } 164 165 void helper_store_hid0_601(CPUPPCState *env, target_ulong val) 166 { 167 target_ulong hid0; 168 169 hid0 = env->spr[SPR_HID0]; 170 if ((val ^ hid0) & 0x00000008) { 171 /* Change current endianness */ 172 env->hflags &= ~(1 << MSR_LE); 173 env->hflags_nmsr &= ~(1 << MSR_LE); 174 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); 175 env->hflags |= env->hflags_nmsr; 176 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, 177 val & 0x8 ? 'l' : 'b', env->hflags); 178 } 179 env->spr[SPR_HID0] = (uint32_t)val; 180 } 181 182 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) 183 { 184 if (likely(env->pb[num] != value)) { 185 env->pb[num] = value; 186 /* Should be optimized */ 187 tlb_flush(env_cpu(env)); 188 } 189 } 190 191 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) 192 { 193 store_40x_dbcr0(env, val); 194 } 195 196 void helper_store_40x_sler(CPUPPCState *env, target_ulong val) 197 { 198 store_40x_sler(env, val); 199 } 200 #endif 201 /*****************************************************************************/ 202 /* PowerPC 601 specific instructions (POWER bridge) */ 203 204 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg) 205 { 206 switch (arg) { 207 case 0x0CUL: 208 /* Instruction cache line size */ 209 return env->icache_line_size; 210 break; 211 case 0x0DUL: 212 /* Data cache line size */ 213 return env->dcache_line_size; 214 break; 215 case 0x0EUL: 216 /* Minimum cache line size */ 217 return (env->icache_line_size < env->dcache_line_size) ? 218 env->icache_line_size : env->dcache_line_size; 219 break; 220 case 0x0FUL: 221 /* Maximum cache line size */ 222 return (env->icache_line_size > env->dcache_line_size) ? 223 env->icache_line_size : env->dcache_line_size; 224 break; 225 default: 226 /* Undefined */ 227 return 0; 228 break; 229 } 230 } 231 232 /*****************************************************************************/ 233 /* Special registers manipulation */ 234 235 /* GDBstub can read and write MSR... */ 236 void ppc_store_msr(CPUPPCState *env, target_ulong value) 237 { 238 hreg_store_msr(env, value, 0); 239 } 240 241 /* 242 * This code is lifted from MacOnLinux. It is called whenever THRM1,2 243 * or 3 is read an fixes up the values in such a way that will make 244 * MacOS not hang. These registers exist on some 75x and 74xx 245 * processors. 246 */ 247 void helper_fixup_thrm(CPUPPCState *env) 248 { 249 target_ulong v, t; 250 int i; 251 252 #define THRM1_TIN (1 << 31) 253 #define THRM1_TIV (1 << 30) 254 #define THRM1_THRES(x) (((x) & 0x7f) << 23) 255 #define THRM1_TID (1 << 2) 256 #define THRM1_TIE (1 << 1) 257 #define THRM1_V (1 << 0) 258 #define THRM3_E (1 << 0) 259 260 if (!(env->spr[SPR_THRM3] & THRM3_E)) { 261 return; 262 } 263 264 /* Note: Thermal interrupts are unimplemented */ 265 for (i = SPR_THRM1; i <= SPR_THRM2; i++) { 266 v = env->spr[i]; 267 if (!(v & THRM1_V)) { 268 continue; 269 } 270 v |= THRM1_TIV; 271 v &= ~THRM1_TIN; 272 t = v & THRM1_THRES(127); 273 if ((v & THRM1_TID) && t < THRM1_THRES(24)) { 274 v |= THRM1_TIN; 275 } 276 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) { 277 v |= THRM1_TIN; 278 } 279 env->spr[i] = v; 280 } 281 } 282