1 /* 2 * PowerPC memory access emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/target_page.h" 24 #include "qemu/host-utils.h" 25 #include "exec/helper-proto.h" 26 #include "helper_regs.h" 27 #include "accel/tcg/cpu-ldst.h" 28 #include "internal.h" 29 #include "qemu/atomic128.h" 30 31 /* #define DEBUG_OP */ 32 33 static inline bool needs_byteswap(const CPUPPCState *env) 34 { 35 #if TARGET_BIG_ENDIAN 36 return FIELD_EX64(env->msr, MSR, LE); 37 #else 38 return !FIELD_EX64(env->msr, MSR, LE); 39 #endif 40 } 41 42 /*****************************************************************************/ 43 /* Memory load and stores */ 44 45 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, 46 target_long arg) 47 { 48 #if defined(TARGET_PPC64) 49 if (!msr_is_64bit(env, env->msr)) { 50 return (uint32_t)(addr + arg); 51 } else 52 #endif 53 { 54 return addr + arg; 55 } 56 } 57 58 static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb, 59 MMUAccessType access_type, int mmu_idx, 60 uintptr_t raddr) 61 { 62 void *host1, *host2; 63 uint32_t nb_pg1, nb_pg2; 64 65 nb_pg1 = -(addr | TARGET_PAGE_MASK); 66 if (likely(nb <= nb_pg1)) { 67 /* The entire operation is on a single page. */ 68 return probe_access(env, addr, nb, access_type, mmu_idx, raddr); 69 } 70 71 /* The operation spans two pages. */ 72 nb_pg2 = nb - nb_pg1; 73 host1 = probe_access(env, addr, nb_pg1, access_type, mmu_idx, raddr); 74 addr = addr_add(env, addr, nb_pg1); 75 host2 = probe_access(env, addr, nb_pg2, access_type, mmu_idx, raddr); 76 77 /* If the two host pages are contiguous, optimize. */ 78 if (host2 == host1 + nb_pg1) { 79 return host1; 80 } 81 return NULL; 82 } 83 84 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 85 { 86 uintptr_t raddr = GETPC(); 87 int mmu_idx = ppc_env_mmu_index(env, false); 88 void *host = probe_contiguous(env, addr, (32 - reg) * 4, 89 MMU_DATA_LOAD, mmu_idx, raddr); 90 91 if (likely(host)) { 92 /* Fast path -- the entire operation is in RAM at host. */ 93 for (; reg < 32; reg++) { 94 env->gpr[reg] = (uint32_t)ldl_be_p(host); 95 host += 4; 96 } 97 } else { 98 /* Slow path -- at least some of the operation requires i/o. */ 99 for (; reg < 32; reg++) { 100 env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr); 101 addr = addr_add(env, addr, 4); 102 } 103 } 104 } 105 106 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 107 { 108 uintptr_t raddr = GETPC(); 109 int mmu_idx = ppc_env_mmu_index(env, false); 110 void *host = probe_contiguous(env, addr, (32 - reg) * 4, 111 MMU_DATA_STORE, mmu_idx, raddr); 112 113 if (likely(host)) { 114 /* Fast path -- the entire operation is in RAM at host. */ 115 for (; reg < 32; reg++) { 116 stl_be_p(host, env->gpr[reg]); 117 host += 4; 118 } 119 } else { 120 /* Slow path -- at least some of the operation requires i/o. */ 121 for (; reg < 32; reg++) { 122 cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr); 123 addr = addr_add(env, addr, 4); 124 } 125 } 126 } 127 128 static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 129 uint32_t reg, uintptr_t raddr) 130 { 131 int mmu_idx; 132 void *host; 133 uint32_t val; 134 135 if (unlikely(nb == 0)) { 136 return; 137 } 138 139 mmu_idx = ppc_env_mmu_index(env, false); 140 host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr); 141 142 if (likely(host)) { 143 /* Fast path -- the entire operation is in RAM at host. */ 144 for (; nb > 3; nb -= 4) { 145 env->gpr[reg] = (uint32_t)ldl_be_p(host); 146 reg = (reg + 1) % 32; 147 host += 4; 148 } 149 switch (nb) { 150 default: 151 return; 152 case 1: 153 val = ldub_p(host) << 24; 154 break; 155 case 2: 156 val = lduw_be_p(host) << 16; 157 break; 158 case 3: 159 val = (lduw_be_p(host) << 16) | (ldub_p(host + 2) << 8); 160 break; 161 } 162 } else { 163 /* Slow path -- at least some of the operation requires i/o. */ 164 for (; nb > 3; nb -= 4) { 165 env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr); 166 reg = (reg + 1) % 32; 167 addr = addr_add(env, addr, 4); 168 } 169 switch (nb) { 170 default: 171 return; 172 case 1: 173 val = cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24; 174 break; 175 case 2: 176 val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16; 177 break; 178 case 3: 179 val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16; 180 addr = addr_add(env, addr, 2); 181 val |= cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8; 182 break; 183 } 184 } 185 env->gpr[reg] = val; 186 } 187 188 void helper_lsw(CPUPPCState *env, target_ulong addr, 189 uint32_t nb, uint32_t reg) 190 { 191 do_lsw(env, addr, nb, reg, GETPC()); 192 } 193 194 /* 195 * PPC32 specification says we must generate an exception if rA is in 196 * the range of registers to be loaded. In an other hand, IBM says 197 * this is valid, but rA won't be loaded. For now, I'll follow the 198 * spec... 199 */ 200 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, 201 uint32_t ra, uint32_t rb) 202 { 203 if (likely(xer_bc != 0)) { 204 int num_used_regs = DIV_ROUND_UP(xer_bc, 4); 205 if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) || 206 lsw_reg_in_range(reg, num_used_regs, rb))) { 207 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 208 POWERPC_EXCP_INVAL | 209 POWERPC_EXCP_INVAL_LSWX, GETPC()); 210 } else { 211 do_lsw(env, addr, xer_bc, reg, GETPC()); 212 } 213 } 214 } 215 216 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 217 uint32_t reg) 218 { 219 uintptr_t raddr = GETPC(); 220 int mmu_idx; 221 void *host; 222 uint32_t val; 223 224 if (unlikely(nb == 0)) { 225 return; 226 } 227 228 mmu_idx = ppc_env_mmu_index(env, false); 229 host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr); 230 231 if (likely(host)) { 232 /* Fast path -- the entire operation is in RAM at host. */ 233 for (; nb > 3; nb -= 4) { 234 stl_be_p(host, env->gpr[reg]); 235 reg = (reg + 1) % 32; 236 host += 4; 237 } 238 val = env->gpr[reg]; 239 switch (nb) { 240 case 1: 241 stb_p(host, val >> 24); 242 break; 243 case 2: 244 stw_be_p(host, val >> 16); 245 break; 246 case 3: 247 stw_be_p(host, val >> 16); 248 stb_p(host + 2, val >> 8); 249 break; 250 } 251 } else { 252 for (; nb > 3; nb -= 4) { 253 cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr); 254 reg = (reg + 1) % 32; 255 addr = addr_add(env, addr, 4); 256 } 257 val = env->gpr[reg]; 258 switch (nb) { 259 case 1: 260 cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr); 261 break; 262 case 2: 263 cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr); 264 break; 265 case 3: 266 cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr); 267 addr = addr_add(env, addr, 2); 268 cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr); 269 break; 270 } 271 } 272 } 273 274 static void dcbz_common(CPUPPCState *env, target_ulong addr, 275 int mmu_idx, int dcbz_size, uintptr_t retaddr) 276 { 277 target_ulong mask = ~(target_ulong)(dcbz_size - 1); 278 void *haddr; 279 280 /* Align address */ 281 addr &= mask; 282 283 /* Check reservation */ 284 if (unlikely((env->reserve_addr & mask) == addr)) { 285 env->reserve_addr = (target_ulong)-1ULL; 286 } 287 288 /* Try fast path translate */ 289 #ifdef CONFIG_USER_ONLY 290 haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx); 291 #else 292 haddr = probe_write(env, addr, dcbz_size, mmu_idx, retaddr); 293 if (unlikely(!haddr)) { 294 /* Slow path */ 295 for (int i = 0; i < dcbz_size; i += 8) { 296 cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr); 297 } 298 return; 299 } 300 #endif 301 302 set_helper_retaddr(retaddr); 303 memset(haddr, 0, dcbz_size); 304 clear_helper_retaddr(); 305 } 306 307 void helper_dcbz(CPUPPCState *env, target_ulong addr, int mmu_idx) 308 { 309 dcbz_common(env, addr, mmu_idx, env->dcache_line_size, GETPC()); 310 } 311 312 #ifdef TARGET_PPC64 313 void helper_dcbzl(CPUPPCState *env, target_ulong addr) 314 { 315 int dcbz_size = env->dcache_line_size; 316 317 /* 318 * The translator checked for POWERPC_EXCP_970. 319 * All that's left is to check HID5. 320 */ 321 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { 322 dcbz_size = 32; 323 } 324 325 dcbz_common(env, addr, ppc_env_mmu_index(env, false), dcbz_size, GETPC()); 326 } 327 #endif 328 329 void helper_icbi(CPUPPCState *env, target_ulong addr) 330 { 331 addr &= ~(env->dcache_line_size - 1); 332 /* 333 * Invalidate one cache line : 334 * PowerPC specification says this is to be treated like a load 335 * (not a fetch) by the MMU. To be sure it will be so, 336 * do the load "by hand". 337 */ 338 cpu_ldl_data_ra(env, addr, GETPC()); 339 } 340 341 void helper_icbiep(CPUPPCState *env, target_ulong addr) 342 { 343 #if !defined(CONFIG_USER_ONLY) 344 /* See comments above */ 345 addr &= ~(env->dcache_line_size - 1); 346 cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC()); 347 #endif 348 } 349 350 /* XXX: to be tested */ 351 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, 352 uint32_t ra, uint32_t rb) 353 { 354 int i, c, d; 355 356 d = 24; 357 for (i = 0; i < xer_bc; i++) { 358 c = cpu_ldub_data_ra(env, addr, GETPC()); 359 addr = addr_add(env, addr, 1); 360 /* ra (if not 0) and rb are never modified */ 361 if (likely(reg != rb && (ra == 0 || reg != ra))) { 362 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); 363 } 364 if (unlikely(c == xer_cmp)) { 365 break; 366 } 367 if (likely(d != 0)) { 368 d -= 8; 369 } else { 370 d = 24; 371 reg++; 372 reg = reg & 0x1F; 373 } 374 } 375 return i; 376 } 377 378 /*****************************************************************************/ 379 /* Altivec extension helpers */ 380 #if HOST_BIG_ENDIAN 381 #define HI_IDX 0 382 #define LO_IDX 1 383 #else 384 #define HI_IDX 1 385 #define LO_IDX 0 386 #endif 387 388 /* 389 * We use MSR_LE to determine index ordering in a vector. However, 390 * byteswapping is not simply controlled by MSR_LE. We also need to 391 * take into account endianness of the target. This is done for the 392 * little-endian PPC64 user-mode target. 393 */ 394 395 #define LVE(name, access, swap, element) \ 396 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 397 target_ulong addr) \ 398 { \ 399 size_t n_elems = ARRAY_SIZE(r->element); \ 400 int adjust = HI_IDX * (n_elems - 1); \ 401 int sh = sizeof(r->element[0]) >> 1; \ 402 int index = (addr & 0xf) >> sh; \ 403 if (FIELD_EX64(env->msr, MSR, LE)) { \ 404 index = n_elems - index - 1; \ 405 } \ 406 \ 407 if (needs_byteswap(env)) { \ 408 r->element[LO_IDX ? index : (adjust - index)] = \ 409 swap(access(env, addr, GETPC())); \ 410 } else { \ 411 r->element[LO_IDX ? index : (adjust - index)] = \ 412 access(env, addr, GETPC()); \ 413 } \ 414 } 415 #define I(x) (x) 416 LVE(LVEBX, cpu_ldub_data_ra, I, u8) 417 LVE(LVEHX, cpu_lduw_data_ra, bswap16, u16) 418 LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) 419 #undef I 420 #undef LVE 421 422 #define STVE(name, access, swap, element) \ 423 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 424 target_ulong addr) \ 425 { \ 426 size_t n_elems = ARRAY_SIZE(r->element); \ 427 int adjust = HI_IDX * (n_elems - 1); \ 428 int sh = sizeof(r->element[0]) >> 1; \ 429 int index = (addr & 0xf) >> sh; \ 430 if (FIELD_EX64(env->msr, MSR, LE)) { \ 431 index = n_elems - index - 1; \ 432 } \ 433 \ 434 if (needs_byteswap(env)) { \ 435 access(env, addr, swap(r->element[LO_IDX ? index : \ 436 (adjust - index)]), \ 437 GETPC()); \ 438 } else { \ 439 access(env, addr, r->element[LO_IDX ? index : \ 440 (adjust - index)], GETPC()); \ 441 } \ 442 } 443 #define I(x) (x) 444 STVE(STVEBX, cpu_stb_data_ra, I, u8) 445 STVE(STVEHX, cpu_stw_data_ra, bswap16, u16) 446 STVE(STVEWX, cpu_stl_data_ra, bswap32, u32) 447 #undef I 448 #undef LVE 449 450 #ifdef TARGET_PPC64 451 #define GET_NB(rb) ((rb >> 56) & 0xFF) 452 453 #define VSX_LXVL(name, lj) \ 454 void helper_##name(CPUPPCState *env, target_ulong addr, \ 455 ppc_vsr_t *xt, target_ulong rb) \ 456 { \ 457 ppc_vsr_t t; \ 458 uint64_t nb = GET_NB(rb); \ 459 int i; \ 460 \ 461 t.s128 = int128_zero(); \ 462 if (nb) { \ 463 nb = (nb >= 16) ? 16 : nb; \ 464 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \ 465 for (i = 16; i > 16 - nb; i--) { \ 466 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \ 467 addr = addr_add(env, addr, 1); \ 468 } \ 469 } else { \ 470 for (i = 0; i < nb; i++) { \ 471 t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \ 472 addr = addr_add(env, addr, 1); \ 473 } \ 474 } \ 475 } \ 476 *xt = t; \ 477 } 478 479 VSX_LXVL(LXVL, 0) 480 VSX_LXVL(LXVLL, 1) 481 #undef VSX_LXVL 482 483 #define VSX_STXVL(name, lj) \ 484 void helper_##name(CPUPPCState *env, target_ulong addr, \ 485 ppc_vsr_t *xt, target_ulong rb) \ 486 { \ 487 target_ulong nb = GET_NB(rb); \ 488 int i; \ 489 \ 490 if (!nb) { \ 491 return; \ 492 } \ 493 \ 494 nb = (nb >= 16) ? 16 : nb; \ 495 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \ 496 for (i = 16; i > 16 - nb; i--) { \ 497 cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \ 498 addr = addr_add(env, addr, 1); \ 499 } \ 500 } else { \ 501 for (i = 0; i < nb; i++) { \ 502 cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC()); \ 503 addr = addr_add(env, addr, 1); \ 504 } \ 505 } \ 506 } 507 508 VSX_STXVL(STXVL, 0) 509 VSX_STXVL(STXVLL, 1) 510 #undef VSX_STXVL 511 #undef GET_NB 512 #endif /* TARGET_PPC64 */ 513 514 #undef HI_IDX 515 #undef LO_IDX 516 517 void helper_tbegin(CPUPPCState *env) 518 { 519 /* 520 * As a degenerate implementation, always fail tbegin. The reason 521 * given is "Nesting overflow". The "persistent" bit is set, 522 * providing a hint to the error handler to not retry. The TFIAR 523 * captures the address of the failure, which is this tbegin 524 * instruction. Instruction execution will continue with the next 525 * instruction in memory, which is precisely what we want. 526 */ 527 528 env->spr[SPR_TEXASR] = 529 (1ULL << TEXASR_FAILURE_PERSISTENT) | 530 (1ULL << TEXASR_NESTING_OVERFLOW) | 531 (FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) | 532 (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) | 533 (1ULL << TEXASR_FAILURE_SUMMARY) | 534 (1ULL << TEXASR_TFIAR_EXACT); 535 env->spr[SPR_TFIAR] = env->nip | (FIELD_EX64_HV(env->msr) << 1) | 536 FIELD_EX64(env->msr, MSR, PR); 537 env->spr[SPR_TFHAR] = env->nip + 4; 538 env->crf[0] = 0xB; /* 0b1010 = transaction failure */ 539 } 540